935007610602 [NXP]
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch;
| 型号： | 935007610602 |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F5074
Synchronizing dual D-type flip-flop/clock
driver
Product specification
IC15 Data Handbook
1990 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
FEATURES
PIN CONFIGURATION
• Metastable immune characteristics
V
1
2
3
4
5
14
13
CC
RD0
D0
• Output skew guaranteed less than 1.5ns
RD1
• High source current (I = 15mA) ideal for clock driver
OH
12 D1
CP0
applications
11
10
9
CP1
SD1
Q1
SD0
Q0
• Pin out compatible with 74F74
• 74F50728 for synchronizing cascaded D–type flip–flop
Q0
6
7
• See 74F50729 for synchronizing dual D–type flip–flop with
8
GND
Q1
edge–triggered set and reset
SF00582
• See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
• Industrial temperature range available (–40°C to +85°C)
IEC/IEEE SYMBOL
TYPICAL SUPPLY
CURRENT (TOTAL)
TYPE
TYPICAL f
max
2
12
74F5074
120MHz
20mA
D0 D1
3
4
CP0
SD0
RD0
1
ORDERING INFORMATION
11
CP1
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%,
10
13
SD1
RD1
DESCRIPTION
PKG DWG #
Q0 Q0 Q1 Q1
V
CC
T
amb
= 0°C to +70°C
5
6
9
8
14–pin plastic DIP
14–pin plastic SO
N74F5074N
SOT27-1
V
= Pin 14
CC
SF00583
GND = Pin 7
N74F5074D
SOT108-1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
LOGIC SYMBOL
74F
4
3
&
LOAD VAL-
UE HIGH/
LOW
S
(U.L.)
HIGH/
LOW
3
6
PINS
DESCRIPTION
C1
2
1
1D
D0, D1
Data inputs
1.0/0.417
1.0/1.0
1.0/1.0
1.0/1.0
750/33
20µA/250µA
20µA/20µA
20µA/20µA
20µA/20µA
Clock inputs (active
rising edge)
R
S
CP0, CP1
SD0, SD1
RD0, RD1
10
11
Set inputs (active low)
9
Reset inputs (active
low)
C2
12
13
2D
R
Q0, Q1, Q0,
Q1
8
Data outputs
15mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high
state and 0.6mA in the low state.
SF00584
2
September 14, 1990
853-1391 00419
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
LOGIC DIAGRAM
4, 10
SD
Figure 2 shows clearly that the Q output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q output did not change
state even though the Q output glitched to at least 1.5 volts, the
trigger point of the scope.
5, 9
6, 8
1, 13
RD
Q
Q
3, 11
CP
2, 12
D
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductor patented circuitry. If a metastable
event occurs within the flop the only outward manifestation of the
event will be an increased clock–to–Q/Q propagation delay. This
propagation delay is, of course, a function of the metastability
V
= Pin 14
GND = Pin 7
CC
SF00585
DESCRIPTION
The 74F5074 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
characteristics of the part defined by τ and T
0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low–to–high transition of the clock for
guaranteed propagation delays.
After determining the T and t of the flop, calculating the mean time
0
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F5074 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
(t’/t)
The 74F5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
MTBF = e / T f f
o C I
In this formula, f is the frequency of the clock, f is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
C
I
metastable state. Typical metastability parameters for the 74F5074
6
I
are: τ 135ps and T
9.8 X 10 sec where τ represents a
o
function of the rate at which a latch in a metastable state resolves
15
2
Multiplying f by f gives an answer of 10 Hz . From Fig. 4 it is
I
C
that condition and T represents a function of the measurement of
0
10
clear that the MTBF is greater than 10 seconds. Using the above
formula the actual MTBF is 1.51 X 10 seconds or about 480 years.
the propensity of a latch to enter a metastable state.
10
Metastable Immune Characteristics
Philips Semiconductor uses the term ’metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display an output anomaly under any
circumstances including setup and hold time violations. This claim is
easily verified on the 74F5074. By running two independent signal
generators (see Fig. 1) at nearly the same frequency (in this case
10MHz clock and 10.02 MHz data) the device–under–test can be
often be driven into a metastable state. If the Q output is then used
to trigger a digital scope set to infinite persistence the Q output will
build a waveform. An experiment was run by continuously operating
the devices in the region where metastability will occur.
TRIGGER
DIGITAL
SIGNAL GENERATOR
SIGNAL GENERATOR
D
Q
Q
SCOPE
CP
INPUT
SF00586
Figure 1. Test Set-up
3
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00587
Figure 2. 74F74 Q Output triggered by Q output, set-up and hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q Output triggered by Q output, set-up and hold times violated
4
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
6
8
10
12
10
10
10
10
14
15
10
12
11
10
9
10
10
10
10
10
10
10
10 = f f
C I
10,000 years
100 years
MTBF in seconds
8
one year
7
6
one week
7
8
9
10
t’ in nanoseconds
SF00589
6
NOTE: V = 5V, T
= 25°C, τ =135ps, To = 9.8 X 10 sec
CC
amb
Figure 4.
TYPICAL VALUES FOR τ AND T AT VARIOUS V S AND TEMPERATURES
0
CC
T
amb
= 0°C
T
amb
= 25°C
T = 70°C
amb
V
CC
τ
T
0
τ
T
0
τ
T
0
9
6
5
5.5V
5.0V
4.5V
125ps
115ps
115ps
1.0 X 10 sec
138ps
135ps
132ps
5.4 X 10 sec
160ps
167ps
175ps
1.7 X 10 sec
10
6
4
1.3 X 10 sec
9.8 X 10 sec
3.9 X 10 sec
13
8
4
3.4 X 10 sec
5.1 X 10 sec
7.3 X 10 sec
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
SD
RD
H
L
CP
D
X
X
X
h
l
Q
Q
L
X
X
X
↑
H
L
L
H
H
L
Asynchronous set
H
Asynchronous reset
Undetermined*
Load “1”
L
L
H
H
H
H
H
H
H
H
↑
L
H
Load “0”
↑
X
NC
NC
Hold
NOTES:
H
h
L
l
=
=
=
=
High voltage level
High voltage level one setup time prior to low–to–high clock transition
Low voltage level
Low voltage level one setup time prior to low–to–high clock transition
No change from the previous setup
Don’t care
Low–to–high clock transition
Not low–to–high clock transition
NC=
X
↑
↑
*
=
=
=
=
This setup is unstable and will change when either set or reset return to the high level
5
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
40
mA
°C
°C
OUT
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
T = –40 to +85°C
A
MIN
4.5
MAX
UNIT
V
CC
V
IH
V
IL
Supply voltage
5.5
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
V
0.8
–18
–12
–15
20
V
I
Ik
mA
mA
mA
mA
V
± 10%
± 5%
I
High–level output current
CC
OH
V
CC
I
OL
Low–level output current
T
amb
Operating free air temperature range
0
+70
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
1
2
MIN TYP
MAX
V
High–level output voltage
V
= MIN, V
=
I
OH
= MAX
2.5
V
V
±10%V
OH
CC
IL
IL
CC
MAX,
V
IH
= MIN
2.7
3.4
±5%V
CC
V
CC
= MIN, V
=
V
OL
Low–level output voltage
I
OL
= MAX
0.30
0.30
0.50
0.50
V
±10%V
CC
MAX,
V
V
V
V
V
V
V
V
= MIN
V
±5%V
IH
CC
V
IK
Input clamp voltage
= MIN, I = I
IK
-0.73 -1.2
100
V
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
Input current at maximum input voltage
High–level input current
= MAX, V = 7.0V
µA
µA
µA
µA
mA
mA
I
I
= MAX, V = 2.7V
20
IH
IL
I
Low–level input current
Dn
= MAX, V = 0.5V
-250
I
CPn, SDn, RDn
= MAX, V = 0.5V
-20
I
3
I
I
Short circuit output current
= MAX
= MAX
-60
-150
OS
4
Supply current (total)
20
30
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
6
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
105
120
90
ns
ns
max
t
t
Propagation delay
CPn to Qn or Qn
2.0
2.0
3.9
3.9
6.0
6.0
1.5
2.0
6.5
6.5
PLH
PHL
t
t
Propagation delay
SDn, RDn to Qn or Qn
3.0
3.0
4.5
5.0
7.5
7.5
2.5
2.5
8.0
8.0
PLH
PHL
Waveform 2
Waveform 4
ns
ns
1,2
t
Output skew
1.5
1.5
sk(o)
NOTES:
1. |t actual – t actual| for any output compared to any other output where N and M are either LH or HL.
PN
PM
2. Skew times are valid only under same test conditions (temperature, V , loading, etc.,).
CC
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CPn
1.5
1.5
2.0
2.0
su
su
Waveform 1
Waveform 1
ns
ns
t (H)
Hold time, high or low
Dn to CPn
1.0
1.0
1.5
1.5
h
t (L)
h
t
t
(H)
(L)
CPn pulse width,
high or low
3.0
4.0
3.0
4.5
w
w
Waveform 1
Waveform 2
Waveform 3
ns
ns
ns
t
t
(L)
SDn or RDn pulse width, low
3.0
3.0
4.0
3.5
w
Recovery time
SDn or RDn to CPn
rec
7
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
AC WAVEFORMS
t
(L)
Dn
w
V
t
V
V
V
M
M
M
M
SDn
RDn
V
V
M
M
t
(H)
t (H)
h
(L)
t (L)
h
su
su
1/f
M
max
t
(L)
w
V
V
M
t
(L)
M
CPn
Qn
w
V
V
M
V
M
t
(H)
w
t
t
PHL
PLH
t
PHL
t
PLH
Qn
Qn
V
V
V
M
M
M
V
V
M
M
M
t
t
PLH
PHL
t
t
PHL
PLH
V
M
V
M
V
Qn
SF00050
SF00049
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Waveform 1. Propagation delay for data to output, data
setup time and hold times, and clock
width, and maximum clock frequency
V
Qn, Qn
M
t
sk(o)
SDn or RDn
CPn
V
M
t
Qn, Qn
V
M
rec
SF00590
V
M
Waveform 4. Output skew
SF00051
Waveform 3. Recovery time for set or reset to output
NOTES:
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
0V
V
CC
90%
90%
NEGATIVE
V
V
M
M
PULSE
10%
10%
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
V
rep. rate
t
w
t
t
THL
amplitude
3.0V
M
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
74F
1.5V
1MHz
500ns
SF00006
8
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
9
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
10
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
NOTES
11
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop/clock driver
74F5074
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05207
Document order number:
Philips
Semiconductors
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NXP
935007650118
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch
NXP
935007650602
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch
NXP
935007660602
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, 0.300 INCH, PLASTIC, MO-001AA, SOT-27-1, DIP-14, FF/Latch
NXP
935007670118
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch
NXP
935007670602
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14, FF/Latch
NXP
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