935014090005 [NXP]
IC LIQUID CRYSTAL DISPLAY DRIVER, UUC54, DIE-54, Display Driver;
| 型号： | 935014090005 |
| 厂家： | 
NXP |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, UUC54, DIE-54, Display Driver 驱动 接口集成电路 |
| 文件： | 总46页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8578
LCD row/column driver for dot
matrix graphic displays
1998 Sep 08
Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
CONTENTS
18
SOLDERING
18.1
18.2
18.3
18.3.1
18.3.2
18.3.3
18.4
Introduction
Reflow soldering
Wave soldering
LQFP
1
2
3
4
5
6
7
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
VSO
Method (LQFP and VSO)
Repairing soldered joints
PINNING
19
20
21
DEFINITIONS
FUNCTIONAL DESCRIPTION
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
7.1
7.2
Mixed mode
Row mode
7.3
7.4
7.5
Multiplexed LCD bias generation
Power-on reset
Internal clock
7.6
External clock
7.7
7.8
7.9
Timing generator
Row/column drivers
Display mode controller
Display RAM
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
Data pointer
Subaddress counter
I2C-bus controller
Input filters
RAM access
Display control
TEST pin
8
I2C-BUS PROTOCOL
8.1
9
Command decoder
CHARACTERISTICS OF THE I2C-BUS
9.1
9.2
9.3
9.4
Bit transfer
Start and stop conditions
System configuration
Acknowledge
10
11
12
13
14
15
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16
17
CHIP-ON GLASS INFORMATION
PACKAGE OUTLINE
1998 Sep 08
2
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
1
FEATURES
• Single chip LCD controller/driver
• Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible)
• 40 driver outputs, configurable as 32⁄8, 24⁄16, 16
⁄
24 or
8
⁄
32 rows/columns
2
APPLICATIONS
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
• Externally selectable bias configuration, 5 or 6 levels
• 1280-bit RAM for display data storage and scratch pad
• Display memory bank switching
• Automotive information systems
• Telecommunication systems
• Point-of-sale terminals
• Computer terminals
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579)
• Instrumentation.
• Provides display synchronization for PCF8579
• On-chip oscillator, requires only 1 external resistor
• Power-on reset blanks display
• Logic voltage supply range 2.5 to 6 V
• Maximum LCD supply voltage 9 V
• Low power consumption
3
GENERAL DESCRIPTION
The PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device
has 40 outputs, of which 24 are programmable,
configurable as 32⁄8, 24⁄16, 16 24 or 8⁄32 rows/columns.
⁄
The PCF8578 can function as a stand-alone LCD
controller/driver for use in small systems, or for larger
systems can be used in conjunction with up to
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
32 PCF8579s for which it has been optimized. Together
these two devices form a general purpose LCD dot matrix
driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). Communication overheads are
minimized by a display RAM with auto-incremented
addressing and display bank switching.
• Optimized pinning for single plane wiring in multiple
device applications (with PCF8579)
• Space saving 56-lead plastic mini-pack and 64 pin quad
flat pack
• Compatible with chip-on-glass technology.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8578T
PCF8578U/2
PCF8578H
VSO56
−
plastic very small outline package; 56 leads
chip with bumps in tray
SOT190-1
−
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
1998 Sep 08
3
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
5
BLOCK DIAGRAM
C39 - C32
R31/C31 - R8/C8
R7 - R0
17 - 56
(29 to 35, 37, 38 to 46
48 to 62, 63, 64, 1 to 6)
9 (20)
V
DD
10 (21)
11 (22)
12 (23)
13 (24)
14 (25)
V
2
(1)
V
V
V
3
4
5
ROW/COLUMN
DRIVERS
PCF8578
V
LCD
6 (12)
TEST
DISPLAY
MODE
CONTROLLER
OUTPUT
CONTROLLER
Y DECODER
AND SENSING
AMPLIFIERS
32 x 40-BIT
DISPLAY RAM
DISPLAY
DECODER
X DECODER
(9) 3
SYNC
SUBADDRESS
COUNTER
TIMING
GENERATOR
POWER-ON
RESET
RAM DATA POINTER
(10) 4
CLK
Y
X
(16) 8
OSC
2 (8)
1 (7)
2
SCL
SDA
INPUT
FILTERS
I C-BUS
COMMAND
DECODER
OSCILLATOR
CONTROLLER
R
OSC
(11) 5
(14, 15, 17 to 19
26 to 28 36, 47)
V
SS
15, 16
n.c.
7 (13)
SA0
MSA842
n.c.
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
4
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
6
PINNING
SYMBOL
PIN
DESCRIPTION
I2C-bus serial data input/output
I2C-bus serial clock input
cascade synchronization output
external clock input/output
ground (logic)
VSO56
LQFP64
SDA
1
7
8
SCL
2
SYNC
CLK
3
9
4
10
VSS
5
11
TEST
SA0
6
12
test pin (connect to VSS)
I2C-bus slave address input (bit 0)
7
8
13
OSC
VDD
16
oscillator input
9
20
positive supply voltage
LCD bias voltage inputs
LCD supply voltage
V2 to V5
VLCD
n.c.
10 to 13
14
21 to 24
25
15, 16
14, 15, 17 to 19, not connected
26 to 28, 36, 47
C39 to C32
17 to 24
25 to 48
49 to 56
29 to 35, 37
38 to 46, 48 to 62 LCD row/column driver outputs
63, 64, 1 to 6 LCD row driver outputs
LCD column driver outputs
R31/C31 to R8/C8
R7 to R0
1998 Sep 08
5
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
SDA
SCL
1
2
56 R0
55
54
R1
R2
SYNC
CLK
3
4
53 R3
52 R4
51 R5
V
5
SS
TEST
SA0
6
50
7
R6
OSC
8
49
48 R8/C8
R7
V
9
DD
V
2
10
11
12
47
46
45
44
43
42
R9/C9
V
3
R10/C10
R11/C11
R12/C12
R13/C13
R14/C14
R15/C15
R16/C16
R17/C17
R18/C18
R19/C19
R20/C20
R21/C21
R22/C22
V
4
V
5
13
14
15
V
LCD
PCF8578
n.c.
n.c. 16
17
41
40
39
C39
C38 18
19
20
C37
C36
38
37
36
35
C35 21
22
C33 23
24
R31/C31 25
26
C34
34
C32
33 R23/C23
32 R24/C24
R30/C30
31
30
R25/C25
R26/C26
R29/C29 27
R28/C28 28
29 R27/C27
MSA839
Fig.2 Pin configuration (VSO56).
6
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
1
48
47
R22/C22
n.c.
R5
R4
R3
2
3
4
5
6
7
8
9
46 R23/C23
R2
45
44
R24/C24
R25/C25
R1
R0
43 R26/C26
R27/C27
42
SDA
SCL
SYNC
41 R28/C28
40 R29/C29
39 R30/C30
38 R31/C31
PCF8578
CLK 10
V
11
SS
TEST 12
SA0 13
n.c. 14
37
36
35
34
C32
n.c.
C33
C34
n.c.
15
OSC 16
33 C35
MBH588
Fig.3 Pin configuration (LQFP64).
7
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
7
FUNCTIONAL DESCRIPTION
The PCF8578 row/column driver is designed for use in one
of three ways:
connected between OSC and VSS
.
Commands sent on the I2C-bus from the host
• Stand-alone row/column driver for small displays
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at 0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
(mixed mode)
• Row/column driver with cascaded PCF8579s
(mixed mode)
• Row driver with cascaded PCF8579s (mixed mode).
7.1
Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
7.2
Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Table 1 Possible displays configurations
MIXED MODE
MULTIPLEX
ROW MODE
APPLICATION
RATE
TYPICAL APPLICATIONS
ROWS
COLUMNS
ROWS
COLUMNS
Stand alone
1 : 8
1 : 16
1 : 24
1 : 32
1 : 8
8
16
32
24
−
−
−
−
small digital or
alphanumerical displays
24
16
−
−
32
8
−
−
With PCF8579
8(1)
16(1)
24(1)
32(1)
632(1)
624(1)
616(1)
608(1)
8 × 4 4(2)
16 × 2(2)
24(2)
24(2)
640(2)
640(2)
640(2)
640(2)
alphanumeric displays and
dot matrix graphic displays
1 : 16
1 : 24
1 : 32
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
1998 Sep 08
8
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.3
Multiplexed LCD bias generation
7.4
Power-on reset
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of Vop (Vop = VDD − VLCD), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for Vop is obtained by equating Voff(rms) with Vth. Figure 4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
At power-on the PCF8578 resets to a defined starting
condition as follows:
1. Display blank
2. 1 : 32 multiplex rate, row mode
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Table 2 Optimum LCD voltages
MULTIPLEX RATE
PARAMETER
1 : 8
1 : 16
1 : 24
1 : 32
MSA838
1.0
V2
V
--------
Vop
0.739
0.800
0.830
0.850
bias
V
V
V
op
2
3
0.8
0.6
0.4
0.2
0
V 3
--------
V op
0.522
0.478
0.261
0.297
0.430
1.447
3.370
0.600
0.400
0.200
0.245
0.316
1.291
4.080
0.661
0.339
0.170
0.214
0.263
1.230
4.680
0.700
0.300
0.150
0.193
0.230
1.196
5.190
V 4
--------
V op
V
V
4
5
V 5
--------
V op
V off (rms)
-----------------------
Vop
1:8
1:16
1:24
1:32
multiplex rate
V on (rms)
----------------------
Vop
Vbias = V2, V3, V4, V5. See Table 2.
V on (rms)
D =
-----------------------
Voff (rms)
Fig.4 Vbias/Vop as a function of the multiplex rate.
V op
--------
Vth
Table 3 Multiplex rates and resistor values for Fig.5
MULTIPLEX RATE (n)
RESISTORS
n = 8
n = 16, 24, 32
R1
R2
R3
R
R
R
( n – 2) R
(3 – n) R
( n – 3) R
1998 Sep 08
9
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LCD DISPLAY
n
rows
40
columns
n
V
V
V
DD
DD
40
columns
R1
R2
R3
R2
R1
C
C
C
C
C
2
V
3
V
V
A0
A1
DD
DD
HOST
MICROCONTROLLER
V
V
V
subaddress 1
LCD
LCD
PCF8578
PCF8579
V
V
/ V
4
SS DD
A2
A3
V
SS
SS
SCL
SDA
V
V
/
SA0
SS DD
V
V
3
CLK SYNC
SDA SCL
4
V
5
V
V
LCD
SS
SA0
V
/ V
SS DD
OSC
V
V
R
LCD
SS
OSC
CLK SYNC
SDA SCL
MSA843
Fig.5 Typical mixed mode configuration.
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
T
frame
ON
OFF
0
1
2
3
4
5
6
7
V
V
V
V
V
V
DD
2
3
ROW 0
4
5
LCD
1:8
V
V
V
V
V
V
DD
2
3
4
COLUMN
5
LCD
SYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:16
V
DD
V
2
V
3
V
COLUMN
4
V
5
V
LCD
SYNC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:24
V
DD
V
2
V
3
4
V
COLUMN
V
5
V
LCD
SYNC
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:32
V
DD
V
2
V
3
V
COLUMN
4
V
5
V
LCD
SYNC
column
display
MSA841
Fig.6 LCD row/column waveforms.
11
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
T
state 1 (OFF)
state 2 (ON)
frame
V
DD
V
2
V
ROW 1
R1 (t)
3
V
V
V
4
5
LCD
V
V
V
V
V
V
DD
2
ROW 2
R2 (t)
3
dot matrix
1:8 multiplex rate
4
5
LCD
V
V
V
V
V
V
DD
2
COL 1
C1 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
COL 2
C2 (t)
3
4
5
LCD
V
op
0.261 V
op
V
(t)
0 V
state 1
0.261 V
op
V
V
op
op
0.478 V
op
op
0.261 V
V
(t)
0 V
state 2
0.261 V
op
0.478 V
op
V
op
MSA840
V
(t) = C1(t) R1(t):
general relationship (n = multiplex rate)
state 1
V
V
on(rms)
on(rms)
1
8
8
1
1
n
n
1
1
=
=
=
=
0.430
(
)
(
)
V
V
8
8
1
n
n
op
op
V
(t) = C2(t) R2(t):
state 2
V
off(rms)
(
)
n 1
n
2
2
V
(
)
1
n
V
op
off(rms)
(
)
1
2
8
=
=
0.297
2
(
)
V
8
8
1
op
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
12
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
state 1 (OFF)
state 2 (ON)
T
frame
V
V
V
V
V
V
DD
2
ROW 1
R1 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
ROW 2
R2 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
COL 1
C1 (t)
3
4
5
dot matrix
1:16 multiplex rate
LCD
V
V
V
V
V
V
DD
2
COL 2
C2 (t)
3
4
5
LCD
V
op
0.2 V
op
V
(t)
0 V
0.2 V
state 1
op
V
V
op
op
0.6 V
op
0.2 V
op
V
(t)
0 V
0.2 V
state 2
op
0.6 V
op
V
op
MSA836
V
(t) = C1(t) R1(t):
general relationship (n = multiplex rate)
state 1
V
V
on(rms)
on(rms)
1
16
(
1
1
n
n
1
1
=
=
=
=
0.316
)
(
)
V
V
16 16 16
1
n
n
op
op
V
V
(t) = C2(t) R2(t):
state 2
V
off(rms)
(
)
n 1
n
2
2
V
(
)
1
n
op
off(rms)
(
)
1
2
16
=
=
0.254
2
(
)
V
16 16
1
op
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
13
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.5
Internal clock
7.6
External clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor ROSC, see Fig.9.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at CLK
and has a frequency 1⁄6 (multiplex rate 1 : 8, 1 : 16 and
1 : 32) or 1⁄8 (multiplex rate 1 : 24) of the oscillator
frequency.
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7
Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
MSA837
3
10
f
OSC
7.8
Row/column drivers
(kHz)
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
2
10
10
1
10
2
3
4
10
10
10
(kΩ)
R
OSC
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
To avoid capacitive coupling, which could adversely affect oscillator
stability, ROSC should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to ROSC
.
Fig.9 Oscillator frequency as a function of
external oscillator resistor, ROSC
.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.
OSCILLATOR
FREQUENCY
fOSC(2) (Hz)
FRAME FREQUENCY
fSYNC (Hz)
DIVISION
RATIO
CLOCK FREQUENCY
fCLK (Hz)
MULTIPLEX RATE (n)
12288
12288
64
64
1 : 8, 1 : 16, 1 : 32
1 : 24
6
8
2048
1536
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. ROSC = 330 kΩ.
1998 Sep 08
14
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.9
Display mode controller
7.15 RAM access
The configuration of the outputs (row or column) and the
selection of the appropriate driver waveforms are
controlled by the display mode controller.
RAM operations are only possible when the PCF8578 is
in mixed mode.
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
used in conjunction with the PCF8578 must start at 0001.
7.10 Display RAM
The PCF8578 contains a 32 x 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks
of 40 bytes (4 x 8 x 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus. The first
eight columns of data (0 to 7) cannot be displayed but
are available for general data storage and provide
compatibility with the PCF8579. There is a direct
correspondence between X-address and column output
number.
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Full-graphic.
These modes are specified by bits G1 to G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.10).
7.11 Data pointer
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.11):
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
• Device subaddress (specified by the DEVICE SELECT
command)
• RAM X-address (specified by the LOAD X-ADDRESS
command)
• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
7.12 Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes
place only when the contents of the subaddress counter
agree with the hardware subaddress. The hardware
subaddress of the PCF8578, valid in mixed mode only, is
fixed at 0000.
Subsequent data bytes will be written or read according to
the chosen RAM ACCESS mode. Device subaddresses
are automatically incremented between devices until the
last device is reached. If the last device has
subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to 0.
7.13 I2C-bus controller
7.16 Display control
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8578 acts as an
I2C-bus slave transmitter/receiver in mixed mode, and as
a slave receiver in row mode. A slave device cannot
control bus communication.
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.12. This feature is useful when scrolling in
alphanumeric applications.
7.14 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.17 TEST pin
The TEST pin must be connected to VSS
.
1998 Sep 08
15
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PCF8578/PCF8579
driver 1
PCF8579
driver 2
driver k
bank 0
bank 1
bank 2
bank 3
RAM
4 bytes
PCF8578/PCF8579 system RAM
LSB
40-bits
1
k
16
1 byte
0
1
2
3
4
5
6
7
8
9 10 11
character mode
MSB
0
1
2
3
4
5
6
7
8
9
10 12 14 16 18 20 22
11 13 15 17 19 21 23
2 bytes
half-graphic mode
0
1
2
3
4
5
6
7
8
9
12 16 20 24 28 32 36 40 44
13 17 21 25 29 33 37 41 45
4 bytes
10 14 18 22 26 30 34 38 42 46
11 15 19 23 27 31 35 39 43 47
MSA849
full-graphic mode
RAM data bytes are
written or read as
indicated above
Fig.10 RAM ACCESS mode.
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DEVICE SELECT:
subaddress 12
bank 0
bank 1
bank 2
bank 3
RAM ACCESS:
character mode
bank 1
RAM
LOAD X-ADDRESS: X-address = 8
R / W
slave address
S
A
0
READ
0
1
1
1
1
0
DATA
1
A
A
S
R / W
slave address
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
S
A
0
0
1
1
1
1
0
0
A
1
1
1
0
1
1
0
A
1
0
0
0
1
0
0
A
0
1
1
1
0
0
0
A
1
0
0
S
last command
DATA
A
DATA
A
WRITE
MSA835
Fig.11 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
RAM
bank 0
top of LCD
bank 1
bank 2
bank 3
LCD
MSA851
Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
1998 Sep 08
18
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
I2C-BUS PROTOCOL
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowledgement. After this
8
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types
of PCF8578 or PCF8579 can be distinguished on the
same I2C-bus which allows:
acknowledgement the master transmitter becomes a
master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop condition
(P).
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.13.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has been acknowledged, the I2C-bus master issues a stop
condition (P).
1998 Sep 08
19
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
acknowledge
acknowledge by
all addressed
PCF8578s / PCF8579s
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
R / W
slave address
S
A
0
0
1
1
1
1
0
0
A C
A
DISPLAY DATA
A
P
COMMAND
0 byte(s)
S
1 byte
n
n
0 byte(s)
update data pointers
and if necessary,
subaddress counter
MSA830
(a)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
slave address
S
A
0
S
A
0
0
1
1
1
1
0
0
A
C
A
0
1
1
1
1
0
1
A
DATA
A
DATA
1
COMMAND
P
S
S
n
1 byte
n bytes
last byte
R / W
R / W
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
update data pointers
and if necessary
subaddress counter
MSA832
(b)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
S
A
0
0
1
1
1
1
0
1
A
A
DATA
1
S
DATA
P
MSA831
n bytes
last byte
R / W
update data pointers
and if necessary,
subaddress counter
(c)
Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
1998 Sep 08
20
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
8.1
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. The most-significant bit of a
command is the continuation bit C (see Fig.14). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
MSB
LSB
C
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
The five commands available to the PCF8578 are defined
in Tables 5 and 6.
Fig.14 General information of command byte.
Table 5 Summary of commands
COMMAND
SET MODE
OPCODE(1)
DESCRIPTION
C
C
C
C
1
1
1
1
0
1
1
1
D
1
0
1
D
1
D
1
D
D
D
D
D
D
D
D
multiplex rate, display status, system type
defines bank at top of LCD
SET START BANK
DEVICE SELECT
RAM ACCESS
D
D
D
D
defines device subaddress
graphic mode, bank select (D D D D ≥ 12 is not
allowed; see SET START BANK opcode)
LOAD X-ADDRESS
C
0
D
D
D
D
D
D
0 to 39
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
1998 Sep 08
21
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Table 6 Definition of PCF8578/PCF8579 commands
COMMAND
SET MODE
OPCODE
OPTIONS
DESCRIPTION
C
C
1
1
0
1
T
E1 E0 M1 M0 see Table 7
see Table 8
defines LCD drive mode
defines display status
defines system type
see Table 9
SET START BANK
DEVICE SELECT
RAM ACCESS
1
1
1
B1 B0 see Table 10 defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo-motion and
background preparation of new display
C
C
1
1
1
1
0
1
A3 A2 A1 A0 see Table 11
four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
G1 G0 Y1 Y0 see Table 12 defines the auto-increment behaviour of
the address for RAM access
see Table 13 two bits of immediate data, bits Y0 to
Y1, are transferred to the X-address
pointer to define one of forty display
RAM columns
LOAD X-ADDRESS
C
0
X5 X4 X3 X2 X1 X0 see Table 14 six bits of immediate data, bits
X0 to X5, are transferred to the
X-address pointer to define one of forty
display RAM columns
1998 Sep 08
22
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Table 7 Set mode option 1
Table 11 Device select option 1
BITS
DESCRIPTION
BITS
LCD DRIVE MODE
Decimal value 0 to 15
A3
A2
A1
A0
M1
M0
1 : 8
MUX ( 8 rows)
MUX (16 rows)
MUX (24 rows)
MUX (32 rows)
0
1
1
0
1
0
1
0
Table 12 RAM access option 1
1 : 16
1 : 24
1 : 32
BITS
RAM ACCESS MODE
G1
G0
Character
0
0
1
1
0
1
0
1
Table 8 Set mode option 2
Half-graphic
BITS
Full-graphic
DISPLAY STATUS
Not allowed (note 1)
E1
E0
Blank
0
0
1
1
0
1
0
1
Note
Normal
1. See opcode for SET START BANK in Table 6.
All segments on
Inverse video
Table 13 Device select option 1
DESCRIPTION
BITS
Table 9 Set mode option 3
Decimal value 0 to 3
Y1
Y0
SYSTEM TYPE
BIT T
Table 14 Device select option 1
PCF8578 row only
0
1
PCF8578 mixed mode
DESCRIPTION
BITS
Decimal value 0 to 39
X5 X4 X3 X2 X1 X0
Table 10 Set start bank option 1
BITS
START BANK POINTER
B1
B0
Bank 0
Bank 1
Bank 2
Bank 3
0
0
1
1
0
1
0
1
1998 Sep 08
23
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
CHARACTERISTICS OF THE I2C-BUS
9.4
Acknowledge
9
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
9.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
9.3
System configuration
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.15 Bit transfer.
1998 Sep 08
24
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBA608
Fig.16 Definition of start and stop condition.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.17 System configuration.
clock pulse for
acknowledgement
START
condition
SCL FROM
MASTER
2
9
1
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.18 Acknowledgement on the I2C-bus.
25
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+8.0
VDD
UNIT
supply voltage
V
V
V
V
V
V
VLCD
VI1
VI2
Vo1
Vo2
II
LCD supply voltage
V
V
V
V
V
DD − 11
input voltage SDA, SCL, CLK, TEST, SA0 and OSC
input voltage V2 to V5
SS − 0.5 VDD + 0.5
LCD − 0.5 VDD + 0.5
SS − 0.5 VDD + 0.5
LCD − 0.5 VDD + 0.5
output voltage SYNC and CLK
output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39
DC input current
−10
−10
−50
−
+10
+10
+50
400
100
+150
mA
mA
mA
mW
mW
°C
IO
DC output current
IDD, ISS, ILCD
VDD, VSS or VLCD current
Ptot
Po
total power dissipation per package
power dissipation per output
storage temperature
−
Tstg
−65
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under “Handling MOS Devices”.
1998 Sep 08
26
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
−
6
6.0
V
VLCD
IDD1
IDD2
VPOR
LCD supply voltage
V
−
−
DD − 9
VDD − 3.5 V
supply current external clock
supply current internal clock
power-on reset level
fCLK = 2 kHz; note 1
ROSC = 330 kΩ
note 2
15
50
1.8
µA
20
µA
0.8
1.3
V
Logic
VIL
LOW level input voltage
HIGH level input voltage
VSS
0.7VDD
1
−
−
−
0.3VDD
VDD
−
V
VIH
IOL1
V
LOW level output current at SYNC
and CLK
VOL = 1 V; VDD = 5 V
VOH = 4 V; VDD = 5 V
VOL = 0.4 V; VDD = 5 V
mA
IOH1
HIGH level output current at SYNC
and CLK
−
−
−1
mA
IOL2
IL1
LOW level output current at SDA
3
−
−
−
mA
mA
leakage current at SDA, SCL, SYNC, Vi = VDD or VSS
CLK, TEST and SA0
−
+1
IL2
Ci
leakage current at OSC
Vi = VDD
note 3
−
−
−
−
+1
5
µA
input capacitance at SCL and SDA
pF
LCD outputs
IL3
leakage current at V2 to V5
Vi = VDD or VLCD
−2
−
+2
µA
VDC
DC component of LCD drivers
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
−
±20
−
mV
RROW
RCOL
output resistance R0 to R7 and
R8/C8 to R31/C31
row mode; note 4
−
−
1.5
3
3
6
kΩ
kΩ
output resistance R8/C8 to R31/C31 column mode; note 4
and C32 to C39
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD < VPOR
3. Periodically sampled; not 100% tested.
.
4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V2 to V5, VDD and VLCD) when the specified current flows through one output under the following conditions
(see Table 2):
a) Vop = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; ILOAD = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
1998 Sep 08
27
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
13 AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD
.
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
fCLK1
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
clock frequency at multiplex rates of
1 : 8, 1 : 16 and 1 : 32
ROSC = 330 kΩ; VDD = 6 V
1.2
2.1
3.3
kHz
fCLK2
clock frequency at multiplex rates of
1 : 24
ROSC = 330 kΩ; VDD = 6 V
0.9
1.6
2.5
kHz
tPSYNC
tPLCD
SYNC propagation delay
driver delays
−
−
−
−
500
100
ns
VDD − VLCD = 9 V;
µs
with test loads
I2C-bus
fSCL
SCL clock frequency
tolerable spike width on bus
bus free time
−
−
100
100
−
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
tSW
−
−
tBUF
4.7
4.7
4.0
4.7
4.0
−
−
tSU;STA
tHD;STA
tLOW
tHIGH
tr
start condition set-up time
start condition hold time
SCL LOW time
repeated start codes only
−
−
4.0
−
−
−
SCL HIGH time
−
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
−
1
tf
−
−
0.3
−
tSU;DAT
tHD;DAT
tSU;STO
250
0
−
data hold time
−
−
stop condition set-up time
4.0
−
−
3.3 kΩ
1.5 kΩ
SYNC, CLK
0.5 V
SDA
V
DD
DD
1 nF
C39 to C32,
R31/C31 to R8/C8
and R7 to R0
MSA829
Fig.19 AC test loads.
28
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
1/ f
CLK
0.7 V
DD
DD
CLK
0.3 V
0.7 V
0.3 V
DD
DD
SYNC
t
t
PSYNC
PSYNC
0.5 V
C39 to C32,
R31/C31 to R8/C8
and R7 to R0
(V
V
= 9 V)
DD
LCD
t
0.5 V
PLCD
MSA834
Fig.20 Driver timing waveforms.
SDA
SCL
SDA
t
t
t
f
BUF
LOW
t
t
t
t
HD;STA
r
t
HIGH
HD;DAT
SU;DAT
t
SU;STA
MGA728
t
SU;STO
Fig.21 I2C-bus timing waveforms.
29
1998 Sep 08
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LCD DISPLAY
R0 R1 R2 R3 R4 R5 R6 R7
R8/ R9/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R18/ R19/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/
C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27
PCF8578
V
R31/ R30/ R29/ R28/
C31 C30 C29 C28
SA0
SS
V
V
5
V
V
2
V
V
OSC DD
LCD
C39 C38 C37 C36 C35 C34 C33
SDA SCLSYNC
3
4
n.c. n.c.
C32
CLK
TEST
R
OSC
MSA844
Fig.22 Stand-alone application using 8 rows and 32 columns.
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PCF8578: Segment Driver
a
Application
R0
f
b
g
one line of 24 digits 7 segment
one line of 12 digits star-burst
(mux 1:16)
e
c
R7
R8
d
dp
LCD
Total: 384 segments
R15
12
1
(Using 1:16 mux, the first
character data must be
loaded in bank 0 and 1
starting at byte number 16)
C16
C17
C39
LSB
a
b
f
g
c
16 17
39
0
Bank
0
e
d
dp
1
MSB
DISPLAY
RAM
PCF8578
(1)
ALTERNATE DISPLAY BANK
ALTERNATE DISPLAY BANK
2
3
MLB423
1-byte
(1) Can be used for creating blinking characters.
Fig.23 Segment driver application for up to 384 segments.
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V
DD
V
DD
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
32
R
C
C
C
C
C
LCD DISPLAY
subaddress 0
V
2
rows
R
(4
R
R
V
3
8
2
3)R
40
columns
40
columns
40
columns
PCF8578
(ROW MODE)
V
unused columns
4
subaddress 1
subaddress k 1
V
5
V
DD
V
V
V
V
V
A0
A1
A2
A3
A0
A1
A2
A3
A0
SA0
V
R
DD
DD
DD
DD
DD
SS
V
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
OSC
V
V
V
V
4
4
4
V
V
CLK SYNC
SYNC CLK
SYNC CLK
SYNC CLK
V
SDA SCL
SS
SCL SDA SA0
SS
SCL SDA SA0
SS
SCL SDA SA0
V
SS
OSC
SS
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA845
Fig.24 Typical LCD driver system with 1 : 32 multiplex rate.
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V
V
V
DD
V
V
V
V
V
V
DD
SS
DD
SS
SS
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
CLK
k
CLK
2
CLK
1
SS
SS
SS
V
3
V
3
V
3
A2
A2
A2
V
4
V
4
V
4
PCF8579
PCF8579
PCF8579
A1
A0
V
A1
A0
V
A1
A0
V
LCD
LCD
LCD
V
V
V
V
V
V
DD
DD
DD
DD
DD
subaddress 0
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
V
DD
R
16
1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)
V
V
V
LCD DISPLAY
DD
rows
C
C
C
C
C
2
16
1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)
R
R
R
R
rows
3
8
40
columns
40
columns
40
columns
PCF8578
(ROW MODE)
V
4
subaddress 0
subaddress 1
V
subaddress k 1
unused columns
V
5
V
DD
V
A0
A1
A2
V
V
A0
A1
A2
A3
V
A0
SA0
DD
DD
DD
DD
DD
V
V
/
SS DD
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
V
OSC
V
V
A3
V
V
4
4
4
R
V
V
SCL CLK SYNC
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
V
SDA
SS
SDA SA0
SS
SDA SA0
V
SS
SDA SA0
V
SS
OSC
SS
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA847
Fig.25 Split screen application with 1 : 16 multiplex rate for improved contrast.
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V
V
V
DD
V
V
V
V
V
V
DD
SS
DD
SS
SS
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
CLK
k
CLK
2
CLK
1
SS
SS
SS
V
3
V
3
V
3
A2
A2
A2
V
4
V
4
V
4
PCF8579
PCF8579
PCF8579
A1
A0
V
A1
A0
V
A1
A0
V
LCD
LCD
LCD
V
V
V
V
V
V
DD
DD
DD
DD
DD
subaddress 0
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
V
DD
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
V
V
V
LCD DISPLAY
DD
R
R
C
C
C
C
C
32
2
32
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
(4
2 3)R
rows
3
8
40
40
columns
40
columns
PCF8578
(ROW MODE)
V
4
columns
subaddress 0
subaddress 1
V
subaddress k 1
unused columns
R
R
V
5
V
DD
V
A0
A1
A2
V
V
A0
A1
A2
A3
V
A0
SA0
DD
DD
DD
DD
DD
V
V
/
SS DD
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
V
OSC
V
V
A3
V
V
4
4
4
R
V
V
SCL CLK SYNC
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
V
SDA
SS
SDA SA0
SS
SDA SA0
V
SS
SDA SA0
V
SS
OSC
SS
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA846
Fig.26 Split screen application with 1 : 32 multiplex rate.
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V
SS
V
SCL
SDA
DD
V
LCD
R0
R
R
OSC
R
(4
2 3)R
R
R
n.c.
n.c.
LCD DISPLAY
PCF8578
R31/C31
C0
C27
C28
C39
C0
C27
C28
C39
PCF8579
PCF8579
to other
PCF8579s
MSA852
Fig.27 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
y
7
8
6
5
4
3
2
1
54 53 52 51 50
49
R5
OSC
48
47
46
R6
R7
R8/C8
R9/C9
V
9
DD
45
V
2
10
11
V
3
R10/C10
R11/C11
44
43
V
4
12
13
V
5
42
41
R12/C12
R13/C13
4.88
mm
V
LCD
14
0
x
0
R14/C14
40
39
38
R15/C15
R16/C16
R17/C17
R18/C18
R19/C19
R20/C20
37
36
35
34
C39
C38
C37
C36
15
16
17
18
19
PCF8578
R21/C21
R22/C22
33
32
C35
20
21
22
23
24 25 26
27 28 29 30 31
MBH589
3.06 mm
Chip area: 14.93 mm2.
Bonding pad dimensions: 120 µm × 120 µm.
The numbers given in the small squares refer to the pad numbers.
Fig.28 Bonding pad locations.
36
1998 Sep 08
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Table 15 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip, see Fig.28.
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
1
2
SDA
SCL
174
−30
2241
2241
1
2
7
8
3
SYNC
CLK
−234
2241
3
9
4
−468
2241
4
10
11
12
13
16
20
21
22
23
24
25
29
30
31
32
33
34
35
37
38
39
40
41
42
43
44
45
46
48
49
50
51
52
53
5
VSS
−726
2241
5
6
TEST
SA0
−1014
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1308
−1014
−726
2241
6
7
2241
7
8
OSC
1917
8
9
VDD
1113
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
V2
873
10
11
12
13
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
V3
663
V4
459
V5
255
VLCD
51
C39
−1149
−1353
−1557
−1773
−1995
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−2241
−1977
−1731
−1515
−1305
−1101
−897
C38
C37
C36
C35
C34
C33
C32
R31/C31
R30/C30
R29/C29
R28/C28
R27/C27
R26/C26
R25/C25
R24/C24
R23/C23
R22/C22
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
−468
−234
−30
174
468
672
876
1080
1308
1308
1308
1308
1308
1308
1308
1998 Sep 08
37
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
−
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R7
1308
1308
1308
1308
1308
1308
1308
1308
1308
1308
1308
1308
1308
1080
876
−693
−489
−285
−81
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
54
55
56
57
58
59
60
61
62
63
64
1
123
351
603
1101
1305
1515
1731
1977
2241
2241
2241
2241
2241
−
R6
R5
R4
2
R3
3
R2
4
R1
672
5
R0
468
6
n.c.
−
15, 16
14, 15, 17 to 19,
26 to 28, 36, 47
1998 Sep 08
38
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V
V
DD
DD
V
3
V
4
V
LCD
V
SS
CLK
SYNC
SCL
SDA
V
3
V
4
V
LCD
V
SS
CLK
SYNC
SCL
SDA
PCF8578
PCF8579
R0 to R31
C0 C1 C2
LCD
DISPLAY
MSA850
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled to VDD
.
Fig.29 Typical chip-on glass application (viewed from the underside of the chip).
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
17 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v
M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.008 0.004 0.004
0.0295
0.089
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-04-02
97-08-11
SOT190-1
1998 Sep 08
40
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-01
SOT314-2
1998 Sep 08
41
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
If wave soldering cannot be avoided, for LQFP
18 SOLDERING
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
18.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
18.3.2 VSO
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
18.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
VSO packages.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• The package footprint must incorporate solder thieves at
the downstream end.
18.3.3 METHOD (LQFP AND VSO)
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
18.3 Wave soldering
18.3.1 LQFP
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
18.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Sep 08
42
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Sep 08
43
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/750/04/pp44
Date of release: 1998 Sep 08
Document order number: 9397 750 04312
Philips Semiconductors: Product information on PCF8578, LCD row/column driver for dot matrix graphic displays
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PCF8578; LCD row/column driver for dot matrix graphic displays
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Description
Relevant Links
The PCF8578 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays
at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has 40 outputs, of which 24 are
programmable, configurable as 32/8, 24/16, 16/24 or 8/32 rows/columns. The PCF8578 can function as a
stand-alone LCD controller/driver for use in small systems, or for larger systems can be used in
conjunction with up to 32 PCF8579s for which it has been optimized. Together these two devices form a
general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The
PCF8578 is compatible with most microcontrollers and communicates via a two-line bidirectional bus
(I2PC-bus). Communication overheads are minimized by a display RAM with auto-incremented addressing
and display bank switching.
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PCF8578
PCF8578
Features
● Single chip LCD controller/driver
● Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible)
● 40 driver outputsconfigurable as 32/8, 24/16, 16/24 or 8/32 rows/columns
● Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
● Externally selectable bias configuration, 5 or 6 levels
● 1280-bit RAM for display data storage and scratch pad
● Display memory bank switching
● Auto-incremented data loading across hardware subaddress boundaries (with PCF8579)
● Provides display synchronization for PCF8579
● On-chip oscillator, requires only 1 external resistor
● Power-on reset blanks display
● Logic voltage supply range 2.5 to 6 V
● Maximum LCD supply voltage 9 V
● Low power consumption
● I2PC-bus interface
● TTL/CMOS compatible
● Compatible with most microcontrollers
● Optimized pinning for single plane wiring in multiple device applications (with PCF8579)
● Space saving 56-lead plastic mini-pack and 64 pin quad flat pack
● Compatible with chip-on-glass technology.
Applications
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Philips Semiconductors: Product information on PCF8578, LCD row/column driver for dot matrix graphic displays
● Automotive information systems
● Telecommunication systems
● Point-of-sale terminals
● Computer terminals
● Instrumentation.
Datasheet
File
size
(kB)
Publication
release date
Page
count
Type nr. Title
Datasheet status
Datasheet
PCF8578 LCD row/column driver 08-Sep-98
for dot matrix graphic
Product
Specification
44
248
Download
displays
Products, packages, availability and ordering
North
American
Partnumber
marking/packing
Order code
(12nc)
Partnumber
package
device status
buy online
Discretes
packing info
Standard
Marking * Tray
PCF8578H/F1 PCF8578HBD 9352 005 40557 Dry Pack,
SOT314-2
(LQFP64)
order this
Full production
-
Bakeable,
Multiple
Standard
9339 646 20112 Marking * Bulk
Pack
SOT190-1
(VSO56)
order this
-
PCF8578T
PCF8578TD
Full production
Full production
Standard
SOT190-1
(VSO56)
-
PCF8578TD-T 9339 646 20118 Marking * Reel
Pack, SMD, 13"
No Marking *
Chips on Wafer,
Pre-Sawn, On
PCF8578U/10
9350 140 90005
-
Full production
-
FFC
No Marking *
Chips on Wafer,
Pre-Sawn, On
FFC
PCF8578U/12
9350 642 00005
-
-
Full production
Full production
-
-
No Marking *
9352 623 42026 Die In Waffle
Carriers
PCF8578U/2/F1
Products in the above table are all in production. Some variants are discontinued; click here for information
on these variants.
Find similar products:
PCF8578 links to the similar products page containing an overview of products that are similar in
function or related to the part number(s) as listed on this page. The similar products page includes
products from the same catalog tree(s) , relevant selection guides and products from the same functional
category.
Copyright © 2001
Royal Philips Electronics
All rights reserved.
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