935014990118 [NXP]
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20;
| 型号： | 935014990118 |
| 厂家： | 
NXP |
| 描述： | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT374
Octal D-type flip-flop; positive
edge-trigger; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive
edge-trigger; 3-state
74HC/HCT374
The 74HC/HCT374 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
FEATURES
• 3-state non-inverting outputs for bus oriented
applications
• 8-bit positive, edge-triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
• ICC category: MSI
GENERAL DESCRIPTION
The “374” is functionally identical to the “534”, but has
non-inverting outputs.
The 74HC/HCT374 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
PARAMETER
CONDITIONS
UNIT
ns
HC
15
HCT
13
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
fmax
CI
77
3.5
17
48
3.5
17
MHz
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
3-state flip-flop outputs
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
CP
3, 4, 7, 8, 13, 14, 17, 18
data inputs
10
11
20
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODES
INTERNAL
FLIP-FLOPS
OE CP Dn
Q0 to Q7
load and read
register
L
L
↑
↑
l
h
L
H
L
H
load register and
disable outputs
H
H
↑
↑
l
h
L
H
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP
transition
Z = high impedance OFF-state
↑ = LOW-to-HIGH CP transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
50
18
14
165
33
28
205
41
35
250
50
43
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
PZH/ tPZL 3-state output enable time
OE to Qn
41
15
12
150
30
26
190
38
33
225
45
38
2.0 Fig.7
4.5
6.0
PHZ/ tPLZ 3-state output disable time
OE to Qn
50
18
14
150
30
26
190
38
33
225
45
38
2.0 Fig.7
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.6
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
19
7
6
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
tsu
set-up time
Dn to CP
60
12
10
14
5
4
75
15
13
90
18
15
2.0 Fig.8
4.5
6.0
th
hold time
Dn to CP
5
5
5
−6
−2
−2
5
5
5
5
5
5
2.0 Fig.8
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
23
70
83
4.8
24
28
4.0
20
24
MHz 2.0 Fig.6
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
OE
CP
Dn
1.25
0.90
0.35
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
16
16
18
5
32
30
28
12
40
38
35
15
48
45
42
18
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.6
4.5 Fig.6
4.5 Fig.8
4.5 Fig.8
tPZH/ tPZL 3-state output enable time
OE to Qn
t
PHZ/ tPLZ 3-state output disable time
OE to Qn
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
19
12
5
11
7
24
15
5
29
18
5
tsu
th
set-up time
Dn to CP
hold time
Dn to CP
−3
44
fmax
maximum clock pulse
frequency
26
21
17
MHz 4.5 Fig.6
December 1990
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the data set-up and hold times for Dn input.
December 1990
7
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT374
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
8
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