935020600602 [NXP]
IC PHASE LOCKED LOOP, 50 MHz, PDIP16, PLASTIC, SOT-38, DIP-16, PLL or Frequency Synthesis Circuit;
| 型号： | 935020600602 |
| 厂家： | 
NXP |
| 描述： | IC PHASE LOCKED LOOP, 50 MHz, PDIP16, PLASTIC, SOT-38, DIP-16, PLL or Frequency Synthesis Circuit 光电二极管 |
| 文件： | 总9页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
DESCRIPTION
PIN CONFIGURATIONS
The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor.
D, N Packages
1
2
3
4
5
6
7
8
16
V+
TTL OUTPUT
LOOP GAIN CONTROL
15
14
HYSTERESIS SET
FEATURES
• Operation with single 5V supply
INPUT TO PHASE COMP
FROM VCO
ANALOG OUT
13 FREQ. SET CAP
LOOP FILTER
LOOP FILTER
• TTL-compatible inputs and outputs
• Guaranteed operation to 50MHz
• External loop gain control
12
11
10
9
FREQ. SET CAP
VCO OUT 2
FM/RF INPUT
• Reduced carrier feedthrough
BIAS FILTER
GND
V+
VCO OUT TTL
• No elaborate filtering needed in FSK applications
• Can be used as a modulator
TOP VIEW
• Variable loop gain (externally controlled)
SR01025
Figure 1. Pin Configuration
• Signal generators
APPLICATIONS
• High speed modems
• FSK receivers and transmitters
• Frequency Synthesizers
• Various satcom/TV systems
• pin configuration
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
NE564D
DWG #
SOT109-1
SOT38-4
SOT38-4
16-Pin Plastic Small Outline (SO) Package
16-Pin Plastic Dual In-Line Package (DIP)
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70°C
NE564N
-55 to +125°C
SE564N
BLOCK DIAGRAM
V
+
14
4
5
1
PHASE
COMPARATOR
2
LIMITER
7
6
DC
RETRIEVER
3
AMPLIFIER
SCHMITT
TRIGGER
11
16
9
POST DETECTION
PROCESSOR
VCO
15
10
8
12
13
SR01026
Figure 2. Block Diagram
1
1994 Aug 31
853-0908 13720
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V+
Supply voltage
Pin 1
14
6
V
V
Pin 10
I
Sink Max (Pin 9) and sourcing (Pin 11)
Bias current adjust pin (sinking)
Power dissipation
11
1
mA
mA
mW
OUT
I
BIAS
P
D
600
Operating ambient temperature
NE
°C
°C
°C
T
0 to +70
A
SE
-55 to +125
-65 to +150
T
Storage temperature range
STG
NOTE:
Operation above 5V will require heatsinking of the case.
DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= 5V; T = 0 to 25°C; f = 5MHz, I = 400µA; unless otherwise specified.
A
O
2
LIMITS
SE564
TYP
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NE564
TYP
60
UNITS
MAX
MIN
MAX
MIN
Maximum VCO frequency
Lock range
C = 0 (stray)
1
50
65
45
MHz
Input > 200mV
RMS
°
T = 25 C
40
20
50
70
30
80
40
70
A
°
T = 125 C
A
% of f
°
O
T = -55 C
A
o
T = 0 C
70
40
A
°
T = 70 C
A
Capture range
Input > 200mV
, R = 27Ω
20
30
20
30
% of f
O
RMS
2
f
= 5MHz,
O
°
°
T = -55 C to +125 C
T = 0 to +70 C
= 0 to +70 C
f
T = -55 C to +125 C
T = 0 to +70 C
500
1500
800
A
A
°
VCO frequency drift with
temperature
°
o
600
500
PPM/ C
= 5MHz,
300
O
°
°
A
A
°
C = 91pF
= 100Ω “Internal”
1
VCO free-running frequency
4
5
3
6
8
3.5
5
3
6.5
8
MHz
R
C
VCO frequency change with
supply voltage
V
= 4.5V to 5.5V
% of f
CC
O
Modulation frequency: 1kHz
f
= 5MHz, input deviation:
O
°
2%T = 25 C
16
8
28
14
mV
mV
mV
mV
mV
mV
RMS
RMS
RMS
RMS
RMS
RMS
28
14
13
°
1%T = 25 C
Demodulated output voltage
°
1%T = 0 C
16
8
°
1%T = -55 C
6
10
°
1%T = 70 C
15
°
1%T = 125 C
12
16
1
Distortion
Deviation: 1% to 8%
1
%
S/N
Signal-to-noise ratio
AM rejection
Std. condition, 1% to 10% dev.
Std. condition, 30% AM
40
35
40
35
dB
dB
Modulation frequency: 1kHz
f
= 5MHz, input deviation: 1%
Demodulated output at oper-
ating voltage
mV
mV
O
RMS
RMS
V
CC
V
CC
= 4.5V
= 5.5V
7
8
12
14
7
8
12
14
I
Supply current
V
CC
= 5V I , I
10
45
60
45
60
mA
CC
1
Output
“1” output leakage current
“0” output voltage
V
= 5V, Pins 16, 9
= 2mA, Pins 16, 9
= 6mA, Pins 16, 9
1
0.3
0.4
20
0.6
0.8
1
0.3
0.4
20
0.6
0.8
µA
V
V
OUT
I
OUT
OUT
I
2
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS
Lock Range vs Signal Input
1000
8
6
I
= 40
A
µ
0
PIN
VCO Capacitor vs Frequency
2
6
5
4
3
10
10
10
10
4
2
I
= 0µA
PIN
2
100
8
2
10
6
10
1
4
V
5V
2
3
4
5
10
CC
= 5MHz
.1
1
10
10
10
10
2
f
o
FREQUENCY kHz
10
0.7
0.8
0.9
1.0
1.1
1.2
1.3
NORMALIZED LOCK RANGE
Typical Noirmalized VCO
Frequency as a Function of
Temperature
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
1.10
VCO FREQUENCY: 50MHz
1.05
1.00
0.95
1.10
FREQUENCY: 50MHz
1.01
BIAS CURRENT: — 200µA
FREQUENCY: 5MHz
1.00
0.99
1.05
1.00
0.98
0.95
0.90
FREQUENCY: 500MHz
BIAS CURRENT: — 200µA
0.97
0.96
0.90
–600µA –400
–200
0
+200
–50 –25
25
0
25
50
75 100 125
–600µA –400 –200
0
+200 +400
o
BIAS CURENT (µA), PIN 2
BIAS CURENT (µA), PIN 2
TEMPERATURE (IN C)
SR01027
Figure 3. Typical Performance Characteristics
3
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
V
– PHASE COMPARATOR’S
D
OUTPUT VOLTAGE IN mV
800
VCO FREQUENCY
IN MHz
I
= 200µA
= 0µA
BIAS
600
400
200
I
= 400µA
BIAS
I
1.6
1.4
1.2
I
µ
BIAS = 800 A
BIAS
I
= 800µA
BIAS
I
µ
BIAS = 00 A
f
= 1.0MHz
o
0
–400
–200
200
400
600
800
40
60
100
120
140
160
V
IN mV
D
0 – PHASE
ERROR IN
DEGREES
.8
.6
–200
–400
–600
–800
Variation of the Comparator’s Output Voltage
vs Phase Error and Bias Current (K )
VCO Output Frequency as a Function of
Input Voltage and Bias Current (K )
D
O
SR01028
Figure 4. Typical Performance Characteristics (cont.)
TEST CIRCUIT
+5V
R3
1K
R1
VCO
15
pF
OUYPUT
390
C3
INPUT
9
1
10
16
2
6
7
3
DEMODULATED
OUTPUT
0.1µF
1K
14
13
0.1µF
564
8
R2
C2
C2
4
430pF
C1
R2
5
12
430pF
SR01029
Figure 5. Test Circuit
4
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
FUNCTIONAL DESCRIPTION
Phase Comparator Section
The phase detection processor consists of a doubled-balanced
modulator with a limiter amplifier to improve AM rejection.
Schottky-clamped vertical PNPs are used to obtain TTL level inputs.
(Figure 6)
The NE564 is a monolithic phase-locked loop with a post detection
processor. The use of Schottky clamped transistors and optimized
device geometries extends the frequency of operation to greater
than 50MHz.
The loop gain can be varied by changing the current in Q and Q
which effectively changes the gain of the differential amplifiers. This
can be accomplished by introducing a current at Pin 2.
4
15
In addition to the classical PLL applications, the NE564 can be used
as a modulator with a controllable frequency deviation.
Post Detection Processor Section
The post detection processor consists of a unity gain
transconductance amplifier and comparator. The amplifier can be
used as a DC retriever for demodulation of FSK signals, and as a
post detection filter for linear FM demodulation. The comparator has
adjustable hysteresis so that phase jitter in the output signal can be
eliminated.
The output of the PLL can be written as shown in the following
equation:
(f - f )
IN
O
(1)
V
O
=
K
VCO
K
VCO
= conversion gain of the VCO
As shown in the equivalent schematic, the DC retriever is formed by
the transconductance amplifier Q - Q together with an external
42
43
f
f
= frequency of the input signal
IN
O
capacitor which is connected at the amplifier output (Pin 14). This
forms an integrator whose output voltage is shown in the following
equation:
= free-running frequency of the VCO
The process of recovering FSK signals involves the conversion of
the PLL output into logic compatible signals. For high data rates, a
considerable amount of carrier will be present at the output of the
PLL due to the wideband nature of the loop filter. To avoid the use
of complicated filters, a comparator with hysteresis or Schmitt trigger
is required. With the conversion gain of the VCO fixed, the output
voltage as given by Equation 1 varies according to the frequency
deviation of f from f . Since this differs from system to system, it
g
C
M
(3)
V
O
=
V dt
IN
2
g
M
= transconductance of the amplifier
C = capacitor at the output (Pin 14)
2
V
IN
= signal voltage at amplifier input
IN
O
is necessary that the hysteresis of the Schmitt trigger be capable of
being changed, so that it can be optimized for a particular system.
This is accomplished in the 564 by varying the voltage at Pin 15
which results in a change of the hysteresis of the Schmitt trigger.
With proper selection of C , the integrator time constant can be
2
varied so that the output voltage is the DC or average value of the
input signal for use in FSK, or as a post detection filter in linear
demodulation.
For FSK signals, an important factor to be considered is the drift in
the free-running frequency of the VCO itself. If this changes due to
temperature, according to Equation 1 it will lead to a change in the
DC levels of the PLL output, and consequently to errors in the digital
output signal. This is especially true for narrowband signals where
The comparator with hysteresis is made up of Q - Q with
49
50
positive feedback being provided by Q - Q . The hysteresis is
47
48
varied by changing the current in Q with a resulting variation in the
52
loop gain of the comparator. This method of hysteresis control,
which is a DC control, provides symmetric variation around the
nominal value.
the deviation in f itself may be less than the change in f due to
IN
O
temperature. This effect can be eliminated if the DC or average
value of the signal is retrieved and used as the reference to the
comparator. In this manner, variations in the DC levels of the PLL
output do not affect the FSK output.
Design Formula
The free-running frequency of the VCO is shown by the following
equation:
1
VCO Section
(4)
f
O
22 R (C + C )
Due to its inherent high-frequency performance, an emitter-coupled
oscillator is used in the VCO. In the circuit, shown in the equivalent
schematic, transistors Q21 and Q23 with current sources Q25 - Q26
form the basic oscillator. The approximate free-running frequency of
the oscillator is shown in the following equation:
C
1
S
R
= 100Ω
C
C = external cap in farads
1
C
= stray capacitance
S
1
(2)
f
O
The loop filter diagram shown is explained by the following equation:
1
22 R (C + C )
C
1
S
(5)
f
S
=
(First Order)
R
= R = R = 100Ω (INTERNAL)
19 20
C
1 + sRC
3
C = external frequency setting capacitor
1
R = R = R = 1.3kΩ (Internal)*
12
13
C
= stray capacitance
S
By adding capacitors to Pins 4 and 5, a pole is added to the loop
transfer at
Variation of V (phase detector output voltage) changes the
D
frequency of the oscillator. As indicated by Equation 2, the
frequency of the oscillator has a negative temperature coefficient
due to the monolithic resistor. To compensate for this, a current I
1
RC
NOTE:
*Refer to Figure 6.
ω =
3
R
with negative temperature coefficient is introduced to achieve a low
frequency drift with temperature.
5
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
EQUIVALENT SCHEMATIC
PHASE
COMPARATOR
7
5
1
LIMITER
D1
D2
Q7
Q10
Q11
Q9
Q12
1
DC RETRIEVER
14
SCHMITT TRIGGER
15
QR
Q2 Q3
Q16
6
R7 R8
1k 1k
Q13
Q14
Q1
3
2
Q5
Q6
Q41
Q47
D3
Q40
Q48
Q15
Q4
D5
D4
D10
D11
16
8
R27
10k
Q50
Q49
Q42
10
Q41
R26
10k
R29
10k
Q20
Q17
Q42
Q35
R48
10k
Q44
Q14
Q24
Q15
Q22
D12
D11
Q23
R35
11
Q30
Q45
Q58
Q46
Q22
Q21
9
Q29
R36
100
Q32
Q31
100
Q37
Q31
Q27
Q26
D7
D6
Q34
Q25
Q36
Q33
Q39
Q28
D9
D8
AMPLIFIER
VCO
12
13
SR01030
Figure 6. Equivalent Schematic
LOCK RANGE ADJUSTMENT
I
2
0.01µF
LOOP FILTER
0.01µF
16
2
11
4
0.47µF
.01µF
FM INPUT
6
7
5
15
14
f
= 5MHz
O
M
1k
ANALOG OUT
1kHz
f
= 1kHz
564
BIAS FILTER
3
1
POST DETECTION FILTER
0.1µF
13
8
10
9
12
80pF
f
= 5MHz
O
FREQUENCY SET CAP
1k
5V
5V
SR01031
Figure 7. FM Demodulator at 5V
6
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
APPLICATIONS
5V
FINE FREQUENCY
ADJUSTMENT
I
FM Demodulator
2
The NE564 can be used as an FM demodulator. The connections
for operation at 5V and 12V are shown in Figures 7 and 8,
respectively. The input signal is AC coupled with the output signal
being extracted at Pin 14. Loop filtering is provided by the
capacitors at Pins 4 and 5 with additional filtering being provided by
the capacitor at Pin 14. Since the conversion gain of the VCO is not
very high, to obtain sufficient demodulated output signal the
frequency deviation in the input signal should be 1% or higher.
2k
MODULATING
INPUT
1kHz
16
2
11
4
0.47µF
1kHz
6
7
5
15
14
1k
564
.01µF
3
1
Modulation Techniques
13
The NE564 phase-locked loop can be modulated at either the loop
filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure
9. The approximate modulation frequency can be determined from
the frequency conversion gain curve shown in Figure 10. This curve
will be appropriate for signals injected into Pins 4 and 5 as shown in
Figure 9.
8
10
9
12
80pF
f
= 5MHz
O
FREQUENCY SET CAP
5V
1k
MODULATED OUTPUT
(TTL)
5V
I
2
LOCK RANGE ADJUSTMENT
0.01µF
SR01033
Figure 9. Modulator
The lock range graph indicates that the +1.0MHz frequency
deviations will be within the lock range for input signal levels greater
than approximately 50mV with zero Pin 2 bias current. (While
strictly this figure is appropriate only for 50MHz, it can be used as a
LOOP FILTER
0.01µF
16
2
11
4
0.47µF
.01µF
FM INPUT
f
= 5MHz
6
7
5
O
M
1k
f
= 1kHz
ANALOG OUT
1kHz
guide for lock range estimates at other f ’ frequencies).
15
14
O
564
BIAS
FILTER
POST
DETECTION
FILTER
The hysteresis was adjusted experimentally via the 10kΩ
potentiometer and 2kΩ bias arrangement to give the waveshape
shown in Figure 12 for 20k, 500k, 2M baud rates with square wave
FSK modulation. Note the magnitude and phase relationships of the
phase comparators’ output voltages with respect to each other and
to the FSK output. The high-frequency sum components of the input
and VCO frequency also are viable as noise on the phase
comparator’s outputs.
3
1
0.1µF
13
8
10
9
12
80pF
f
= 5MHz
O
.01µF
FREQUENCY SET CAP
200
1k
OUTLINE OF SETUP PROCEDURE
12V
SR01032
1. Determine operating frequency of the VCO: IF÷ N in feedback
Figure 8. FM Demodulator at 12V
loop, then
FSK Demodulation
f = N x f .
O IN
The 564 PLL is particularly attractive for FSK demodulation since it
contains an internal voltage comparator and VCO which have TTL
compatible inputs and outputs, and it can operate from a single 5V
power supply. Demodulated DC voltages associated with the mark
and space frequencies are recovered with a single external
capacitor in a DC retriever without utilizing extensive filtering
networks. An internal comparator, acting as a Schmitt trigger with
an adjustable hysteresis, shapes the demodulated voltages into
compatible TTL output levels. The high-frequency design of the 564
enables it to demodulate FSK at high data rates in excess of 1.0M
baud.
2. Calculate value of the VCO frequency set capacitor:
1
C
O
2200 f
O
3. Set I (current sinking into Pin 2) for 100µA. After operation is
2
obtained, this value may be adjusted for best dynamic behavior,
VCC * 1.3V
and replace with fixed resistor value of R =
.
2
IB2
4. Check VCO output frequency with digital counter at Pin 9 of
device (loop open, VCO to φ det.). Adjust C trim or frequency
O
adj. Pins 4 - 5 for exact center frequency, if needed.
Figure 10 shows a high-frequency FSK decoder designed for input
frequency deviations of +1.0MHz centered around a free-running
frequency of 10.8MHz. the value of the timing capacitance required
was estimated from Figure 8 to be approximately 40pF. A trimmer
5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6
with two-channel scope. Lock should occur with ∆φ
equal to
3 - 6
o
90 (phase error).
capacitor was added to fine tune f ’ 10.8MHz.
O
7
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
6. If pulsed burst or ramp frequency is used for input signal, special
loop filter design may be required in place of simple single
capacitor filter on Pins 4 and 5. (See PLL application section)
50% in duty cycle, DC offsets will occur in the loop which tend to
create an artificial or biased VCO.
8. For multiplier circuits where phase jitter is a problem, loop filter
capacitors may be increased to a value of 10 - 50µF on Pins 4,
5. Also, careful supply decoupling may be necessary. This
7. The input signal to Pin 6 and the VCO feedback signal to Pin 3
must have a duty cycle of 50% for proper operation of the phase
detector. Due to the nature of a balanced mixer if signals are not
includes the counter chain V lines.
CC
BIAS
ADJ
0.22µF 0.22µF
+5V
2k
10k
10k
1.2k
HYSTERESIS
ADJUST
FSK
OUTPUT
2k
1
10
15
16
2
6
0.1µF
0.1µF
FSK
INPUT
1k
14
7
10µF/8V
1k
NE564
3
9
510Ω
0–20pF
*NOTE:
12
+5V
Use R
only if rise time is critical.
9-11
*510Ω
33pF
11
13
8
300pF
4
5
300pF
SR01034
Figure 10. 10.8MHz FSK Decoder Using the 564
8
1994 Aug 31
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
SR01035
Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs
+5V
BIAS ADJUST
.47µF
10k
CER.
I
2
.47µF CER.
2k
.33µF
2
1
10
4
5
INPUT SIGNAL
510Ω
LOOP
FILTER
6
11
.33µF
*510Ω
NE564
f
1kΩ
.47µF
T
DET.
7
VCO
9
OUTPUT
VCO
3
8
12
13
Nxf
T
C
O
*NOTE:
Use R
only if rise time is critical.
9-11
f = Nxf
T
÷N
Figure 12. NE564 Phase-Locked Frequency Multiplier
9
1994 Aug 31
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明