935053560602 [NXP]
F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOL-20;
| 型号： | 935053560602 |
| 厂家： | 
NXP |
| 描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOL-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F273A
Octal D flip-flop
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
FEATURES
• High impedance inputs for reduced loading
(20µA in Low and High states)
• Ideal buffer for MOS microprocessor or memory
• Eight edge–triggered D–type flip–flops
• Buffered common clock
TYPICAL
TYPICAL SUPPLY CURRENT
(TOTAL)
TYPE
f
MAX
74F273A
170MHz
25mA
• Buffered asynchronous Master Reset
• See 74F377A for clock enable version
• See 74F373 for transparent latch version
• See 74F374 for 3–State version
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V±10%;
V
CC
PACKAGES
PKG. DWG. #
T
amb
= 0°C to +70°C
DESCRIPTION
20–pin plastic DIP
20–pin plastic SOL
74F273AN
SOT146-1
SOT163-1
The 74F273 has eight edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
74F273AD
The register is fully edge–triggered. The state of each D input, one
setup time before the Low–to–High clock transition, is transferred to
the corresponding flip–flop’s Q output.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
PINS
DESCRIPTION
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
D0 – D7
MR
Data inputs
1.0/0.033
1.0/0.033
1.0/0.033
50/33
Master Reset input (active–Low)
Clock pulse input (active rising edge)
Data outputs
CP
Q0 – Q7
PIN CONFIGURATION
LOGIC SYMBOL
20
V
CC
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
3
4
7
8
13 14 17 18
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
11
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
GND 10
11
CP
2
5
6
9
12 15 16 19
SF00346
V
= Pin 20
CC
GND = Pin 10
SF00347
2
1996 Mar 12
853–0066 16555
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
LOGIC SYMBOL (IEEE/IEC)
1
R
11
C1
3
4
2
5
1D
7
6
8
9
13
14
17
18
12
15
16
19
SF00348
LOGIC DIAGRAM
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
11
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
1
MR
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
V
= Pin 20
CC
Q0
Q1
Q2
Q3
GND = Pin 10
SF00349
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
MR
L
CP
X
Dn
Q0 – Q7
X
h
l
L
H
L
Reset (clear)
Load ”1”
H
↑
H
↑
Load ”0”
H
h
L
l
X
↑
=
=
=
=
=
=
High voltage level
High voltage level one set–up time prior to the Low–to–High clock transition
Low voltage level
Low voltage level one set–up time prior to the Low–to–High clock transition
Don’t care
Low–to–High clock transition
3
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
V
IN
V
I
IN
mA
V
I
Voltage applied to output in High output state
Current applied to output in Low output state
–0.5 to V
V
OUT
CC
40
mA
°C
°C
OUT
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
T
–65 to +150
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
TYP
MAX
V
Supply voltage
5.0
5.5
V
V
CC
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
IH
V
0.8
–18
–1
V
IL
I
mA
mA
mA
Ik
I
High–level output current
Low–level output current
OH
I
OL
20
T
amb
Operating free air temperature range
0
+70
°C
4
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN
2.5
2.7
2.5
2.7
TYP
MAX
3
MR & CP
inputs
V
V
V
V
V
V
V
V
V
V
= MIN, V = 0.0V ,
±10%V
V
V
CC
IL
CC
3
V
High-level output voltage
= 4.5V , I = MAX
±5%V
3.4
OH
IH
OH
CC
other
= MIN, V = MAX,
±10%V
V
CC
IL
CC
CC
CC
inputs
= MIN, I = MAX
±5%V
3.4
V
IH
OH
V
Low-level output voltage
Input clamp voltage
= MIN, V = MAX,
±10%V
0.30
0.30
0.50
0.50
-1.2
100
20
V
OL
CC
IL
= MIN, I = MAX
±5%V
CC
V
IH
OH
V
= MIN, I = I
IK
–0.73
V
IK
CC
CC
CC
CC
I
I
I
Input current at maximum input voltage
High–level input current
= 0.0V, V = 7.0V
µA
µA
µA
I
I
= MAX, V = 2.7V
I
IH
I
Low–level input current
= MAX, V = 0.5V
–20
IL
I
4
Short–circuit output current
I
I
V
CC
V
CC
= MAX
= MAX
-60
-150
mA
OS
CC
Supply current (total)
I
I
24
27
38
43
mA
mA
CCH
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. To reduce the effect of external noise during test.
4. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC CHARACTERISTICS FOR ’F273A
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ±10%
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
Min
Typ
Max
Min
Max
f
Maximum clock frequency
1
1
150
170
125
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
3.5
5.0
5.0
7.0
8.0
9.5
3.0
4.5
9.0
10.0
PLH
PHL
Propagation delay
MR to Qn
t
2
5.0
7.0
9.0
5.0
9.5
ns
PHL
5
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
AC SETUP REQUIREMENTS FOR ’F273A
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ±10%
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
C = 50pF
L
C = 50pF
L
R = 500Ω
L
R = 500Ω
L
Min
Typ
Max
Min
Max
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
3.0
2.0
2.5
2.5
s
3
3
t (H)
Hold time, High or Low
Dn to CP
0.5
0.0
2.5
1.0
h
ns
t (L)
h
t (H)
t (L)
w
Clock pulse width
High or Low
4.5
3.5
5.0
4.0
w
1
2
2
ns
ns
ns
t (L)
w
Master Reset pulse width, Low
3.0
4.0
3.5
5.0
Recovery time
MR to CP
t
REC
AC WAVEFORMS
1/f
max
CP
V
V
V
M
M
M
Dn
CP
V
V
t
V
V
M
M
M
M
t
(H)
w
t
t
w
(L)
t
PLH
PHL
t (H)
(H)
t (L)
t
(L)
s
h
s
h
V
V
M
M
Qn
V
V
M
M
SF00294
SF00191
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 3. Data Setup and Hold Times
NOTE: For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output
performance.
MR
CP
V
V
M
M
t
w
(L)
t
REC
V
M
t
PHL
Qn
V
M
SF00158
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
6
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
0V
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
amplitude
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
7
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip-flop
74F273A
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
8
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip-flop
74F273A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
9
1996 Mar 12
Philips Semiconductors
Product specification
Octal D flip-flop
74F273A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05113
Document order number:
Philips
Semiconductors
it Q
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74F273A; Octal D
flip-flop
download datasheet
Download datasheet
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General description
The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip–flops simultaneously.
Catalog by
System
•
The register is fully edge–triggered. The state of each D input, one setup time before the Low–to–High clock
transition, is transferred to the corresponding flip–flop’s Q output.
Cross-reference
Packages
•
•
End of Life
information
Distributors Go
Here!
•
•
All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR
input. The device is useful for applications where the true output only is required and the CP and MR are
common to all elements.
Models
•
•
SoC solutions
Features
●
●
●
●
●
●
●
●
High impedance inputs for reduced loading (20µA in Low and High states)
Ideal buffer for MOS microprocessor or memory
Eight edge–triggered D–type flip–flops
Buffered common clock
Buffered asynchronous Master Reset
See 74F377A for clock enable version
See 74F373 for transparent latch version
See 74F374 for 3–State version
Applications
AN202_1: Testing and specifying FAST logic (date 01-Jun-87)
AN2021_1: Thermal considerations for FAST logic products (date 13-Mar-95)
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
AN216_2: Arbitration in shared resource systems (date 18-Jul-88)
Datasheet
Type number Title
Publication release Datasheet status
date
Page
count
File
size
(kB)
Datasheet
74F273A
Octal D 3/12/1996
flip-flop
Product specification 10
89
Download
Blockdiagram(s)
Block diagram of
N74F273AD
Parametrics
Type
number
Package Description Propagation Voltage No. Power
Logic
Switching Drive
Pins Considerations Levels Capability
Output
Delay(ns)
of Dissipation
D-Type Flip-
Flop with
Reset;
Positive-
Edge
SOT163
(SO20)
5 Volts
+
N74F273AD
6~10
20 None
TTL
TTL
Low
Trigger
D-Type Flip-
Flop with
Reset;
Positive-
Edge
SOT146-
N74F273AN 1
(DIP20)
5 Volts
+
6~10
20 None
Low
Trigger
Products, packages, availability and ordering
Type
North
Ordering code Marking/Packing Package Device
Buy online
IC packing info
number
American
type number
(12NC)
status
Standard Marking
N74F273AD N74F273AD 9350 535 60602 * Tube
(Signetics)
SOT163
(SO20)
Full production
Standard Marking
* Reel Pack,
SMD, 13"
SOT163
(SO20)
N74F273AD-
T
Full production
9350 535 60623
(Signetics)
Standard Marking SOT146-
N74F273AN N74F273AN 9350 535 70602 * Tube
(Signetics)
1 (DIP20) Full production
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