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935056850623 [NXP]

ABT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14;
935056850623
型号： 935056850623
厂家： NXP    NXP
描述：

ABT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14

驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路
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74ABT125  
Quad buffer; 3-state  
Rev. 6 — 3 November 2011  
Product data sheet  
1. General description  
The 74ABT125 high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device  
features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state  
outputs.  
2. Features and benefits  
Quad bus interface  
3-state buffers  
Live insertion and extraction permitted  
Output capability: HIGH 32 mA; LOW +64 mA  
Power-up 3-state  
Inputs are disabled during 3-state mode  
Latch-up protection exceeds 500 mA per JESD78 class II level A  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
3. Ordering information  
Table 1.  
Type number Package  
Temperature range Name  
Ordering information  
Description  
Version  
74ABT125N  
74ABT125D  
40 C to +85 C  
40 C to +85 C  
DIP14  
SO14  
plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
SOT108-1  
plastic small outline package; 14 leads;  
body width 3.9 mm  
74ABT125DB 40 C to +85 C  
74ABT125PW 40 C to +85 C  
74ABT125BQ 40 C to +85 C  
SSOP14  
plastic shrink small outline package; 14 leads;  
body width 5.3 mm  
SOT337-1  
SOT402-1  
TSSOP14  
plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1  
thin quad flat package; no leads; 14 terminals;  
body 2.5 3 0.85 mm  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
4. Functional diagram  
1A  
1Y  
2Y  
3Y  
4Y  
3
6
2
2
1
3
6
1OE  
2A  
1
5
1
5
EN1  
nY  
nA  
4
9
2OE  
3A  
4
9
8
8
nOE  
10  
12  
13  
mna227  
3OE  
4A  
10  
12  
11  
11  
4OE  
13  
mna229  
mna228  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
Fig 3. Logic diagram (one buffer)  
5. Pinning information  
5.1 Pinning  
74ABT125  
terminal 1  
index area  
74ABT125  
1
2
3
4
5
6
7
14  
V
1OE  
1A  
CC  
2
3
4
5
6
13  
12  
11  
10  
9
1A  
4OE  
4A  
13  
12  
11  
10  
9
4OE  
4A  
1Y  
2OE  
2A  
1Y  
4Y  
2OE  
2A  
4Y  
(1)  
3OE  
3A  
3OE  
3A  
GND  
2Y  
2Y  
GND  
8
3Y  
001aai027  
001aai028  
Transparent top view  
(1) This is not a supply pin. The substrate is attached to this  
pad using conductive die attach material. There is no  
electrical or mechanical requirement to solder this pad.  
However, if it is soldered, the solder land should remain  
floating or be connected to GND.  
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14  
Fig 5. Pin configuration DHVQFN14  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
2 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
5.2 Pin description  
Table 2.  
Symbol  
1OE to 4OE  
1A to 4A  
1Y to 4Y  
GND  
Pin description  
Pin  
Description  
1, 4, 10, 13  
2, 5, 9, 12  
3, 6, 8, 11  
7
output enable input (active LOW)  
data input  
data output  
ground (0 V)  
VCC  
14  
supply voltage  
6. Functional description  
Table 3.  
Function selection[1]  
Inputs  
Output  
nOE  
L
nA  
L
nY  
L
L
H
H
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
7. Limiting values  
Table 4.  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Limiting values[1]  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
0.5  
1.2  
0.5  
18  
50  
-
Max  
+7.0  
+7.0  
+5.5  
-
Unit  
V
supply voltage  
input voltage  
V
VO  
output voltage  
output in OFF-state or HIGH-state  
VI < 0 V  
V
IIK  
input clamping current  
output clamping current  
output current  
mA  
mA  
mA  
C  
IOK  
IO  
VO < 0 V  
-
output in LOW-state  
128  
150  
+150  
500  
[2]  
[3]  
Tj  
junction temperature  
storage temperature  
total power dissipation  
-
Tstg  
Ptot  
65  
-
C  
Tamb = 40 C to +85 C  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability.  
[3] SO14 packages: above 70 C Ptot derate linearly with 8 mW/K  
SSOP14 and TSSOP20 packages: above 60 C Ptot derate linearly with 5.5 mW/K  
DHVQFN14 packages: above 60 C Ptot derate linearly with 4.5 mW/K  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
3 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
8. Recommended operating conditions  
Table 5.  
Operating conditions  
Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
4.5  
0
Max  
5.5  
VCC  
-
Unit  
V
supply voltage  
input voltage  
V
VIH  
HIGH-level input voltage  
LOW-level Input voltage  
HIGH-level output current  
LOW-level output current  
input transition rise and fall rate  
ambient temperature  
2.0  
-
V
VIL  
0.8  
-
V
IOH  
32  
-
mA  
mA  
ns/V  
C  
IOL  
64  
t/V  
Tamb  
-
10  
in free air  
40  
+85  
9. Static characteristics  
Table 6.  
Static characteristics  
Symbol Parameter  
Conditions  
25 C  
Min  
-
40 C to +85 C Unit  
Typ Max  
Min  
Max  
VIK  
input clamping voltage VCC = 4.5 V; IIK = 18 mA  
0.9 1.2  
-
1.2  
V
VOH  
HIGH-level output  
voltage  
VI = VIL or VIH  
VCC = 4.5 V; IOH = 3 mA  
VCC = 5.0 V; IOH = 3 mA  
2.5  
3.0  
2.0  
-
2.9  
3.4  
2.4  
-
-
-
2.5  
3.0  
2.0  
-
-
V
V
V
V
-
-
VCC = 4.5 V; IOH = 32 mA  
VOL  
LOW-level output  
voltage  
VCC = 4.5 V; IOL = 64 mA;  
VI = VIL or VIH  
0.35 0.55  
0.55  
II  
input leakage current VCC = 5.5 V; VI = GND or 5.5 V  
-
-
0.01 1.0  
5.0 100  
-
-
1.0 A  
100 A  
IOFF  
power-off leakage  
current  
VCC = 0.0 V; VI or VO 4.5 V  
[1]  
IO(pu/pd)  
IOZ  
power-up/power-down VCC = 2.1 V; VO = 0.5 V;  
-
5.0 50  
-
50  
A  
output current  
VI = GND or VCC; OE = don’t care  
OFF-state output  
current  
VCC = 5.5 V; VI = VIL or VIH  
VO = 2.7 V  
-
-
-
1.0  
1.0 50  
5.0 50  
50  
-
-
-
50  
50  
50  
A  
A  
A  
VO = 0.5 V  
ILO  
output leakage current HIGH-state; VO = 5.5 V;  
VCC = 5.5 V; VI = GND or VCC  
[2]  
IO  
output current  
supply current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
50 100 180  
50  
180 mA  
ICC  
-
-
-
65  
12  
65  
250  
15  
-
-
-
250  
30  
A  
mA  
A  
outputs LOW-state  
outputs disabled  
250  
50  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
4 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
Table 6.  
Static characteristics …continued  
Symbol Parameter  
Conditions  
25 C  
40 C to +85 C Unit  
Min  
Typ Max  
Min  
Max  
[3]  
ICC  
additional supply  
current  
per control pin; VCC = 5.5 V;  
one control input at 3.4 V, other  
inputs at VCC or GND  
outputs enabled  
outputs disabled  
-
-
-
0.5  
50  
1.5  
250  
1.5  
-
-
-
1.5  
250  
1.5  
mA  
mA  
mA  
one enable input at 3.4 V and other  
inputs at VCC or GND; outputs  
disabled  
0.5  
CI  
input capacitance  
output capacitance  
VI = 0 V or VCC  
-
-
4
7
-
-
-
-
-
-
pF  
pF  
CO  
outputs disabled; VO = 0 V or VCC  
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V 10 %,  
a transition time of up to 100 s is permitted.  
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
[3] This is the increase in supply current for each input at 3.4 V.  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
GND = 0 V. Test circuit is shown in Figure 8.  
Symbol Parameter  
Conditions  
25 C; VCC = 5.0 V 40 C to +85 C; Unit  
VCC = 5.0 V 0.5 V  
Min  
Typ Max  
Min  
Max  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
LOW to HIGH  
propagation delay  
nA to nY, see Figure 6  
nA to nY; see Figure 6  
1.0  
2.8  
3.1  
3.2  
4.2  
4.1  
2.8  
4.1  
4.6  
5.0  
6.2  
5.4  
5.0  
1.0  
4.6  
ns  
ns  
ns  
ns  
ns  
ns  
HIGH to LOW  
propagation delay  
1.0  
1.0  
1.0  
1.0  
1.5  
1.0  
1.0  
1.0  
1.0  
1.5  
4.9  
5.9  
6.8  
6.2  
5.5  
OFF-state to HIGH nOE to nY; see Figure 7  
propagation delay  
OFF-state to LOW nOE to nY; see Figure 7  
propagation delay  
HIGH to OFF-state nOE to nY; see Figure 7  
propagation delay  
LOW to OFF-state nOE to nY; see Figure 7  
propagation delay  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
5 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
11. Waveforms  
V
I
V
nA input  
M
GND  
t
t
PHL  
PLH  
V
OH  
V
nY output  
M
V
OL  
mna230  
VM = 1.5 V  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 6. Propagation delay input (nA) to output (nY)  
V
I
nOE input  
V
M
V
M
GND  
3.5 V  
t
t
PZL  
PLZ  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
+ 0.3 V  
OL  
V
V
OL  
t
t
PHZ  
PZH  
V
OH  
− 0.3 V  
OH  
output  
V
HIGH-to-OFF  
OFF-to-HIGH  
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
001aal294  
VM = 1.5 V  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 7. Enable and disable times  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
6 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
EXT  
V
V
M
M
V
CC  
10 %  
10 %  
0 V  
R
L
V
V
O
t
t
r
I
f
G
DUT  
t
t
f
r
V
I
R
T
C
L
R
L
90 %  
90 %  
positive  
pulse  
V
M
V
M
mna616  
10 %  
10 %  
0 V  
t
W
001aai298  
a. Input pulse definition  
b. Test circuit  
Test data is given in Table 8.  
Test circuit definitions:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
EXT = Test voltage for switching times.  
V
Fig 8. Load circuitry for switching times  
Table 8.  
Input  
VI  
Test data  
Load  
CL  
VEXT  
fI  
tW  
tr, tf  
RL  
tPHL, tPLH  
open  
tPZH, tPHZ  
tPZL, tPLZ  
7.0 V  
3.0 V  
1 MHz  
500 ns  
2.5 ns  
50 pF  
500   
open  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
7 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
12. Package outline  
DIP14: plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
D
M
E
A
2
A
A
1
L
c
e
w M  
Z
b
1
(e )  
1
b
M
H
14  
8
pin 1 index  
E
1
7
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
Z
A
A
A
2
(1)  
(1)  
1
UNIT  
mm  
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.  
min.  
max.  
max.  
1.73  
1.13  
0.53  
0.38  
0.36  
0.23  
19.50  
18.55  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.1  
7.62  
0.3  
0.254  
0.01  
2.2  
0.068  
0.044  
0.021  
0.015  
0.014  
0.009  
0.77  
0.73  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.02  
0.13  
0.087  
Note  
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-13  
SOT27-1  
050G04  
MO-001  
SC-501-14  
Fig 9. Package outline SOT27-1 (DIP14)  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
8 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
SO14: plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
7
e
detail X  
w
M
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
8.75  
8.55  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.75  
1.27  
0.05  
1.05  
0.25  
0.01  
0.25  
0.1  
0.25  
0.01  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.35  
0.014 0.0075 0.34  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches  
0.041  
0.01 0.004  
0.069  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT108-1  
076E06  
MS-012  
Fig 10. Package outline SOT108-1 (SO14)  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
9 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm  
SOT337-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
7
1
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.4  
0.9  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT337-1  
MO-150  
Fig 11. Package outline SOT337-1 (SSOP14)  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
10 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm  
SOT402-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
7
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.72  
0.38  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT402-1  
MO-153  
Fig 12. Package outline SOT402-1 (TSSOP14)  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
11 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;  
14 terminals; body 2.5 x 3 x 0.85 mm  
SOT762-1  
B
A
D
A
A
1
E
c
detail X  
terminal 1  
index area  
C
terminal 1  
index area  
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14  
13  
9
D
h
X
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.  
0.05 0.30  
0.00 0.18  
3.1  
2.9  
1.65  
1.35  
2.6  
2.4  
1.15  
0.85  
0.5  
0.3  
mm  
0.05  
0.1  
1
0.2  
0.5  
2
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-10-17  
03-01-27  
SOT762-1  
- - -  
MO-241  
- - -  
Fig 13. Package outline SOT762-1 (DHVQFN14)  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
12 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
13. Abbreviations  
Table 9.  
Acronym  
BiCMOS  
DUT  
Abbreviations  
Description  
BipolarCMOS  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
ESD  
HBM  
MM  
14. Revision history  
Table 10. Revision history  
Document ID  
74ABT125 v.6  
Modifications:  
74ABT125 v.5  
74ABT125 v.4  
74ABT125 v.3  
74ABT125 v.2  
74ABT125 v.1  
Release date  
20111103  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74ABT125 v.5  
• Legal pages updated  
20101124  
20100427  
20080429  
19980116  
19960305  
Product data sheet  
-
-
-
-
-
74ABT125 v.4  
74ABT125 v.3  
74ABT125 v.2  
74ABT125 v.1  
-
Product data sheet  
Product data sheet  
Product specification  
-
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
13 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
15.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
14 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74ABT125  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 6 — 3 November 2011  
15 of 16  
74ABT125  
NXP Semiconductors  
Quad buffer; 3-state  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
6
Functional description . . . . . . . . . . . . . . . . . . . 3  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 15  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 3 November 2011  
Document identifier: 74ABT125  

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