935069180118 [NXP]
ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, SOT-340-1, SSOP-24;
| 型号： | 935069180118 |
| 厂家： | 
NXP |
| 描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, SOT-340-1, SSOP-24 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT657
Octal transceiver with parity
generator/checker (3-State)
Product specification
IC23 Data Handbook
1995 Dec 11
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
The Output Enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
High. The parity select (ODD/EVEN) input gives the user the option
of odd or even parity systems. The parity (PARITY) pin is an output
from the generator/checker when transmitting from the port A to B
(T/R = High) and an input when receiving from port B to A port (T/R
= Low). When transmitting (T/R = High) the parity select
(ODD/EVEN) input is set, then the A port data is polled to determine
the number of High bits. The parity (PARITY) output then goes to the
logic state determined by the parity select (ODD/EVEN) setting and
by the number of High bits on port A. For example, if the parity
select (ODD/EVEN) is set Low (even parity), and the number of
High bits on port A is odd, then the parity (PARITY) output will be
High, transmitting even parity. If the number of High bits on port A is
even, then the parity (PARITY) output will be Low, keeping even
parity. When in receive mode (T/R = Low) the B port is polled to
determine the number of High bits. If parity select (ODD/EVEN) is
Low (even parity) and the number of Highs on port B is:
FEATURES
• Combinational functions in one package
• Low static and dynamic power dissipation with high speed and
high output drive
• Output capability: +64mA/–32mA
• Power-up 3-State
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT657 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers
with 3-State outputs and an 8-bit parity generator/checker, and is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 64mA. The
(1) odd and the parity (PARITY) input is High, then ERROR will be
High, signifying no error.
Transmit/Receive (T/R) input determines the direction of the data
flow through the bidirectional transceivers. Transmit (active-High)
enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
(2) even and the parity (PARITY) input is High, then ERROR will be
asserted Low, indicating an error.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
An to Bn or Bn to An
Input capacitance
PLH
PHL
C = 50pF; V = 5V
3.3
4
ns
pF
pF
nA
L
CC
C
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
I/O capacitance
7
I/O
V
O
CC
I
Total supply current
Outputs disabled; V =5.5V
500
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT657 N
74ABT657 D
74ABT657 DB
74ABT657 PW
74ABT657 N
74ABT657 D
24-Pin plastic SO
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT657 DB
74ABT657PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
Parity output
T/R
A0
A1
A2
A3
A4
1
2
3
4
5
24 OE
13
11
12
1
PARITY
ODD/EVEN
ERROR
T/R
23
22
21
20
B0
B1
B2
B3
Parity select input
Error output
Transmit/receive input
2, 3, 4, 5,
6, 8, 9, 10
A0 - A7
B0 - B7
A port 3-State outputs
B port 3-State outputs
6
7
8
9
19 GND
18 GND
TOP VIEW
V
23, 22, 21, 20,
17, 16, 15, 14
CC
A5
17
16
15
14
B4
B5
B6
B7
24
18, 19
7
OE
Output enable input (active-Low)
Ground (0V)
A6
GND
A7 10
ODD/EVEN 11
ERROR 12
V
CC
Positive supply voltage
13 PARITY
SA00181
2
1995 Dec 11
853–1615 16106
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
0 BUS B TO A
0
1
0
2
1 BUS A TO B
24
M
ƪ ƫ
2
3
4
5
6
8
9
10
2 HIGH Z
11
G3[EVEN]
A0 A1 A2 A3 A4 A5 A6 A7
G4[ODD]
T/R
1
24
11
13
12
PARITY
OE
2K
=
ERROR
13
12
ODD/EVEN
1,3[EVEN]
1,4[ODD]
0,3[EVEN
0,4]ODD
B0 B1 B2 B3 B4 B5 B6 B7
2
23
22
21
20
17
16
15
14
0
2
23 22 21 20 17 16 15 14
3
4
5
SA00182
6
8
9
10
SA00194
FUNCTION TABLE
INPUT/
OUTPUT
INPUTS
T/R
OUTPUTS
NUMBER OF HIGH INPUTS
OE
ODD/EVEN
PARITY
ERROR
OUTPUTS MODE
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
H
L
H
L
H
L
Z
Z
H
L
L
H
Transmit
Transmit
Receive
Receive
Receive
Receive
0, 2, 4, 6, 8
L
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
L
H
H
L
H
L
Z
Z
L
H
H
L
Transmit
Transmit
Receive
Receive
Receive
Receive
1, 3, 5, 7
L
Don’t care
H
X
X
Z
Z
3-State
H
L
X
Z
=
=
=
=
High voltage level
Low voltage level
Don’t care
High impedance ”off” state
3
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
LOGIC DIAGRAM
1
T/R
24
OE
23
22
21
20
17
16
15
14
2
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
3
4
5
6
8
9
10
13
11
PARITY
ODD/EVEN
12
ERROR
SA00215
4
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
5
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–0.9
3.5
–1.2
–1.2
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
4.0
V
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.6
V
OH
I
IL
V
OL
Low-level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.42
±0.01
±5
0.55
±1.0
±100
±100
0.55
±1.0
±100
±100
V
OL
I
IL
I
Input leakage Control pins
= 5.5V; V = GND or 5.5V
µA
µA
µA
I
I
current
Data pins
= 5.5V; V = GND or 5.5V
I
I
Power-off leakage current
0.0V; V or V ≤ 4.5V
±5.0
OFF
O
I
Power-up/down 3-State
output current
V
CC
V
OE
2.0V; V = 0.5V; V = GND or V
;
O
I
CC
I
I
±5.0
±50
±50
µA
PU PD
3
= V
CC
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
–80
0.5
20
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
OZL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
250
30
–50
–180
250
30
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
50
250
1.5
250
1.5
250
1.5
250
1.5
µA
mA
µA
CCZ
V = GND or V
I
CC
Outputs enabled, one data input at 3.4V,
other inputs at V or GND; V = 5.5V
CC
CC
Outputs 3-State, one data input at 3.4V, other
inputs at V or GND; V = 5.5V
Additional supply current per
∆I
CC
2
input pin
CC
CC
Outputs 3-State, one enable input at 3.4V,
other inputs at V or GND; V = 5.5V
0.5
mA
CC
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
6
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0V
= +5.0V ±10%
Min
Typ
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
1.1
1.2
3.3
3.0
5.0
4.3
1.1
1.2
5.5
4.8
PLH
PHL
2
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to PARITY
2.5
2.8
6.5
7.0
8.7
9.1
2.5
2.8
10.1
10.6
PLH
PHL
1, 2
1, 2
1, 2
1, 2
3, 4
3, 4
t
t
Propagation delay
ODD/EVEN to PARITY, ERROR
1.7
1.9
5.0
5.0
6.6
6.6
1.7
1.9
7.3
7.3
PLH
PHL
t
t
Propagation delay
Bn to ERROR
3.9
4.0
9.2
9.6
11.7
12.1
3.9
4.0
13.8
14.5
PLH
PHL
t
t
Propagation delay
PARITY to ERROR
2.7
3.2
6.0
6.4
7.6
8.0
2.7
3.2
9.4
9.4
PLH
PHL
1
t
Output enable time
to High or Low level
1.3
1.9
3.8
4.4
5.6
7.0
1.3
1.9
6.6
8.2
PZH
t
PZL
t
Output disable time
from High or Low level
2.4
2.7
5.1
5.4
7.0
7.6
2.4
2.7
7.6
8.1
PHZ
t
PLZ
NOTES:
1. These delay times reflect the 3-State recovery time only and do not include the delay through the buffers and the parity check circuitry which
affect the ERROR output. To assure valid information at the ERROR pin, time must be allowed for the signal to propagate through the
drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the ERROR pin ≥ (B to A)
+ (A to PARITY).
AC WAVEFORMS
NOTE: For all waveforms, V = 1.5V.
M
An, Bn
ODD/EVEN
An, Bn
ODD/EVEN
PARITY
V
V
M
PARITY
M
V
V
M
M
t
t
PHL
PLH
t
t
PLH
PHL
An, Bn,
PARITY,
ERROR
PARITY,
ERROR
V
V
M
M
V
V
M
M
SA00219
SA00220
Waveform 1. Propagation Delay For Inverting Output
Waveform 2. Propagation Delay For Non-Inverting Output
V
V
OE
V
OE
M
M
V
M
t
M
t
t
PHZ
t
PLZ
PZH
PZL
An, Bn
PARITY, ERROR
V
–0.3V
0V
An, Bn
PARITY, ERROR
OH
V
V
M
M
V
+0.3V
0V
OL
SA00222
SA00221
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
7
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
R
L
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t
)
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
8
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
SOT137-1
SOT340-1
SOT355-1
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
9
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
NOTES
10
1995 Dec 11
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
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74ABT657; Octal
transceiver with
parity
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(3-State)
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The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high
speed and high output drive.
End of Life
information
Distributors Go
Here!
•
•
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-State outputs and an 8-bit parity
generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking
capability of 64mA. The Transmit/Receive (T/R) input determines the direction of the data flow through the
bidirectional transceivers. Transmit (active-High) enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
Models
•
•
SoC solutions
The Output Enable (OE) input disables both the A and B ports by placing them in a high impedance condition when
the OE input is High. The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems.
The parity (PARITY) pin is an output from the generator/checker when transmitting from the port A to B (T/R =
High) and an input when receiving from port B to A port (T/R = Low). When transmitting (T/R = High) the parity
select (ODD/EVEN) input is set, then the A port data is polled to determine the number of High bits. The parity
(PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number
of High bits on port A. For example, if the parity select (ODD/EVEN) is set Low (even parity), and the number of
High bits on port A is odd, then the parity (PARITY) output will be High, transmitting even parity. If the number of
High bits on port A is even, then the parity (PARITY) output will be Low, keeping even parity. When in receive
mode (T/R = Low) the B port is polled to determine the number of High bits. If parity select (ODD/EVEN) is Low
(even parity) and the number of Highs on port B is:
1. odd and the parity (PARITY) input is High, then ERROR will be High, signifying no error.
2. even and the parity (PARITY) input is High, then ERROR will be asserted Low, indicating an error.
Features
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●
●
●
●
●
Combinational functions in one package
Low static and dynamic power dissipation with high speed and high output drive
Output capability: +64mA/-32mA
Power-up 3-State
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
Applications
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
AN2301: Simulation Support for Philips' Advanced BiCMOS Products
Datasheet
Type number Title
Publication
release date
Datasheet status Page
count
File
size
(kB)
Datasheet
74ABT657
Octal transceiver with
parity generator/checker
(3-State)
12/11/1995
Product
specification
11
72
Download
Blockdiagram(s)
Block diagram of
74ABT657D
Parametrics
Type number Package Description
Propagation Voltage No. Power
Delay(ns) of Dissipation
Pins Considerations Levels
Logic
Switching Drive
Capability
Output
Octal Transceiver
with Parity
Generator/Checker; 4~6
Non-Inverting (3-
State)
SOT137
(SO24)
5 Volts
+
74ABT657D
74ABT657DB
74ABT657N
24 None
24 None
24 None
TTL
TTL
TTL
High
Octal Transceiver
with Parity
Generator/Checker; 4~6
Non-Inverting (3-
State)
SOT340-1
(SSOP24)
5 Volts
+
High
High
Octal Transceiver
with Parity
Generator/Checker; 4~6
Non-Inverting (3-
State)
SOT222-1
(DIP24)
5 Volts
+
Octal Transceiver
with Parity
Generator/Checker; 4~6
Non-Inverting (3-
State)
SOT355-1
(TSSOP24)
5 Volts
+
74ABT657PW
24 None
TTL
High
Products, packages, availability and ordering
Type number North
Ordering code Marking/Packing Package Device status Buy online
IC packing info
American type (12NC)
number
SOT137
(SO24)
Standard Marking
* Tube (Signetics)
Full production
Full production
Full production
Full production
74ABT657D 74ABT657D
9350 452 90602
Standard Marking
74ABT657D-T 9350 452 90623 * Reel Pack, SMD,
13" (Signetics)
SOT137
(SO24)
SOT340-1
(SSOP24)
Standard Marking
* Tube
74ABT657DB 74ABT657DB
9350 691 80112
Standard Marking
9350 691 80118 * Reel Pack, SMD,
13"
SOT340-1
(SSOP24)
74ABT657DB-
T
SOT222-1
(DIP24)
Standard Marking
9350 453 00602
Full production
Full production
74ABT657N 74ABT657N
* Tube (Signetics)
SOT355-1
Standard Marking
74ABT657PW 74ABT657PW 9351 789 00112
74ABT657PW-
(TSSOP24)
* Tube
Standard Marking
SOT355-1
Full production
9351 789 00118 * Reel Pack, SMD,
13"
(TSSOP24)
T
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
Similar products
74ABT657 links to the similar products page containing an overview of products that are similar in function or
related to the type number(s) as listed on this page. The similar products page includes products from the same
catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
ABT family characteristics, Family specifications(date 01-Mar-98)
Introduction to Advanced BiCMOS Logic Products(date 01-Mar-98)
Advanced BiCMOS features(date 01-Jan-98)
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