935173420112_技术文档

INTEGRATED CIRCUITS

74ABT16543

16-bit latched transceiver

with dual enable (3-State)

Product data

2002 Apr 03

Replaces 74ABT16543; 74ABTH16543 dated 1998 Feb 27

Philips

Semiconductors

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

FEATURES

DESCRIPTION

The 74ABT16543 high-performance BiCMOS device combines low

static and dynamic power dissipation with high speed and high

output drive.

• Two 8-bit octal transceivers with D-type latch

• Live insertion/extraction permitted

• Power-up 3-State

The 74ABT16543 16-bit registered transceiver contains two sets of

D-type latches for temporary storage of data flowing in either

direction. Separate Latch Enable (nLEAB, nLEBA) and Output

Enable (nOEAB, nOEBA) inputs are provided for each register to

permit independent control of data transfer in either direction. The

outputs are guaranteed to sink 64 mA.

• Power-up reset

• Multiple V and GND pins minimize switching noise

CC

• Back-to-back registers for storage

• Separate controls for data flow in each direction

• Output capability: +64 mA/–32 mA

• Latch-up protection exceeds 500 mA per JEDEC Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

QUICK REFERENCE DATA

CONDITIONS

= 25 °C; GND = 0 V

SYMBOL

PARAMETER

TYPICAL

UNIT

T

amb

t

Propagation delay

nAx to nBx

2.5

2.2

PLH

PHL

C = 50 pF; V = 5 V

ns

L

CC

C

Input capacitance

I/O capacitance

V = 0 V or V

CC

3

7

pF

IN

I

C

V

O

= 0 V or V

3-State

CC;

I/O

I

Outputs disabled; V = 5.5 V

550

9

µA

mA

CCZ

CC

Quiescent supply current

I

Outputs low; V = 5.5 V

CC

CCL

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

74ABT16543DL

74ABT16543DGG

DWG NUMBER

SOT371-1

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

–40 °C to +85 °C

SOT364-1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

Data inputs/outputs

5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24

1A0 – 1A7,

2A0 – 2A7

52, 51, 49, 48, 47, 45, 44, 43

42, 41, 40,38, 37, 36, 34, 33

1B0 – 1B7,

2B0 – 2B7

1, 56

28, 29

1OEAB, 1OEBA,

2OEAB, 2OEBA

A-to-B / B-to-A Output Enable inputs (Active-LOW)

A-to-B / B-to-A Enable inputs (Active-LOW)

3, 54

26, 31

1EAB, 1EBA,

2EAB, 2EBA

2, 55

27, 30

1LEAB, 1LEBA,

2LEAB, 2LEBA

A-to-B / B-to-A Latch Enable inputs (Active-LOW)

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

GND

Ground (0 V)

V

CC

Positive supply voltage

2

2002 Apr 03

853-1739 27958

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

LOGIC SYMBOL (IEEE/IEC)

PIN CONFIGURATION

1

2

56

55

1OEAB

1LEAB

1EAB

GND

1OEBA

1LEBA

56

1OEBA

1EBA

1EN3

G1

54

3

54 1EBA

55

1

1LEBA

1OEAB

1C5

GND

1B0

4

53

52

2EN4

1A0

5

3

2

1EAB

G2

1A1

6

51 1B1

1LEAB

2C6

7

50

49

48

47

46

45

44

43

42

41

40

39

38

V

CC

29

31

2OEBA

2EBA

7EN9

G7

8

1A2

1A3

1B2

1B3

9

30

28

1A4

1B4

10

11

12

13

14

15

16

17

18

19

2LEBA

2OEAB

7C11

GND

1A5

1A6

1A7

2A0

GND

1B5

1B6

1B7

2B0

8EN10

26

27

2EAB

G8

2LEAB

8C12

5

52

3

1A0

1B0

5D

2A1

2A2

2B1

2B2

6D

4

6

51

49

48

47

45

1A1

1A2

1A3

1A4

1A5

1B1

1B2

1B3

1B4

1B5

8

GND

2A3

GND

2B3

9

10

12

2A4 20

37 2B4

21

22

23

24

36

35

34

33

2A5

2B5

V

13

14

15

44

43

42

1A6

1A7

2A0

1B6

1B7

2B0

V

CC

2A6

2B6

2B7

9

11D

10

2A7

12D

GND 25

32 GND

16

17

19

41

40

38

2A1

2A2

2A3

2B1

2B2

2B3

26

27

28

31

30

29

2EAB

2LEAB

2OEAB

2EBA

2LEBA

2OEBA

20

21

37

36

2A4

2A5

2B4

2B5

SH00037

23

24

34

33

2A6

2A7

2B6

2B7

SH00036

3

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

The 74ABT16543 contains two sets of eight D-type latches, with

separate control pins for each set. Using data flow from A to B as an

example, when the A-to-B Enable (nEAB) input and the A-to-B Latch

Enable (nLEAB) input are LOW the A-to-B path is transparent.

5

6

8

9

10 12 13 14

1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7

1EAB

A subsequent LOW-to-HIGH transition of the nLEAB signal puts the

A data into the latches where it is stored and the B outputs no longer

change with the A inputs. With EAB and nOEAB both LOW, the

3-State B output buffers are active and display the data present at

the outputs of the A latches.

3

54

2

1EBA

1OEAB

1OEBA

1

1LEAB

1LEBA

56

55

1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7

Control of data flow from B to A is similar, but using the nEBA,

nLEBA, and nOEBA inputs.

52 51 49 48 47 45 44 43

15 16 17 19 20 21 23 24

2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7

2EAB

26

31

27

30

2EBA

2OEAB

2OEBA

28

29

2LEAB

2LEBA

2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7

42 41 40 38 37 36 34 33

SH00038

FUNCTION TABLE

INPUTS

OUTPUTS

STATUS

nBx or nAx

nOEXX

nEXX

nLEXX

nAx or nBx

H

X

H

X

Z

Disabled

L

↑

L

h

l

Z

Disabled + Latch

Latch + Display

L

↑

h

l

H

L

H

L

H

L

Transparent

Hold

L

H

X

NC

H

h

L

l

X

↑

=

High voltage level

High voltage level one set-up time prior to the LOW-to-HIGH transition of nLEXX or nEXX (XX = AB or BA)

Low voltage level

Low voltage level one set-up time prior to the LOW-to-HIGH transition of nLEXX or nEXX (XX = AB or BA)

Don’t care

LOW-to-HIGH transition of nLEXX or nEXX (XX = AB or BA)

NC= No change

High impedance or “off” state

Z

=

4

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

LOGIC DIAGRAM

DETAIL A

nB0

D

Q

LE

nA0

Q

D

LE

nA1

nA2

nA3

nA4

nA5

nA6

nA7

nB1

nB2

nB3

nB4

nB5

nB6

nB7

DETAIL A X 7

nOEBA

nOEAB

nEAB

nEBA

nLEBA

nLEAB

SH00039

1, 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +7.0

UNIT

V

CC

I

IK

DC input diode current

V < 0 V

I

–18

–1.2 to +7.0

–50

mA

V

3

V

I

DC input voltage

I

DC output diode current

V

O

< 0 V

mA

V

OK

3

V

OUT

DC output voltage

output in Off or HIGH state

output in LOW state

–0.5 to +5.5

128

mA

°C

I

DC output current

OUT

output in HIGH state

–64

T

stg

Storage temperature range

–65 to +150

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

UNIT

Max

Min

4.5

0

V

CC

DC supply voltage

5.5

V

I

Input voltage

V

CC

V

HIGH-level input voltage

LOW-level Input voltage

HIGH-level output current

LOW-level output current

Input transition rise or fall rate

2.0

V

IH

V

0.8

–32

64

V

IL

I

mA

ns/V

°C

OH

I

OL

∆t/∆v

0

10

T

amb

Operating free-air temperature range

–40

+85

DC ELECTRICAL CHARACTERISTICS

LIMITS

T

= –40 °C

to +85 °C

amb

T

amb

= +25 °C

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

MAX

V

Input clamp voltage

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 4.5 V; I = –18 mA

–1.2

V

IK

= 4.5 V; I = –3 mA; V = V or V

2.5

3.0

2.0

2.9

3.4

2.5

3.0

2.0

OH

I

IL

IH

V

OH

HIGH-level output voltage

= 5.0 V; I = –3 mA; V = V or V

OH

I

IL

= 4.5 V; I = –32 mA; V = V or V

IH

2.4

OH

I

IL

V

OL

LOW-level output voltage

= 4.5 V; I = 64 mA; V = V or V

IH

0.36

0.13

0.55

OL

I

IL

3

V

RST

Power-up output voltage

= 5.5 V; I = 1 mA; V = GND or V

O I CC

Input leakage

current

Control

pins

"0.01

"2.0

"1.0

I

V

= 5.5 V; V = GND or 5.5 V

±1.0

±100

±50

±1.0

±100

±50

µA

I

CC

I

Power-off leakage current

Power-up/down 3-State

V

= 0.0 V; V or V ≤ 4.5 V

OFF

CC

O

I

= 2.1 V; V = 0.0 V or V

;

CC

O

I

PU/PD

4

output current

V = GND or V ; V = Don’t care

I

CC

OE

I

+ I

3-State output High current

3-State output Low current

Output High leakage current

V

= 5.5 V; V = 5.5 V; V = V or V

1.0

–1.0

1.0

10

–10

50

10

–10

50

µA

IH

OZH

OZL

CC

O

I

IL

IH

I

= 5.5 V; V = 0.0 V; V = V or V

O I IL

IL

I

= 5.5 V; V = 5.5 V; V = GND or V

CC

µA

CEX

O

I

1

I

O

Output current

= 5.5 V; V = 2.5 V

–50

–100

0.55

9

–200

2

–50

–200

2

mA

O

I

= 5.5 V; Outputs HIGH, V = GND or V

CCH

I

CC

I

= 5.5 V; Outputs LOW, V = GND or V

19

CCL

I

CC

Quiescent supply current

Additional supply current

= 5.5 V; Outputs 3–State;

I

0.55

5.0

2

mA

CCZ

V = GND or V

I

CC

V

CC

= 5.5 V; one input at 3.4 V,

∆I

CC

50

µA

2

per input pin

other inputs at V or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4 V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V between 0 V and 2.1 V, with a transition time of up to 10 msec. From V = 2.1 V to V = 5 V ± 10% a

CC

transition time of up to 100 µsec is permitted.

6

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

AC CHARACTERISTICS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

R

F

L

LIMITS

T

V

= +25 °C

= +5.0 V

T

= –40 °C to +85 °C

amb

CC

amb

V

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0 V ±0.5 V

CC

MIN

TYP

MAX

MIN

MAX

t

Propagation delay

nAx to nBx, nBx to nAx

1.0

2.5

2.2

3.3

4.4

1.0

3.8

5.1

PLH

PHL

2

ns

t

Propagation delay

LEBA to nAx, LEAB to nBx

1.0

1.2

3.1

3.0

4.3

4.8

1.0

1.2

5.2

5.6

PLH

PHL

1, 2

t

Output enable time

OEBA to nAx, OEAB to nBx

4

5

1.0

1.1

3.3

4.3

5.9

1.0

1.1

5.2

7.0

PZH

t

PZL

t

Output disable time

OEBA to nAx, OEAB to nBx

4

5

1.9

1.6

3.5

2.6

5.0

4.2

1.9

1.6

5.7

4.6

PHZ

t

PLZ

t

Output enable time

EBA to nAx, EAB to nBx

4

5

1.0

1.2

3.4

4.9

6.5

1.0

1.2

6.2

7.8

PZH

t

PZL

t

Output disable time

EBA to nAx, EAB to nBx

4

5

2.0

1.7

3.4

2.6

5.6

5.1

2.0

1.7

6.6

5.4

PHZ

t

PLZ

AC SETUP REQUIREMENTS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

R

F

L

LIMITS

T

V

= +25 °C

= +5.0 V

T

= –40 °C to +85 °C

amb

CC

amb

V

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0 V ±0.5 V

CC

MIN

TYP

MIN

t (H)

t (L)

s

Set-up time

nAx to LEAB, nBx to LEBA

1.5

3.5

0.4

–0.1

1.5

3.5

s

3

ns

t (H)

Hold time

nAx to LEAB, nBx to LEBA

1.5

2.0

0.2

–0.3

1.5

2.0

h

t (L)

h

t (H)

Set-up time

nAx to EAB, nBx to EBA

1.5

3.5

0.2

–0.3

1.5

3.5

s

t (L)

s

t (H)

t (L)

h

Hold time

nAx to EAB, nBx to EBA

1.5

2.0

0.3

–0.2

1.5

2.0

h

3

ns

t (L)

w

Latch enable pulse width, LOW

4.0

3.1

4.0

AC WAVEFORMS

V

M

= 1.5 V, V = GND to 3.0 V

IN

V

IN

V

M

t

M

t

PLH

PHL

PLH

V

OUT

V

M

SH00040

SH00041

Waveform 1. Propagation Delay for Inverting Output

Waveform 2. Propagation Delay for Non-Inverting Output

7

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

AC WAVEFORMS (Continued)

V

M

= 1.5 V, V = GND to 3.0 V

IN

nAx, nBx

nOEAB, nOEBA,

nEAB, nEBA

V

M

V

M

t

t (H)

t (L)

s

t

(H)

t (L)

h

s

h

t

PZL

PLZ

nLEAB, nLEBA,

nEAB, nEBA

V

nAx, nBx

V

M

V

+0.3V

OL

t

(L)

w

OL

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

SH00042

SH00044

Waveform 3. Data Setup and Hold Times

and Latch Enable Pulse Width

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

nOEAB, nOEBA,

nEAB, nEBA

V

M

t

PZH

PHZ

V

OH

V

–0.3V

OH

V

nAx, nBx

M

0V

SH00043

Waveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORMS

t

W

V

AMP (V)

CC

90%

7.0V

NEGATIVE

PULSE

V

M

10%

90%

R

L

0V

(t

V

OUT

IN

PULSE

GENERATOR

D.U.T.

t

(t

)

t

TLH

)

THL

F

R

)

t

(t )

R

L

C

TLH

R

THL F

T

L

AMP (V)

90%

M

POSITIVE

PULSE

V

M

Test Circuit for 3-State Outputs

10%

t

W

0V

SWITCH POSITION

V

= 1.5V

M

TEST

SWITCH

Input Pulse Definition

t

closed

PLZ

PZL

t

closed

open

All other

INPUT PULSE REQUIREMENTS

DEFINITIONS

R = Load resistor; see AC CHARACTERISTICS for value.

L

FAMILY

Amplitude

3.0V

Rep. Rate

1MHz

t

F

W

R

C = Load capacitance includes jig and probe capacitance;

L

see AC CHARACTERISTICS for value.

74ABT/H16

500ns 2.5ns 2.5ns

R = Termination resistance should be equal to Z

T

of

OUT

pulse generators.

SA00018

8

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

9

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

10

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

NOTES

11

2002 Apr 03

Philips Semiconductors

Product data

16-bit latched transceiver with dual enable

(3-State)

74ABT16543

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 04-02

9397 750 09692

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

12

2002 Apr 03


型号：	935173420112
厂家：	NXP
描述：	IC ABT SERIES, 16 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP3-56, Bus Driver/Transceiver 光电二极管输出元件
文件：	总12页 (文件大小：107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935173420112 [NXP]

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