935175110118 [NXP]

IC HCT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20, Bus Driver/Transceiver;


型号：	935175110118
厂家：	NXP
描述：	IC HCT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20, Bus Driver/Transceiver 驱动光电二极管输出元件逻辑集成电路
文件：	总7页 (文件大小：56K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT574

Octal D-type flip-flop; positive

edge-trigger; 3-state

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive

edge-trigger; 3-state

74HC/HCT574

The 8 flip-flops will store the state of

their individual D-inputs that meet the

set-up and hold time requirements on

the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the

8 flip-flops are available at the

outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the flip-flops.

FEATURES

GENERAL DESCRIPTION

• 3-state non-inverting outputs for

bus oriented applications

The 74HC/HCT574 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

no. 7A.

• 8-bit positive edge-triggered

• Common 3-state output enable

input

The 74HC/HCT574 are octal D-type

flip-flops featuring separate D-type

inputs for each flip-flop and

non-inverting 3-state outputs for bus

oriented applications. A clock (CP)

and an output enable (OE) input are

common to all flip-flops.

• Independent register and 3-state

buffer operation

• Output capability: bus driver

• I_CCcategory: MSI

The “574” is functionally identical to

the “564”, but has non-inverting

outputs.

The “574” is functionally identical to

the “374”, but has a different pinning.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

UNIT

SYMBOL

PARAMETER

CONDITIONS

HCT

t_PHL/t_PLH

f_max

propagation delay CP to Q_n

maximum clock frequency

input capacitance

C_L= 15 pF; V_CC= 5 V

3.5

123

3.5

MHz

C_I

C_PD

power dissipation capacitance per flip-flop

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74HC/HCT574

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

3-state output enable input (active LOW)

data inputs

2, 3, 4, 5, 6, 7, 8, 9

D₀to D₇

GND

ground (0 V)

clock input (LOW-to-HIGH, edge-triggered)

3-state ﬂip-ﬂop outputs

19, 18, 17, 16, 15, 14, 13, 12

Q₀to Q₇

V_CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74HC/HCT574

FUNCTION TABLE

INPUTS

OE CP

OUTPUTS

OPERATING

MODES

INTERNAL

FLIP-FLOPS

D_n

Q₀to Q₇

load and read

↑

load register and

disable outputs

↑

Notes

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH

CP transition

L = LOW voltage level

l = LOW voltage level on set-up time prior to the LOW-to-HIGH

CP transition

Z = HIGH impedance OFF-state

↑ = LOW-to-HIGH clock transition

Fig.4 Functional diagram.

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74HC/HCT574

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

WAVEFORMS

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP to Q_n

150

190

225

2.0 Fig.6

4.5

6.0

_PZH/ t_PZL3-state output enable

time OE to Q_n

140

175

210

2.0 Fig.7

4.5

6.0

_PHZ/ t_PLZ3-state output disable

time OE to Q_n

125

155

190

2.0 Fig.7

4.5

6.0

_THL/ t_TLHoutput transition time

2.0 Fig.6

4.5

6.0

t_W

clock pulse width

HIGH or LOW

100

120

2.0 Fig.6

4.5

6.0

t_su

set-up time

D_nto CP

2.0 Fig.8

4.5

6.0

t_h

hold time

D_nto CP

2.0 Fig.8

4.5

6.0

f_max

maximum clock pulse

frequency

6.0

112

133

4.8

4.0

MHz 2.0 Fig.6

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74HC/HCT574

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

0.5

1.25

1.5

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP to Q_n

4.5 Fig.6

4.5 Fig.7

4.5 Fig.6

4.5 Fig.8

t_PZH/ t_PZL3-state output enable

time OE to Q_n

_PHZ/ t_PLZ3-state output disable

time OE to Q_n

t_THL/ t_TLHoutput transition time

t_W

clock pulse width

HIGH or LOW

t_su

t_h

set-up time

D_nto CP

hold time

D_nto CP

−1

f_max

maximum clock pulse

frequency

MHz 4.5 Fig.6

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74HC/HCT574

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the clock input (CP)

pulse width, the CP input to output (Q_n)

propagation delays, the output transition

times and the maximum clock pulse

frequency.

Fig.7 Waveforms showing the 3-state enable and

disable times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the data set-up and

hold times for D_ninput to CP input.

December 1990

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