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935175140112 [NXP]

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-16, FF/Latch;
935175140112
型号： 935175140112
厂家： NXP    NXP
描述：

IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-16, FF/Latch

光电二极管 输出元件 逻辑集成电路 触发器
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INTEGRATED CIRCUITS  
74LV74  
Dual D-type flip-flop with set and reset;  
positive-edge trigger  
Product specification  
1998 Apr 20  
Supersedes data of 1996 Nov 07  
IC24 Data Handbook  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
FEATURES  
• Wide operating voltage: 1.0 to 5.5V  
• Optimized for Low Voltage applications: 1.0 to 3.6V  
DESCRIPTION  
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and  
function compatible with 74HC/HCT74.  
The 74LV74 is a dual positive edge triggered, D-type flip-flop with  
individual data (D) inputs, clock (CP) inputs, set (S ) and (R )  
inputs; also complementary Q and Q outputs.  
• Accepts TTL input levels between V = 2.7V and V = 3.6V  
CC  
CC  
D
D
• Typical V  
(output ground bounce) t 0.8V @ V = 3.3V,  
OLP  
CC  
The set and reset are asynchronous active LOW inputs and operate  
independently of the clock input. Information on the data input is  
transferred to the Q output on the LOW-to-HIGH transition of the  
clock pulse. The D inputs must be stable one set-up time prior to the  
LOW-to-HIGH clock transition, for predictable operation.  
T
= 25°C  
amb  
• Typical V  
(output V undershoot) u 2V @ V = 3.3V,  
OHV  
OH  
CC  
T
= 25°C  
amb  
• Output capability: standard  
Schmitt-trigger action in the clock input makes the circuit highly  
tolerant to slower clock rise and fall times.  
• I category: flip-flops  
CC  
QUICK REFERENCE DATA  
GND = 0V; T  
= 25°C; t =t v2.5 ns  
amb  
r f  
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
Propagation delay  
nCP to nQ, nQ  
C = 15pF  
L
11  
14  
14  
V
CC  
= 3.3V  
t
f
/t  
ns  
PHL PLH  
nS to nQ, nQ  
D
nR to nQ, nQ  
D
C = 15pF  
L
CC  
Maximum clock frequency  
Input capacitance  
76  
MHz  
max  
V
= 3.3V  
C
C
3.5  
24  
pF  
pF  
I
Power dissipation capacitance per flip-flop  
Notes 1 and 2  
PD  
NOTES:  
1. C is used to determine the dynamic power dissipation (P in µW)  
PD  
D
2
2
P
= C   V  
x f )S (C   V  
  f ) where:  
D
PD  
CC  
i
L
CC o  
f = input frequency in MHz; C = output load capacitance in pF;  
i
L
f = output frequency in MHz; V = supply voltage in V;  
o
CC  
2
S (C   V  
  f ) = sum of the outputs.  
L
CC  
o
2. The condition is V = GND to V  
I
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74LV74 N  
PKG. DWG. #  
SOT27-1  
14-Pin Plastic DIL  
–40°C to +125°C  
–40°C to +125°C  
–40°C to +125°C  
–40°C to +125°C  
74LV74 N  
74LV74 D  
14-Pin Plastic SO  
74LV74 D  
SOT108-1  
SOT337-1  
SOT402-1  
14-Pin Plastic SSOP Type II  
14-Pin Plastic TSSOP Type I  
74LV74 DB  
74LV74 PW  
74LV74 DB  
74LV74PW DH  
PIN DESCRIPTION  
FUNCTION TABLE  
PIN  
INPUTS  
OUTPUTS  
SYMBOL  
NUMBER  
FUNCTION  
SD  
RD  
CP  
D
Q
Q
Asynchronous reset-direct input  
(active-LOW)  
1, 13  
2, 12  
3, 11  
1R 2R  
D, D  
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
1D, 2D  
Data inputs  
Clock input (LOW-to-HIGH),  
edge-triggered)  
1CP, 2CP  
INPUTS  
OUTPUTS  
Qn+1 Qn+1  
Asynchronous set-direct input  
(active-LOW)  
SD  
RD  
CP  
D
4, 10  
1S 2S  
D, D  
H
H
H
H
°
°
L
H
L
H
5, 9  
6, 8  
7
1Q, 2Q  
True flip-flop outputs  
Complement flip-flop outputs  
Ground (0V)  
H
L
1Q 2Q  
,
H
L
X
°
=
HIGH voltage level  
LOW voltage level  
don’t care  
LOW-to-HIGH CP transition  
state after the next LOW-to-HIGH CP transition  
=
=
=
=
GND  
14  
V
CC  
Positive supply voltage  
Q
n+1  
2
1998 Apr 20  
853-1888 19258  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
PIN CONFIGURATION  
LOGIC SYMBOL  
V
1R  
1
2
14  
13  
CC  
D
10  
2S  
4
D
1D  
2R  
2D  
1S  
D
D
D
S
D
3
1CP  
12  
11  
2
1D  
1Q  
2Q  
5
9
Q
12 2D  
3
1CP  
2CP  
1S  
4
5
D
CP  
FF  
Q
11 2CP  
1Q  
2Q  
6
2S  
D
1Q  
1Q  
10  
9
8
R
D
6
7
2Q  
2Q  
1R  
2R  
13  
D
1
D
GND  
8
SV00330  
SV00331  
FUNCTIONAL DIAGRAM  
LOGIC SYMBOL (IEEE/IEC)  
4
S
5
6
1S  
1D  
4
2
D
3
C1  
S
D
1Q  
1Q  
5
6
D
Q
2
1D  
3
1CP  
1
CP FF1  
Q
R
10  
R
S
D
9
8
1R  
1
D
11  
12  
C2  
2S  
10  
D
2D  
R
13  
S
D
12 2D  
11 2CP  
2Q  
2Q  
9
8
D
Q
SV00332  
CP FF2  
Q
R
D
13  
2R  
D
SV00333  
3
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
LOGIC DIAGRAM (ONE FLIP-FLOP)  
Q
C
C
C
C
C
C
C
D
Q
C
R
D
S
D
CP  
C
C
SV00334  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
1.0  
0
TYP.  
3.3  
–
MAX  
5.5  
UNIT  
V
CC  
DC supply voltage  
See Note1  
V
V
V
V
I
Input voltage  
V
CC  
CC  
V
O
Output voltage  
0
–
V
Operating ambient temperature range in free  
air  
See DC and AC  
characteristics  
–40  
–40  
+85  
+125  
T
amb  
°C  
V
CC  
V
CC  
V
CC  
V
CC  
= 1.0V to 2.0V  
= 2.0V to 2.7V  
= 2.7V to 3.6V  
= 3.6V to 5.5V  
–
–
–
–
–
–
–
–
500  
200  
100  
50  
Input rise and fall times except for  
Schmitt-trigger inputs  
t , t  
r
ns/V  
f
NOTE:  
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.  
CC  
CC  
CC  
CC  
1, 2  
ABSOLUTE MAXIMUM RATINGS  
In accordance with the Absolute Maximum Rating System (IEC 134)  
Voltages are referenced to GND (ground = 0V)  
SYMBOL  
PARAMETER  
DC supply voltage  
CONDITIONS  
RATING  
–0.5 to +7.0  
20  
UNIT  
V
CC  
V
±I  
IK  
DC input diode current  
DC output diode current  
V < –0.5 or V > V + 0.5V  
mA  
mA  
I
I
CC  
±I  
OK  
V
O
< –0.5 or V > V + 0.5V  
50  
O
CC  
DC output source or sink current  
– standard outputs  
±I  
O
–0.5V < V < V + 0.5V  
mA  
O
CC  
25  
DC V or GND current for types with  
–standard outputs  
CC  
±I  
±I  
,
mA  
GND  
50  
CC  
T
Storage temperature range  
Power dissipation per package  
–plastic DIL  
–65 to +150  
°C  
stg  
for temperature range: –40 to +125°C  
above +70°C derate linearly with 12mW/K  
above +70°C derate linearly with 8 mW/K  
above +60°C derate linearly with 5.5 mW/K  
750  
500  
400  
P
mW  
tot  
–plastic mini-pack (SO)  
–plastic shrink mini-pack (SSOP and TSSOP)  
NOTES:  
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the  
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may affect device reliability.  
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
4
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
DC CHARACTERISTICS  
Over recommended operating conditions voltages are referenced to GND (ground = 0V)  
LIMITS  
MAX  
-40°C to +85°C  
-40°C to +125°C  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
= 1.2V  
UNIT  
1
MIN  
0.9  
1.4  
2.0  
TYP  
MIN  
0.9  
1.4  
2.0  
MAX  
V
V
V
V
V
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
= 2.0V  
HIGH level Input  
voltage  
V
IH  
V
= 2.7 to 3.6V  
= 4.5 to 5.5V  
= 1.2V  
0.7*V  
0.7*V  
CC  
CC  
0.3  
0.6  
0.8  
0.3  
0.6  
0.8  
= 2.0V  
LOW level Input  
voltage  
V
IL  
V
= 2.7 to 3.6V  
= 4.5 to 5.5  
0.3*V  
0.3*V  
CC  
CC  
= 1.2V; V = V or V –I = 100µA  
1.2  
2.0  
2.7  
3.0  
4.5  
I
IH  
IL;  
O
= 2.0V; V = V or V –I = 100µA  
1.8  
2.5  
2.8  
4.3  
1.8  
2.5  
2.8  
4.3  
I
IH  
IL;  
O
HIGH level output  
voltage; all outputs  
= 2.7V; V = V or V –I = 100µA  
V
V
V
V
V
V
I
IH  
IL;  
O
OH  
= 3.0V; V = V or V –I = 100µA  
I
IH  
IL;  
O
= 4.5V;V = V or V –I = 100µA  
I
IH  
IL;  
O
HIGH level output  
voltage;  
STANDARD  
V
V
= 3.0V;V = V or V –I = 6mA  
2.40  
3.60  
2.82  
4.20  
2.20  
3.50  
CC  
I
IH  
IL;  
O
OH  
= 4.5V;V = V or V –I = 12mA  
CC  
I
IH  
IL;  
O
outputs  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 1.2V; V = V or V I  
IL; O  
= 100µA  
= 100µA  
= 100µA  
0
0
0
0
0
I
IH  
= 2.0V; V = V or V  
I
0.2  
0.2  
0.2  
0.2  
0.2  
I
IH  
IL; O  
LOW level output  
voltage; all outputs  
= 2.7V; V = V or V  
I
0.2  
0.2  
0.2  
V
V
I
IH  
IL; O  
OL  
= 3.0V;V = V or V I  
= 100µA  
I = 100µA  
I
IH  
IL; O  
= 4.5V;V = V or V  
IL; O  
I
IH  
LOW level output  
voltage;  
STANDARD  
V
CC  
V
CC  
V
CC  
= 3.0V;V = V or V I = 6mA  
IL; O  
0.25  
0.35  
0.40  
0.55  
1.0  
0.50  
0.65  
1.0  
I
IH  
OL  
= 4.5V;V = V or V I = 12mA  
IL; O  
I
IH  
outputs  
Input leakage  
current  
I
I
= 5.5V; V = V or GND  
µA  
µA  
I
CC  
Quiescent supply  
current; flip-flops  
I
V
= 5.5V; V = V or GND; I = 0  
20.0  
500  
80  
CC  
CC  
CC  
I
CC  
O
Additional  
quiescent supply  
current per input  
∆I  
CC  
V
= 2.7V to 3.6V; V = V –0.6V  
850  
µA  
I
CC  
NOTE:  
1. All typical values are measured at T  
= 25°C.  
amb  
5
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
AC CHARACTERISTICS  
GND = 0V; t = t v 2.5ns; C = 50pF; R = 1KΩ  
r
f
L
L
LIMITS  
–40 to +85 °C  
LIMITS  
–40 to +125 °C  
CONDITION  
(V)  
SYMBOL  
PARAMETER  
WAVEFORM  
UNIT  
1
V
CC  
MIN  
–
TYP  
MAX  
–
MIN  
–
MAX  
–
1.2  
2.0  
2.7  
70  
24  
18  
–
44  
28  
26  
17  
–
–
56  
41  
33  
23  
–
Propagation delay  
nCP to nQ, nQ  
–
–
t
t
t
t
Figures, 1, 3  
Figures 2, 3  
Figures 2, 3  
ns  
PHL/ PLH  
2
3.0 to 3.6  
4.5 to 5.5  
1.2  
–
13  
–
3
–
9.5  
–
–
90  
31  
23  
–
2.0  
–
46  
34  
27  
19  
–
–
58  
43  
34  
24  
–
Propagation delay  
nS to nQ, nQ  
D
2.7  
–
–
t
ns  
ns  
PHL/ PLH  
2
3.0 to 3.6  
4.5 to 5.5  
1.2  
–
17  
–
3
–
12  
–
–
90  
31  
23  
–
2.0  
–
46  
34  
27  
19  
–
–
58  
43  
34  
24  
–
Propagation delay  
2.7  
–
–
t
PHL/ PLH  
nR to nQ, nQ  
D
2
3.0 to 3.6  
4.5 to 5.5  
2.0  
–
17  
–
3
–
12  
–
34  
25  
20  
15  
34  
25  
20  
15  
–
10  
8
41  
30  
24  
18  
41  
30  
24  
18  
–
2.7  
–
–
Clock pulse width  
HIGH to LOW  
t
t
Figure 1  
Figure 2  
ns  
ns  
W
2
3.0 to 3.6  
4.5 to 5.5  
2.0  
7
–
–
3
6
–
–
10  
8
–
–
2.7  
–
–
Set or reset pulse  
width LOW  
W
2
3.0 to 3.6  
4.5 to 5.5  
1.2  
7
–
–
3
6
–
–
5
2
1
–
–
2.0  
14  
10  
8
–
15  
11  
9
–
Removal time  
set or reset  
2.7  
–
–
t
Figure 2  
Figure 1  
ns  
ns  
rem  
2
3.0 to 3.6  
4.5 to 5.5  
1.2  
1
–
–
3
6
1
–
7
–
–
10  
4
–
–
–
2.0  
22  
12  
8
–
26  
15  
10  
8
–
Set-up time  
nD to nCP  
2.7  
3
–
–
t
su  
2
3.0 to 3.6  
4.5 to 5.5  
1.2  
2
–
–
2
6
1
–
–
–
–10  
–2  
–
–
–
2.0  
3
–
3
–
Hold time  
nD to nCP  
2.7  
3
–2  
–
3
–
t
Figure 1  
Figure 1  
ns  
h
2
3.0 to 3.6  
4.5 to 5.5  
2.0  
3
–2  
–
3
–
3
3
–2  
–
3
–
14  
50  
60  
70  
40  
90  
–
12  
40  
48  
56  
–
2.7  
–
–
Maximum clock  
pulse frequency  
f
MHz  
max  
2
3.0 to 3.6  
4.5 to 5.5  
100  
–
–
3
110  
–
–
NOTE:  
1. Unless otherwise stated, all typical values are at T  
= 25°C.  
amb  
2. Typical value measured at V = 3.3V.  
CC  
3. Typical value measured at V = 5.0V.  
CC  
6
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
AC WAVEFORMS  
TEST CIRCUIT  
V
V
V
= 1.5V at V w 2.7V v 3.6V  
M
CC  
V
cc  
= 0.5 * V at V t 2.7V and w 4.5V  
M
CC  
CC  
and V are the typical output voltage drop that occur with the  
OL  
OH  
output load.  
V
V
O
l
PULSE  
GENERATOR  
D.U.T.  
V
I
50pF  
R = 1k  
L
R
T
nD INPUT  
GND  
VM  
C
L
t
h
t
h
t
su  
t
su  
Test Circuit for Outputs  
1/f  
max  
V
I
DEFINITIONS  
R
L
C
L
R
T
= Load resistor  
nCP INPUT  
GND  
V
M
= Load capacitance includes jig and probe capacitiance  
= Termination resistance should be equal to Z of pulse generators.  
t
OUT  
W
t
t
PHL  
PLH  
V
OH  
TEST  
V
V
I
CC  
nQ OUTPUT  
V
M
t
t
< 2.7V  
2.7–3.6V  
≥ 4.5 V  
V
CC  
PLH/ PHL  
V
OL  
2.7V  
V
OH  
V
CC  
nQ OUTPUT  
V
M
SV00902  
V
OL  
Figure 3. Load circuitry for switching times  
t
t
PHL  
PLH  
SV00335  
Figure 1.The clock (nCP) to output (nQ, nQ) propagation  
delays, the clock pulse width, the nD to nCP setup times, the  
nCP to nD hold times, the output transition times and the  
maximum clock pulse frequency  
NOTE:  
The shaded areas indicate when the input is permitted to change for  
predictable output performance.  
V
I
V
t
nCP INPUT  
GND  
M
rem  
V
I
nS INPUT  
D
V
M
GND  
t
W
t
W
V
I
nR INPUT  
D
V
M
GND  
t
t
PHL  
PLH  
V
OH  
nQ OUTPUT  
V
V
M
V
OL  
V
OH  
nQ OUTPUT  
M
V
OL  
t
t
PLH  
PHL  
SV00336  
Figure 2.The set (nS ) and reset (nR ) input to output (nQ, nQ)  
D
D
propagation delays, the set and reset pulse widths and the nR  
to nCP removal time  
D
7
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
DIP14: plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
8
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
SO14: plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
9
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm  
SOT337-1  
10  
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm  
SOT402-1  
11  
1998 Apr 20  
Philips Semiconductors  
Product specification  
Dual D-type flip-flop with set and reset;  
positive edge-trigger  
74LV74  
DEFINITIONS  
Data Sheet Identification  
Product Status  
Definition  
This data sheet contains the design target or goal specifications for product development. Specifications  
may change in any manner without notice.  
Objective Specification  
Formative or in Design  
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to make changes at any time without notice in order to improve design  
and supply the best possible product.  
Preliminary Specification  
Product Specification  
Preproduction Product  
Full Production  
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes  
at any time without notice, in order to improve design and supply the best possible product.  
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,  
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,  
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes  
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting  
or modification.  
LIFE SUPPORT APPLICATIONS  
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,  
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected  
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips  
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully  
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 05-96  
9397-750-04414  
Document order number:  
Philips  
Semiconductors  

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