935175550112 [NXP]
LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, 4.40 MM WIDTH, MO-153, SOT360-1, PLASTIC, TSSOP-20;
| 型号： | 935175550112 |
| 厂家： | 
NXP |
| 描述： | LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, 4.40 MM WIDTH, MO-153, SOT360-1, PLASTIC, TSSOP-20 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Rev. 4 — 24 December 2013
Product data sheet
1. General description
The 74LVT245 is a high-performance BiCMOS product designed for VCC operation at
3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. It features an output enable (OE) input for easy cascading
and a direction (DIR) input for direction control.
2. Features and benefits
3-state buffers
Octal bidirectional bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/32 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT245D
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVT245DB
74LVT245PW
74LVT245BQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
4. Functional diagram
DIR
1
OE
19
18
17
A0
2
B0
B1
A1
3
A2
4
19
G3
B2
B3
B4
B5
B6
B7
1
16
15
3EN1
3EN2
A3
5
1
A4
6
18
2
2
14
13
12
11
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A5
7
A6
8
A7
9
mna174
mna175
Fig 1. Logic diagram
Fig 2. IEC logic symbol
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
2 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
5. Pinning information
5.1 Pinning
74LVT245
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
A0
A1
A2
A3
A4
A5
A6
A7
OE
B0
B1
B2
B3
B4
B5
B6
1
2
20
19
18
17
16
15
14
13
12
11
DIR
A0
V
CC
OE
B0
B1
B2
B3
B4
B5
B6
B7
3
A1
4
A2
5
A3
74LVT245
6
A4
(1)
GND
7
A5
8
A6
9
A7
001aah722
10
GND
Transparent top view
001aah721
(1) The die substrate is attached to this pad using a
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3. Pin configuration for SO20 and (T)SSOP20
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
DIR
Pin description
Pin
Description
1
direction control
A0 to A7
GND
2, 3, 4, 5, 6, 7, 8, 9
data input/output
ground (0 V)
10
B0 to B7
OE
18, 17, 16, 15, 14, 13, 12, 11
data input/output
output enable input (active LOW)
supply voltage
19
20
VCC
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
3 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
6. Functional description
Table 3.
Function selection
Inputs
Inputs/outputs
OE
L
DIR
An
Bn
L
An = Bn
inputs
Z
inputs
Bn = An
Z
L
H
X
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1][2]
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
50
50
-
Max
+4.6
7.0
+7
Unit
V
supply voltage
[3]
[3]
input voltage
V
VO
output voltage
output in OFF or HIGH state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
-
mA
mA
mA
mA
C
IOK
VO < 0 V
-
IO
output in LOW state
output in HIGH state
128
-
64
65
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
+150
+150
500
C
[4]
Ptot
Tamb = 40 C to +85 C
-
mW
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[4] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
2.7
0
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
5.5
V
IOH
HIGH-level output current
-
32
mA
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
4 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Table 5.
Recommended operating conditions …continued
Symbol Parameter
Conditions
Min
Max
32
Unit
mA
mA
C
IOL
LOW-level output current
-
current duty cycle 50 %; fi 1 kHz
in free air
-
64
Tamb
ambient temperature
40
+85
10
t/V
input transition rise and fall rate
output enabled
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
Unit
Min
Typ[1]
Max
-
VIK
VIH
VIL
input clamping voltage
VCC = 2.7 V; IIK = –18 mA
1.2
2.0
-
0.9
V
V
HIGH-level input voltage
LOW-level input voltage
-
-
-
0.8
-
VOH
HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = 100 A
VCC = 2.7 V; IOH = 8 mA
VCC 0.2 VCC 0.1
V
2.4
2.0
2.5
2.2
0.1
0.3
0.25
0.3
0.4
-
VCC = 3.0 V; IOH = 32 mA
-
V
V
V
V
V
V
VOL
LOW-level output voltage
input leakage current
VCC = 2.7 V; IOL = 100 A
VCC = 2.7 V; IOL = 24 mA
VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
control pins
0.2
0.5
0.4
0.5
0.55
-
-
-
-
II
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC or GND
I/O data pins
-
-
1
10
A
A
0.1
1
[2]
VCC = 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC
-
-
1
0.1
1
1
20
1
A
A
A
VCC = 3.6 V; VI = 0 V
5
-
-
IOFF
ILO
power-off leakage current
output leakage current
VCC = 0 V; VI or VO = 0 V to 4.5 V
VO = 5.5 V; VCC = 3.6 V; output HIGH
100 A
125 A
100 A
-
60
15
[3]
IO(pu/pd) power-up/power-down
output current
VCC 1.2 V VO = 0.5 V to VCC;
-
VI = GND or VCC; OE = don’t care
IBHL
bus hold LOW current
bus hold HIGH current
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0 V
VCC = 0 V to 3.0 V; VI = 3.6 V
75
-
150
150
-
-
A
75 A
A
IBHH
IBHLO
[4]
[4]
bus hold LOW
overdrive current
500
-
IBHHO
bus hold HIGH
VCC = 0 V to 3.0 V; VI = 3.6 V
-
-
500 A
overdrive current
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
5 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
Unit
Min
Typ[1]
Max
ICC
supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
outputs HIGH
-
-
-
-
0.13
3
0.19 mA
12 mA
outputs LOW
outputs disabled
0.13
0.1
0.19 mA
0.2 mA
[5]
ICC
additional supply current
per input pin; VCC = 3.0 V to 3.6 V;
one input = VCC 0.6 V;
other inputs at VCC or GND
CI
input capacitance
DIR and OE inputs; outputs disabled;
VI = 0 V or 3.0 V
-
-
4
-
-
pF
pF
CI/O
input/output capacitance
at input/output data pins, outputs disabled;
VI/O = 0 V or 3.0 V
10
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
[2] Unused pins at VCC or GND.
[3] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V
a transition time of 100 ms is permitted. This parameter is valid for Tamb = +25 C only.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
40 C to +85 C
Unit
Min
Typ[1]
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
LOW to HIGH propagation delay
An to Bn or Bn to An
VCC = 2.7 V
-
-
4.7
4.0
ns
ns
VCC = 3.3 V 0.3 V
An to Bn or Bn to An
VCC = 2.7 V
1.0
2.4
HIGH to LOW propagation delay
-
-
4.6
4.0
ns
ns
VCC = 3.3 V 0.3 V
1.0
2.4
OFF-state to HIGH propagation delay see Figure 6
VCC = 2.7 V
-
-
7.1
5.5
ns
ns
VCC = 3.3 V 0.3 V
1.1
3.3
OFF-state to LOW propagation delay see Figure 6
VCC = 2.7 V
-
-
6.5
5.5
ns
ns
VCC = 3.3 V 0.3 V
1.1
3.3
HIGH to OFF-state propagation delay see Figure 6
VCC = 2.7 V
-
-
6.5
5.9
ns
ns
VCC = 3.3 V 0.3 V
2.2
3.6
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
6 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions
40 C to +85 C
Unit
Min
Typ[1]
Max
tPLZ
LOW to OFF-state propagation delay see Figure 6
VCC = 2.7 V
-
-
4.8
4.8
ns
ns
VCC = 3.3 V 0.3 V
2.0
3.4
[1] Typical values are measured at Tamb = 25 C and VCC = 3.3 V.
11. Waveforms
V
I
V
V
M
An, Bn input
GND
M
t
t
PLH
PHL
V
OH
V
V
M
Bn, An output
M
V
OL
001aah732
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times
V
I
V
OE input
M
GND
3.0 V
t
t
PZL
PLZ
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aah733
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. 3-state output enable and disable times
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
7 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Table 8.
VCC
Measurement points
Input
VI
Output
VM
VM
VX
VY
2.7 V to 3.6 V
GND to 2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for switching times
Table 9.
Input
VI
Test data
Load
RL
VEXT
fi
tW
tr, tf
CL
tPHZ, tPZH
GND
tPLZ, tPZL
6 V
tPLH, tPHL
2.7 V
10 MHz
500 ns
2.5 ns
500
50 pF
open
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
8 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 8. Package outline SOT163-1 (SO20)
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
9 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 9. Package outline SOT339-1 (SSOP20)
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
10 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 10. Package outline SOT360-1 (TSSOP20)
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
11 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
C
1
y
e
b
v
M
C
C
A
B
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 11. Package outline SOT764-1 (DHVQFN20)
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
12 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LVT245 v.4
Modifications:
74LVT245 v.3
74LVT245 v.2
74LVT245 v.1
Release date
Data sheet status
Change notice
Supersedes
20131224
Product data sheet
-
74LVT245 v.3
• Minimum, typical and maximum value of IBHH corrected (errata).
20080508
19980219
19940520
Product data sheet
Product specification
Product specification
-
-
-
74LVT245 v.2
74LVT245 v.1
-
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
13 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
14 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2013
15 of 16
NXP Semiconductors
74LVT245
3.3 V octal transceiver with direction pin (3-state)
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 December 2013
Document identifier: 74LVT245
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