935190180118 [NXP]
IC HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, SOT-338-1, SSOP-16, Shift Register;
| 型号： | 935190180118 |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, SOT-338-1, SSOP-16, Shift Register 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT597
8-bit shift register with input
flip-flops
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
FEATURES
GENERAL DESCRIPTION
• 8-bit parallel storage register inputs
• Shift register has direct overriding load and clear
• Output capability: standard
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
• ICC category: MSI
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
SHCP to Q
17
25
21
96
20
ns
STCP to Q
29
26
83
3.5
32
ns
PL to Q
ns
fmax
CI
maximum clock frequency SHCP
input capacitance
MHz
pF
3.5
29
CPD
power dissipation capacitance per package notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
V
CC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
PIN DESCRIPTION
PIN NO.
SYMBOL
GND
Q
NAME AND FUNCTION
ground (0 V)
8
9
serial data output
10
11
12
13
14
MR
asynchronous reset input (active LOW)
SHCP
STCP
PL
shift clock input (LOW-to-HIGH, edge-triggered)
storage clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
serial data input
DS
15, 1, 2, 3, 4, 5, 6, 7 D0 to D7
parallel data inputs
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.4 Functional diagram.
FUNCTION TABLE
STCP
SHCP
PL
MR
FUNCTION
↑
X
X
X
X
X
↑
X
L
X
H
H
L
data loaded to input latches
↑
data loaded from inputs to shift register
no clock edge
L
data transferred from input flip-flops to shift register
invalid logic, state of shift register indeterminate when signals removed
shift register cleared
X
X
X
L
H
H
L
H
shift register clocked Qn = Qn−1, Q0 = DS
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.6 Timing diagram.
December 1990
6
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
SHCP to Q
55
20
16
175
35
30
220
44
37
265
53
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
tPHL
propagation delay
MR to Q
58
21
17
175
35
30
220
44
37
265
53
45
2.0 Fig.8
4.5
6.0
t
t
t
PHL/ tPLH propagation delay
80
29
23
250
50
43
315
63
54
375
75
64
2.0 Fig.7
4.5
6.0
STCP to Q
PHL/ tPLH propagation delay
PL to Q
69
25
20
215
43
37
270
54
46
325
65
55
2.0 Fig.9
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.9
4.5
6.0
tW
STCP pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
SHCP pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
MR pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
tW
PL pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
2.0 Fig.9
4.5
6.0
trem
removal time
MR to SHCP
60
12
10
−3
−1
−1
75
15
13
90
18
15
2.0 Fig.10
4.5
6.0
tsu
set-up time
Dn to STCP
60
12
10
8
3
2
75
15
13
90
18
15
2.0 Fig.11
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tsu
tsu
th
set-up time
DS to SHCP
60
12
10
11
4
3
75
15
13
90
18
15
ns
ns
ns
ns
2.0 Fig.11
4.5
6.0
set-up time
PL to SHCP
60
12
10
11
4
3
75
15
13
90
18
15
2.0 Fig.12
4.5
6.0
hold time
Dn to STCP
5
5
5
−3
−1
−1
5
5
5
5
5
5
2.0 Fig.11
4.5
6.0
th
hold time
PL, DS to SHCP
5
5
5
−6
−2
−2
5
5
5
5
5
5
2.0 Fig.11
4.5
6.0
fmax
maximum pulse frequency 6.0
29
87
104
4.8
24
28
4.0
20
24
MHz 2.0 Fig.7
SHCP
30
35
4.5
6.0
December 1990
8
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
DS
Dn
0.25
0.30
1.50
1.50
PL, MR
STCP, SHCP
December 1990
9
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
AC WAVEFORMS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
SHCP to Q
23
28
33
30
7
40
49
57
52
15
50
61
71
65
19
60
74
86
78
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.8
4.5 Fig.7
4.5 Fig.9
4.5 Fig.9
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.9
4.5 Fig.10
4.5 Fig.11
4.5 Fig.11
4.5 Fig.12
4.5 Fig.11
4.5 Fig.11
tPHL
propagation delay
MR to Q
t
PHL/ tPLH propagation delay
STCP to Q
tPHL/ tPLH propagation delay
PL to Q
t
THL/ tTLH output transition time
tW
tW
tW
tW
trem
tsu
tsu
tsu
th
SHCP pulse width
HIGH or LOW
16
16
25
20
12
12
12
12
5
7
20
20
31
25
15
15
15
15
5
24
24
38
30
18
18
18
18
5
STCP pulse width
HIGH or LOW
6
MR pulse width
LOW
14
10
−2
5
PL pulse width
LOW
removal time
MR to SHCP
set-up time
Dn to STCP
set-up time
DS to SHCP
2
set-up time
PL to SHCP
4
hold time
−1
−2
75
Dn to STCP
th
hold time
5
5
5
PL, DS to SHCP
fmax
maximum pulse frequency 30
SHCP
24
20
MHz 4.5 Fig.7
December 1990
10
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the MR input to Q
output propagation delays and the MR
pulse width.
Fig.7 Waveforms showing the SHCP and STCP
inputs to Q output propagation delays, the
SHCP and STCP pulse widths and maximum
clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the MR input to SHCP
STCP removal times.
,
Fig.9 Waveforms showing the PL input to Q
output propagation delays, PL pulse width
and output transition times.
December 1990
11
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing hold and set-up times
for DS, Dn inputs to SHCP, STCP inputs.
Fig.12 Waveforms showing set-up times for PL
input to SHCP input.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
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