935190320112 [NXP]

IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDSO14, PLASTIC, SSOP-14, Counter;


型号：	935190320112
厂家：	NXP
描述：	IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDSO14, PLASTIC, SSOP-14, Counter 光电二极管
文件：	总7页 (文件大小：43K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT93

4-bit binary ripple counter

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

divide-by-two section and a

the device may be operated in various

counting modes. In a 4-bit ripple

counter the output Q₀must be

connected externally to input CP₁.

The input count pulses are applied to

clock input CP₀. Simultaneous

frequency divisions of 2, 4, 8 and 16

are performed at the Q₀, Q₁, Q₂and

Q₃outputs as shown in the function

table. As a 3-bit ripple counter the

input count pulses are applied to input

CP₁.

Simultaneous frequency divisions of

2, 4 and 8 are available at the Q₁, Q₂

and Q₃outputs. Independent use of

the first flip-flop is available if the reset

function coincides with reset of the

3-bit ripple-through counter.

FEATURES

divide-by-eight section. Each section

has a separate clock input (CP₀and

CP₁) to initiate state changes of the

counter on the HIGH-to-LOW clock

transition. State changes of the Q_n

outputs do not occur simultaneously

because of internal ripple delays.

Therefore, decoded output signals

are subject to decoding spikes and

should not be used for clocks or

strobes.

• Various counting modes

• Asynchronous master reset

• Output capability: standard

• I_CCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT93 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

no. 7A.

A gated AND asynchronous master

reset (MR₁and MR₂) is provided

which overrides both clocks and

resets (clears) all flip-flops.

The 74HC/HCT93 are 4-bit binary

ripple counters. The devices consist

of four master-slave flip-flops

Since the output from the

divide-by-two section is not internally

connected to the succeeding stages,

internally connected to provide a

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

UNIT

SYMBOL

PARAMETER

CONDITIONS

HCT

t_PHL/ t_PLH

f_max

propagation delay CP₀to Q₀

maximum clock frequency

C_L= 15 pF; V_CC= 5 V

100

3.5

MHz

C_I

input capacitance

C_PD

power dissipation capacitance per package

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF; V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC; for HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

CP₁

clock input 2^nd, 3^rdand 4^thsection (HIGH-to-LOW, edge-triggered)

asynchronous master reset (active HIGH)

not connected

2, 3

MR₁, MR₂

n.c.

4, 6, 7, 13

V_CC

positive supply voltage

GND

ground (0 V)

12, 9, 8, 11

Q₀to Q₃

CP₀

ﬂip-ﬂop outputs

clock input 1^stsection (HIGH-to-LOW, edge-triggered)

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

FUNCTION TABLE

OUTPUTS

COUNT

Q₀

Q₁

Q₂

Q₃

Fig.4 Functional diagram.

Notes

1. Output Q₀connected to CP₁.

H = HIGH voltage level

L = LOW voltage level

MODE SELECTION

RESET

OUTPUTS

INPUTS

MR₁MR₂Q₀

Q₁Q₂Q₃

count

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP₀to Q₀

125

155

190

2.0 Fig.6

4.5

6.0

_PHL/ t_PLHpropagation delay

CP₁to Q₁

135

170

205

2.0 Fig.6

4.5

6.0

_PHL/ t_PLHpropagation delay

CP₁to Q₂

185

230

280

2.0 Fig.6

4.5

6.0

_PHL/ t_PLHpropagation delay

CP₁to Q₃

245

305

370

2.0 Fig.6

4.5

6.0

t_PHL

propagation delay

MR_nto Q_n

155

195

235

2.0 Fig.7

4.5

6.0

t_THL/ t_TLHoutput transition time

110

2.0 Fig.6

4.5

6.0

t_rem

removal time

2.0 Fig.7

4.5

6.0

MR_nto CP₀, CP₁

t_W

pulse width

CP₀, CP₁

100

120

2.0 Fig.6

4.5

6.0

t_W

master reset pulse width 80

100

120

2.0 Fig.7

4.5

6.0

MR_n

f_max

maximum clock pulse

frequency

CP₀, CP₁

6.0

108

4.8

4.0

MHz 2.0 Fig.6

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

CP₀, CP₁

MR_n

0.60

0.40

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP₀to Q₀

4.5 Fig.6

4.5 Fig.7

4.5 Fig.6

4.5 Fig.7

4.5 Fig.6

4.5 Fig.7

_PHL/ t_PLHpropagation delay

CP₁to Q₁

_PHL/ t_PLHpropagation delay

CP₁to Q₂

_PHL/ t_PLHpropagation delay

CP₁to Q₃

t_PHL

propagation delay

MR_nto Q_n

_THL/ t_TLHoutput transition time

t_rem

t_W

removal time

MR_nto CP₀, CP₁

pulse width

CP₀, CP₁

t_W

master reset pulse width 16

MR_n

f_max

maximum clock pulse

frequency

MHz 4.5 Fig.6

CP₀, CP₁

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit binary ripple counter

74HC/HCT93

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the clock (CP_n) to output (Q_n) propagation delays, the clock pulse width, output

transition times and the maximum clock pulse frequency.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the master reset (MR_n) pulse width, the master reset to output (Q_n) propagation

delays and the master reset to clock (CP_n) removal time.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

相关型号：