935190350118 [NXP]

IC HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, SOT-338-1, SSOP-16, Shift Register;


型号：	935190350118
厂家：	NXP
描述：	IC HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, SOT-338-1, SSOP-16, Shift Register 光电二极管输出元件
文件：	总10页 (文件大小：69K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT165

8-bit parallel-in/serial-out shift

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

When PL is HIGH, data enters the register serially at the

D_sinput and shifts one place to the right

(Q₀→ Q₁→ Q₂, etc.) with each positive-going clock

transition. This feature allows parallel-to-serial converter

expansion by tying the Q₇output to the D_Sinput of the

succeeding stage.

FEATURES

• Asynchronous 8-bit parallel load

• Synchronous serial input

• Output capability: standard

• I_CCcategory: MSI

The clock input is a gated-OR structure which allows one

input to be used as an active LOW clock enable (CE) input.

The pin assignment for the CP and CE inputs is arbitrary

and can be reversed for layout convenience. The

LOW-to-HIGH transition of input CE should only take

place while CP HIGH for predictable operation. Either the

CP or the CE should be HIGH before the

GENERAL DESCRIPTION

The 74HC/HCT165 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

LOW-to-HIGH transition of PL to prevent shifting the data

when PL is activated.

The 74HC/HCT165 are 8-bit parallel-load or serial-in shift

registers with complementary serial outputs (Q₇and

Q₇) available from the last stage. When the parallel load

(PL) input is LOW, parallel data from the D₀to

APPLICATIONS

D₇inputs are loaded into the register asynchronously.

• Parallel-to-serial data conversion

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

PARAMETER

propagation delay

CONDITIONS

UNIT

HCT

t_PHL/ t_PLH

C_L= 15 pF; V_CC= 5 V

CP to Q_7,Q₇

PL to Q_7,Q₇

D₇to Q_7,Q₇

f_max

C_I

maximum clock frequency

input capacitance

3.5

MHz

C_PD

power dissipation capacitance per

package

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

asynchronous parallel load input (active LOW)

complementary output from the last stage

serial output from the last stage

clock input (LOW-to-HIGH edge-triggered)

ground (0 V)

Q₇

GND

D_s

serial data input

11, 12, 13, 14, 3, 4, 5, 6

D₀to D₇

parallel data inputs

clock enable input (active LOW)

positive supply voltage

V_CC

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

Fig.4 Functional diagram.

FUNCTION TABLE

OPERATING MODES

INPUTS

Q_nREGISTERS

OUTPUTS

Q₇Q₇

D_S

D₀-D₇

Q₀

Q₁-Q₆

parallel load

serial shift

L - L

H - H

↑

q₀-q₅

q₆

hold “do nothing”

q₀

q₁-q₆

q₇

Note

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition

q = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH clock transition

X = don’t care

↑ = LOW-to-HIGH clock transition

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

AC CHARACTERISTICS FOR HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CE, CP to Q₇, Q₇

165

205

250

2.0

4.5

6.0

Fig.6

_PHL/ t_PLHpropagation delay

PL to Q₇, Q₇

165

205

250

2.0

4.5

6.0

_PHL/ t_PLHpropagation delay

D₇to Q₇, Q₇

120

150

180

2.0

4.5

6.0

_THL/ t_TLHoutput transition

time

110

2.0

4.5

6.0

t_W

clock pulse width

HIGH or LOW

100

120

2.0

4.5

6.0

t_W

parallel load pulse

width; LOW

100

120

2.0

4.5

6.0

t_rem

t_su

removal time

PL to CP, CE

100 22

125

150

2.0

4.5

6.0

set-up time

D_sto CP, CE

100

120

2.0

4.5

6.0

set-up time

CE to CP;

CP to CE

100

120

2.0

4.5

6.0

set-up time

D_nto PL

100

120

2.0

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min. max.

t_h

hold time

D_sto CP, CE

D_nto PL

2.0

4.5

6.0

Fig.6

t_h

hold time

CE to CP

CP to CE

−17

−6

−5

2.0

4.5

6.0

f_max

maximum clock

pulse frequency

MHz

2.0

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

D_s

0.35

0.65

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CE, CP to Q₇, Q₇

4.5 Fig.6

_PHL/ t_PLHpropagation delay

PL to Q₇, Q₇

_PHL/ t_PLHpropagation delay

D₇to Q₇, Q₇

t_THL/ t_TLHoutput transition time

t_W

clock pulse width

HIGH or LOW

t_W

parallel load pulse

width; LOW

t_rem

t_su

t_h

removal time

PL to CP, CE

set-up time

D_sto CP, CE

set-up time

CE to CP; CP to CE

set-up time

D_nto PL

−1

−7

hold time

D_sto CP, CE; D_nto PL

t_h

hold time

CE to CP, CP to CE

f_max

maximum clock pulse

frequency

MHz 4.5 Fig.6

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

AC WAVEFORMS

The changing to output assumes internal Q₆

opposite state from Q₇.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the clock (CP) to output (Q₇or Q₇) propagation delays, the clock pulse width, the

output transition times and the maximum clock frequency.

The changing to output assumes internal Q₆

opposite state from Q₇.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q₇or Q₇) propagation

delays, the parallel load to clock (CP) and clock enable (CE) removal time.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the data input (D_n) to output (Q₇or Q₇) propagation delays when PL is LOW.

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit parallel-in/serial-out shift register

74HC/HCT165

CE may change only from HIGH-to-LOW while CP

is LOW.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.9 Waveforms showing the set-up and hold times from the serial data input (D_s) to the clock (CP) and clock

enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)

to the clock enable input (CE).

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.10 Waveforms showing the set-up and hold times from the data inputs (D_n) to the parallel load input (PL).

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

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