935191070112 [NXP]
IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP1-16, FF/Latch;
| 型号： | 935191070112 |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP1-16, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
1998 Apr 28
Supersedes data of 1997 Mar 18
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
FEATURES
• Wide supply voltage range of 1.2 to 3.6 V
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
• In accordance with JEDEC standard no. 8-1A.
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
The 74LVC109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (S ) and reset
D
(R ) inputs; also complementary Q and Q outputs.
D
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K inputs together.
• I category: flip-flops
CC
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t ≤ 2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
nCP to nQ, nQ
4.0
4.5
4.5
t
/t
ns
PHL PLH
C = 50 pF;
L
nS to nQ, nQ
D
V
CC
= 3.3 V
nR to nQ, nQ
D
f
Maximum clock frequency
Input capacitance
250
5.0
27
MHz
pF
max
C
I
1
C
Power dissipation capacitance per flip-flop
V = GND to V
I CC
pF
PD
NOTE:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )Σ (C × V
× f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
Σ (C × V
× f ) = sum of the outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVC109 D
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
16-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC109 D
74LVC109 DB
74LVC109 PW
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
74LVC109 DB
74LVC109PW DH
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1R
V
1
2
3
4
5
6
7
8
16
15
D
CC
2R
D
1J
1K
Asynchronous reset input
(active LOW)
1, 15
1R , 2R
D
D
14 2J
Synchronous inputs;
flip-flops 1 and 2
1CP
13 2K
12 2CP
2, 14, 3, 13 1J, 2J, 1K, 2K
1S
D
Clock input
2S
4, 12
5, 11
1CP, 2CP
11
D
1Q
1Q
(LOW-to-HIGH, edge-triggered)
10 2Q
Asynchronous set inputs
(active LOW)
1S 2S
D,
D
GND
9
2Q
6, 10
7, 9
8
1Q, 2Q
1Q, 2Q
GND
True flip-flop outputs
Complement flip-flop outputs
Ground (O V)
SV00517
16
V
CC
Positive supply voltage
2
1998 Apr 28
853–1947 19308
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
5
2
4
11
5
1S
D
S
S
S
D
1J
1CP
1K
2
4
3
1Q
1Q
6
7
10
J
14
12
6
7
Q
1J
1J
CP FF1
Q
K
C1
C1
R
D
3
1
13
15
9
1R
D
1K
R
1K
R
1
11 2S
D
S
D
2J
2CP
2K
14
12
13
2Q
2Q
J
10
9
Q
(a)
(b)
SV00519
FF2
Q
CP
K
LOGIC SYMBOL
R
D
5
11
2R
D
15
1S
2S
D
D
SV00520
2 1J
J
1Q 6
14 2J
Q
Q
2Q 10
4 1CP
CP
K
12 2CP
1Q 7
2Q 9
3 1K
13 2K
1R
2R
15
D
1
D
SV00518
LOGIC DIAGRAM
Q
Q
C
C
C
C
C
C
C
C
K
J
S
R
C
C
CP
SV00521
3
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
FUNCTION TABLE
INPUTS
OUTPUTS
nQ
OPERATING MODES
nS
nR
nCP
nJ
nK
nQ
D
D
Asynchronous set
Asynchronous reset
Undetermined
L
H
L
H
L
L
X
X
X
X
X
X
X
X
X
H
L
L
H
H
H
Toggle
H
H
H
H
H
H
H
H
↑
↑
↑
↑
h
l
l
q
L
q
H
L
Load “0” (reset)
Load “1” (set)
Hold “no change”
l
h
l
h
h
H
q
q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I
= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
↑ = LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MAX
MIN
2.7
1.2
0
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
3.6
V
CC
V
3.6
V
I
5.5
V
V
V
O
DC output voltage range
0
V
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +6.5
–50
UNIT
V
V
CC
I
IK
DC input diode current
DC input voltage
V t 0
mA
V
I
V
I
Note 2
–0.5 to +5.5
"50
I
DC output diode current
DC output voltage
V
O
uV or V t 0
mA
V
OK
CC
O
V
O
Note 2
= 0 to V
CC
–0.5 to V +0.5
CC
I
O
DC output source or sink current
V
O
"50
"100
mA
mA
°C
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*1.0
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
V
V
= 3.0V; V = V or V I
= –12mA
I = –24mA
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
10
I
IH
IL
O
V
OL
= 3.0V; V = V or V ; I = 100µA
GND
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND
"0.1
µA
µA
I
I
I
Quiescent supply current
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF; R = 500W; T
= –40_C to +85_C
r
f
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
UNIT
TYP
1
MIN
TYP
MAX
MIN
MAX
NO TAG
Propagation delay
nCP to nQ, nQ
t
/t
Figures 1, 3
Figures 2, 3
4.3
7.5
8.0
8.5
9.0
ns
ns
PHL PLH
Propagation delay
nS to nQ
D
t
4.5
PLH
nR to nQ
D
Propagation delay
nS to nQ
t
Figures 2, 3
5.2
2.0
9.0
10
ns
D
PHL
nR to nQ
D
Clock pulse width
HIGH or LOW
t
t
Figure 1
Figure 2
Figure 2
Figure 1
Figure 1
Figure 1
3.3
3.0
3.0
2.5
2.0
150
ns
ns
W
Set or reset pulse width
HIGH or LOW
W
Removal time
t
ns
rem
nS nR to nCP
D,
D
Set-up time
nJ, nK to CP
t
su
ns
Hold time
nJ, nK to nCP
t
h
ns
Maximum clock pulse
frequency
f
225
MHz
max
NOTE:
1. These typical values are at V = 3.3V and T
= 25°C.
amb
CC
5
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
AC WAVEFORMS
V
V
= 1.5 V at V ≥ 2.7 V; V = 0.5 × V at V < 2.7 V.
M
CC M CC CC
and V are the typical output voltage drop that occur with the output load.
OL
OH
V
V
I
l
nJ, nK
INPUT
nCP
INPUT
V
M
V
M
GND
GND
t
t
su
su
t
rem
t
t
h
V
l
h
1/f
max
V
nS
D
I
V
M
INPUT
GND
nCP
INPUT
V
t
t
rem
M
t
W
W
GND
V
l
t
W
t
t
nR
D
INPUT
PHL
PLH
V
M
V
OH
GND
nQ
OUTPUT
t
t
PHL
V
V
PLH
M
V
OH
V
OL
nQ
OUTPUT
V
M
V
OH
V
OL
nQ
OUTPUT
t
t
PLH
PHL
M
V
OH
V
OL
nQ
V
M
OUTPUT
t
t
PLH
PHL
V
OL
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
SV00523
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up,
the nCP to nJ, nK hold times
Figure 2. Set (nS ) and reset (nR ) input to output (nQ, nQ)
D D
propagation delays, the set and reset pulse widths
and the nR , nS to nCP removal time.
D
D
and the maximum clock pulse frequency.
TEST CIRCUIT
t
W
V
I
90%
S
90%
1
V
cc
2 < V
Open
GND
CC
V
V
M
M
NEGATIVE
PULSE
10%
10%
90%
0V
(t )
R
R
L
L
V
V
O
t
t
(t )
t
TLH
l
THL
TLH
f
r
PULSE
GENERATOR
D.U.T.
(t )
r
t
(t )
THL f
V
R
T
I
C
90%
M
L
POSITIVE
PULSE
V
V
M
10%
10%
t
W
0V
Test Circuit for Outputs
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
SWITCH POSITION
R = Load resistor; see AC CHARACTERISTICS for value.
L
TEST
S
1
V
CC
V
I
C = Load capacitance includes jig and probe capacitance:
See AC CHARACTERISTICS for value.
L
t
t
Open
< 2.7V
2.7–3.6V
≥ 4.5 V
V
CC
PLH/ PHL
2.7V
R = Termination resistance should be equal to Z
T
of
OUT
V
CC
pulse generators.
SV00904
Figure 3. Load circuitry for switching times.
6
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
7
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
8
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
9
1998 Apr 28
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04489
Document order number:
Philips
Semiconductors
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