935193810112 [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PDIP56, 0.600 INCH, PLASTIC, SOT-400, SDIP-56, Consumer IC:Other;
| 型号： | 935193810112 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PDIP56, 0.600 INCH, PLASTIC, SOT-400, SDIP-56, Consumer IC:Other 光电二极管 商用集成电路 |
| 文件： | 总75页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA837x family
I2C-bus controlled economy
PAL/NTSC and NTSC
TV-processors
1997 Jul 01
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
FEATURES
Available in all ICs:
• Vision IF amplifier with high sensitivity and good figures
for differential phase and gain
• PLL demodulator for the IF signal
• Alignment-free sound demodulator
GENERAL DESCRIPTION
• Flexible source selection with a CVBS input for the
internal signal and Y/C or CVBS input for the external
signal
The various versions of the TDA837x series are I2C-bus
controlled single-chip TV processors which are intended to
be applied in PAL/NTSC (TDA8374 and TDA8375) and
NTSC (TDA8373 and TDA8377) television receivers.
All ICs are available in an SDIP56 package and some
versions are also available in a QFP64 package. The ICs
are pin compatible so that with one application board
NTSC and PAL/NTSC (or multistandard together with the
SECAM decoder TDA8395) receivers can be built.
• Audio switch
• The output signal of the CVBS (Y/C) switch is externally
available
• Integrated chrominance trap and band-pass filters
(auto-calibrated)
• Luminance delay line integrated
• A symmetrical peaking circuit in the luminance channel
Functionally this IC series is split in to 2 categories:
• Black stretching of non-standard CVBS or luminance
• Versions intended to be used in economy TV receivers
signals
with all basic functions
• RGB control circuit with black current stabilization and
white point adjustment
• Versions with additional functions such as E-W
geometry control, horizontal and vertical zoom function
and YUV interface which are intended for TV receivers
with 110° picture tubes.
• Linear RGB inputs and fast blanking
• Horizontal synchronization with two control loops and
The various type numbers are given in Table 1.
alignment-free horizontal oscillator
• Slow start and slow stop of the horizontal drive pulses
• Vertical count-down circuit
The detailed differences between the various ICs are
given in Table 2.
• Vertical driver optimized for DC-coupled vertical output
stages
• I2C-bus control of various functions
• Low dissipation
• Small amount of peripheral components compared with
competition ICs.
Table 1 TV receiver versions
SDIP56 PACKAGE
QFP64 PACKAGE
ECONOMY MID/HIGH END
TV RECEIVERS
ECONOMY
MID/HIGH END
PAL only
TDA8374B
TDA8374 and TDA8374A
TDA8373
−
TDA8374BH
TDA8374AH
−
−
PAL/NTSC (SECAM)
NTSC
TDA8375 and TDA8375A
TDA8377 and TDA8377A
TDA8375AH
−
1997 Jul 01
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Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Table 2 Differences between the various ICs
IC VERSION (TDA)
8374 8374A(H) 8374B(H) 8375 8375A(H) 8377
CIRCUITS
8373
8377A
Multistandard IF
−
X
X
−
−
−
−
X
X
−
−
−
−
Automatic Volume Levelling
(AVL)
X
−
−
PAL decoder
−
−
X
−
X
−
−
−
X
X
X
X
−
−
−
−
X
X
X
X
−
−
−
−
X
X
X
X
−
−
−
−
X
X
X
X
−
X
X
X
X
−
−
−
−
−
SECAM interface
NTSC decoder
X
−
X
−
Colour matrix PAL/NTSC (Japan)
Colour matrix NTSC (USA/Japan)
YUV interface
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Horizontal geometry
Horizontal and vertical zoom
QUICK REFERENCE DATA
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
IP
supply voltage
−
−
8.0
−
−
V
supply current
110
mA
Input voltages
V48,49(rms)
video IF amplifiers sensitivity
(RMS value)
−
−
−
−
−
−
70
−
−
−
−
−
−
µV
mV
mV
V
V1(rms)
sound IF amplifiers sensitivity
(RMS value)
1.0
500
1.0
0.3
0.7
V2(rms)
external audio input voltage
(RMS value)
V11(p-p)
V10(p-p)
V23-25(p-p)
external CVBS/Y input voltage
(peak-to-peak value)
external chrominance input voltage
(burst amplitude) (peak-to-peak value)
V
RGB input voltage
V
(peak-to-peak value)
Output signals
V6(p-p)
IF video output voltage
(peak-to-peak value)
−
2.5
−
V
I54
tuner AGC output current range
0
−
5
mA
V
VoVSW
output signal level of video switch
(peak-to-peak value)
−
1.0
−
V30(p-p)
−(R − Y) output voltage
−
525
−
mV
(peak-to-peak value)
1997 Jul 01
3
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
V29(p-p)
PARAMETER
−(B − Y) output voltage
CONDITIONS
MIN.
TYP.
675
MAX.
UNIT
mV
−
−
−
−
−
−
(peak-to-peak value)
V28(p-p)
luminance output voltage
(peak-to-peak value)
1.4
2.0
V
V
V19-21(p-p)
RGB output signal amplitudes
(peak-to-peak value)
I40
horizontal output current
−
−
10
1
−
−
mA
mA
I46,47(p-p)
vertical output current
(peak-to-peak value)
I45(peak)
E-W output current (peak value)
TDA8375A,
TDA8377A,
TDA8375 and
TDA8377
−
1.2
−
mA
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA837xA
TDA837xH
SDIP56
QFP64
plastic shrink dual in-line package; 56 leads (600 mil)
SOT400-1
SOT319-1
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 × 20 × 2.7 mm; high stand-off height
1997 Jul 01
4
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
BLOCK DIAGRAM
GM2K86
o
1997 Jul 01
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
GM2K87
1997 Jul 01
6
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
GM2K8
o
1997 Jul 01
7
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
GM2K89
f
1997 Jul 01
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
PINNING
PIN
SYMBOL
DESCRIPTION
SDIP56
QFP64
SIF
1
2
10
11
sound IF input
AUDI
VCO1
VCO2
PLL
external audio input
IF VCO 1 tuned circuit
IF VCO 2 tuned circuit
PLL loop filter
3
13
4
14
5
15
IFVO
SCL
6
16
IF video output
7
17
serial clock input (I2C-bus)
serial data input/output (I2C-bus)
band gap decoupling
chrominance input
CVBS/Y input
SDA
8
18
DECBG
CHROMA
CVBS/Y
VP1
9
19
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27(2)
28
29
30
31
32
33(1)
34
35(1)
36
37
38
20
21
22 and 23
24
main supply voltage (+8 V)
internal CVBS input
ground
CVBSint
GND1
AUDO
DECFT
CVBSext
BLKIN
BO
25 and 26
27
audio output
28
decoupling filter tuning
external CVBS input
black current input
blue output
29
30
31
GO
32
green output
RO
33
red output
BCLIN
RI
34
beam current input
red input
35
GI
36
green input
BI
37
blue input
RGBIN
YIN
38
RGB insertion input
luminance input
39
YOUT
BYO
40
luminance output
(B − Y) output
45
RYO
46
(R − Y) output
RYI
47
(R − Y) input
BYI
48
(B − Y) input
SECref
XTAL1
XTAL2
LFBP
VP2
49
SECAM reference output
3.58 MHz crystal connection
4.43 MHz crystal connection
loop filter burst phase detector
50
51
52
53
horizontal oscillator supply voltage (+8 V)
CVBS output
CVBSO
54
1997 Jul 01
9
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
PIN
SYMBOL
DESCRIPTION
black peak hold capacitor
SDIP56
QFP64
BLPH
HOUT
FBI/SCO
PH2
39
40
41
42
43
44
45(2)
46
47
48
49
50
51
52
53
54
55
56
−
55
56
horizontal drive output
flyback input and sandcastle output
phase 2 filter/protection
phase 1 filter
57
58
PH1
59
GND2
EWD
VDOB
VDOA
IFIN1
IFIN2
EHT/PRO
VSAW
Iref
60 and 61
ground 2
62
63
64
1
east-west drive output
vertical drive output B
vertical drive output A
IF input 1
2
IF input 2
3
EHT/overvoltage protection input
vertical sawtooth capacitor
reference current input
AGC decoupling capacitor
tuner AGC output
4
5
DECAGC
AGCOUT
AUDEEM
DEC
6
7
8
audio deemphasis
9
decoupling sound demodulator
internally connected
internally connected
internally connected
internally connected
internally connected
i.c.
12
41
42
43
44
i.c.
−
i.c.
−
i.c.
−
i.c.
−
Notes
1. In the TDA8373 and TDA8377 pin 35 (4.43 MHz crystal) is internally connected and pin 33 is just a subcarrier output
which can be used as a reference signal for comb filter ICs.
2. In the TDA8373 and TDA8374 the following pins are different (SDIP56): Pin 27: not connected; Pin 45: AVL
capacitor.
1997 Jul 01
10
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
handbook, halfpage
SIF
AUDI
VCO1
VCO2
PLL
1
2
3
4
5
6
7
8
9
56 DEC
AUDEEM
55
54 AGCOUT
53 DEC
AGC
I
52
51
50
49
48
ref
IFVO
SCL
VSAW
EHT/PRO
IFIN2
SDA
DEC
BG
IFIN1
47 VDOA
46 VDOB
CHROMA 10
CVBS/Y 11
V
EWD
12
13
45
44
43
42
41
40
39
38
37
P1
CVBS
GND2
PH1
int
GND1 14
AUDO 15
DEC
TDA837x
PH2
FBI/SCO
HOUT
BLPH
CVBSO
16
17
18
19
20
FT
ext
CVBS
BLKIN
BO
GO
V
P2
36 LFBP
35 XTAL2
34 XTAL1
RO 21
BCLIN 22
RI 23
SEC
BYI
GI 24
33
32
31
30
ref
BI 25
RGBIN 26
YIN 27
RYI
RYO
29 BYO
YOUT 28
MGK284
Fig.5 Pin configuration (SDIP56).
11
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
IFIN1
IFIN2
1
2
3
4
5
6
7
8
9
48 BYI
RYI
47
EHT/PRO
VSAW
46 RYO
45 BYO
I
i.c.
44
ref
DEC
AGC
43 i.c.
42 i.c.
AGCOUT
AUDEEM
DEC
i.c.
41
TDA837xH
40 YOUT
39 YIN
38 RGBIN
37 BI
SIF 10
AUDI 11
i.c. 12
VCO1 13
VCO2 14
PLL 15
36 GI
RI
35
34 BCLIN
33 RO
IFVO 16
MGK285
Fig.6 Pin configuration (QFP64).
12
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
to a gated black level AGC. Because a black level clamp
pulse is required for this method of operation the circuit will
only switch to black level AGC in the internal mode.
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF amplifier contains 3 AC-coupled control stages with
a total gain control range which is higher than 66 dB.
The sensitivity of the circuit is comparable with that of
modern IF-ICs.
The circuits contain a second fast video identification
circuit which is independent of the synchronization
identification circuit. Consequently, search tuning is also
possible when the display section of the receiver is used
as a monitor. However, this identification circuit cannot be
made as sensitive as the slower sync identification circuit
(SL) and it is recommended to use both identification
outputs to obtain a reliable search system.
The video signal is demodulated by a PLL carrier
regenerator. This circuit contains a frequency detector and
a phase detector. During acquisition the frequency
detector will tune the VCO to the correct frequency.
The initial adjustment of the oscillator is realized via the
I2C-bus.
The identification output is applied to the tuning system via
the I2C-bus.
The input of the identification circuit is connected to pin 13,
the internal CVBS input (see Fig.1). This has the
advantage that the identification circuit can also be made
operative when a scrambled signal is received
[descrambler connected between the IF video output
(pin 6) and pin 13]. A second advantage is that the
identification circuit can be used when the IF amplifier is
not used (e.g. with built-in satellite tuners).
The switching, between SECAM L and L’, can also be
realized via the I2C-bus. After lock-in the phase detector
controls the VCO so that a stable phase relationship
between the VCO and the input signal is achieved.
The VCO operates at twice the IF frequency.
The reference signal for the demodulator is obtained by
using a frequency divider circuit.
The AFC output is obtained by using the VCO control
voltage of the PLL and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased by a factor of 3. The setting is realized with
the AFW bit.
The video identification circuit can also be used to identify
the selected CBVS or Y/C signal. The switching between
the two modes can be realized with bit VIM.
Video switches
Depending on the device type the AGC detector operates
on top-sync level (single standard versions) or on top-sync
and top-white level (multistandard versions).
The circuit has two CVBS inputs (CVBSint and CVBSext
)
and a Y/C input. When the Y/C input is not required pin 11
can be used as the third CVBS input. The switch
configuration is illustrated in Fig.7. The selection of the
various sources is made via the I2C-bus.
The demodulation polarity is switched via the I2C-bus.
The AGC detector time constant capacitor is connected
externally. This is mainly because of the flexibility of the
application. The time constant of the AGC system during
positive modulation is rather long, this is to avoid visible
variations of the signal amplitude. To improve the speed of
the AGC system, a circuit has been included which detects
whether the AGC detector is activated every frame period.
When, during 3 frame periods, no action is detected the
speed of the system is increased. For signals without
peak-white information the system switches automatically
The output signal of the CVBS switch is externally
available and can be used to drive the teletext decoder, the
SECAM add-on decoder and a comb filter.
In applications with comb filters a Y/C input is only possible
when additional switches are added. In applications
without comb filters the Y/C input signal can be switched
to the CVBS output.
1997 Jul 01
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Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
to luminance/
sync processing
IDENT
VIM
to chrominance
processing
VIDEO
IDENTIFICATION
+
S0 S0 S5
S1 S1 S6
S2 S3 S7
S4
S8
TDA837x
13
17
11
10
38
MGK301
CVBS
CVBS
CVBS/Y
CHROMA CVBSO
int
ext
Fig.7 Configuration CVBS switch and interfacing of video identification.
Sound circuit
Synchronization circuit
The sound band-pass and trap filters have to be
connected externally. The filtered intercarrier signal is fed
to a limiter circuit and is demodulated by a PLL
demodulator. This PLL circuit automatically tunes to the
incoming carrier signal, hence no adjustment is required.
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which operates at
50% of the amplitude.
The separated sync pulses are fed to the first phase
detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is
synchronized and can also be used for transmitter
identification. The circuit can be made less sensitive by
using the STM bit. This mode can be used during search
tuning to ensure that the tuning system will not stop at very
weak input signals. The first PLL has a very high static
steepness so that the phase of the picture is independent
of the line frequency.
The volume is controlled via the I2C-bus. The de-emphasis
capacitor has to be connected externally.
The non-controlled audio signal can be obtained from this
pin (pin 55) (via a buffer stage).
The FM demodulator can be muted via the I2C-bus. This
function can be used to switch-off the sound during a
channel change so that high output peaks are prevented
(also on the de-emphasis output).
The TDA8373 and TDA8374 contain an Automatic Volume
Levelling (AVL) circuit which automatically stabilizes the
audio output signal to a certain level which can be set by
the user via the volume control. This function prevents big
audio output fluctuations due to variations of the
modulation depth of the transmitter. The AVL function can
be activated via the I2C-bus.
The line oscillator operates at twice the line frequency.
The oscillator capacitor is internal. Because of the spread
of internal components an automatic calibration circuit has
been added to the IC. The circuit compares the oscillator
frequency with that of the crystal oscillator in the colour
decoder.
1997 Jul 01
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
This results in a free-running frequency which deviates
less than 2% from the typical value. When the IC is
switched on the horizontal output signal is suppressed and
the oscillator is calibrated as soon as all subaddress bytes
have been sent. When the frequency of the oscillator is
correct the horizontal drive signal is switched on. To obtain
a smooth switching on and switching off behaviour of the
horizontal output stage the horizontal output frequency is
doubled during switch-on and switch-off (slow start/stop).
During that time the duty cycle of the output pulse has such
a value that maximum safety is obtained for the output
stage.
For this reason this protection input can be used as ‘flash
protection’.
The drive pulses for the vertical sawtooth generator are
obtained from a vertical countdown circuit. This countdown
circuit has various windows depending on the incoming
signal (50 or 60 Hz and standard or non-standard).
The countdown circuit can be forced in various modes via
the I2C-bus. To obtain short switching times of the
countdown circuit during a channel change the divider can
be forced in the search window using the NCIN bit.
The vertical deflection can be set in the de-interlace mode
via the I2C-bus.
To protect the horizontal output transistor, the horizontal
drive is immediately switched off (via the slow stop
procedure) when a power-on reset is detected. The drive
signal is switched on again when the normal switch-on
procedure is followed, i.e. all subaddress bytes must be
sent and, after calibration, the horizontal drive signal will
be released again via the slow start procedure.
To avoid damage of the picture tube when the vertical
deflection fails, the guard output current of the TDA8350
and TDA8351 can be supplied to the beam current limiting
input. When a failure is detected the RGB outputs are
blanked and a bit is set (NDF) in the status byte of the
I2C-bus. When no vertical deflection output stage is
connected this guard circuit will also blank the output
signals. This can be overruled using the EVG bit.
When the coincidence detector indicates an out-of-lock
situation the calibration procedure is repeated.
The circuit has a second control loop to generate the drive
pulses for the horizontal driver stage. The horizontal
output is gated with the flyback pulse so that the horizontal
output transistor cannot be switched on during the flyback
time.
Chrominance and luminance processing
The circuit contains a chrominance band-pass and trap
circuit. The filters are realized by using gyrator circuits.
They are automatically calibrated by comparing the tuning
frequency with the crystal frequency of the decoder.
The luminance delay line and the delay for the peaking
circuit are also realized by using gyrator circuits.
Adjustments can be made to the horizontal shift, vertical
shift, vertical slope, vertical amplitude and the S-correction
via the I2C-bus. In the TDA8375A, TDA8377A, TDA8375
and TDA8377 the E-W drive can also be adjusted via the
I2C-bus. The TDA8375 and TDA8377 have a flexible zoom
adjustment possibility for the vertical and horizontal
deflection. When the horizontal scan is reduced to display
4 : 3 pictures on a 16 : 9 picture tube an accurate video
blanking can be switched on to obtain well defined edges
on the screen. The geometry processor has a differential
output for the vertical drive signal and a single-ended
output for the E-W drive (TDA8375A, TDA8377A,
TDA8375 and TDA8377). Overvoltage conditions (X-ray
protection) can be detected via the EHT tracking pin.
When an overvoltage condition is detected the horizontal
output drive signal will be switched off via the slow stop
procedure. However, it is also possible that the drive is not
switched off and that just a protection indication is given in
the I2C-bus output byte. The choice is made via the input
bit PRD. The ICs have a second protection input on the
phase-2 filter capacitor pin. When this input is activated the
drive signal is switched off immediately (without slow stop)
and switched on again via the slow start procedure.
The centre frequency of the chrominance band-pass filter
is 10% higher than the subcarrier frequency. This
compensates for the high frequency attenuation of the IF
saw filter. During SECAM reception the centre frequency
of the chrominance trap is reduced to obtain a better
suppression of the SECAM carrier frequencies. All ICs
have a black stretcher circuit which corrects the black level
for incoming video signals which have a deviation between
the black level and the blanking level (back porch).
The TDA8375A, TDA8377A, TDA8375 and TDA8377
have a defeatable coring function in the peaking circuit.
Some of the ICs have a YUV interface so that picture
improvement ICs such as the TDA9170 (contrast
improvement), TDA9177 (sharpness improvement) and
TDA4556 and TDA4566 (CTI) can be applied. When the
TDA4556 or TDA4566 is applied it is possible to increase
the gain of the luminance channel by using the GAI bit in
subaddress 03 so that the resulting RGB output signals
will not be affected.
1997 Jul 01
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
For a reliable calibration of the horizontal oscillator it is
very important that the crystal indication bits (XA and XB)
are not corrupted. For this reason the crystal bits can be
read in the output bytes so that the software can check the
I2C-bus transmission.
Colour decoder
Depending on the IC type the colour decoder can decode
NTSC signals (TDA8373 and TDA8377) or PAL/NTSC
signals (TDA8374 and TDA8375). The circuit contains an
alignment-free crystal oscillator, a killer circuit and two
colour difference demodulators. The 90° phase shift for the
reference signal is made internally.
RGB output circuit and black current stabilization
The colour difference signals are matrixed with the
luminance signal to obtain the RGB signals. Linear
amplifiers have been chosen for the RGB inputs so that the
circuit is suited for signals that are input from the SCART
connector. The insertion blanking can be switched on or off
using the IE1 bit. To ascertain whether the insertion pin
has a (continuous) HIGH level or not can be read via the
IN1 bit. The contrast and brightness control operate on
internal and external signals.
The TDA8373 and TDA8377 contain an Automatic Colour
Limiting (ACL) circuit which prevents over saturation
occurring when signals with a high chroma-to-burst ratio
are received. This ACL function is also available in the
TDA8374 and TDA8375, however, it is only active during
the reception of NTSC signals.
The TDA8373 and TDA8377 have a switchable colour
difference matrix (via the I2C-bus) so that the colour
reproduction can be adapted to the market requirements.
The output signal has an amplitude of approximately 2 V
(black-to-white) at nominal input signals and nominal
settings of the controls. To increase the flexibility of the IC
it is possible to add OSD and/or teletext signals directly at
the RGB outputs. This insertion mode is controlled via the
insertion input. The action to switch the RGB outputs to
black has some delay which must be compensated for
externally.
In the TDA8374 and TDA8375 the colour difference matrix
switches automatically between PAL and NTSC, however,
it is also possible to fix the matrix in the PAL standard.
The TDA8374 and TDA8375 can operate in conjunction
with the SECAM decoder TDA8395 so that an automatic
multistandard decoder can be realized. The subcarrier
reference output for the SECAM decoder can also be used
as a reference signal for a comb filter. Consequently, the
reference signal is continuously available when PAL or
NTSC signals are detected and only present during the
vertical retrace period when a SECAM signal is detected.
The black current stabilization is realized by using a
feedback from the video output amplifiers to the RGB
control circuit. The black current of the 3 guns of the
picture tube is internally measured and stabilized.
The black level control is active during 4 lines at the end of
the vertical blanking. The vertical blanking is adapted to
the incoming CVBS signal (50 or 60 Hz). When the flyback
time of the vertical output stage is longer than the 60 Hz
blanking time, or when additional lines need to be blanked
(e.g. for close captioning lines) the blanking can be
increased to the same value as that of the 50 Hz blanking.
This can be set using the LBM bit. The leakage current is
measured during the first line and, during the following
3 lines, the 3 guns are adjusted to the required level.
The maximum acceptable leakage current is ±100 µA.
The nominal value of the black current is 10 µA. The ratio
of the currents for the various guns automatically tracks
with the white point adjustment so that the background
colour is the same as the adjusted white point.
Which standard the TDA8374 and TDA8375 can decode
depends on the external crystals. The crystal to be
connected to pin 34 must have a frequency of 3.5 MHz
(NTSC-M, PAL-M or PAL-N). Pin 35 can handle crystals
with a frequency of 4.4 and 3.5 MHz. Because the crystal
frequency is used to tune the line oscillator, the value of
the crystal frequency must be communicated to the IC via
the I2C-bus. It is also possible to use the IC in the so called
‘3-norma’ mode for South America. In that event one
crystal must be connected to pin 35 and the other two to
pin 34. Switching between the 2 latter crystals must be
performed externally. Consequently, the search loop of the
decoder must be controlled by the microcontroller.
To prevent calibration problems of the horizontal oscillator
the external switching between the two crystals should be
performed when the oscillator is forced to pin 35.
1997 Jul 01
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
The input impedance of the black current measuring pin is
14 kΩ. To prevent the voltage on this pin exceeding the
supply voltage during scan an internal protection diode
has been included.
to ascertain whether the picture tube is warming up. As
soon as the current supplied to the measuring input
exceeds a value of 190 µA the stabilization circuit will be
activated. After a waiting time of approximately 0.8 s the
blanking and beam current limiting input pins are released.
The remaining switch-on behaviour of the picture is
determined by the external time constant of the beam
current limiting network.
When the TV receiver is switched on the black current
stabilization circuit is not active, the RGB outputs are
blanked and the beam current limiting input pin is
short-circuited. Only during the measuring lines will the
outputs supply a voltage of 4.2 V to the video output stage
I2C-bus specification
Table 3 Slave address (8A)
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
0
1
I/O
The slave address is identical for all types. The
on when the oscillator is calibrated. Each time before the
data in the IC is refreshed, the status bytes must be read.
If POR = 1, then the procedure given above must be
carried out to restart the IC. When this procedure is not
followed the horizontal frequency in the TDA8374 and
TDA8375 may be incorrect after power-up or a power dip.
subaddresses of the various types are slightly different.
The list of subaddresses for each type is given in
Tables 4, 6, 8 and 10.
START-UP PROCEDURE
Read the status bytes until POR = 0 and send all
subaddress bytes. The horizontal output signal is switched
1997 Jul 01
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
TDA8373
Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes.
Auto-increment mode available for subaddresses.
Table 4 Inputs
DATA BYTE
SUB
FUNCTION
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Control 0
00
01
02
03
08
09
0A
0B
0C
0D
0E
0F
10
11
INA
0
INB
0
INC
DL
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
0
STB
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
FOA
POC
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
0
FOB
0
0
0
Control 1
1
1
Hue
AVL
VIM
NCIN
VID
0
AKB
GAI
STM
LBM
EVG
PRD
0
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
0
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
0
Horizontal Shift (HS)
Vertical Slope (VS)
Vertical Amplitude (VA)
S-Correction (SC)
Vertical shift (VSH)
White point R
White point G
White point B
Peaking
SBL
0
0
0
MAT
0
0
0
Brightness
RBL
IE1
AFW
0
0
A5
A5
A5
A5
A5
A5
0
A4
A4
A4
A4
A4
A4
0
Saturation
0
Contrast
12
13
14
15
16
IFS
VSW
FAV
A6
0
AGC takeover
Volume control
Adjustment IF-PLL
Spare
SM
L’FA
0
Table 5 Output status bytes (note 1)
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00
01
02
POR
NDF
X
X
IN1
X
X
X
X
SL
IFI
XPR
AFA
X
CD2
AFB
ID2
CD1
SXA
ID1
CD0
SXB
ID0
IVW
Note
1. X = don’t care.
1997 Jul 01
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
TDA8374, TDA8374AH and TDA8374BH
Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes.
Auto-increment mode available for subaddresses.
Table 6 Inputs (notes 1 and 2)
DATA BYTE
SUB
FUNCTION
ADDRESS
D7
INA
FORF
AVL
VIM
NCIN
VID
0
D6
INB
FORS
AKB
GAI
STM
LBM
EVG
PRD
0
D5
INC
DL
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
D4
0
D3
FOA
POC
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
0
D2
FOB
CM2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
0
D1
XA
CM1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
0
D0
XB
CM0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
0
Control 0
00
01
02
03
08
09
0A
0B
0C
0D
0E
0F
10
11
Control 1
STB
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
Hue
Horizontal Shift (HS)
Vertical Slope (VS)
Vertical Amplitude (VA)
S-Correction (SC)
Vertical shift (VSH)
White point R
White point G
White point B
Peaking
SBL
0
0
0
MAT
0
0
0
Brightness
RBL
IE1
AFW
MOD
SM
L’FA
0
0
A5
A5
A5
A5
A5
A5
0
A4
A4
A4
A4
A4
A4
0
Saturation
0
Contrast
12
13
14
15
16
IFS
VSW
FAV
A6
AGC takeover
Volume control
Adjustment IF-PLL
Spare
0
Notes
1. The AVL and MOD bit are not available in the TDA8374A.
2. In the TDA8374B the AVL and MOD bit is also missing and the CM0 to CM2 and CD0 to CD2 bits have less
possibilities because this IC can only decode PAL or PAL/SECAM signals (when the TDA8395 is applied).
Table 7 Output status bytes (note 1)
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00
01
02
POR
NDF
X
FSI
IN1
X
X
X
X
SL
IFI
XPR
AFA
X
CD2
AFB
ID2
CD1
SXA
ID1
CD0
SXB
ID0
IVW
Note
1. X = don’t care.
1997 Jul 01
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
TDA8375 and TDA8375AH
Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for
subaddresses.
Table 8 Inputs
DATA BYTE
SUB
FUNCTION
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Control 0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
INA
INB
INC
DL
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
0
STB
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
FOA
POC
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
FOB
CM2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
XA
CM1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
XB
CM0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
Control 1
FORF FORS
Hue
HBL
VIM
0
AKB
GAI
0
Horizontal Shift (HS)
E-W width (EW)
E-W Parabola/Width (PW)
E-W Corner Parabola (CP)
E-W trapezium (TC)
Vertical Slope (VS)
Vertical Amplitude (VA)
S-Correction (SC)
Vertical shift (VSH)
White point R
0
0
0
0
0
0
NCIN
VID
HCO
SBL
0
STM
LBM
EVG
PRD
0
White point G
0
0
White point B
MAT
0
0
Peaking
0
Brightness
RBL
IE1
AFW
MOD
SM
L’FA
0
COR
0
A5
A5
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A4
A4
Saturation
Contrast
12
13
14
15
16
IFS
VSW
FAV
A6
0
AGC takeover
Volume control
Adjustment IF-PLL
Vertical zoom (VX)(1)
Note
1. The vertical zoom byte and the HBL bit are active only in the TDA8375.
Table 9 Output status bytes (note 1)
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00
01
02
POR
NDF
X
FSI
IN1
X
X
X
X
SL
IFI
XPR
AFA
X
CD2
AFB
ID2
CD1
SXA
ID1
CD0
SXB
ID0
IVW
Note
1. X = don’t care.
1997 Jul 01
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
TDA8377 and TDA8377A
Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for
subaddresses.
Table 10 Inputs
DATA BYTE
SUB
FUNCTION
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Control 0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
INA
0
INB
0
INC
DL
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
0
STB
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
FOA
POC
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
FOB
0
0
1
Control 1
1
1
Hue
HBL
VIM
0
AKB
GAI
0
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
Horizontal Shift (HS)
E-W width (EW)
E-W Parabola/Width (PW)
E-W Corner Parabola (CP)
E-W trapezium (TC)
Vertical Slope (VS)
Vertical Amplitude (VA)
S-Correction (SC)
Vertical shift (VSH)
White point R
0
0
0
0
0
0
NCIN
VID
HCO
SBL
0
STM
0
EVG
PRD
0
White point G
0
0
White point B
MAT
0
0
Peaking
0
Brightness
RBL
IE1
AFW
0
COR
0
A5
A5
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A4
A4
Saturation
Contrast
12
13
14
15
16
IFS
VSW
FAV
A6
0
AGC takeover
Volume control
Adjustment IF-PLL
Vertical zoom (VX)(1)
SM
L’FA
0
Note
1. The vertical zoom byte and the HBL bit are active only in the TDA8377.
Table 11 Output status bytes (note 1)
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00
01
02
POR
NDF
X
X
IN1
X
X
X
X
SL
IFI
XPR
AFA
X
CD2
AFB
ID2
CD1
SXA
ID1
CD0
SXB
ID0
IVW
Note
1. X = don’t care.
1997 Jul 01
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
INPUT CONTROL BITS
Table 12 Source select
SELECTED SIGNALS
(DECODER AND AUDIO)
INA
INB
INC
SWITCH OUTPUT
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
internal CVBS plus audio
external CVBS plus audio
Y/C plus external audio
CVBS3 plus external audio
Y/C plus internal audio
Y/C plus external audio
internal CVBS
external CVBS
Y/C (Y plus C)
CVBS3
internal CVBS
external CVBS
Table 13 Phase 1 (ϕ-1) time constant
FOA
FOB
MODE
0
0
1
1
0
1
0
1
normal
slow and gated
slow/fast and gated
fast
Table 14 Crystal indication
XA
XB
CRYSTAL
0
0
1
1
0
1
0
1
two 3.6 MHz crystals
one 3.6 MHz crystal (pin 34)
one 4.4 MHz crystal (pin 35)
3.6 MHz and 4.4 MHz crystals (pins 34 and 35)
Table 15 Forced field frequency TDA8374 and TDA8375
FORF
FORS
FIELD FREQUENCY
0
0
1
1
0
1
0
1
auto (60 Hz when line not synchronized)
60 Hz; note 1
keep last detected field frequency
auto (50 Hz when line not synchronized)
Note
1. When switched to this mode while locked to a 50 Hz signal, the divider will only switch to forced 60 Hz when an
out-of-sync is detected in the horizontal PLL.
1997 Jul 01
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Table 16 Interlace
Table 22 Black current stabilization
DL
STATUS
AKB
STABILIZATION
0
1
interlace
0
1
black-current stabilization on
black-current stabilization off
de-interlace
Table 17 Standby
Table 23 Video identification mode
STB
MODE
VIM
VIDEO IDENT MODE
0
1
standby
normal
0
video identification coupled to the internal
CVBS input (pin 13)
1
video identification coupled to the selected
CVBS input
Table 18 Synchronization mode
POC
MODE
Table 24 Gain of luminance channel
0
1
synchronization active
GAI
GAIN
synchronization not active
0
normal gain of luminance channel
[V27 = 1.0 V (b-w)]
Table 19 Colour decoder mode
1
high gain of luminance channel
[V27 = 0.45 V (p-p)]
CM2 CM1 CM0
DECODER MODE
0
0
0
not forced, own intelligence, two
crystals
Table 25 Vertical divider mode
0
0
1
forced crystal pin 34
(PAL/NTSC)
NCIN
VERTICAL DIVIDER MODE
0
1
normal operation of the vertical divider
vertical divider switched to search window
0
0
1
1
1
0
0
1
0
forced crystal pin 34 (PAL)
forced crystal pin 34 (NTSC)
forced crystal pin 35
(PAL/NTSC)
Table 26 Search tuning mode
STM
SEARCH TUNING MODE
1
1
1
0
1
1
1
0
1
forced crystal pin 35 (PAL)
forced crystal pin 35 (NTSC)
forced SECAM crystal pin 35
0
1
normal operation
reduced sensitivity of the coincidence
detector (bit SL)
Table 20 Automatic volume levelling
Table 27 Video identification mode
(TDA8373 and TDA8374)
VID
VIDEO IDENT MODE
AVL
LEVEL
0
video identification switches phase 1 loop on
and off
0
1
automatic volume levelling not active
automatic volume levelling active
1
video identification not active
Table 21 RGB blanking mode (TDA8375 and TDA8377)
Table 28 Long blanking mode (TDA8374 and TDA8375)
HBL
MODE
LBM
BLANKING MODE
0
normal blanking with horizontal blanking
pulse
0
1
blanking adapted to standard (50 or 60 Hz)
fixed blanking in accordance with 50 Hz
standard
1
wider blanking to obtain well defined edges
1997 Jul 01
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Table 29 EHT tracking mode (TDA8375 and TDA8377)
Table 36 Noise coring peaking
(TDA8375 and TDA8377))
HCO
TRACKING MODE
COR
MODE
noise coring off
0
1
EHT tracking only on vertical
0
1
EHT tracking on vertical and E-W
noise coring on
Table 30 Enable vertical guard (RGB blanking)
Table 37 Enable fast blanking
EVG
VERTICAL GUARD MODE
vertical guard not active
vertical guard active
IE1
0
FAST BLANKING
0
1
fast blanking not active
fast blanking active
1
Table 31 Service blanking
Table 38 AFC window
SBL
SERVICE BLANKING MODE
AFW
AFC WINDOW
0
1
service blanking off
service blanking on
0
1
normal window
enlarged window
Table 32 Overvoltage input mode
Table 39 IF sensitivity
PRD
OVERVOLTAGE MODE
IFS
IF SENSITIVITY
normal sensitivity
reduced sensitivity
0
1
overvoltage detection mode
overvoltage protection mode
0
1
Table 33 PAL/NTSC or NTSC matrix
(TDA8374 and TDA8375)
Table 40 Modulation standard (TDA8374 and TDA8375)
MAT
MATRIX
MOD
MODULATION
negative modulation
positive modulation
0
matrix adapted to standard
(NTSC = Japanese)
0
1
1
PAL matrix
Table 41 Video mute
Table 34 PAL/NTSC or NTSC matrix
VSW
STATE
(TDA8373 and TDA8377)
0
1
normal operation
MAT
MATRIX
IF video signal switched off
0
1
Japanese matrix
USA matrix
Table 42 Sound mute
SM
STATE
Table 35 RGB blanking
0
1
normal operation
sound muted
RBL
MODE
0
1
blanking not active
blanking active
1997 Jul 01
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Table 43 Fixed audio volume
Table 50 Output vertical guard
FAV
STATE
normal volume control
audio output level fixed
NDF
VERTICAL OUTPUT STAGE
vertical output stage OK
failure in vertical output stage
0
1
0
1
Table 44 Demodulator frequency adjustment
Table 51 Indication RGB insertion
L’FA
STATE
normal IF frequency
frequency shift for L’ standard
IN1
0
RGB INSERTION
0
1
no insertion
insertion
1
OUTPUT CONTROL BITS
Table 45 Power-on-reset
POR
Table 52 Output video identification
IFI
VIDEO SIGNAL
0
1
no video signal identified
video signal identified
MODE
0
1
normal mode
power-down mode
Table 53 AFC output
Table 46 Field frequency (TDA8374 and TDA8375)
AFA
AFB
CONDITION
0
0
1
1
0
1
0
1
outside window; too low
FSI
FREQUENCY
outside window; too high
0
1
50 Hz
60 Hz
inside window; below reference
inside window; above reference
Table 47 Phase 1 lock indication
Table 54 Crystal indication
SL
0
INDICATION
SXA
SXB
CRYSTAL
not locked
locked
0
0
1
1
0
1
0
1
two 3.6 MHz crystals
one 3.6 MHz crystal
1
Table 48 X-ray protection
one 4.4 MHz crystal
3.6 MHz and 4.4 MHz crystals
XPR
OVERVOLTAGE
no overvoltage detected
overvoltage detected
0
1
Table 55 Condition vertical divider
IVW
VIDEO SIGNAL
Table 49 Colour decoder mode (TDA8374 and TDA8375)
0
1
no standard video signal detected
standard video signal detected
(525 or 625 lines)
CD2
CD1
CD0
STANDARD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no colour standard identified
NTSC with crystal at pin 34
PAL with crystal at pin 35
SECAM
NTSC with crystal at pin 35
PAL with crystal at pin 34
spare
spare
1997 Jul 01
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Table 56 IC version indication
ID2
ID1
ID0
STANDARD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TDA8373
TDA8377
TDA8374B
TDA8374A
TDA8374
TDA8377A
TDA8375A
TDA8375
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
supply voltage
MIN.
MAX.
9.0
UNIT
VP
−
V
Tstg
Tamb
Tsld
Tj
storage temperature
−25
0
+150
70
°C
°C
°C
°C
V
operating ambient temperature
soldering temperature
for 5 s
−
260
operating junction temperature
electrostatic handling
−
150
Ves
HBM; all pins; notes 1 and 2
MM; all pins; notes 1 and 3
−2000
−200
+2000
+200
V
Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
3. Machine Model (MM): R = 0 Ω; C = 200 pF.
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The number of the quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9397 750 00192.
Latch-up
• Itrigger ≥ 100 mA or ≥1.5VP(max)
• Itrigger ≤ −100 mA or ≤−0.5VP(max)
.
1997 Jul 01
26
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; the pin numbers given refer to the SDIP56 package; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
MAIN SUPPLY (PIN 12)
VP1
IP1
supply voltage
supply current
total power dissipation
7.2
8.0
8.8
V
−
−
110
900
−
−
mA
Ptot
mW
HORIZONTAL OSCILLATOR SUPPLY (PIN 37)
VP2
IP2
supply voltage
supply current
7.2
8.0
6
8.8
V
−
−
mA
IF circuit
VISION IF AMPLIFIER INPUTS (PINS 48 AND 49)
Vi(rms)
input sensitivity (RMS value)
note 1
fi = 38.90 MHz
−
70
70
70
2
100
100
100
−
µV
µV
µV
kΩ
pF
dB
mV
fi = 45.75 MHz
fi = 58.75 MHz
−
−
Ri
input resistance (differential)
input capacitance (differential)
voltage gain control range
note 2
−
Ci
note 2
−
3
−
∆Gv
64
100
−
−
Vi(max)(rms)
maximum input signal
(RMS value)
150
−
PLL DEMODULATOR (PLL FILTER ON PIN 5); note 3
fPLL
PLL frequency range
PLL catching range
PLL acquisition time
32
−
−
60
−
MHz
MHz
ms
fcr(PLL)
tacq(PLL)
∆fVCO(T)
2
−
−
20
−
VCO frequency variation with
temperature
note 4
−
tbf
kHz/K
ftune(VCO)
VCO tuning range
via the I2C-bus
−
−
2.5
20
−
−
MHz
kHz
∆fDAC
frequency variation per step of
the DAC (A0 to A6)
fshift(L’)
frequency shift with the L’ FA bit
−
5.5
−
MHz
1997 Jul 01
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIDEO AMPLIFIER OUTPUT (PIN 6); note 5
Vo
zero signal output level
negative modulation;
note 6
−
−
4.7
−
−
V
positive modulation; note 6
negative modulation
2.0
2.0
4.5
V
V
V
V6(ts)
V6(w)
top sync level
white level
1.9
2.1
positive modulation when
available
−
−
∆V6
difference in amplitude between
negative and positive
modulation
−
0
15
%
Zo
video output impedance
−
50
−
−
Ω
Ibias
internal bias current of NPN
1.0
−
mA
emitter follower output transistor
Isource(max)
B
maximum source current
−
−
5
mA
bandwidth of demodulated
output signal
at −3 dB
6
9
−
MHz
Gdiff
differential gain
note 7
−
−
−
−
−
2
5
5
5
−
−
%
deg
%
V
ϕdiff
differential phase
video non-linearity
white spot clamp level
notes 4 and 7
note 8
−
NLvid
Vclamp
Nth(clamp)
−
5.3
1.7
noise inverter threshold clamp
level
note 9
V
Nins
noise inverter insertion level
intermodulation
blue
note 9
−
2.6
−
V
δ
notes 4 and 10
Vo = 0.92 or 1.1 MHz
Vo = 2.66 or 3.3 MHz
Vo = 0.92 or 1.1 MHz
Vo = 2.66 or 3.3 MHz
notes 4 and 11
Vi = 10 mV
60
60
56
60
66
66
62
66
−
−
−
−
dB
dB
dB
dB
yellow
S/N
signal-to-noise ratio
52
52
−
60
−
−
−
−
dB
at end of control range
note 4
61
dB
V6(rc)
residual carrier signal
5.5
2.5
mV
mV
V6(2H)
residual 2nd harmonic of carrier note 4
signal
−
1997 Jul 01
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF AND TUNER AGC; note 12
Timing of IF-AGC with a 2.2 µF capacitor (pin 53)
modulated video interference
30% AM for 1 to 100 mV;
0 to 200 Hz (system B/G)
−
−
−
10
%
tres(IFinc)
response time to an IF input
signal amplitude increase of
52 dB
positive (when available)
and negative modulation
2
−
ms
tres(IFdec)
response to an IF input signal
amplitude decrease of 52 dB
negative modulation
−
−
50
−
−
ms
ms
positive modulation (when
available)
100
I53
allowed leakage current of the
AGC capacitor
negative modulation
−
−
−
−
10
µA
positive modulation (when
available)
200
nA
Tuner take-over adjustment (via I2C-bus)
Vi(min)(rms)
minimum starting level for tuner
take-over (RMS value)
−
0.4
80
0.8
mV
mV
Vi(max)(rms)
maximum starting level for tuner
take-over (RMS value)
40
−
Tuner control output (pin 54)
VoAGC(max) maximum tuner AGC output
maximum tuner gain;
note 2
−
−
5
−
−
−
VP + 1
300
−
V
voltage
Vo(sat)
output saturation voltage
minimum tuner gain;
I54 = 2 mA
mV
mA
IoAGC(max)
maximum tuner AGC output
swing
ILI(RF)
leakage current RF AGC
−
−
1
4
µA
∆Vi
input signal variation for a
0.5
2
dB
control current variation of 1 mA
AFC OUTPUT (VIA I2C-BUS); note 13
RESAFC
wsen
AFC resolution
−
2
−
bits
kHz
kHz
window sensitivity
65
195
80
240
100
300
wsenL
window sensitivity in large
window mode
VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS)
td
delay time of identification after
the AGC has stabilized on a
new transmitter
−
−
10
ms
1997 Jul 01
29
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Sound circuit
DEMODULATOR PART
Vi(crPLL)(rms)
input limiting voltage for PLL
catching range (RMS value)
−
1
2
mV
fcr(PLL)
Ri
PLL catching range
input resistance
input capacitance
AM rejection
note 14
4.2
−
−
6.8
−
MHz
kΩ
note 2
note 2
8.5
−
Ci
−
5
pF
AMR
Vi = 50 mV (RMS); note 15 60
66
−
dB
DE-EMPHASIS
Vo(rms)
output signal amplitude
(RMS value)
note 14
−
500
−
mV
Ro
VO
output resistance
DC output voltage
−
−
15
3
−
−
kΩ
V
AUDIO ATTENUATOR CIRCUIT
Vo(rms)
controlled output signal
amplitude (RMS value)
at −6 dB; note 14
500
300
−
700
400
500
900
500
−
mV
mV
mV
VoAVL(rms)
VoFAV(rms)
output signal level when AVL is note 16
activated (RMS value)
output signal level when FAV is note 14
activated (RMS value)
Ro
output resistance
DC output voltage
−
−
−
−
−
−
−
−
500
3.3
−
−
Ω
VO
−
V
THD
total harmonic distortion
note 17
0.5
tbf
−
%
FAV = 1; note 18
note 4
−
%
PSRR
S/Nint
power supply ripple rejection
internal signal-to-noise ratio
external signal-to-noise ratio
tbf
60
80
−
dB
dB
dB
dB
notes 4 and 19
notes 4 and 19
notes 4 and 20
−
S/Next
Tdep(out)
−
temperature dependancy of
output level
tbf
CR
control range
tbf
80
tbf
dB
dB
VCstep
step size volume control
control curve
−
1.5
−
see Fig.8
−
OSS
Vshift
suppression of output signal
when the mute is active
−
−
80
10
dB
DC shift of the output level when
the mute is activated
50
mV
EXTERNAL AUDIO INPUT
Vi(rms)
input signal amplitude
(RMS value)
−
−
500
25
1500
mV
Ri
input resistance
−
kΩ
1997 Jul 01
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
12
MAX.
UNIT
dB
Gv(in-out)
voltage gain between input and maximum volume
output
−
−
−
αct
crosstalk between audio signals
60
−
AUTOMATIC VOLUME LEVELLING CIRCUIT (TDA8373 AND TDA8374 ONLY; CAPACITOR CONNECTED TO PIN 45)
Gmax
Gmin
gain
maximum boost; note 16
minimum boost
−
−
−
−
−
−
6
−
−
−
−
−
−
dB
dB
mA
nA
V
gain
−14
1
Iatt
attack charge current
decay discharge current
control voltage
control voltage
Idec
200
1
Vctrl(max)
Vctrl(min)
maximum boost
minimum boost
5
V
CVBS, Y/C, RGB, CD inputs and luminance input and output
CVBS AND Y/C SWITCH (PINS 11, 13, 17 AND 38)
V11(p-p)
CVBS or Y input voltage
(peak-to-peak value)
note 21
−
1.0
1.4
V
I17
CVBS input current
−
4
−
−
µA
SSCVBS
suppression of non-selected
CVBS input signal
notes 4 and 22
notes 2 and 23
50
−
dB
V10(p-p)
chrominance input voltage
(burst amplitude) (peak-to-peak
value)
−
−
0.3
1.0
0.45
V
V
V38(p-p)
output signal amplitude
(peak-to-peak value)
−
Zo
output impedance
top sync level
−
−
−
250
Ω
Vsync
2.5
−
V
RGB INPUTS (PINS 23, 24 AND 25)
V23-25(p-p)
input signal amplitude for an
note 24
note 4
−
0.7
0.8
V
output signal of 2 V
(black-to-white) (peak-to-peak
value)
V23-25(p-p)
input signal amplitude before
clipping occurs (peak-to-peak
value)
1.0
−
−
−
V
∆Vo
difference between black level
of internal and external signals
at the outputs
−
20
mV
I23-25
input currents
note 2
note 4
−
−
0.1
0
1
µA
∆td
delay difference for the three
channels
−
ns
FAST BLANKING (PIN 26)
Vi
input voltage
no data insertion
data insertion
insertion
−
−
−
−
0.3
−
V
V
V
0.9
−
V26(max)
maximum input pulse
3.0
1997 Jul 01
31
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
50
UNIT
ns
∆td(blank,RGB) delay difference of blanking and note 4
−
−
−
RGB signals
tsw
switching speed of blanking
circuit
10
−
ns
I26
input current
−
−
−
0.2
mA
dB
SSint
suppression of internal RGB
signals
insertion; fi = 0 to 5 MHz;
notes 4 and 22
55
−
SSext
suppression of external RGB
signals
no insertion;
fi = 0 to 5 MHz;
notes 4 and 22
−
55
−
−
dB
V
Vi
input voltage to insert black level
at the RGB outputs to facilitate
‘On Screen Display’ signals
being applied to the outputs
4
−
td(blank-RGB)
delay between blanking input
and RGB outputs
−
−
80
ns
COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32)
V31(p-p)
V32(p-p)
I31,32
input signal amplitude (R − Y)
(peak-to-peak value)
note 2
note 2
note 2
−
−
−
1.05
1.35
0.1
−
V
input signal amplitude (B − Y)
(peak-to-peak value)
−
V
input current for both inputs
1.0
µA
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); note 25
V27,28
output signal amplitude
(black-to-white)
−
1
−
V
Chrominance filters
CHROMINANCE TRAP CIRCUIT; note 26
ftrap
trap frequency
−
−
fosc
2
−
−
−
−
MHz
QF
trap quality factor
colour subcarrier rejection
trap frequency
note 27
CSR
20
−
dB
ftrap(SECAM)
during SECAM reception
−
4.3
MHz
CHROMINANCE BAND-PASS CIRCUIT
fc
centre frequency
−
−
1.1fosc
3
−
−
MHz
Qbp
band-pass quality factor
Luminance processing
Y DELAY LINE
td(Y)
delay time
note 4
−
480
−
−
ns
Bdel(int)
bandwidth of internal delay line note 4
8
−
MHz
PEAKING CONTROL; note 28
tW
width of preshoot or overshoot
at 50% of pulse; note 8
−
160
−
ns
1997 Jul 01
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
Sc(th)
PARAMETER
CONDITIONS
MIN.
TYP.
50
MAX.
UNIT
peaking signal compression
threshold
−
−
IRE
OS
overshoot at maximum peaking positive
negative
−
−
−
45
80
1.8
−
−
−
%
%
neg/pos
ratio of negative and positive
overshoots
peaking control curve
16 steps
see Fig.9
15
NOISE CORING STAGE
S
coring range
−
−
IRE
BLACK LEVEL STRETCHER; note 29
BLshift(max)
BLshift
maximum black level shift
level shift
15
−1
−1
6
21
0
27
+1
+3
10
IRE
IRE
IRE
IRE
at 100% of peak white
at 50% of peak white
at 15% of peak white
−
8
Horizontal and vertical synchronization and drive circuits
SYNC VIDEO INPUT (PINS 11, 13 AND 17)
V11,13,17
SLHS
sync pulse amplitude
note 2
50
−
300
50
350
−
mV
%
slicing level for horizontal sync
slicing level for vertical sync
note 30
note 30
SLVS
−
30
−
%
HORIZONTAL OSCILLATOR
ffr
free running frequency
−
−
15625
−
Hz
%
∆ffr
spread on free running
frequency
−
±2
∆f/∆VP
frequency variation with respect VP = 8.0 V ±10%; note 4
to the supply voltage
−
−
0.2
0.5
80
%
∆f(max)(T)
maximum frequency variation
with temperature
Tamb = 0 to 70 °C; note 4
−
Hz
FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 43); note 31
fhr(PLL)
fcr(PLL)
S/N
holding range PLL
catching range PLL
−
±0.9
±0.9
20
±1.2
−
kHz
kHz
dB
note 4
±0.6
−
signal-to-noise ratio of the video
input signal at which the time
constant is switched
−
HYS
hysteresis at the switching point
−
1
−
dB
SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 42)
∆ϕi/∆ϕo
control sensitivity
−
150
12
−
−
µs/µs
µs
tcr
control range from start of
horizontal output to flyback at
nominal shift position
11
tshift
horizontal shift range
63 steps
±2
−
−
µs
1997 Jul 01
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
∆ϕ
PARAMETER
CONDITIONS
MIN.
TYP.
5.3
MAX.
UNIT
control sensitivity for dynamic
phase compensation
−
6
−
−
−
1
µs/V
Vprot
voltage to switch-on the flash
protection
note 32
−
−
V
Ii(prot)
input current during protection
mA
HORIZONTAL OUTPUT (PIN 40); note 33
VOL
LOW level output voltage
Io = 10 mA
−
−
−
0.3
V
Io(max)
maximum allowed output
current
10
−
mA
Vo(max)
maximum allowed output
voltage
−
−
VP
V
δ
duty factor
note 4
−
−
−
50
75
2fH
−
−
−
%
Vo = HIGH
%
fsw
tsw
frequency during switch-on and
switch-off
Hz
switch-on time
−
−
−
50
−
−
−
ms
ms
ms
maximum RGB drive
minimum RGB drive
100
50
FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT (PIN 41)
Ii(fb)
required input current during the note 4
flyback pulse
100
−
300
µA
V41
output voltage
during burst key
4.8
1.8
2.6
5.3
2.0
3.0
5.8
2.2
3.4
V
V
V
during blanking
Vi(clamp)
tW
clamped input voltage during
flyback
pulse width
burst key pulse
3.3
−
3.5
14
3.7
−
µs
vertical blanking; note 34
lines
µs
td(bk-sync)
delay of start of burst key to start
of sync
5.2
5.4
5.6
VERTICAL OSCILLATOR; TDA8373 AND TDA8377 OPERATING AT 60 HZ; note 35
ffr
free running frequency
frequency locking range
divider value not locked
locking range
−
50/60
−
Hz
flock
45
−
−
64.5
−
Hz
625/525
lines
LR
488
−
722
lines/
frame
VERTICAL RAMP GENERATOR (PINS 51 AND 52)
V51(p-p)
sawtooth amplitude
(peak-to-peak value)
VS = 1FH;
C = 100 nF; R = 39 kΩ
−
3.5
−
V
Idch
Ich
discharge current
−
−
1
−
−
mA
charge current set by external
resistor
note 36
19
µA
Vslope
vertical slope
control range (63 steps)
−20
−
+20
%
1997 Jul 01
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
∆Ich
VrampL
PARAMETER
CONDITIONS
f = 60 Hz
MIN.
TYP.
20
MAX.
UNIT
charge current increase
−
−
−
−
%
LOW voltage level of ramp in
the normal or expand mode
2.07
V
VERTICAL DRIVE OUTPUTS (PINS 46 AND 47)
Io(dif)(p-p)
differential output current
(peak-to-peak value)
VA = 1FH
−
0.95
−
−
mA
ICM
common mode current
output voltage range
−
400
µA
V46,47
0
−
4.0
V
EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 50)
∆V50
mscan
vsen
input voltage range
1.2
−5
−
−
2.8
+5
−
V
scan modulation range
vertical sensitivity
−
%
6.3
−6.3
−
%/V
%/V
µA
V
EWsen
Ieq
E-W sensitivity
when switched on
note 32
−
−
E-W equivalent output current
overvoltage detection level
+100
−
−100
−
V50
3.9
DE-INTERLACE
ffd
first field delay
−
0.5H
−
E-W WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377); note 37
CR
control range
63 steps
100
0
−
−
−
−
65
%
Ieq
equivalent E-W output current
E-W output voltage range
E-W output current range
700
8.0
µA
V
VoEW
IoEW
1.0
0
1200
µA
E-W PARABOLA/WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377)
CR
Ieq
control range
63 steps
0
0
−
−
22
%
equivalent E-W output current
E-W = 3FH
440
µA
E-W CORNER/PARABOLA (TDA8375A, TDA8377A, TDA8375 AND TDA8377)
CR
Ieq
control range
63 steps
−43
−
−
0
0
%
equivalent E-W output current
PW = 3FH; E-W = 3FH
−190
µA
E-W TRAPEZIUM (TDA8375A, TDA8377A, TDA8375 AND TDA8377)
CR
Ieq
control range
63 steps
−5
−
−
+5
%
equivalent E-W output current
−100
+100
µA
VERTICAL AMPLITUDE
CR
control range
63 steps; SC = 00H
SC = 00H
80
−
−
120
%
Ieq(dif)(p-p)
equivalent differential vertical
drive output current
760
1140
µA
(peak-to-peak value)
VERTICAL SHIFT
CR
control range
63 steps
−5
−
−
+5
%
Ieq(dif)
equivalent differential vertical
drive output current
−50
+50
µA
1997 Jul 01
35
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
S-CORRECTION
CR
control range
63 steps
0
−
30
%
VERTICAL EXPAND (ZOOM) MODE (TDA8375 AND TDA8377); note 38
Output current variation compared with nominal scan
∆Io
vertical expand factor
0.75
1.38
A
A
Io(lim)
output current limiting and RGB
blanking
1.08
Colour demodulation part
CHROMINANCE AMPLIFIER
CRACC
ACC control range
note 39
26
−
−
−
dB
dB
∆VACC
change in amplitude of the
output signals over the ACC
range
−
2
thon
threshold colour killer ON
hysteresis colour killer OFF
−30
−
−
−
dB
dB
hysoff
at strong signal conditions;
−
+3
S/N ≥ 40 dB; note 4
at noisy input signals;
note 4
−
−
+1
−
dB
ACL CIRCUIT; note 40
chrominance burst ratio at which
the ACL starts to operate
3.0
−
REFERENCE PART
Phase-locked loop; note 41
fcr
frequency catching range
±360
±600
−
Hz
∆ϕ
phase shift for a ±400 Hz
deviation of the oscillator
frequency
note 4
−
−
2
deg
Oscillator
TCosc
temperature coefficient of the
oscillator frequency
note 4
−
−
2.0
2.5
Hz/K
Hz
∆fosc
oscillator frequency deviation
with respect to the supply
VP = 8 V ±10%; note 4
−
250
Rneg(min)
CL(max)
minimum negative resistance
maximum load capacitance
−
−
−
−
1
kΩ
15
pF
HUE CONTROL
CRhue
hue control range
hue control curve
63 steps
±35
±40
−
deg
see Fig.10
1997 Jul 01
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
∆hue
∆hue(T)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
hue variation for ±10% VP
note 4
amb = 0 to 70 °C; note 4
−
−
0
0
−
−
deg
deg
hue variation with temperature
T
DEMODULATORS (PINS 29 AND 30)
V30(p-p)
V29(p-p)
G
(R − Y) output signal amplitude TDA8374 and TDA8375;
(peak-to-peak value) note 42
(B − Y) output signal amplitude TDA8374 and TDA8375;
−
−
0.525
0.675
1.78
−
−
V
V
(peak-to-peak value)
note 42
gain ratio between both
demodulators G(B − Y) and
G(R − Y)
1.60
1.96
∆V
spread of signal amplitude ratio TDA8374 and TDA8375;
−1
−
−
+1
dB
PAL/NTSC
note 4
Zo
output impedance between
note 2
500
650
−
Ω
(R − Y) and (B − Y)
B
bandwidth of demodulators
−3 dB; note 43
−
−
kHz
mV
mV
mV
mV
mV
V29,30(p-p)
residual carrier output
(peak-to-peak value)
fc; (R − Y) output
fc; (B − Y) output
2fc; (R − Y) output
2fc; (B − Y) output
5
−
−
5
5
−
−
−
−
5
V30(p-p)
∆Vo(T)
∆Vo/VP
Eϕ
H/2 ripple at (R − Y) output
(peak-to-peak value)
25
change of output signal
amplitude with temperature
note 4
note 4
−
−
−
0.1
−
−
%/K
dB
change of output signal
±0.1
±5
amplitude with supply voltage
phase error in the demodulated note 4
signals
−
deg
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8374 AND TDA8375
PAL or (SECAM when TDA8395 is applied); (R − Y) and (B − Y) not affected
(G − Y)/
(R − Y)
ratio of demodulated signals
−
−
−0.51
±10%
−
−
(G − Y)/
(B − Y)
ratio of demodulated signals
−0.19
±25%
NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)
(B − Y)
(R − Y)
(G − Y)
(B − Y) signal 2.03/0°
(R − Y) signal 1.59/95°
(G − Y) signal 0.61/240°
2.03UR
−0.14UR + 1.58VR
−0.31UR − 0.53VR
1997 Jul 01
37
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8373 AND TDA8377
MAT = 0; the colour-difference matrix results in the following signals (nominal hue setting)
(B − Y)
(R − Y)
(G − Y)
(B − Y) signal 2.03/0°
(R − Y) signal 1.59/95°
(G − Y) signal 0.61/240°
2.03UR
−0.14UR + 1.58VR
−0.31UR − 0.53VR
MAT = 1; the colour-difference matrix results in the following signals (nominal hue setting)
(B − Y)
(R − Y)
(G − Y)
(B − Y) signal 1.14/−10°
(R − Y) signal 1.14/100°
(G − Y) signal 0.30/235°
1.12UR − 0.20VR
−0.20UR + 1.12VR
−0.17UR − 0.25VR
REFERENCE SIGNAL OUTPUT (PIN 33); note 44
fref
reference frequency
−
3.58 or
4.43
−
MHz
V
V33(p-p)
output signal amplitude
(peak-to-peak value)
0.2
0.25
0.3
COMMUNICATION WITH THE TDA8395 (TDA8374 AND TDA8375 ONLY)
Vo
output level
PAL/NTSC identified
−
−
1.5
5.0
−
−
V
V
no PAL/NTSC identified;
SECAM (by TDA8395)
identified
I31
required current to stop
PAL/NTSC identification circuit
during SECAM
150
−
−
µA
Control part
SATURATION CONTROL; note 24 (SEE Fig.11)
CRsat
saturation control range
63 steps
63 steps
52
−
−
dB
CONTRAST CONTROL; note 24 (SEE Fig.12)
CRcon
contrast control range
−
−
15
−
dB
dB
tracking between the three
channels over a control range of
10 dB
−
0.5
BRIGHTNESS CONTROL (SEE Fig.13)
CRbri
brightness control range
63 steps
note 24
−
±0.7
−
V
V
RGB OUTPUT SIGNALS (PINS 19 TO 21)
V19-21(p-p)
output signal amplitude at
1.8
2.1
2.4
nominal luminance input signal,
nominal contrast and white point
adjustment (peak-to-peak value)
Vo(max)(p-p)
output signal at maximum white
point setting (peak-to-peak
value)
−
3.0
−
V
1997 Jul 01
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
note 45
MIN.
TYP.
2.6
MAX.
UNIT
VBW(max)(p-p) maximum signal amplitude
(black-to-white)
−
−
−
−
V
VWP(max)(p-p) maximum signal amplitude at
maximum white point setting
(peak-to-peak value)
3.6
2.1
V
V
Vred(p-p)
output signal amplitude for the
‘red’ channel at nominal settings
for contrast and saturation
control and no luminance signal
to the input (R − Y, PAL)
tbf
tbf
(peak-to-peak value)
∆Vblank
difference between blanking
level measuring pulse
0.7
0.8
0.9
V
tW(blank)
width of the video blanking pulse TDA8375, TDA8377,
14.4
14.7
15.0
µs
when the HBL bit is active
TDA8375A and
TDA8377A; note 46
Ibias
internal bias current of NPN
−
1.5
−
mA
emitter follower output transistor
Io
available output current
output impedance
−
−
−
5
−
mA
Ω
Zo
150
−
−
CRbl
control range of the black
current stabilization
at Vbl = 2.5 V and nominal
brightness and white-point
adjustment (with respect to
the measuring pulse)
±1
V
Vbl
black level shift with picture
content
note 4
−
−
−
−
20
−
mV
V
Vo(4L)
∆bl(T)
∆bl
output voltage of the 4-L pulse
after switch-on
4.2
1.0
variation of black level with
temperature
note 4
note 4
−
mV/K
relative variation in black level
between the three channels
during variations of
supply voltage (±10%)
saturation (50 dB)
nominal controls
nominal contrast
nominal saturation
nominal controls
−
−
−
−
−
−
−
−
−
−
20
20
20
20
20
−
mV
mV
mV
mV
mV
dB
−
contrast (15 dB)
−
brightness (±0.5 V)
temperature (range 40 °C)
−
−
S/N
signal-to-noise ratio of the
output signals
RGB input; note 47
CVBS input; note 47
at fosc
60
50
−
−
dB
Vr(p-p)
residual voltage at the RGB
outputs (peak-to-peak value)
15
15
mV
mV
at 2fosc plus higher
−
harmonics in RGB outputs
1997 Jul 01
39
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SYMBOL
PARAMETER
CONDITIONS
RGB input at −3 dB
CVBS input at −3 dB;
MIN.
TYP.
MAX.
UNIT
MHz
B
bandwidth of output signals
8
−
−
−
−
2.8
3.5
−
MHz
f
osc = 3.6 MHz
CVBS input at −3 dB;
osc = 4.44 MHz
S-VHS input; at −3 dB
−
−
−
MHz
MHz
f
5
WHITE-POINT ADJUSTMENT
I2C-bus setting for nominal gain HEX code
−
20H
50
−
Ginc(max)
Gdec(max)
maximum increase of the gain
HEX code 3FH
40
35
60
55
%
%
maximum decrease of the gain HEX code 00H
45
BLACK CURRENT STABILIZATION (PIN 18); note 48
Ibias
bias current for the picture tube nominal white point setting
−
10
−
µA
cathode
IL
acceptable leakage current
maximum current during scan
input impedance
−
−
−
±100
0.3
−
−
−
µA
mA
kΩ
Iscan(max)
Zi
15
BEAM CURRENT LIMITING/VERTICAL GUARD INPUT (PIN 22); note 49
VCR
contrast reduction starting
voltage
−
−
−
−
3.1
2
−
−
−
−
V
V
V
V
VdifCR
VBR
voltage difference for full
contrast reduction
brightness reduction starting
voltage
1.6
1
VdifBR
voltage difference for full
brightness reduction
Vbias
Zint
internal bias voltage
−
−
−
−
3.3
40
−
−
−
−
V
internal impedance
kΩ
V
Vdet
Ii(min)
detection level for vertical guard
3.65
100
minimum input current to
activate the guard circuit
µA
Ii(max)
maximum allowable input
current
−
1
−
mA
Notes
1. On set AGC.
2. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with sync level as FPLL
input signal level). LC-VCO circuit: Q0 ≥ 60, Cext = 12 pF, Cint = 20 pF.
4. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
5. Measured at 10 mV (RMS) top sync input signal.
6. So called projected zero point, i.e. with switched demodulator.
1997 Jul 01
40
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
7. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is
reduced to 87%.
a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.15.
9. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).
10. The test set-up and input conditions are given in Fig.16. The figures are measured with an input signal of
10 mV (RMS).
VO(b-w)
11. Measured with a source impedance of 75 Ω, where:S/N = 20 log
---------------------------------------------------------
Vm (rms) (B = 5 MHz)
12. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid
when the PLL is in lock.
13. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning
information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value
is valid only when the SL bit = 1.
14. Vi = 100 mV (RMS), FM: 1 kHz, ∆f = ±50 kHz.
15. Vi = 50 mV (RMS), f = 4.5 to 5.5 MHz; FM: 70 Hz, ±50 kHz deviation; AM: 1 kHz, 30% modulation.
16. The Automatic Volume Levelling (AVL) circuit automatically stabilizes the audio output signal to a certain level which
can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation
of the modulation depth of the transmitter. The AVL can be switched on and off via the I2C-bus.
For the TDA8373 the AVL is active over an input voltage range (measured at the de-emphasis output) between
75 and 750 mV (RMS). For the TDA8374 this input level is dependent on the crystals which are connected to the
colour decoder. When only 3.5 MHz crystals are connected (indicated via the XA/XB bits) the active input level is
identical to that of the TDA8373. When a 4.4 MHz crystal is connected the input signal range is increased to
150 to 1500 mV (RMS), this to cope with the larger FM swing of European transmitters.
The AVL control curve for the 2 standards is given in Fig.29 and Fig.30. The control range of +6 to −14 dB is valid
for input signals with 50% of the maximum frequency deviation.
17. Vi = 100 mV (RMS), f = 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation, 15 kHz bandwidth; audio attenuator at −6 dB.
18. Vi = 100 mV (RMS), f = 4.5 to 5.5 MHz, FM: 1 kHz, ±100 kHz deviation.
19. Unweighted RMS value, Vi = 100 mV (RMS), FM: 1 kHz, ±50 kHz deviation, volume control: −6 dB.
20. Audio attenuator at −20 dB; temperature range = 10 to 50 °C.
21. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
22. This parameter is measured at nominal settings of the various controls.
23. Indicated as a signal for a colour bar with 75% saturation (chroma-to-burst ratio = 2.2 : 1).
24. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. At nominal
settings of brightness and white point the black level at the outputs is 300 mV lower than the level of the black current
measuring pulses.
25. The luminance output and input of the TDA8375A, TDA8377A, TDA8375 and TDA8377 can be connected directly.
When additional picture improvement ICs (such as the TDA9170) are applied the inputs of these ICs must be
AC-coupled because of the black level clamp requirement. The output of the picture improvement ICs can be directly
coupled to the luminance input as long as the DC level of the signal has a value between 1 and 7 V.
To be able to apply CTI ICs such as the TDA4565 and TDA4566 the gain of the luminance channel can be increased
via the setting of the GAI bit in the I2C-bus subaddress 03.
1997 Jul 01
41
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
26. When the colour decoder is forced to a fixed subcarrier frequency (via the XA/XB or the CM bits) the chroma trap is
always switched on, also when no colour signal is identified. When 2 crystals are active the chroma trap is switched
off when no colour signal is identified.
27. The −3 dB bandwidth of the circuit can be calculated using the following equation:
1
2Q
f–3 dB = fosc 1 –
-------
28. Valid for a signal amplitude on the Y input of 0.7 V (black-to-white) (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
29. For video signals with a black level which deviates from the back porch blanking level the signal is ‘stretched’ to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.17). The black level is
detected by means of an external capacitor. The black level stretcher can be made inoperative by connecting the pin
to ground. The values given are valid only when the luminance input signal has an amplitude of 1 V (p-p).
30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is
4 V (p-p).
31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the bus. Therefore the circuit contains a noise
detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’ mode,
during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head
switching of the VCR are corrected as soon as possible. Switching between the two modes can be made
automatically or overruled by the bus (see Tables 4, 6, 8 and 10).
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not on the input. This ensures a stable
On-Screen-Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with
the first loop can be overruled via the I2C-bus. The coupling between the phase 1 detector and the video identification
circuit is only active for ‘internal’ CVBS signals.
To prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as Macrovision, the
phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output
voltage. The width of the gate pulse is approximately 22 µs. Furthermore the phase detector is gated during the lower
part of the picture (pulse width = 12 µs) to prevent disturbances due to overmodulated subtitles. The latter gating is
active only with standard signals (number of lines per frame 625 or 525). During weak signal conditions (noise
detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to
5.7 µs so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various
conditions are given in Table 57.
32. The ICs have 2 protection inputs.
The protection at pin 42 is intended to be used as ‘flash’ protection. When this protection is activated the horizontal
drive is switched off immediately and then switched on again via the slow start procedure.
The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive can be switched off directly (via the slow stop procedure). It is also possible to continue the horizontal
drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the 2 modes of
operation is made with the PRD bit.
1997 Jul 01
42
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
33. During switch-on the horizontal output starts with twice the frequency and with a duty cycle of 75% (Vo = HIGH). After
approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents
in the horizontal output transistor are limited. Also during switch-off the frequency is switched to twice the value and
the RGB drive is set to maximum so that the EHT capacitor is discharged. This switching to maximum drive occurs
only when RBL = 0, for RBL = 1 the drive voltage remains minimum during switch-off. After approximately 100 ms
the RGB drive is set to minimum and 50 ms later the horizontal drive is switched off.
The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on
during the flyback time.
34. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The width of the
vertical sync pulse in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the
picture due to timing modulation of the incoming flyback pulse.
35. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This
divider circuit has 3 modes of operation. A brief explanation is given below. For the TDA8373 and TDA8377 only the
60 Hz figures are valid.
a) Search mode ‘large window’:
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines
per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264) is received.
In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).
b) Standard mode ‘narrow window’:
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz):
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are
in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched
to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical
sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 08.
36. Conditions: frequency is 60 Hz; normal mode; VS = 1F.
37. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA
variation in E-W output current is equivalent to 20% variation in picture width. Because of the horizontal and vertical
zoom feature in the TDA8375 and TDA8377 (see also note 38) the E-W width control range is increased compared
with previous ICs such as the TDA8366. The increased E-W width control is also available in the TDA8375A and
TDA8377A although these devices do not have the vertical zoom feature.
38. The TDA8375 and TDA8377 have a zoom adjustment possibility for the vertical and horizontal deflection. For this
reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude
between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.08 of the nominal scan the output current is limited
and the blanking of the RGB outputs is activated (see Fig.28). In addition to the variation of the vertical amplitude the
vertical slope control range is also increased. This gives the possibility to vary the position of the bottom part of the
picture independent from the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical
‘zoom’ DAC
1997 Jul 01
43
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
39. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.
40. The ACL function is available in the NTSC devices and is active in the PAL/NTSC devices when NTSC signals are
received. The ACL circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which
exceeds a value of 3.0.
41. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are
measured with the Philips crystal series 9922 520 with a series capacitor of 18 pF. The oscillator circuit is rather
insensitive to the spurious responses of the crystal. As long as the resonance resistance of the 3rd overtone is higher
than that of the fundamental frequency the oscillator will operate at the correct frequency. Typical parameters for the
above mentioned crystals are as follows:
a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz (CL = 20 pF).
b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal).
c) Parallel capacitance Cpar = 5 pF for both crystals.
The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures
given are therefore valid for the specified crystal series. In this figure tolerances of the crystal with respect to nominal
frequency, motional capacitance and ageing have been taken into account and have been counted for gaussian
addition. Whenever different typical crystal parameters are used the following equation might be helpful for
calculating the impact on the detuning capabilities:
C
--------------m-----o--t---------
The detuning range divided by
2
Cpar
1 +
-----------
CL
The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the
crystal. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances
on and off chip. For 3-norma applications with 2 crystals connected to one pin the maximum parasitic capacitance of
the crystal pin should not exceed 15 pF.
42. The (R − Y) and (B − Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain
(B – Y)
ratio
.
= 1.78
--------------------
(R – Y)
The output signal amplitudes of the TDA8373 and TDA8377A have twice the value. This is necessary to compensate
for the gain of the baseband delay line (TDA4665). The matrixing to the required signals is realized in the control part.
43. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
44. The sub-carrier output signal can be used as reference signal of external comb filter ICs (all ICs) and as a reference
signal for the SECAM decoder TDA8395 (only TDA8374 and TDA8375). In the latter types the output signal is
continuously available when PAL or NTSC signals are detected. When the system identifies a SECAM signal the
reference signal is only present in the vertical retrace period. This to prevent interference between the reference
signal and the SECAM input signal. For comb filter applications the DC load on this pin should be limited to 50 µA to
avoid problems with SECAM identification.
45. At nominal setting of the gain control. When this amplitude is exceeded the signal will be clipped.
46. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by means of a reduction of the horizontal
scan amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding additional
blanking to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly related to the
incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal blanking signal
with approximately 1 µs on both sides. This blanking is activated with the HBL bit (only in the TDA8375 and
TDA8377).
47. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
1997 Jul 01
44
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
48. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain
(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a
result the ‘black current’ of each gun is adapted to the white point setting so that the background colour will follow
the white point adjustment.
49. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting
function is active during the vertical scan period.
Table 57 Output current of the phase detector in the various conditions
I2C-BUS COMMANDS
IC CONDITIONS
ϕ-1 CURRENT/MODE
VID
−
POC
FOA
0
FOB
0
IDENT
COIN
yes
yes
no
NOISE
SCAN
180
30
V-RETR GATING MODE
0
0
0
0
0
0
0
−
0
1
yes
yes
yes
yes
yes
yes
yes
−
no
yes
−
270
30
yes(1)
yes
no
auto
auto
auto
slow
slow
fast
−
0
0
−
0
0
180
30
270
30
−
0
1
yes
no
−
yes
no
−
0
1
−
180
180
30
270
270
30
−
1
0
yes
yes
−
no
yes
−
yes
yes
no
−
1
0
slow
fast
−
1
1
180
6
270
6
0
−
−
no
−
−
no
OSD
off
−
−
−
−
−
−
−
−
−
Note
1. During vertical retrace the width is 22 µs and during the lower part of the picture 12 µs. In the other conditions the
width is 5.7 µs and the gating is continuous.
MGK290
MGK291
handbook, halfpage
handbook, halfpage
0
(dB)
−20
40
(%)
30
20
10
−40
−60
−80
0
0
−100
4
8
C
F 10
0
10
20
30
40
DAC (HEX)
DAC (HEX)
Positive overshoot.
Fig.8 Volume control curve.
Fig.9 Peaking control curve.
1997 Jul 01
45
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MGK292
MGK293
handbook, halfpage
handbook, halfpage
(deg)
300
(%)
40
250
20
0
200
150
100
50
−20
−40
0
0
0
10
20
30
40
10
20
30
40
DAC (HEX)
DAC (HEX)
Fig.10 Hue control curve.
Fig.11 Saturation control curve.
MGK294
MGK295
handbook, halfpage
handbook, halfpage
0.7
100
(%)
(V)
80
60
40
20
0.35
0
−0.35
−0.7
0
0
10
20
30
DAC (HEX)
40
0
10
20
30
40
DAC (HEX)
Relative variation with respect to the measuring pulse.
Fig.12 Contrast control curve.
Fig.13 Brightness control curve.
1997 Jul 01
46
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MBC212
100%
92%
16 %
30%
for negative modulation
100% = 10% rest carrier
Fig.14 Video output signal.
MBC211
100%
86%
72%
58%
44%
30%
µs
32 36 40 44 48 52 56 60 64
10 12
22 26
Fig.15 Test signal waveform.
1997 Jul 01
47
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
3.2 dB
10 dB
13.2 dB
13.2 dB
30 dB
30 dB
SC CC
PC
SC CC
PC
MBC213
BLUE
YELLOW
PC
Σ
TEST
CIRCUIT
SPECTRUM
ANALYZER
SC
ATTENUATOR
gain setting
adjusted for blue
CC
MBC210
Input signal conditions: SC = Sound Carrier; CC = Colour Carrier; PC = Picture Carrier.
All amplitudes with respect to top sync level.
VO at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB
VO at 0.92 or 1.1 MHz
VO at 3.58 or 4.4 MHz
Value at 2.66 or 3.3 MHz = 20 log ------------------------------------------------------------
VO at 2.66 or 3.3 MHz
Fig.16 Test set-up intermodulation.
48
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MGK297
100
handbook, halfpage
out
(IRE)
80
60
40
20
B
0
B
A
A
−20
0
20
40
60
80
100
in (IRE)
A-A = maximum black level shift; B-B = level shift at 15% of peak white.
Fig.17 Input/output relationship of the black level stretcher.
TEST AND APPLICATION INFORMATION
BAND-
PASS
from
tuner
4
3
16
10
11 27 17 18
35 36 37 38
58
59
33
32
31
SAW
FILTER
30
34
TRAP
24
29
TDA837x
62
63
64
56
21
20
54
50
51
46 45
39 47 48 57
4.4
3.5
MHz
MHz
TDA8395
TDA4665
MGK302
Fig.18 Simplified application diagram.
49
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
East-West output stage
In order to obtain correct tracking of the vertical and horizontal EHT correction, the E-W output stage should be
dimensioned as illustrated in Fig.19.
Resistor Rew determines the gain of the E-W output stage. Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 kΩ which results in a reference
current of 100 µA (Vref = 3.9 V).
Vscan
The value of Rew must be: Rew = R ×
----------------------
c
18 × Vref
Example: With Vref = 3.9 V; Rc = 39 kΩ and Vscan = 120 V then Rew ≈ 68 kΩ.
V
supply
HORIZONTAL
DEFLECTION
STAGE
V
scan
R
ew
TDA8375
TDA8377
DIODE
MODULATOR
V
45
EW
E-W drive
E-W
52
51
OUTPUT
STAGE
V
ref
MGK300
R
C
saw
100 nF
c
39 kΩ
(2%)
(5%)
Fig.19 East-West output stage.
Control ranges of geometry control parameters
Typical case curves; Rc = 39 kΩ, CSAW = 100 nF.
Figures 20 to 23 are valid for all types. Figures 24 to 27 are valid for TDA8375 and TDA8377.
1997 Jul 01
50
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MGH367
MGH366
500
vert
600
vert
handbook, halfpage
handbook, halfpage
I
I
(µA)
(µA)
300
400
100
−100
−300
−500
200
0
−200
−400
−700
−600
1
1
0
/2 t
t
0
/2 t
t
time
time
VA = 0, 31H and 63H; VSH = 31H; SC = 0.
VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.
Fig.20 Control range of vertical amplitude.
Fig.21 Control range of vertical slope.
MGH368
MGH369
600
vert
600
vert
handbook, halfpage
handbook, halfpage
I
I
(µA)
(µA)
400
400
200
0
200
0
−200
−400
−200
−400
−600
−600
1
1
0
/2 t
t
0
/2 t
t
time
time
SC = 0, 31H and 63H; VA = 31H; VHS = 31H.
Picture height does not change with S-correction for
nominal vertical amplitude (VA = 31).
VSH = 0, 31H and 63H; VA = 31H; SC = 0.
Fig.22 Control range of vertical shift.
Fig.23 Control range of S-correction.
1997 Jul 01
51
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MBK039
MBK040
1200
ew
900
ew
handbook, halfpage
handbook, halfpage
I
I
(µA)
(µA)
1000
800
700
600
500
400
800
600
400
200
300
0
0
1
/2 t
1
0
t
/2 t
t
time
time
EW = 0, 31H and 63H; PW = 31H; CP = 31H.
PW = 0, 31H and 63H; EW = 31H; CP = 31H.
Fig.24 Control range of E-W width.
Fig.25 Control range of E-W parabola/width ratio.
MBK041
MBK042
700
900
ew
(µA)
handbook, halfpage
handbook, halfpage
I
I
ew
(µA)
800
600
700
600
500
400
500
400
300
300
0
1
/2 t
1
0
t
/2 t
t
time
time
CP = 0, 31H and 63H; EW = 31H; PW = 63H.
TC = 0, 31H and 63H; EW = 31H; PW = 31H; CP = 0.
Fig.26 Control range of E-W corner/parabola ratio.
Fig.27 Control range of E-W trapezium correction.
1997 Jul 01
52
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction and on the demands upon vertical linearity.
Adjustment of geometry control parameters
The deflection processor of the TDA8373 and TDA8374
offers 5 control parameters for picture alignment:
For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
mode can be entered by setting the SBL bit HIGH. In this
mode the RGB outputs are blanked during the second half
of the picture. There are 2 different methods for alignment
of the picture in vertical direction. Both methods make use
of the service blanking mode.
• Vertical picture alignment
– S-correction
– vertical amplitude
– vertical slope
– vertical shift
– Horizontal shift alignment.
The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment the vertical shift should not be changed.
The top of the picture is placed by adjusting the vertical
amplitude and the bottom by adjusting the vertical slope.
The TDA8375, TDA8377, TDA8375A and TDA8377A offer
in addition the following functions for horizontal alignment:
• E-W width
• E-W parabola/width
• E-W corner/parabola
• E-W trapezium correction.
The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method a video signal is required in which the middle of the
picture is indicated (e.g. the white line in the circle test
pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
symmetrically with respect to the middle of the screen by
adjustment of the vertical amplitude and vertical shift. After
this adjustment the vertical shift has the correct setting and
should not be changed.
It is important to notice that the ICs are designed for use
with a DC-coupled vertical deflection stage. This is the
reason why a vertical linearity alignment is not necessary
(and, therefore, not available).
For a particular combination of picture tube type and
vertical output stage and E-W output stage, it is
determined which are the required values for the settings
of S-correction. These parameters can be preset via the
I2C-bus and do not need any additional adjustment.
The remainder of the parameters are preset with the
mid-value of their control range (i.e. 1FH), or with the
values obtained by previous TV set adjustments.
If the vertical shift alignment is not required VSH should be
set to its mid-value (i.e. VSH = 1FH). The top of the picture
is then placed by adjusting the vertical amplitude and the
bottom by adjusting the vertical slope. After the vertical
picture alignment the picture is positioned in the horizontal
direction by adjusting the horizontal shift.
The vertical shift control is intended for compensation of
off-sets in the external vertical output stage or in the
picture tube. It can be shown that without compensation
these off-sets will result in a certain linearity error,
especially with picture tubes that need large S-correction.
The total linearity error is in 1st order approximation
proportional to the value of the off-set and to the square of
the S-correction needed. The necessity to use the vertical
To obtain the full range of the vertical zoom function with
the TDA8375 and TDA8377 the adjustment of the vertical
geometry should be carried out at a nominal setting of the
zoom DAC at position 19H.
1997 Jul 01
53
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MGK296
70
top
picture
vertical
position
(%)
60
50
138%
40
100%
75%
30
20
10
t
1/2 t
0
time
−10
−20
−30
−40
−50
−60
bottom
picture
blanking for exponential 138%
Fig.28 Sawtooth waveform and blanking pulse of the TDA8375 and TDA8377.
MGK298
4
10
handbook, halfpage
AVL on
AVL off
audio
output
(mV) (RMS)
14 dB
3
10
25 kHz (norm)
6 dB
A
B
C
D
2
10
2
3
4
10
10
10
de-emphasis (mV) (RMS)
10
See Table 58.
Fig.29 AVL characteristics of the TDA8373 and TDA8374 for 3.5 MHz standard.
54
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
MGK299
4
10
handbook, halfpage
AVL on
AVL off
audio
output
(mV) (RMS)
14 dB
3
10
50 kHz (norm)
6 dB
A
BC
D
E
3
2
10
2
4
10
10
10
10
de-emphasis (mV) (RMS)
See Table 59.
Fig.30 AVL characteristics of the TDA8374 for 4.4 MHz standard.
Table 58 Explanation to Fig.29
A
B
C
D
DESCRIPTION
50
5
100
10
250
25
500
50
de-emphasis pin 55 [mV (RMS)]
FM swing (kHz)
50
100
100
200
250
500
500
1000
AVL input [mV (RMS)]
external input [mV (RMS)]
Table 59 Explanation to Fig.30
A
B
C
D
DESCRIPTION
100
10
200
20
250
25
1000
100
de-emphasis pin 55 [mV (RMS)]
FM swing (kHz)
50
100
200
125
250
500
AVL input [mV (RMS)]
external input [mV (RMS)]
100
1000
1997 Jul 01
55
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
INTERNAL PIN CONFIGURATION
sound limiter
TSTCON
plus demodulator
sound switch
plus amplifier
+
10 pF
1
300 Ω 2.2 kΩ
25
kΩ
100 Ω
15
pF
2
15
kΩ
15
kΩ
4 V
MGK304
MGK303
Fig.32 Pin 2.
Fig.31 Pin 1.
+
+
3
4
+
+
5
6
kΩ
6
kΩ
MGK305
Fig.33 Pins 3, 4 and 5.
+
+
200
Ω
5 V
300 Ω
7
6
MGK343
MGK306
Fig.34 Pin 6.
Fig.35 Pin 7.
1997 Jul 01
56
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
5 V
+
+
300 Ω
8
9
30 Ω
MGK307
MGK308
Fig.36 Pin 8.
Fig.37 Pin 9.
+
+
TSTCON
100
kΩ
100 Ω
10 pF
DUMMY
CLAMP
10
30 kΩ
300 Ω
11, 13, 17
100
kΩ
V
ref
TXT
DECODER
PIP
MGK309
decoder
chroma
switch
output
switch control
decoder
luma
sync
MGK310
Fig.38 Pin 10.
Fig.39 Pins 11, 13 and 17.
+
+
12, 37
14
analog supply
GND1
MGK344
MGK333
Fig.40 Pins 12 and 37.
Fig.41 Pin 14.
1997 Jul 01
57
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
−100 µA/ +100 µA
filter
tuning
2 kΩ
+
+
sound
50 kΩ
300 Ω
amplifier
16
300 Ω
15
10 pF
100 µA
MGK313
MGK312
Fig.42 Pin 15.
Fig.43 Pin 16.
+
V/I
10 pF
+
I
L
+
14 kΩ
V
= 4 V
ref
18
200
µA
10
µA
100 Ω
19, 20, 21
2 mA
MGK315
MGK314
Fig.44 Pin 18.
Fig.45 Pins 19, 20 and 21.
+
V
ref1
+
contrast
control
4 V
40
vertical
guard
+
kΩ
1 kΩ
V
22
ref2
peak white
limiting
brightness
control
200 µA
MGK316
Fig.46 Pin 22.
58
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
+
+
+
insertion
+
+
+
6 V
300 Ω
300 Ω
26
23, 24, 25
4 V
50 µA
blanking
MGK317
MGK318
Fig.47 Pins 23, 24 and 25.
Fig.48 Pin 26.
+
+
+
+
+
500 Ω
6 V
+
50
pF
10 Ω
27
10 Ω
28
500 µA
0.2 µA
MGK320
MGK319
Fig.49 Pin 27.
Fig.50 Pin 28.
+
+
+
+
+
100 Ω
31, 32
2.5 V
100 Ω
29, 30
MGK322
MGK321
Fig.51 Pins 29 and 30.
Fig.52 Pins 31 and 32.
1997 Jul 01
59
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
+
+
+
34, 35
R
30 Ω
250 µA
33
3.7 V
2.7 V
R
MGK323
pin 34: crystal = 3.58 MHz; R = 1 kΩ
pin 35: crystal = 4.43 MHz; R = 1 kΩ
MGK324
Fig.53 Pin 33.
Fig.54 Pins 34 and 35.
+
+
+
+
400 Ω
100 Ω
36
+
TSTCON
100 Ω
38
600
µA
3.8 V
MGK326
MGK325
Fig.55 Pin 36.
Fig.56 Pin 38.
39
+
+
30 Ω
40
MGK328
protection
MGK327
Fig.57 Pin 39.
Fig.58 Pin 40.
1997 Jul 01
60
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
+
J
5.3 V
2.9 V
burstkey
3 V
+
30 Ω
41
V blank
2 µA
burstkey
MGK329
Fig.59 Pin 41.
+
+
5.3 V
+
flash
level
300 Ω
42
MGK330
Fig.60 Pin 42.
+
+
J
300 Ω
300 Ω
43
4 V
dF
HOSC
4.7 V
3.3 V
4 V
MGK331
(NC plus POR)
Fig.61 Pin 43.
61
1997 Jul 01
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
45
GND2, connected to substrate
44
MGK311
600 Ω
MGK332
Fig.62 Pin 44.
Fig.63 Pin 45.
+
+
+
+
100 Ω
48
49
1 kΩ
1 kΩ
+
2.4 pF
to
46, 47
IF amplifier
100 Ω
MGK334
MGK335
Fig.64 Pins 46 and 47.
Fig.65 Pins 48 and 49.
+
+
J
+
J
300 Ω
+
50
3.9 V
51
XPR
2 V
MGK336
J
MGK337
Fig.66 Pin 50.
Fig.67 Pin 51.
1997 Jul 01
62
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
I
ref
+
52
V
ref
MGK338
Fig.68 Pin 52.
+
1.5
mA
+
+
53
AGC det
LSPEED
gating
NEGMOD
clamp
500
nA
50
µA
600
µA
MGK339
Fig.69 Pin 53.
+
+
55
sound switch
plus amplifier
sound
TSTCON
demodulator
54
20 kΩ
MGK340
3 V
MGK341
Fig.70 Pin 54.
Fig.71 Pin 55.
1997 Jul 01
63
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
+
100 µA
56
DC
stabilisation
−50/50 µA
MGK342
Fig.72 Pin 56.
1997 Jul 01
64
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
PACKAGE OUTLINES
QFP64: plastic quad flat package;
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
y
X
A
51
33
52
32
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
pin 1 index
b
L
20
64
detail X
1
19
w M
Z
v
M
M
D
A
b
p
e
D
B
H
v
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.36 2.87
0.10 2.57
0.50 0.25 20.1 14.1
0.35 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0 1.43
0.6 1.23
1.2
0.8
1.2
0.8
mm
3.3
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT319-1
1997 Jul 01
65
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
SDIP56: plastic shrink dual in-line package; 56 leads (600 mil)
SOT400-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
56
29
pin 1 index
E
1
28
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
52.4
51.6
14.0
13.6
3.2
2.8
15.80
15.24
17.15
15.90
mm
0.51
4.0
5.08
1.778
15.24
0.18
2.3
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-06
SOT400-1
1997 Jul 01
66
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
SDIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
QFP
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering techniques are suitable for all QFP
packages.
REPAIRING SOLDERED JOINTS
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Jul 01
67
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
Short-form specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jul 01
68
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
NOTES
1997 Jul 01
69
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
NOTES
1997 Jul 01
70
Philips Semiconductors
Preliminary specification
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
NOTES
1997 Jul 01
71
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© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp72
Date of release: 1997 Jul 01
Document order number: 9397 750 01808
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Consumer Multimedia
Systems
Communications
The various versions of the TDA837x series are I2C-bus controlled single-chip TV processors which are intended to be applied in
PAL/NTSC (TDA8374 and TDA8375) and NTSC (TDA8373 and TDA8377) television receivers. All ICs are available in an SDIP56 package
and some versions are also available in a QFP64 package. The ICs are pin compatible so that with one application board NTSC and
PAL/NTSC (or multistandard together with the SECAM decoder TDA8395) receivers can be built. Functionally this IC series is split in to 2
categories:
PC/PC-peripherals
Cross reference
Models
Packages
l Versions intended to be used in economy TV receivers with all basic functions
l Versions with additional functions such as E-W geometry control, horizontal and vertical zoom function and YUV interface which are
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
intended for TV receivers with 110° picture tubes.
Features
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l Vision IF amplifier with high sensitivity and good figures for differential phase and gain
l PLL demodulator for the IF signal
l Alignment-free sound demodulator
l Flexible source selection with a CVBS input for the internal signal and Y/C or CVBS input for the external signal
l Audio switch
TDA837x family
TDA837x family
l The output signal of the CVBS (Y/C) switch is externally available
l Integrated chrominance trap and band-pass filters (auto-calibrated)
l Luminance delay line integrated
l A symmetrical peaking circuit in the luminance channel
l Black stretching of non-standard CVBS or luminance signals
l RGB control circuit with black current stabilization and white point adjustment
l Linear RGB inputs and fast blanking
l Horizontal synchronization with two control loops and alignment-free horizontal oscillator
l Slow start and slow stop of the horizontal drive pulses
l Vertical count-down circuit
l Vertical driver optimized for DC-coupled vertical output stages
l I2C-bus control of various functions
l Low dissipation
l Small amount of peripheral components compared with competition ICs.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
TDA837x family I2C-bus controlled economy
PAL/NTSC and NTSC TV-processors
Title
Datasheet
Download
01-Jul-97
Preliminary
Specification
72
476
Blockdiagram
Blockdiagram of TDA8374A
Blockdiagram of TDA8374A
Blockdiagram of TDA8374A
Blockdiagram of TDA8374A
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status
buy online
TDA8373/N3
9352 246 80112 Standard Marking * Tube
9352 246 90112 Standard Marking * Tube
9352 247 00112 Standard Marking * Tube
9351 937 90112 Standard Marking * Tube
SOT400 Full production
SOT400 Full production
SOT400 Full production
SOT400 Samples available
-
TDA8373C/N3 TDA8373CN
TDA8374/N3
-
-
TDA8374A/N1
TDA8374A/N3
TDA8374C/N3
TDA8375A/N1
9352 247 10112 Standard Marking * Tube
9352 247 40112 Standard Marking * Tube
9351 938 10112 Standard Marking * Tube
SOT400 Full production
SOT400 Full production
SOT400 Samples available
-
-
-
Standard Marking * Tray Dry
9352 247 70551
TDA8375AH/N3
SOT319 Full production
-
Pack, Bakeable, Single
Standard Marking * Tray Dry
9352 247 70557
SOT319 Full production
SOT400 Full production
-
-
Pack, Bakeable, Multiple
TDA8377/N3
9352 247 80112 Standard Marking * Tube
Please read information about some discontinued variants of this product.
Find similar products:
TDA837x family links to the similar products page containing an overview of products that are similar in function or related to the part
number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
Copyright © 2000
Royal Philips Electronics
All rights reserved.
Terms and conditions.
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