935209660118 [NXP]
IC ALVT SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver;
| 型号： | 935209660118 |
| 厂家： | 
NXP |
| 描述： | IC ALVT SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVT16374
2.5V/3.3V 16-bit edge-triggered
D-type flip-flop (3-State)
Product specification
1999 Oct 18
Supersedes data of 1998 Feb 13
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
FEATURES
• 16-bit edge-triggered flip-flop
• 5V I/O compatibile
DESCRIPTION
The 74ALVT16374 is a high-performance BiCMOS product
designed for V operation at 2.5V or 3.3V with I/O compatibility up
CC
to 5V.
• 3-State buffers
This device is a 16-bit edge-triggered D-type flip-flop featuring
non-inverting 3-State outputs. The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CP), the Q outputs of the flip-flop take on the logic levels set up at
the D inputs.
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
TYPICAL
CONDITIONS
SYMBOL
PARAMETER
UNIT
T
amb
= 25°C
2.5V
3.3V
t
t
Propagation delay
nCP to nQx
2.6
2.8
2.1
2.3
PLH
PHL
C = 50pF
L
ns
C
Input capacitance DIR, OE
Output capacitance
Total supply current
V = 0V or V
CC
3
9
3
9
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or V
Out
O
CC
I
Outputs disabled
40
40
CCZ
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
AV16374 DL
DWG NUMBER
SOT370-1
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74ALVT16374 DL
74ALVT16374 DGG
AV16374 DGG
SOT362-1
2
1999 Oct 18
853-1844 22537
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
LOGIC SYMBOL
PIN CONFIGURATION
47 46 44 43 41 40 38 37
1OE
1Q0
!Q1
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1CP
48
1
GND
1Q2
1Q3
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
V
42
V
CC
CC
1Q4
1Q5
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
2
3
5
6
8
9
11 12
36 35 33 32 30 29 27 26
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13 14 16 17 19 20 22 23
SW00018
V
18
31
V
CC
CC
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
LOGIC SYMBOL (IEEE/IEC)
1
1OE
1CP
2OE
2CP
1EN
C1
2EN
C2
48
24
25
SW00017
47
46
2
3
5
1D
1
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
PIN DESCRIPTION
44
43
41
PIN NUMBER
SYMBOL
FUNCTION
6
8
9
47, 46, 44, 43, 41, 40,
38, 37 36, 35, 33, 32,
30, 29, 27, 26
1D0 - 1D7
2D0 - 2D7
Data inputs
40
38
11
12
37
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
1Q0 - 1Q7
2Q0 - 2Q7
Data outputs
36
35
13
2D
2
14
16
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
Output enable inputs
(active-Low)
33
32
1, 24
1OE, 2OE
1CP, 2CP
GND
17
19
Clock pulse inputs (active
rising edge)
30
29
48, 25
20
22
23
4, 10, 15, 21, 28, 34,
39, 45
27
26
Ground (0V)
7, 18, 31, 42
V
CC
Positive supply voltage
SW00016
3
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
FUNCTION TABLE
INPUTS
nCP
INTERNAL
REGISTER
OUTPUTS
nQ0 - nQ7
OPERATING MODE
nOE
nDx
L
L
↑
↑
l
h
L
H
L
H
Load and read register
L
↑
X
NC
NC
Hold
H
H
↑
↑
X
nDx
NC
nDx
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low-to-High clock transition
Not a Low-to-High clock transition
↑
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SW00019
4
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
1,2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
DC supply voltage
-0.5 to +4.6
-50
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
-0.5 to +7.0
-50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
-0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
-64
T
stg
Storage temperature range
-65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
2.5V RANGE LIMITS 3.3V RANGE LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.3
0
MAX
2.7
MIN
3.0
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
5.5
V
High-level input voltage
Input voltage
1.7
2.0
V
IH
V
0.7
–8
8
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
OH
I
OL
mA
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
24
10
+85
64
∆t/∆v
10
ns/V
T
amb
–40
–40
+85
°C
5
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–0.85
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.0V; I = –18mA
*1.2
V
V
IK
IK
= 3.0 to 3.6V; I = –100µA
V
0.2
V
CC
OH
CC–
V
OH
High-level output voltage
= 3.0V; I = –32mA
2.0
2.3
0.07
0.25
0.3
OH
= 3.0V; I = 100µA
0.2
0.4
OL
= 3.0V; I = 16mA
OL
V
OL
Low–level output voltage
V
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.4
0.55
OL
6
V
Power-up output low voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.6V; I = 1mA; V = V or GND
0.55
±1
V
RST
O
I
CC
= 3.6V; V = V or GND
Control pins
0.1
0.1
I
CC
= 0 or 3.6V; V = 5.5V
10
I
I
I
Input leakage current
µA
= 3.6V; V = V
0.1
1
I
CC
4
Data pins
= 3.6V; V = 0V
0.1
-5
I
I
Off current
= 0V; V or V = 0 to 4.5V
0.1
±100
µA
µA
OFF
I
O
= 3V; V = 0.8V
75
130
–140
I
Bus Hold current
= 3V; V = 2.0V
–75
I
I
HOLD
7
Data inputs
= 0V to 3.6V; V = 3.6V
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
10
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
O CC I CC
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 3.6V; V = 3.0V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 3.6V; V = 0.5V; V = V or V
*5
0.1
6
OZL
O
I
IL
I
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.04
3.7
CCH
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
CCZ
I
5
I
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.04
0.1
I
Additional supply current per
= 3V to 3.6V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS (3.3V "0.3V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V "0.3V
UNIT
1
MIN
TYP
MAX
f
Maximum clock frequency
1
1
250
MHz
ns
max
t
t
Propagation delay
nCp to nQx
1.0
1.0
2.1
2.3
3.2
3.2
PLH
PHL
t
t
Output enable time
to High and Low level
3
4
1.0
1.0
2.3
2.0
3.8
3.2
PZH
PZL
ns
ns
t
Output disable time
from High and Low Level
3
4
1.0
1.0
2.7
2.3
4.2
3.4
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
6
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–0.85
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3V; I = –18mA
–1.2
V
V
IK
IK
= 2.3 to 3.6V; I = –100µA
V
–0.2
V
CC
OH
CC
V
OH
High-level output voltage
= 2.3V; I = –8mA
1.8
2.1
0.07
0.3
OH
= 2.3V; I = 100µA
0.2
0.5
OL
V
OL
Low-level output voltage
= 2.3V; I = 24mA
OL
7
V
Power-up output low voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = 1mA; V = V or GND
0.55
±1
V
RST
O
I
CC
= 2.7V; V = V
or GND
CC
Control pins
0.1
0.1
0.1
0.1
0.1
90
I
= 0 or 2.7V; V = 5.5V
10
I
I
I
Input leakage current
µA
= 2.7V; V = V
1
I
CC
4
Data pins
= 2.7V; V = 0
-5
I
I
Off current
= 0V; V or V = 0 to 4.5V
"100
µA
µA
OFF
I
O
Bus Hold current
= 2.3V; V = 0.7V
I
I
HOLD
6
Data inputs
= 2.3V; V = 1.7V
–10
I
Current into an output in the
I
V
= 5.5V; V = 2.3V
10
1
125
100
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 2.7V; V = 2.3V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 2.7V; V = 0.5V; V = V or V
–5
OZL
O
I
IL
I
= 2.7V; Outputs High, V = GND or V I 0
CC, O =
0.04
2.7
0.1
4.5
0.1
CCH
I
I
Quiescent supply current
= 2.7V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
CCZ
I
5
I
= 2.7V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.04
I
Additional supply current per
= 2.3V to 2.7V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 2.5V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 2.5V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
AC CHARACTERISTICS (2.5V "0.2V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 2.5V "0.2V
UNIT
1
MIN
TYP
MAX
f
Maximum clock frequency
1
1
150
MHz
ns
max
t
t
Propagation delay
nCp to nQx
1.5
1.5
2.6
2.8
4.2
4.5
PLH
PHL
t
t
Output enable time
to High and Low level
3
4
1.0
1.0
3.4
2.6
5.6
4.7
PZH
PZL
ns
ns
t
Output disable time
from High and Low Level
3
4
2.0
1.0
2.7
2.0
4.4
3.3
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 2.5V and T
= 25°C.
CC
amb
7
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
LIMITS
= 3.3V ±0.3V
V
CC
= 2.5V ±0.2V
V
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
TYP
MIN
TYP
t (H)
t (L)
S
Setup time
nDx to nCP
1.0
1.5
0
0.4
1.0
1.5
0
0
S
2
2
1
ns
ns
ns
t (H)
Hold time
nDx to nCP
0.5
0.5
0
0
0.5
0.5
0
0
h
t (L)
h
t (H)
nCP pulse width
High or Low
1.5
1.5
1.5
1.5
W
t (L)
w
AC WAVEFORMS
V
M
V
X
V
Y
= 1.5V for V w 3.0V; V = V /2 for V v 2.7V
CC M CC CC
= V + 0.3V for V w 3.0V; V = V + 0.15V for V v 2.7V
OL
CC
X
OL
CC
= V – 0.3V for V w 3.0V; V = V – 0.15V for V v 2.7V
OH
CC
Y
OH
CC
1/f
MAX
3.0V or V
whichever
is less
CC
3.0V or V
whichever
is less
CC
V
V
M
nOE
nQx
M
t
nCP
V
t
V
V
M
t
M
M
0V
0V
t
PZH
PHZ
(H)
t
W
(L)
w
V
t
OH
PHL
PLH
V
V
OH
V
Y
V
M
nQx
V
V
M
M
0V
OL
SW00168
SW00170
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
nDx
3.0V or V
3.0V or V
CC
CC
whichever
is less
whichever
is less
V
V
V
V
M
nOE
nQx
M
M
M
V
V
M
M
t
0V
0V
t
(H)
t (L)
s
t
(H)
t (L)
h
s
t
PLZ
h
PZL
3.0V or V
CC
3.0V or V
CC
whichever
is less
V
nCP
M
V
V
M
V
X
M
V
OL
0V
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
SW00169
SW00171
Waveform 2. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
8
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
TEST CIRCUIT AND WAVEFORMS
6V or
V
t
W
V
x 2
CC
AMP (V)
90%
CC
90%
OPEN
NEGATIVE
PULSE
V
V
M
10%
M
10%
GND
V
V
OUT
IN
R
R
L
L
0V
(t
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
M
= 1.5V or V / 2, whichever is less
CC
TEST
SWITCH
Input Pulse Definition
t
/t
GND
PHZ PZH
t
/t
6V or V x 2
PLZ PZL
CC
t
/t
open
PLH PHL
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
R = Load resistor; see AC CHARACTERISTICS for value.
Amplitude
3.0V or V
whichever
is less
Rep. Rate
t
t
t
L
W
R
F
C = Load capacitance includes jig and probe capacitance;
L
CC
see AC CHARACTERISTICS for value.
74ALVT16
≤10MHz
500ns ≤2.5ns ≤2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SW00162
9
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
10
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
11
1999 Oct 18
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 16-bit edge-triggered D-type flip-flop
(3-State)
74ALVT16374
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-99
9397-750-06513
Document order number:
Philips
Semiconductors
it Q
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The 74ALVT16374 is a high-performance BiCMOS product designed for V operation at 2.5V or 3.3V with I/O
CC
Cross-reference
Packages
•
•
compatibility up to 5V.
End of Life
information
Distributors Go
Here!
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-State outputs. The device can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take
on the logic levels set up at the D inputs.
•
•
Models
•
•
SoC solutions
Features
●
●
●
●
●
●
●
●
●
●
●
●
●
16-bit edge-triggered flip-flop
5V I/O compatibile
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
Applications
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
AN214_2: 74F extended octal-plus family applications (date 01-Jun-88)
AN215_2: 74FXXXX Light Load input products (date 01-Apr-88)
AN220_1: Synchronizing and clock driving solutions - using the 74F50XXX family (date 01-Sep-89)
AN2301: Simulation Support for Philips' Advanced BiCMOS Products
AN240: Interfacing 3 Volt and 5 Volt Applications
AN243: LVT (Low Voltage Technology) and ALVT (Advanced LVT) (date 01-Jan-98)
AN246: Transmission Lines and Terminations with Philips Advanced Logic Families
Datasheet
Type number Title
Publication release
date
Datasheet status
Page count File size Datasheet
(kB)
74ALVT16374 2.5 V / 3.3 V 16- 10/18/1999
Product specification 12
110
Download
bit edge-
triggered D-type
flip-flop (3-
State)
Blockdiagram(s)
Block diagram of
74ALVT16374DL
Parametrics
Type number
Package Description Propagation Voltage No. Power
Delay(ns) of Dissipation
Pins Considerations Levels
Logic
Switching Drive
Output
Capability
2.5/3.3V 16-
Bit D-Type
Flip-Flop;
Postive-Edge 2~4
Trigger with
Bus Hold (3-
State)
SOT370-1
(SSOP48)
74ALVT16374DGG
Low
Low
48 None
TTL
TTL
High
2.5/3.3V 16-
Bit D-Type
Flip-Flop;
Postive-Edge 2~4
Trigger with
Bus Hold (3-
State)
SOT370-1
(SSOP48)
74ALVT16374DL
48 None
High
Products, packages, availability and ordering
Type number
North American Ordering code Marking/Packing Package Device
Buy online
IC packing info
type number
(12NC)
status
SOT370-
1
Standard Marking
* Tube
Full production
Full production
Full production
74ALVT16374DGG 74ALVT16374DG 9352 096 60112
(SSOP48)
SOT370-
1
Standard Marking
SMD, 13"
74ALVT16374DG-
T
9352 096 60118 * Reel Pack,
(SSOP48)
SOT370-
1
Standard Marking
* Tube
74ALVT16374DL 74ALVT16374DL 9352 096 50112
(SSOP48)
SOT370-
1
Standard Marking
9352 096 50118 * Reel Pack,
SMD, 13"
74ALVT16374DL-
T
Full production
(SSOP48)
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
Similar products
74ALVT16374 links to the similar products page containing an overview of products that are similar in function or
related to the type number(s) as listed on this page. The similar products page includes products from the same catalog
tree(s), relevant selection guides and products from the same functional category.
Support & tools
Innovative Low Voltage Logic Solutions(date 01-Aug-00)
Introduction to Advanced BiCMOS Logic Products(date 01-Mar-98)
Family specifications ALVT16, family characteristics(date 01-Mar-98)
Introduction to Advanced Low-Voltage Technology(date 01-Mar-98)
Advanced BiCMOS features(date 01-Jan-98)
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