935218860518 [NXP]
IC COLOR SIGNAL ENCODER, PQCC68, PLASTIC, LCC-68, Color Signal Converter;
| 型号： | 935218860518 |
| 厂家： | 
NXP |
| 描述： | IC COLOR SIGNAL ENCODER, PQCC68, PLASTIC, LCC-68, Color Signal Converter 编码器 商用集成电路 |
| 文件： | 总39页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7184; SAA7185B
Digital Video Encoders
(DENC2-M6)
1996 Jul 03
Preliminary specification
Supersedes data of 1995 Nov 14
File under Integrated Circuits, IC22
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
FEATURES
• CMOS 5 V device
• Digital PAL/NTSC encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data
• 8-bit wide MPEG port
GENERAL DESCRIPTION
• Input data format Cb, Y, Cr etc. (CCIR 656)
• 16-bit wide YUV input port
• I2C-bus control port or alternatively MPU parallel control
The SAA7184 and SAA7185B digital video encoders 2
(DENC2-M6) encode digital YUV video data to an NTSC
or PAL CVBS or S-Video signal.
port
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. The device includes a
sync/clock generator and on-chip Digital-to-Analog
Converters (DACs).
• Encoder can be master or slave
• Programmable horizontal and vertical input
synchronization phase
• Programmable horizontal sync output phase
• OVL overlay with Look-Up Tables (LUTs) 8 × 3 bytes
• Colour bar generator
The circuit is compatible to the DIG-TV2 chip family.
• Line 21 closed caption encoder
• Cross-colour reduction
• Macrovision revision_6 Pay-per-View copy protection
system as option (SAA7184 only). Remark: This device
is protected by U.S. patent numbers 4631603 4577216
and 4819098 and other intellectual property rights.
Use of the Macrovision anticopy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
• DACs operating at 27 MHz with 10-bit resolution
• Controlled rise and fall times of output syncs and
blanking
• Down-mode of DACs
• CVBS and S-Video output simultaneously
• PLCC68 package.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic leaded chip carrier; 68 leads
VERSION
SAA7184WP
PLCC68
SOT188-2
SAA7185BWP
1996 Jul 03
2
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
analog supply voltage
digital supply voltage
analog supply current
digital supply current
V
V
VDDD
IDDA
IDDD
Vi
4.5
−
5.0
50
5.5
55
mA
mA
V
−
130
170
input signal voltage levels
TTL compatible
Vo(p-p)
analog output signal voltages Y, C and CVBS without load
(peak-to-peak value)
−
2
−
V
RL
load resistance
80
−
−
−
−
−
−
Ω
ILE
LF integral linearity error
LF differential linearity error
operating ambient temperature
±2
±1
+70
LSB
LSB
°C
DLE
Tamb
−
0
BLOCK DIAGRAM
V
V
DDA1
to
V
KEY
V
DDD1
refH
DDA4
OVL0
to OVL2
to V
IOA
SEL_ED
18
RTCI
43
DDD3
48,50,
54,56
53
47 55
31
32 to 34
17,37,67
20 to 27
MP7
CVBS
Y
8
8
A
to MP0
DATA
MANAGER
OUTPUT
INTERFACE
51
49
ENCODER
8
9 to 16
VP0
D
to VP7
CHROMA
52
46
8
V
8
SSA
internal control bus
V
refL
29
RCM1
8
clock timing signals
8
SAA7184
SAA7185B
30
RCM2
8
CONTROL
SYNC
INTERFACE
CLK
1,8,19
28,35,
42,62
63 to 66
2 to 5
68
61 59 60 58 57
41
40
38 39 36
6
7
MGC679
V
SSD1
to
SSD7
A0/SDA
RES
LLC
CDIR
RCV2
CSN/SA
XTALI
DP0
to DP7
V
RWN/SCL DTACK
XTALO
CREF
RCV1
SEL_MPU
Fig.1 Block diagram.
lpagwdeiht
1996 Jul 03
3
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
PINNING
SYMBOL
VSSD1
PIN
1
I/O
−
DESCRIPTION
digital ground 1
DP4 to DP7
2 to 5
I/O
Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
RCV1
RCV2
6
7
I/O
I/O
Raster control 1 for video port; depending on the synchronization mode, this
pin receives or provides a VS/FS/FSEQ signal.
Raster control 2 for video port; depending on the synchronization mode, this
pin receives or provides an HS/HREF/CBL signal.
VSSD2
8
−
digital ground 2
VP0 to VP7
9 to 16
I
Video port; this is an input for CCIR 656 compatible multiplexed video data. If
the 16-bit DIG-TV2 format is used, then Y data is input.
VDDD1
17
18
I
I
digital supply voltage 1
SEL_ED
select encoder data; selects input data either from the MPEG port or from
the video port
VSSD3
19
20 to 27
28
−
I
digital ground 3
MP7 to MP0
VSSD4
MPEG port; it is an input for CCIR 656 style multiplexed YUV data.
digital ground 4
−
O
O
RCM1
29
Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal.
RCM2
30
Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG
decoder.
KEY
31
32 to 34
35
I
I
key signal for OVL (active HIGH)
OVL0 to OVL2
VSSD5
on-screen display data; this is the index for the internal OVL look-up tables
digital ground 5
−
I
CDIR
36
Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal,
if not LLC and CREF are generated by the internal crystal oscillator.
VDDD2
LLC
37
38
I
digital supply voltage 2
I/O
Line-locked clock; this is the 27 MHz master clock for the encoder. The
direction is set by the CDIR pin.
CREF
39
I/O
Clock reference signal; this is the clock qualifier for DIG-TV2 compatible
signals. The polarity is programmable by software.
XTALO
XTALI
40
41
O
I
crystal oscillator output (to crystal)
Crystal oscillator input (from crystal). If the oscillator is not used, this pin
should be connected to ground.
VSSD6
RTCI
42
43
−
digital ground 6
I
Real time control Input; if the clock is provided by the SAA7151B or
SAA7111, RTCI should be connected to the RTCO pin of the decoder to
improve the signal quality.
AP
44
45
46
47
48
−
−
I
test pin (should be connected to digital ground for normal operation)
test pin (should be connected to digital ground for normal operation)
lower reference voltage input for the DACs
SP
VrefL
VrefH
VDDA1
I
upper reference voltage input for the DACs
I
analog positive supply voltage 1 for the DACs and output amplifiers
1996 Jul 03
4
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SYMBOL
CHROMA
PIN
I/O
DESCRIPTION
analog output of the chrominance signal
49
50
51
52
53
54
55
O
I
VDDA2
Y
analog supply voltage 2 for the DACs and output amplifiers
analog output of the luminance signal
O
−
O
I
VSSA
CVBS
VDDA3
IOA
analog ground for the DACs and output amplifiers
analog output of the CVBS signal
analog supply voltage 3 for the DACs and output amplifiers
I
current input for the output amplifiers (connected via a 15 kΩ resistor to
VDDA
)
VDDA4
RES
56
57
I
I
analog supply voltage 4 for the DACs and output amplifiers
Reset input, active LOW. After reset is applied, all outputs are in 3-state input
mode. The I2C-bus receiver waits for the start condition.
DTACK
58
59
60
61
O
I
Data acknowledge output of the parallel MPU interface, active LOW,
otherwise high impedance.
RWN/SCL
A0/SDA
CSN/SA
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU
interface. Otherwise it is the I2C-bus serial clock input.
I/O
I
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU
interface. Otherwise it is the I2C-bus serial data input/output.
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel
MPU interface. Otherwise it is the I2C-bus slave address select pin. When
LOW slave address = 88H, when HIGH slave address = 8CH.
VSSD7
62
−
digital ground 7
DP0 to DP3
63 to 66
I/O
Lower 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
VDDD3
67
68
I
I
digital supply voltage 3
SEL_MPU
Select MPU interface input; if it is HIGH, the parallel MPU interface is active,
if not the I2C-bus interface will be used.
1996 Jul 03
5
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
61
43 RTCI
CSN/SA
V
V
42
62
SSD7
SSD6
63
64
65
66
67
DP0
DP1
DP2
41 XTALI
40 XTALO
39
CREF
DP3
38 LLC
V
37
36
35
34
V
DDD2
DDD3
SEL_MPU 68
CDIR
V
SAA7184
SAA7185B
V
1
SSD1
SSD5
2
3
4
5
6
7
8
9
DP4
DP5
OVL2
33 OVL1
DP6
32
31
30
29
28
27
OVL0
KEY
DP7
RCM2
RCM1
RCV1
RCV2
V
V
SSD2
VP0
SSD4
MP0
MGC678
Fig.2 Pin configuration.
1996 Jul 03
6
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision.
It also supports OVL via KEY and 3-bit overlay techniques
using a 24 × 8 LUT.
FUNCTIONAL DESCRIPTION
The digital MPEG-compatible video encoder (DENC2-M6)
encodes digital luminance and chrominance into analog
CVBS and S-Video (Y/C) signals simultaneously. NTSC-M
and PAL B/G standards and sub-standards are also
supported.
The IC can be programmed via the I2C-bus or via the 8-bit
MPU interface, but only one interface configuration can be
active at a time. If the 16-bit video port mode (VP and DP)
is being used, only the I2C-bus interface can be selected.
The basic encoder function consists of subcarrier
generation and colour modulation plus insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of RS-170-A and CCIR 624.
A number of possibilities are provided for setting the
different video parameters such as:
black and blanking level control
colour subcarrier frequency
For ease of analog post filtering the signals are twice
oversampled, with respect to the pixel clock, before
digital-to-analog conversion.
black variable burst amplitude etc.
For total filter transfer characteristics see Figs 3, 4,
5 and 6. The DACs are realized with full 10-bit resolution.
The encoder provides three 8-bit wide data ports that
serve different applications.
During reset (RES = LOW) and after reset is released, all
digital I/O stages are set to the input mode. A reset forces
the control interfaces to abort any running bus transfer and
to set register 3AH to contents 1FH, register 61H to
contents 06H, and registers 6CH and 7AH to contents
00H. All other control registers are not influenced by a
reset.
The MPEG port and the video port accept 8 lines
multiplexed Cb-Y-Cr data.
The video port is also able to accommodate DIG-TV2
family compatible 16-bit YUV signals. In this event, the
data port is used for the U/V components.
Data manager
Real time arbitration on the data stream to be encoded is
performed in the data manager.
Alternatively, the data port can accommodate the data of
an 8-bit wide microprocessor interface.
Depending on the hardware conditions (signals on pins
SEL_ED, KEY, OVL2 to OVL0, MP7 to MP0, VP7 to VP0
and DP7 to DP0) and different software programming,
either data from the MP port, from the VP port or from the
OVL port, is selected to be encoded to CVBS and Y/C
signals.
The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656
(D1 format) compatible, but the SAV, EAV etc. codes are
not decoded.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock frequency of
13.5 MHz, needs to be supplied externally. A crystal
oscillator input/output pair of pins and an on-chip clock
driver are provided optionally. It is also possible to connect
the Philips Digital Video Decoder (SAA7111 or
SAA7151B) in conjunction with a CREF clock qualifier to
the DENC2-M6 via the RETCI pin (connected to RTCO) of
a decoder. Information concerning the actual subcarrier,
PAL-ID and (with SAA7111) definite subcarrier phase can
be inserted.
Optionally, the OVL colour look-up tables located in this
block can be read out in a pre-defined sequence
(8 steps per active video line) thereby achieving, for
example, a colour bar test pattern generator without the
need for an external data source. The colour bar function
is only under software control.
Encoder
VIDEO PATH
The DENC2-M6 synthesizes all necessary internal
signals, colour subcarrier frequency and synchronization
signals, from that clock. The DENC2-M6 is always the
timing master for the MPEG port but can also be
configured as master or slave for the video port.
The encoder generates luminance and colour subcarrier
output signals, suitable for use as CVBS or separate Y/C
signals, from the Y, U and V baseband signals.
1996 Jul 03
7
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
The luminance gain and offset are modified (offset being
programmable within a certain range to enable different
black level set-ups). After the signals have been inserted,
a fixed synchronization level in accordance with standard
composite synchronization schemes and blanking level,
(also programmable in a certain range to allow for
manipulations with Macrovision anti-tapping) additional
insertion of AGC super white pulses (programmable in
height) is supported.
It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times horizontal line frequency.
Output interface
In the output interface, encoded Y and C signals are
converted from digital to analog in a 10-bit resolution and
then combined into a 10-bit CVBS signal. Also, in front of
the summation point, the luminance signal can be fed
through a further filter stage (optional), thereby
In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
This filter is also used to define smoothed transients for
synchronization pulses and blanking period. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs 5 and 6.
suppressing components in the subcarrier frequency
range. Thus, a type of cross colour reduction is provided,
which is useful in a standard TV set with CVBS input.
The slopes of the synchronization pulses are not affected
with any active cross colour reduction.
Three different filter characteristics or bypass are
available, see Fig.5.
The chrominance gain is modified (programmable
separately for U and V), a standard dependent burst is
inserted before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thereby
providing a higher colour bandwidth, which can be used for
the Y/C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by 15
⁄16 with respect to Y
and C DACs to make maximum use of conversion ranges.
Outputs of all DACs can be set together, via software
control, to minimum output voltage for either purpose.
Synchronization
The amplitude of the inserted burst is programmable within
a certain range, suitable for standard signals and for
special effects. Colour in a 10-bit resolution is provided on
the subcarrier after the succeeding quadrature modulator.
The synchronization of the DENC2 is able to operate in
two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour, related to the video signal on VP
(and DP, if used), can be influenced by programming the
polarity and on-chip delay of RCV1. The active slope of
RCV1 defines the vertical phase and, as an option, the
odd/even and colour frame phase to be initialized. It can
also be used to set the horizontal phase.
The numeric ratio between Y and C outputs is in
accordance with set standards.
CLOSED CAPTION ENCODER
Using the closed caption encoder circuit, data in
accordance with the specification of closed caption or
extended data service, delivered by the control interface,
can be encoded (line 21). Two dedicated pairs of bytes
(two bytes per field) are possible, each pair preceded by
run-in clocks and framing code.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be applied at pin RCV2. Timing
and trigger behaviour can also be influenced for RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of the DENC2-M6 will become free-running, thus an
arbitrary number of synchronization slopes may miss, but
no additional pulses must occur (such as with wrong
phase).
The actual line number where data is to be encoded, can
be modified within a certain range.
The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
1996 Jul 03
8
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
In the master mode, the time base of the circuit is
continuously free-running. At the RCV1 port, the IC can
output:
The parallel interface is defined by:
D7 to D0 data bus
CS active LOW chip select signal
RW read/write signal, LOW for a write cycle
• A vertical sync signal (VS) with 3 or 2.5 lines duration, or
• An odd/even signal which is LOW in odd fields, or
DTACK 680xx style data acknowledge (handshake),
active-LOW
• A field sequence signal (FSEQ) which is HIGH in the first
of 4 respectively 8 fields.
A0 register select, LOW selects address, HIGH selects
data.
The IC can provide a horizontal pulse with programmable
start and stop phase at the RCV2 port. This pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The parallel interface uses two registers, one
auto-incremental containing the current address of a
control register (equals subaddress with I2C-bus control),
and one containing actual data. The currently addressed
register is mapped to the corresponding control register.
The phase of the output pulses at RCV1 or RCV2 are
referenced to the VP port, polarity of both signals is
selectable.
The status byte can be read (optionally) via a read access
to the address register, no other read access is provided.
The DENC2-M6 is always the timing master for the source
at the MP input. The IC provides two signals for
synchronizing this source:
Input levels and formats
1. At the RCM1 port the same signals as at RCV1
(as output) are available.
DENC2-M6 accepts digital YUV data with levels (digital
codes) in accordance with CCIR 601.
2. At RCM2 the IC provides a horizontal pulse with
programmable start and stop phase.
Deviating amplitudes in the colour difference signals can
be compensated for by independent gain control setting,
while the gain for luminance is set to predefined values,
distinguishable for 7.5 IRE set-up or without set-up.
The start and end of the active part can be programmed.
The active part of a field always starts at the beginning of
a line if the standard blanking option SBLBN is not set.
The MPEG port accepts only 8-bit multiplexed CCIR 656
compatible data.
Control interface
If the I2C-bus interface is used, the VP port can
DENC2-M6 contains two control interfaces, an I2C-bus
slave transceiver and an 8-bit parallel microprocessor
interface. The interfaces cannot be used simultaneously.
accommodate both formats, 8-bit multiplexed Cb-Y-Cr
data on the VP lines, or the 16-bit DTV2 format with the Y
signal on the VP lines and the UV signal on the DP port.
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one status byte which can be read.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
Two I2C-bus slave addresses can be selected
(pin SEL_MPU must be LOW):
88H: pin 61 = LOW
8CH: pin 61 = HIGH.
1996 Jul 03
9
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 1 CCIR signal component levels
SIGNAL
IRE
DIGITAL LEVEL
CODE
0
16
126
235
16
Y
50
straight binary
100
bottom peak
colourless
top peak
bottom peak
colourless
top peak
Cb
Cr
128
240
16
straight binary
straight binary
128
240
Table 2 8-bit multiplexed format (similar to CCIR 656)
TIME
0
1
2
2
4
5
6
7
Sample
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Luminance pixel number
Colour pixel number
0
1
2
3
0
2
Table 3 16-bit multiplexed format (DTV2 format)
TIME
0
1
2
3
4
5
6
7
Sample Y line
Y0
Cb0
0
Y1
Cr0
1
Y2
Cb2
2
Y3
Cr2
3
Sample UV line
Luminance pixel number
Colour pixel number
0
2
1996 Jul 03
10
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
1996 Jul 03
11
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
1996 Jul 03
12
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
I2C-bus format
Table 5 I2C-bus address; see Table 6
S
SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
--------
DATA n ACK
P
Table 6 Explanation of Table 5
PART
DESCRIPTION
S
START condition
Slave address
1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1)
acknowledge, generated by the slave
subaddress byte
ACK
Subaddress (note 2)
DATA
--------
P
data byte
continued data bytes and ACKs
STOP condition
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
Slave Receiver
Table 7 Subaddress 3A
DATA BYTE
LOGIC LEVEL
DESCRIPTION
Cb/Cr data at MP is two’s complement.
MUV2C
0
1
0
1
0
1
0
1
0
1
0
1
Cb/Cr data at MP is straight binary. Default after reset.
Y data at MP is two’s complement.
MY2C
VUV2C
VY2C
Y data at MP is straight binary. Default after reset.
Cb/Cr data input to VP or DP is two’s complement
Cb/Cr data input to VP or DP is straight binary. Default after reset.
Y data input to VP is two’s complement
Y data input to VP is straight binary. Default after reset.
selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr).
selects CCIR 656 compatible format on VP (8 lines Cb, Y, Cr). Default after reset.
data from input ports is encoded. Default after reset.
V656
CBENB
colour bar with programmable colours (entries of OVL_LUTs) is encoded.
The LUTs are read in upward order from index 0 to index 7.
1996 Jul 03
13
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 8 Subaddress 42 to 59
DATA BYTE(1)
COLOUR
INDEX(2)
OVLY
OVLU
OVLV
White
107 (6BH)
107 (6BH)
82 (52H)
0 (00H)
0 (00H)
0 (00H)
0 (00H)
0
Yellow
Cyan
144 (90H)
172 (ACH)
38 (26H)
29 (1DH)
182 (B6H)
200 (C8H)
74 (4AH)
56 (38H)
218 (DAH)
227 (E3H)
112 (70H)
84 (54h)
18 (12H)
14 (0EH)
144 (90H)
172 (ACH)
162 (A2H)
185 (B9H)
94 (5EH)
71 (47H)
112 (70H)
84 (54H)
238 (EEH)
242 (F2H)
0 (00H)
1
2
3
4
5
6
7
34 (22H)
42 (2AH)
03 (03H)
Green
Magenta
Red
17 (11H)
240 (F0H)
234 (EAH)
212 (D4H)
209 (D1H)
193 (C1H)
169 (A9H)
163 (A3H)
144 (90H)
144 (90H)
Blue
Black
0 (00H)
0 (00H)
0 (00H)
Notes
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601
(Y, Cb, Cr), but two’s complement, e.g. for a 100
⁄
100 (upper number) or 100
⁄75 (lower number) colour bar.
2. For normal colour bar with CBENB = logic 1.
Table 9 Subaddress 5A
DATA BYTE
DESCRIPTION
CHPS
phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in
steps of 360/256 degrees.
Table 10 Subaddress 5B and 5D
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINU
variable gain for Cb signal; white-to-black = 92.5 IRE(1)
input representation in
accordance with
GAINU = 118 (76H)
“CCIR 601”
GAINU = 0
output subcarrier of U contribution = 0
output subcarrier of U contribution = nominal
white-to-black = 100 IRE(2)
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
Notes
1. GAINU = −2.17 × nominal to +2.16 × nominal.
2. GAINU = −2.05 × nominal to +2.04 × nominal.
1996 Jul 03
14
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 11 Subaddress 5C and 5E
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINV
variable gain for Cr signal; white-to-black = 92.5 IRE(1)
input representation in
accordance with
GAINV = 165 (A5H)
“CCIR 601”
GAINV = 0
output subcarrier of V contribution = 0
output subcarrier of V contribution = nominal
white-to-black = 100 IRE(2)
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
Notes
1. GAINV = −1.55 × nominal to + 0.55 × nominal.
2. GAINV = −1.46 × nominal to + 0.46 × nominal.
Table 12 Subaddress 5D
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLCKL
variable black level; input white-to-sync = 140 IRE(1)
representation in
accordance with
BLCKL = 63 (3FH)
“CCIR 601”
BLCKL = 0
output black level = 24 IRE
output black level = 49 IRE
white-to-sync = 143 IRE(2)
BLCKL = 0
output black level = 24 IRE
output black level = 50 IRE
BLCKL = 63 (3FH)
Notes
1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal.
2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
Table 13 Subaddress 5E
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLNNL
variable blanking level
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
output blanking level = 42 IRE
BLNNL = 63 (3FH)
white-to-sync = 143 IRE(2)
BLNNL = 0
output blanking level = 17 IRE
output blanking level = 43 IRE
BLNNL = 63 (3FH)
Notes
1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
1996 Jul 03
15
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 14 Subaddress 5F (CCRS and BLNVB; note 1)
DATA BYTE
FUNCTION
CCRS1
CCRS0
0
0
1
1
0
1
0
1
no cross colour reduction (for overall transfer characteristic of luminance see Fig.5)
cross colour reduction #1 active (for overall transfer characteristic see Fig.5)
cross colour reduction #2 active (for overall transfer characteristic see Fig.5)
cross colour reduction #3 active (for overall transfer characteristic see Fig.5)
Note
1. BLNVB = vertical blanking level during vertical blanking interval and its value is typically identical to BLNNL.
Table 15 Subaddress 61
DATA
BYTE
LOGIC
LEVEL
DESCRIPTION
864 total pixel clocks per line. Default after reset.
FISE
0
1
0
1
0
858 total pixel clocks per line
PAL
NTSC encoding (non-alternating V component)
PAL encoding (alternating V component). Default after reset.
SCBW
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4). Default after reset.
RTCE
0
1
no real time control of generated subcarrier frequency. Default after reset.
real time control of generated subcarrier frequency through SAA7151B or SAA7111
(see Fig.9)
YGS
INPI
0
1
0
1
0
1
luminance gain for white − black 100 IRE. Default after reset.
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
PAL switch phase is nominal. Default after reset.
PAL switch phase is inverted compared to nominal
DACs in normal operational mode. Default after reset.
DACs forced to lowest output voltage
DOWN
1996 Jul 03
16
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 16 Subaddress 62
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BSTA
amplitude of colour burst;
input representation in
white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding
accordance with CCIR 601
BSTA = 0 to 1.25 × nominal(1)
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
BSTA = 0 to 1.76 × nominal(2)
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding
BSTA = 0 to 1.20 × nominal(3)
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
BSTA = 0 to 1.67 × nominal(4)
DECTYP
real time control input (RTCI)
logic 0
control from SAA7151B digital
colour decoder
logic 1
control from SAA7111 video
input processor (VIP)
Notes
1. Recommended value: BSTA = 102 (66H).
2. Recommended value: BSTA = 72 (48H).
3. Recommended value: BSTA = 106 (6AH).
4. Recommended value: BSTA = 75 (4BH).
Table 17 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency
(in multiples of line
FSC3 = most significant byte
f
FSC = round fsc × 2 32
-------
fllc
FSC0 = least significant byte
frequency);
f
llc = clock frequency (in
see note 1
multiples of line frequency)
Note
1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
1996 Jul 03
17
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 18 Subaddress 67 to 6A
DATA BYTE(1)
DESCRIPTION
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
Note
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 19 Subaddress 6B
DATA BYTE
SCCLN
DESCRIPTION
selects the actual line, where closed caption or extended data is encoded; see note 1
defines video data of MP port or VP (DP) port to be encoded; see Table 20
0 = normal polarity of CREF for DIG TV2 compatible input signals; 1 = inverted
MODIN
PCREF
Note
1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems.
Table 20 Logic levels and function of MODIN
DATA BYTE
FUNCTION
MODIN1
MODIN0
0
0
1
1
0
1
0
1
unconditionally from MP port
from MP port, if pin SEL_ED = HIGH; otherwise from VP port
unconditionally from VP port
from VP port, if pin SEL_ED = HIGH; otherwise from MP port
1996 Jul 03
18
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 21 Subaddress 6C
DATA BYTE LOGIC LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively. Default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
ORCV2
CBLF
0
1
0
pin RCV2 is switched to input. Default after reset
pin RCV2 is switched to output
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval). Default
after reset
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only
(if TRCV2 = 1). Default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘composite blanking not’ signal i.e. a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking
Interval, which is defined by FAL and LAL (PRCV2 must be LOW)
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization
(if TRCV2 = 1) and as an internal blanking signal
PRCV1
0
1
polarity of RCV1 as output is active HIGH, rising edge is taken when input,
respectively. Default after reset
polarity of RCV1 as output is active LOW, falling edge is taken when input,
respectively
ORCV1
TRCV2
SRCV1
0
1
0
1
−
pin RCV1 is switched to input. Default after reset
pin RCV1 is switched to output
horizontal synchronization is taken from RCV1 port. Default after reset
horizontal synchronization is taken from RCV2 port
defines signal type on pin RCV1; see Table 22
Table 22 Logic levels and function of SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
FUNCTION
SRCV11
SRCV10
0
0
1
0
1
0
VS
FS
VS
FS
vertical sync each field. Default after reset
frame sync (odd/even)
FSEQ
FSEQ
field sequence, vertical sync every fourth field
(PAL = 0) or eighth field (PAL = 1)
1
1
not applicable not applicable
Table 23 Subaddress 6D
DATA BYTE
DESCRIPTION
CCEN
SRCM
enables individual line 21 encoding; see Table 24
defines signal type on pin RCM1; see Table 25
1996 Jul 03
19
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 24 Logic levels and function of CCEN
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
line 21 encoding OFF
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
Table 25 Logic levels and function of SRCM
DATA BYTE
AS OUTPUT
FUNCTION
SRCM1
SRCM0
0
0
1
0
1
0
VS
FS
vertical sync each field
frame sync (odd/even)
FSEQ
field sequence, vertical sync every fourth field (FISE = 1) or eighth
field (FISE = 0)
1
1
not applicable
Table 26 Subaddress 6E to 6F
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 037H
Table 27 Subaddress 70
DATA BYTE LOGIC LEVEL
DESCRIPTION
VTRIG
−
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
SBLBN
PHRES
0
1
vertical blanking is defined by programming of FAL and LAL
vertical blanking is forced in accordance with CCIR-624 (50 Hz) or RS170A (60 Hz);
note 1
−
selects the phase reset mode of the colour subcarrier generator; see Table 28
Note
1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events.
1996 Jul 03
20
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 28 Logic levels and function of PHRES
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
0
1
1
0
1
0
1
no reset or reset via RTCI from SAA7111 if bit RTCE = 1
reset every two lines
reset every eight fields
reset every four fields
Table 29 Subaddress 71 to 73
DATA BYTE
DESCRIPTION
BMRQ
beginning of MP request signal (RCM2)
values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at
BMRQ = 0F9H [117H]
EMRQ
end of MP request signal (RCM2)
values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at
EMRQ = 683H [691H]
Table 30 Subaddress 77 to 79
DATA BYTE
DESCRIPTION
BRCV
beginning of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
BRCV = 0F9H [117H]
ERCV
end of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
ERCV = 683H [691H]
1996 Jul 03
21
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 31 Subaddress 7A
DATA BYTE
DESCRIPTION
FLC1
FLC0
0
0
field length control interlaced 312.5 lines/fields at 50 Hz, 262.5 lines/fields at 60 Hz
(reset default)
0
1
1
1
0
1
field length control non-interlaced 312 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
Table 32 Subaddress 7B to 7D
DATA BYTE
DESCRIPTION
FAL
first active line = FAL + 4 for M systems; = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M systems; = LAL for other systems, measured in lines
LAL = 0 coincides with the first field synchronization pulse
Slave Transmitter
Table 33 Slave Transmitter (slave address 89H or 8DH)
DATA BYTE
D4 D3
REGISTER
SUBADDRESS
FUNCTION
D7
D6
D5
D2
D1
D0
Status byte
−
VER2
VER1
VER0 CCRDO CCRDE FSQ2
FSQ1
FSQ0
Table 34 No subaddress
DATA BYTE
DESCRIPTION
VER
Version identification of the device. It will be changed with all versions of the IC that have different
programming models. Current version is 100 binary.
CCRDO
1 = closed caption bytes of the odd field have been encoded.
0 = the bit is reset after information has been written to the subaddresses 67 and 68. It is set
immediately after the data have been encoded.
CCRDE
FSQ
1 = closed caption bytes of the even field have been encoded.
0 = the bit is reset after information has been written to the subaddresses 69 and 6A. It is set
immediately after the data have been encoded.
State of the internal field sequence counter.
Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH.
1996 Jul 03
22
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
MBE737
6
G
v
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.3 Chrominance transfer characteristic 1.
MBE735
handbook, halfpage
2
G
v
(dB)
0
(1)
(2)
−2
−4
−6
0
0.4
0.8
1.2
1.6
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 2.
23
1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
MBE738
6
G
v
(4)
(dB)
0
(2)
(3)
−6
−12
−18
−24
−30
−36
(1)
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) CCRS1 = 0; CCRS0 = 1.
(2) CCRS1 = 1; CCRS0 = 0.
(3) CCRS1 = 1; CCRS0 = 1.
(4) CCRS1 = 0; CCRS0 = 0.
Fig.5 Luminance transfer characteristic 1.
MBE736
handbook, halfpage
1
G
v
(dB)
0
−1
−2
−3
−4
−5
0
2
4
6
f (MHz)
CCRS1 = 0; CCRS0 = 0.
Fig.6 Luminance transfer characteristic 2.
24
1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
CHARACTERISTICS
VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS
MIN.
MAX.
UNIT
Supply
VDDD
VDDA
IDDD
IDDA
digital supply voltage
4.5
5.5
V
analog supply voltage
digital supply current
analog supply current
4.75
−
5.25
170
55
V
note 1
mA
mA
note 1
−
Inputs
VIL
LOW level input voltage
−0.5
+0.8
V
(except SDA, SCL, AP, SP and XTALI)
VIH
HIGH level input voltage
2.0
VDDD + 0.5 V
(except LLC, SDA, SCL, AP, SP and XTALI)
HIGH level input voltage (LLC)
input leakage current
input capacitance
2.4
−
VDDD + 0.5 V
ILI
CI
1
µA
clocks operating
data available
−
10
8
pF
pF
pF
−
I/Os at high impedance
−
8
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
note 2
note 2
0
0.6
V
VOH
HIGH level output voltage
(except LLC, SDA, DTACK and XTALO)
2.4
2.6
VDDD + 0.5 V
VDDD + 0.5 V
HIGH level output voltage (LLC)
I2C-bus; SDA and SCL
VIL
VIH
II
LOW level input voltage
−0.5
3.0
−10
−
+1.5
V
HIGH level input voltage
input current
VDDD + 0.5 V
VI = LOW or HIGH
IOL = 3 mA
+10
0.4
−
µA
VOL
IO
LOW level output voltage (SDA)
output current
V
during acknowledge
3
mA
Clock timing (LLC)
TLLC
cycle time
note 3
note 4
note 3
note 3
34
40
−
41
60
5
ns
%
δ
tr
tf
duty factor tHIGH/TLLC
rise time
ns
ns
fall time
−
6
Input timing
tSU
input data set-up time (any other except
SEL_MPU, CDIR, RW/SCL, A0/SDA,
CS/SA, RES, AP and SP)
6
3
−
−
ns
ns
tHD
input data hold time (any other except
SEL_MPU, CDIR, RW/SCL, A0/SDA,
CS/SA, RES, AP and SP)
1996 Jul 03
25
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency (usually 27 MHz)
3rd harmonic
−
30
MHz
10−6
∆f/fn
permissible deviation of nominal frequency note 5
−50
+50
CRYSTAL SPECIFICATION
Tamb
CL
operating ambient temperature
0
8
−
70
−
°C
pF
Ω
load capacitance
RS
C1
series resistance
80
motional capacitance (typical)
parallel capacitance (typical)
1.5 −20% 1.5 +20% fF
3.5 −20% 3.5 +20% pF
C0
MPU interface timing
tAS
address set-up time
note 6
note 6
9
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
address hold time
0
−
tRWS
tRWH
tDD
read/write set-up time
9
−
read/write hold time
0
−
data bus floating from CS (read)
data valid from CS (read)
data bus set-up time (write)
data bus hold time (write)
acknowledge delay from CS
CS HIGH from acknowledge
DTACK floating from CS HIGH
notes 7, 8 and 9
notes 7 and 8
note 6
75
38
9
142
105
−
tDF
tDS
tDH
note 6
9
−
tACS
tCSD
tDAT
notes 7 and 8
112
0
180
−
notes 7 and 8; n = 7
75
142
Data and reference signal output timing
CL
output load capacitance
output hold time
7.5
4
40
−
pF
ns
ns
tOH
tOD
output delay time
CREF in output mode
note 10
−
25
Chroma, Y and CVBS outputs
Vo(p-p)
RI
output signal voltage (peak-to-peak value)
1.9
18
80
10
−
2.1
35
−
V
internal series resistance
Ω
RL
output load resistance
Ω
B
output signal bandwidth of DACs
LF integral linearity error of DACs
LF differential linearity error of DACs
−3 dB
−
MHz
LSB
LSB
ILE
DLE
±2
±1
−
1996 Jul 03
26
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Notes to the Characteristics
1. At maximum supply voltage with highly active input signals.
2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF.
3. The data is for both input and output direction.
4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
6. The value is calculated via equation t = tSU + tHD
7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz.
8. The values given are calculated via equation tdmax = tOD + n × tLLC + tLLC + tSU and
tdmin = tOH + n × tLLC + tLLC – tHD
9. The falling edge of DTACK will always occur 1 × LLC after data is valid.
10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
T
LLC
t
HIGH
2.6 V
1.5 V
0.6 V
LLC clock output
t
t
f
t
r
HD; DAT
T
LLC
t
HIGH
2.4 V
1.5 V
0.8 V
LLC clock input
t
t
f
t
r
HD; DAT
t
SU; DAT
2.0 V
0.8 V
valid
valid
input data
valid
not valid
t
d
t
HD; DAT
2.4 V
0.6 V
output data
valid
not valid
MBE742
Fig.7 Clock data timing.
1996 Jul 03
27
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
LLC
CREF
VP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
RCV2
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 lines digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (BRCV2).
Fig.8 Digital TV timing.
H/L transition
count start
4 bits
reserved
5 bits
reserved
sequence
bit (1) reserved (2)
HPLL
increment
128
13
0
21
0
RTCI
not used in DENC2
valid
sample sample
invalid
8/LLC
MBE743
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit.
Fig.9 RTCI timing.
1996 Jul 03
28
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
A0
t
t
AH
AS
CSN
RWN
t
t
RWH
RWS
D(7 to 0)
t
t
DF
DD
DTACK
t
t
t
DAT
MBE740
ACS
CSD
Fig.10 MPU interface timing (READ cycle).
A0
t
t
AS
AH
CSN
RWN
t
t
RWS
RWH
D(7 to 0)
DTACK
t
t
DF
DS
MBE741
t
t
t
DAT
ACS
CSD
Fig.11 MPU interface timing (WRITE cycle).
29
1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
APPLICATION INFORMATION
GM6C80
a n d b o o k , f u l l p a g e w
1996 Jul 03
30
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
PACKAGE OUTLINE
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
e
e
D
E
y
X
A
60
44
Z
E
43
61
b
p
b
1
w
M
68
1
H
E
E
pin 1 index
A
e
A
1
A
4
(A )
3
k
L
1
p
9
k
27
β
detail X
10
26
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 24.33 24.33
0.66 24.13 24.13
23.62 23.62 25.27 25.27 1.22
22.61 22.61 25.02 25.02 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.30
0.020 0.01 0.13
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 0.958 0.958
0.026 0.950 0.950
0.930 0.930 0.995 0.995 0.048
0.890 0.890 0.985 0.985 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT188-2
112E10
MO-047AC
1996 Jul 03
31
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Jul 03
32
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jul 03
33
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
NOTES
1996 Jul 03
34
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
NOTES
1996 Jul 03
35
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Tel. +381 11 825 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com/ps/
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/02/pp36
Date of release: 1996 Jul 03
Document order number: 9397 750 00439
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SAA7184; SAA7185B; Digital Video Encoders (DENC2-M6)
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Description
Consumer Multimedia
Systems
Communications
The SAA7184 and SAA7185B digital video encoders 2 (DENC2-M6) encode digital YUV video data to an NTSC or PAL CVBS or S-Video
signal.
PC/PC-peripherals
Cross reference
The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 :2 :2 multiplexed formats, for example MPEG decoded
data. The device includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs).
Models
Packages
The circuit is compatible to the DIG-TV2 chip family.
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
Features
l CMOS 5 V device
l Digital PAL/NTSC encoder
l System pixel frequency 13.5 MHz
l Accepts MPEG decoded data
Relevant Links
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l 8-bit wide MPEG port
l Input data format Cb, Y, Cr etc. (CCIR 656)
l 16-bit wide YUV input port
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l I2C-bus control port or alternatively MPU parallel control port
l Encoder can be master or slave
SAA7184; SAA7185B
SAA7184; SAA7185B
l Programmable horizontal and vertical input synchronization phase
l Programmable horizontal sync output phase
l OVL overlay with Look-Up Tables (LUTs) 8 x 3 bytes
l Colour bar generator
l Line 21 closed caption encoder
l Cross-colour reduction
l Macrovision revision_6 Pay-per-View copy protection system as option (SAA7184 only). Remark: This device is protected by U.S.
patent numbers 4631603 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in
the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your
nearest Philips Semiconductors sales office for more information.
l DACs operating at 27 MHz with 10-bit resolution
l Controlled rise and fall times of output syncs and blanking
l Down-mode of DACs
l CVBS and S-Video output simultaneously
l PLCC68 package.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
Title
Datasheet
Download
SAA7184; SAA7185B Digital Video Encoders (DENC2-M6)
03-Jul-96
Preliminary
36
252
Specification
Blockdiagram
Blockdiagram of SAA7184WP
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Tube Dry
Pack
SAA7184WP/01
9352 125 30512
9352 125 30518
9352 188 60518
SOT188 Full production
SOT188 Full production
SOT188 Full production
-
-
Standard Marking * Reel Dry
Pack, SMD, 13"
Standard Marking * Reel Dry
Pack, SMD, 13"
SAA7185BWP/01 SAA7185BWPA-T
Please read information about some discontinued variants of this product.
Find similar products:
SAA7184; SAA7185B links to the similar products page containing an overview of products that are similar in function or related to
the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection
guides and products from the same functional category.
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Royal Philips Electronics
All rights reserved.
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