935243450551 [NXP]

IC COLOR SIGNAL ENCODER, PQFP44, PLASTIC, SOT-307, QFP-44, Color Signal Converter;


型号：	935243450551
厂家：	NXP
描述：	IC COLOR SIGNAL ENCODER, PQFP44, PLASTIC, SOT-307, QFP-44, Color Signal Converter 编码器商用集成电路
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INTEGRATED CIRCUITS

DATA SHEET

SAA7120; SAA7121

Digital Video Encoder (ConDENC)

1997 Jan 06

Preliminary speciﬁcation

File under Integrated Circuits, IC22

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

FEATURES

• Monolithic CMOS 3.3 V (5 V) device

• Digital PAL/NTSC encoder

• System pixel frequency 13.5 MHz

• Accepts MPEG decoded data on 8-bit wide input port;

input data format Cb-Y-Cr (CCIR 656), SAV and EAV

• Macrovision Pay-per-View copy protection system rev.7

and rev.6.1 as option.

• Three DACs for Y, C and CVBS, two times oversampled

with 10 bit resolution

This applies to SAA7120 only. The device is protected

by USA patent numbers 4631603, 4577216 and

4819098 and other intellectual property rights. Use of

the Macrovision anti-copy process in the device is

licensed for non-commercial home use only.

Reverse engineering or disassembly is prohibited.

Please contact your nearest Philips Semiconductors

sales office for more information.

• Real time control of subcarrier

• Cross colour reduction filter

• Closed captioning encoding and WST- and

NABTS-Teletext encoding including sequencer and filter

• Line 23 wide screen signalling encoding

• Fast I²C-bus control port (400 kHz)

• Encoder can be master or slave

• QFP44 package.

• Programmable horizontal and vertical input

synchronization phase

GENERAL DESCRIPTION

• Programmable horizontal sync output phase

• Internal colour bar generator (CBG)

The SAA7120; SAA7121 encodes digital YUV video data

to an NTSC or PAL CVBS or S-Video signal.

• 2 × 2 bytes in lines 20 (NTSC) for copy guard

The circuit accepts CCIR compatible YUV data with

720 active pixels per line in 4 : 2 : 2 multiplexed formats,

for example MPEG decoded data. It includes a sync/clock

generator and on-chip DACs.

management system can be loaded via I²C-bus

• Down-mode of DACs

• Controlled rise/fall times of synchronization and

blanking output signals

QUICK REFERENCE DATA

SYMBOL

V_DDA

PARAMETER

MIN.

3.1

TYP.

3.3

MAX.

3.5

UNIT

analog supply voltage

digital supply voltage

analog supply current

digital supply current

V_DDD

I_DDA

I_DDD

V_i

3.0

−

3.3

−

3.6

−

input signal voltage levels

TTL compatible

V_o(p-p)

analog output signal voltages Y, C, and CVBS without load

(peak-to-peak value)

1.2

1.35

1.45

R_L

load resistance

−

300

±3

Ω

ILE

LF integral linearity error

LF differential linearity error

operating ambient temperature

LSB

°C

DLE

T_amb

−

±1

+70

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SAA7120;

SAA7121

QFP44

plastic quad ﬂat package; 44 leads (lead length 2.35 mm);

body 10 × 10 × 1.75 mm

SOT307-2

BLOCK DIAGRAM

DDA1,

handbook, full pagewidth

RCV1 TTXRQ XTALO LLC

DDA2

DDA4

RESET SDA SCL SA

40 42 41 21

RCV2 XCLK

XTALI

DDA3

43 37 34

25, 28, 36

I C-BUS

SYNC

INTERFACE

CLOCK

SAA7120

SAA7121

I C-bus

control

clock

and timing

9 to 16

CVBS

MP7

MP0

DATA

MANAGER

OUTPUT

INTERFACE

ENCODER

CbCr

I C-bus

control

32, 33

SSA1

I C-bus

control

TTX

SSA2

1, 20, 22,

23, 26, 29

5, 18, 38

6, 17, 39

RTCI

MBH787

res.

SP AP

SSD1,

DDD1,

SSD2

DDD2

DDD3

SSD3

Fig.1 Block diagram.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

PINNING

SYMBOL

I/O

DESCRIPTION

res.

−

reserved

test pin; connected to digital ground for normal operation

LLC

line-locked clock; this is the 27 MHz master clock for the encoder

digital ground 1

V_SSD1

V_DDD1

RCV1

RCV2

digital supply voltage 1

I/O

raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal

raster control 2 for video port; this pin provides an HS pulse of programmable length or

receives an HS pulse

MP7

MP6

MP5

MP4

MP3

MP2

MP1

MP0

V_DDD2

V_SSD2

RTCI

MPEG port; it is an input for “CCIR 656” style multiplexed Cb Y, Cr data

digital supply voltage 2

digital ground 2

Real Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B,

RTCI should be connected to pin RTCO of the decoder to improve the signal quality

res.

−

reserved

the I²C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH

res.

−

reserved

res.

reserved

analog output of the chrominance signal

analog supply voltage 1 for the C DAC

reserved

V_DDA1

res.

−

analog output of VBS signal

V_DDA2

res.

analog supply voltage 2 for the Y DAC

reserved

−

CVBS

V_DDA3

V_SSA1

V_SSA2

XTALO

XTALI

analog output of the CVBS signal

analog supply voltage 3 for the CVBS DAC

analog ground 1 for the DACs

analog ground 2 for the oscillator and reference voltage

crystal oscillator output (to crystal)

crystal oscillator input (from crystal); if the oscillator is not used, this pin should be

connected to ground

V_DDA4

XCLK

analog supply voltage 4 for the oscillator and reference voltage

clock output of the crystal oscillator

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

SYMBOL

I/O

DESCRIPTION

V_SSD3

digital ground 3

V_DDD3

RESET

digital supply voltage 3

reset input, active LOW; after reset is applied, all digital I/Os are in input mode;

the I²C-bus receiver waits for the START condition

SCL

I/O

I²C-bus serial clock input

SDA

I²C-bus serial data input/output

teletext request output, indicating when bit stream is valid

teletext bit stream input

TTXRQ

TTX

handbook, full pagewidth

res.

SSA2

SSA1

DDA3

CVBS

res.

LLC

SSD1

SAA7120

SAA7121

DDD1

RCV1

DDA2

res.

RCV2

MP7

DDA1

MP6 10

MP5 11

res.

MBH790

Fig.2 Pin configuration.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

be decoded optionally when the device is to operate in

slave mode.

FUNCTIONAL DESCRIPTION

The digital video encoder (ConDENC) encodes digital

luminance and colour difference signals simultaneously

into analog CVBS and S-Video signals. NTSC-M,

PAL B/G, and sub-standards are supported.

It is also possible to connect a Philips Digital Video

Decoder (SAA7111 or SAA7151B) to the ConDENC.

Via pin RTCI, connected to RTCO of a decoder,

information concerning the actual subcarrier, PAL-ID and

(if used in conjunction with the SAA7111) the subcarrier

phase can be inserted.

Both interlaced and non-interlaced operation is possible

for all standards.

The basic encoder function consists of subcarrier

generation, colour modulation and the insertion of

synchronization signals. Luminance and chrominance

signals are filtered in accordance with the standard

requirements of “RS-170-A” and “CCIR 624”.

The ConDENC synthesizes all necessary internal signals,

colour subcarrier frequency and synchronization signals.

Wide screen signalling data can be loaded via the I²C-bus.

It is inserted into line 23 for 50 Hz field rate standards.

The IC contains closed caption and extended data

services encoding (line 21), and supports anti-taping

signal generation in accordance with Macrovision.

For ease of analog post-filtering the signals are

oversampled twice with respect to the pixel clock prior to

digital-to-analog conversion.

Possibilities are provided for setting video parameters:

Black and blanking level control

Colour subcarrier frequency

The filter characteristics are shown in Figs 3 and 4.

The DACs for Y, C, and CVBS have 10-bit resolution.

The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656”

(D1 format) compatible, but the SAV and EAV codes can

Variable burst amplitude.

MGD672

handbook, full pagewidth

(dB)

(4)

(2)

(3)

−6

−12

−18

(1)

−24

−30

−36

−42

−48

−54

f (MHz)

(1) CCRS1 = 0; CCRS0 = 1.

(2) CCRS1 = 1; CCRS0 = 0.

(3) CCRS1 = 0; CCRS0 = 0.

(4) CCRS1 = 1; CCRS0 = 1.

Fig.3 Luminance transfer characteristic 1.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

During reset (RESET = LOW) and after reset is released,

all digital I/O stages are set to input mode. A reset forces

the I²C-bus interface to abort a running bus transfer and

sets register 3A to 03H, register 61 to 06H,

MBE736

handbook, halfpage

(dB)

(1)

registers 6BH and 6EH to 00H and bit TTX60 to 0.

All other control registers are not influenced by a reset.

−1

−2

−3

−4

−5

Encoder

VIDEO PATH

The encoder generates out of Y, U and V baseband

signals luminance and colour subcarrier output signals,

suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (the latter

programmable in a certain range to enable different black

level set-ups). A fixed synchronization level in accordance

with standard composite synchronization schemes is

inserted. The inserted blanking level is programmable to

allow for manipulations with Macrovision anti-taping.

Additional insertion of AGC super-white pulses,

programmable in height, is supported.

f (MHz)

(1) CCRS1 = 0; CCRS0 = 0.

Fig.4 Luminance transfer characteristic 2.

MBE737

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

(1)

(2)

−42

−48

−54

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig.5 Chrominance transfer characteristic 1.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

signal TTXRQ a single teletext bit has to be provided after

a programmable delay at input pin.

MBE735

handbook, halfpage

Phase variant interpolation is achieved on this bitstream in

the internal teletext encoder, providing sufficient small

phase jitter on the output text lines.

(dB)

(1)

TTXRQ provides a fully programmable request signal to

the teletext source, indicating the insertion period of

bitstream at lines selectable independently for both fields.

The internal insertion window for text is set to 360

(PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext

bits including clock run-in bits. For protocol and timing

see Fig.7.

(2)

−2

−4

−6

CLOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification

of closed caption or extended data service, delivered by

the control interface, can be encoded (Line 21).

Two dedicated pairs of bytes (two bytes per field), each

pair preceded by run-in clocks and framing code, are

possible.

0.4

0.8

1.2

1.6

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig.6 Chrominance transfer characteristic 2.

The actual line number where data is to be encoded in, can

be modified in a certain range.

Data clock frequency is in accordance with definition for

NTSC-M standard 32 times horizontal line frequency.

In order to enable easy analog post-filtering, luminance is

interpolated from 13.5 MHz data rate to 27 MHz data rate,

providing luminance in 10-bit resolution. This filter is also

used to define smoothed transients for synchronization

pulses and blanking period. For transfer characteristic of

the luminance interpolation filter see Figs 3 and 4.

Data LOW at the output of the DACs corresponds to 0 IRE,

data HIGH at the output of the DACs corresponds to

approximately 50 IRE.

It is also possible to encode Closed Caption Data for 50 Hz

field frequencies at 32 times horizontal line frequency.

Chrominance is modified in gain (programmable

separately for U and V), standard dependent burst is

inserted, before baseband colour signals are interpolated

from 6.75 MHz data rate to 27 MHz data rate. One of the

interpolation stages can be bypassed, thus providing a

higher colour bandwidth, which can be made use of for

Y and C output. For transfer characteristics of the

chrominance interpolation filter see Figs 5 and 6.

ANTI-TAPING (SAA7120 ONLY)

For more information contact your nearest Philips

Semiconductors sales office.

Data manager

In the data manager, real time arbitration on the data

stream to be encoded is performed.

The amplitude, beginning and ending of inserted burst is

programmable in a certain range, suitable for standard

signals and for special effects. Behind the succeeding

quadrature modulator, colour in 10-bit resolution is

provided on subcarrier.

A pre-defined colour look-up table located in this block can

be read out in a pre-defined sequence (8 steps per active

video line), achieving a colour bar test pattern generator

without the need for an external data source. The colour

bar function is under software control only.

The numeric ratio between Y and C outputs is in

accordance with set standards.

Output interface/DACs

TELETEXT INSERTION AND ENCODING

In the output interface encoded Y and C signals are

converted from digital to analog in 10-bit resolution.

Pin TTX receives a WST- or NABTS-Teletext bitstream

sampled at the LLC clock. At each rising edge of output

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Y and C signals are also combined to a 10-bit CVBS

signal.

On the RCV2 port, the device can provide a horizontal

synchronization pulse with programmable start and stop

phase; this pulse can be inhibited in the vertical blanking

period to build up, for example, a composite blanking

signal.

The CVBS output occurs with the same processing delay

as the Y and C outputs. Absolute amplitude at the input of

the DAC for CVBS is reduced by ¹⁵

⁄₁₆with respect to

Y and C DACs to make maximum use of conversion

ranges.

The polarity of both RCV1 and RCV2 is selectable by

software control.

Outputs of the DACs can be set together in two groups via

software control to minimum output voltage for either

purpose.

The length of a field and the start and end of its active part

can be programmed. The active part of a field always

starts at the beginning of a line.

Synchronization

Teletext timing

Synchronization of the ConDENC is able to operate in two

modes; slave mode and master mode.

The teletext timing is shown in Fig.7. t_FDis the time needed

to interpolate input data TTX and inserting it into the

CVBS and Y output signal, such that it appears at

In the slave mode, the circuit accepts synchronization

pulses at the bidirectional RCV1 port. The timing and

trigger behaviour related to RCV1 can be influenced by

programming the polarity and the on-chip delay of RCV1.

Active slope of RCV1 defines the vertical phase and

optionally the odd/even and colour frame phase to be

initialized, it can be also used to set the horizontal phase.

t_TTX= 10.2 µs (PAL) or t_TTX= 10.5 µs (NTSC) after the

leading edge of the horizontal synchronization pulse.

Time t_PDis the pipeline delay time introduced by the

source that is gated by TTXRQ in order to deliver TTX

data. This delay is programmable by register TTXHD.

For every active HIGH-state at output pin TTXRQ, a new

teletext bit must be provided by the source.

If the horizontal phase is not to be influenced by RCV1, a

horizontal synchronization pulse needs to be supplied at

the pin RCV2. Timing and trigger behaviour can also be

influenced by RCV2.

Since the beginning of the pulses representing the TTXRQ

signal and the delay between the rising edge of TTXRQ

and valid teletext input data are fully programmable

(TTXHS and TTXHD), the TTX data is always inserted at

the correct position after the leading edge of outgoing

horizontal synchronization pulse.

If there are missing pulses at RCV1 and/or RCV2, the time

base of ConDENC runs free, thus an arbitrary number of

synchronization slopes may be absent, but no additional

pulses (with the incorrect phase) must occur.

Time t_TTXWinis the internally used insertion window for

TTX data; it has a constant length that allows insertion of

360 teletext bits at a text data rate of 6.9375 Mbits/s

(PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s

(World Standard TTX) or 288 teletext bits at a text data

rate of 5.7272 Mbits/s (NABTS). The insertion window is

not opened if the control bit TTXEN is logic 0.

If the vertical and horizontal phase is derived from RCV1,

RCV2 can be used for horizontal or composite blanking

input or output.

Alternatively, the device can be triggered by auxiliary

codes in a “CCIR 656” data stream at the MP port.

In the master mode, the time base of the circuit

continuously runs free. On the RCV1 port, the device can

output:

Using appropriate programming, all suitable lines of the

odd field (TTXOVS and TTXOVE) plus all suitable lines of

the even field (TTXEVS and TTXEVE) can be used for

teletext insertion.

• A Vertical Synchronisation signal (VS) with 3 or 2.5 lines

duration, or

• An ODD/EVEN signal which is LOW in odd fields, or

• A field sequence signal (FSEQ) which is HIGH in the first

of 4 or 8 fields respectively.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

handbook, full pagewidth

CVBS/Y

TTXWin

TTX

textbit #:

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TTX

TTXRQ

MBH788

Fig.7 Teletext timing.

Analog output voltages

Table 1 Digital output signals conversion range

CONVERSION RANGE (peak-to-peak) (digits)

The analog output voltages are dependent on the

open-loop voltage of the operational amplifiers for

full-scale conversion (typical value 1.35 V), the internal

series resistor (typical value 2 Ω), the external series

resistor and the external load impedance.

CVBS, SYNC

TIP-TO-PEAK CARRIER

Y (VBS) SYNC

TIP-TO-WHITE

1016

881

The digital output signals in front of the DACs under

nominal conditions occupy different conversion ranges, as

indicated in Table 1 for a ¹⁰⁰

⁄₁₀₀colour bar signal.

Table 2 “CCIR 601” signal component levels

SIGNALS

COLOUR

Values for the external series resistors result in a 75 Ω

load.

128

146

White

Yellow

Cyan

235

210

170

145

106

Input levels and formats

166

The ConDENC expects digital Y, Cb, Cr data with levels

(digital codes) in accordance with “CCIR 601” (see

Tables 2 and 3).

Green

Magenta

Red

202

222

240

110

128

For C and CVBS outputs, deviating amplitudes of the

colour difference signals can be compensated by

independent gain control setting, while gain for luminance

is set to predefined values, distinguishable for 7.5 IRE

set-up or without set-up.

Blue

240

128

Black

Reference levels are measured with a colour bar,

100% white, 100% amplitude and 100% saturation.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Tables 5 and 4 summarize the format of the I²C-bus

addressing. For more information on how to use the

I²C-bus see “The I²C-bus and how to use it”, order

no. 9398 393 40011. Tables 7 to 42 contain the

programming information for the subaddresses. Table 6

summarises this information.

I²C-bus interface

The I²C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s

guaranteed transfer rate. It uses 8-bit subaddressing with

an auto-increment function. All registers are write only,

except one readable status byte.

Two I²C-bus slave addresses are present:

88H: LOW at pin SA

8CH: HIGH at pin SA.

Table 3 8-bit multiplexed format (similar to “CCIR 601”)

BITS

Sample

Cb₀

Y₀

Cr₀

Y₁

Cb₂

Y₂

Cr₂

Y₃

Luminance pixel number

Colour pixel number

Table 4 I²C-bus address format; see Table 5

SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK

--------

DATA n ACK

Table 5 Explanation of Table 4

PART

DESCRIPTION

START condition

Slave address

ACK

Subaddress⁽²⁾

1 0 0 0 1 0 0 x or 1 0 0 0 1 1 0 x ⁽¹⁾

acknowledge, generated by the slave

subaddress byte

DATA

data byte

--------

continued data bytes and ACKs

STOP condition

Notes

1. x is the read/write control bit; write:

x = logic 0;

read: x = logic 1, no subaddressing with read.

2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Slave Receiver

Table 7 Subaddress 26 and 27

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

WSS

−

wide screen signalling bits:

13 to 11 = reserved

10 to 8 = subtitles

7 to 4 = enhanced services

3 to 0 = aspect ratio

WSSON

wide screen signalling output is disabled

wide screen signalling output is enabled

Table 8 Subaddress 28 and 29

LOGIC

DATA BYTE

DESCRIPTION

REMARKS

PAL : BS = 33 (21H)

LEVEL

−

starting point of burst in clock cycles

ending point of burst in clock cycles

NTSC : BS = 25 (19H)

PAL : BS = 29 (1DH)

NTSC : BS = 29 (1DH)

−

DECCOL

DECFIS

disable colour detection bit of RTCI input

enable colour detection bit of RTCI input

ﬁeld sequence as FISE in subaddress 61

ﬁeld sequence as FISE bit in RTCI input

bit RTCE must be set to 1 (see Fig.10)

Table 9 Subaddress 2A to 2D

DATA BYTE

DESCRIPTION

REMARKS

CGO0

CGO1

CGE0

CGE1

ﬁrst byte of Copy guard data, odd ﬁeld

LSBs of the respective bytes are encoded

immediately after run-in and framing code, the

MSBs of the respective bytes have to carry the

parity bit, in accordance with the deﬁnition of

Line 20 encoding format.

second byte of Copy guard data, odd ﬁeld

ﬁrst byte of Copy guard data, even ﬁeld

second byte of Copy guard data, even ﬁeld

Table 10 Subaddress 2E

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

copy guard encoding off

enables encoding in ﬁeld 1 (odd)

enables encoding in ﬁeld 2 (even)

enables encoding in both ﬁelds

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 11 Subaddress 3A

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

UV2C

Y2C

Cb, Cr data are two’s complement

Cb, Cr data are straight binary; default after reset

Y data is two’s complement

Y data is straight binary; default after reset

SYMP

CBENB

horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset

horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port

data from input ports is encoded; default after reset

colour bar with ﬁxed colours is encoded

Table 12 Subaddress 5A

DATA BYTE

DESCRIPTION

VALUE

3FH

RESULT

CHPS

phase of encoded colour subcarrier

(including burst) relative to horizontal sync;

can be adjusted in steps of

PAL-B/G and data from input ports

PAL-B/G and data from look-up table

NTSC-M and data from input ports

NTSC-M and data from look-up table

69H

67H

360/256 degrees

89H

Remark: in subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.

Table 13 Subaddress 5B and 5D

DATA BYTE

DESCRIPTION

variable gain for

Cb signal; input

representation

accordance with

“CCIR 601”

CONDITIONS

white-to-black = 92.5 IRE

GAINU = 0

REMARKS

GAINU

GAINU = −2.17 × nominal to +2.16 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

GAINU = −2.05 × nominal to +2.04 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

GAINU = 118 (76H)

white-to-black = 100 IRE

GAINU = 0

GAINU = 125 (7DH)

Table 14 Subaddress 5C and 5E

DATA BYTE

DESCRIPTION

variable gain for

Cr signal; input

representation

accordance with

“CCIR 601”

CONDITIONS

white-to-black = 92.5 IRE

GAINV = 0

REMARKS

GAINV

GAINV = −1.55 × nominal to +1.55 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

GAINV = −1.46 × nominal to +1.46 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

GAINV = 165 (A5H)

white-to-black = 100 IRE

GAINV = 0

GAINV = 175 (AFH)

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 15 Subaddress 5D

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLCKL

variable black level; input white-to-sync = 140 IRE⁽¹⁾recommended value: BLCKL = 42 (2AH)

representation

BLCKL = 0

output black level = 34 IRE

output black level = 54 IRE

accordance with

“CCIR 601”

BLCKL = 63 (3FH)

white-to-sync = 143 IRE⁽²⁾recommended value: BLCKL = 35 (23H)

BLCKL = 0

output black level = 32 IRE

BLCKL = 63 (3FH)

output black level = 52 IRE

DECOE

real time control

logic 0

logic 1

disable odd/even ﬁeld control bit from RTCI

enable odd/even ﬁeld control bit from RTCI

(see Fig.10)

Notes

1. Output black level/IRE = BLCKL × 2/6.29 + 34.0

2. Output black level/IRE = BLCKL × 2/6.18 + 31.7

Table 16 Subaddress 5E

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BLNNL

variable blanking level

white-to-sync = 140 IRE⁽¹⁾recommended value: BLNNL = 46 (2EH)

BLNNL = 0

output blanking level = 25 IRE

BLNNL = 63 (3FH)

output blanking level = 45 IRE

white-to-sync = 143 IRE⁽²⁾recommended value: BLNNL = 53 (35H)

BLNNL = 0

output blanking level = 26 IRE

BLNNL = 63 (3FH)

output blanking level = 46 IRE

DECPH

real time control

logic 0

logic 1

disable subcarrier phase reset bit from RTCI

enable subcarrier phase reset bit from RTCI

(see Fig.10)

Notes

1. Output black level/IRE = BLNNL × 2/6.29 + 25.4

2. Output black level/IRE = BLNNL × 2/6.18 + 25.9

Table 17 Subaddress 5F

DATA BYTE

DESCRIPTION

BLNVB

CCRS

variable blanking level during vertical blanking interval is typically identical to value of BLNNL

select cross colour reduction ﬁlter in luminance; see Table 18

Table 18 Logic levels and function of CCRS

CCRS1

CCRS0

DESCRIPTION

no cross colour reduction; for overall transfer characteristic of luminance see Fig.3

cross colour reduction #1 active; for overall transfer characteristic see Fig.3

cross colour reduction #2 active; for overall transfer characteristic see Fig.3

cross colour reduction #3 active; for overall transfer characteristic see Fig.3

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 19 Subaddress 61

LOGIC

DATA BYTE

DESCRIPTION

864 total pixel clocks per line; default after reset

LEVEL

FISE

PAL

858 total pixel clocks per line

NTSC encoding (non-alternating V component)

PAL encoding (alternating V component); default after reset

SCBW

enlarged bandwidth for chrominance encoding (for overall transfer characteristic of

chrominance in baseband representation see Figs 3 and 4)

standard bandwidth for chrominance encoding (for overall transfer characteristic of

chrominance in baseband representation see Figs 3 and 4); default after reset

YGS

luminance gain for white − black 100 IRE; default after reset

luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black

PAL switch phase is nominal; default after reset

INPI

PAL switch phase is inverted compared to nominal

DOWN

DACs for CVBS, Y and C in normal operational mode; default after reset

DACs for CVBS, Y and C forced to lowest output voltage

Table 20 Subaddress 62H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

RTCE

no real time control of generated subcarrier frequency

real time control of generated subcarrier frequency through SAA7151B or SAA7111

(timing see Fig.10)

Table 21 Subaddress 62H

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BSTA

amplitude of colour burst; input

representation in accordance

with “CCIR 601”

white-to-black = 92.5 IRE;

burst = 40 IRE; NTSC encoding BSTA = 63 (3FH)

recommended value:

BSTA = 0 to 2.02 × nominal

white-to-black = 92.5 IRE;

burst = 40 IRE; PAL encoding

recommended value:

BSTA = 45 (2DH)

BSTA = 0 to 2.82 × nominal

white-to-black = 100 IRE;

recommended value:

burst = 43 IRE; NTSC encoding BSTA = 67 (43H)

BSTA = 0 to 1.90 × nominal

white-to-black = 100 IRE;

burst = 43 IRE; PAL encoding

recommended value:

BSTA = 47 (2FH)

BSTA = 0 to 3.02 × nominal

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 22 Subaddress 63 to 66 (four bytes to program subcarrier frequency)

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

FSC0 to FSC3 f_fsc= subcarrier frequency (in

multiples of line frequency);

FSC3 = most signiﬁcant byte

FSC0 = least signiﬁcant byte

FSC = ^fsc× 2 ³²

-------

f_llc

f_llc= clock frequency (in multiples

of line frequency)

rounded up; see note 1

Note

1. Examples:

a) NTSC-M: f_fsc= 227.5, f_llc= 1716 → FSC = 569408543 (21F07C1FH).

b) PAL-B/G: f_fsc= 283.7516, f_llc= 1728 → FSC = 705268427 (2A098ACBH).

Table 23 Subaddress 67 to 6A

DATA BYTE

DESCRIPTION

REMARKS

L21O0

L21O1

L21E0

L21E1

ﬁrst byte of captioning data, odd ﬁeld

second byte of captioning data, odd ﬁeld

ﬁrst byte of extended data, even ﬁeld

second byte of extended data, even ﬁeld

LSBs of the respective bytes are encoded

immediately after run-in and framing code, the

MSBs of the respective bytes have to carry the

parity bit, in accordance with the deﬁnition of

Line 21 encoding format.

Table 24 Subaddress 6B

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

PRCV2

polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;

default after reset

polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively

pin RCV2 is switched to input; default after reset

ORCV2

CBLF

pin RCV2 is switched to output

if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is

deﬁned by RCV2S and RCV2E, also during vertical blanking Interval); default after reset

if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal

synchronization only (if TRCV2 = 1); default after reset

if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, for example a

reference pulse that is deﬁned by RCV2S and RCV2E, excluding Vertical Blanking Interval,

which is deﬁned by FAL and LAL

if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal

synchronization (if TRCV2 = 1) and as an internal blanking signal

PRCV1

ORCV1

TRCV2

polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset

polarity of RCV1 as output is active LOW, falling edge is taken when input

pin RCV1 is switched to input; default after reset

pin RCV1 is switched to output

horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded

frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset

horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)

deﬁnes signal type on pin RCV1; see Table 25

SRCV1

−

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 25 Logic levels and function of SRCV1

DATA BYTE

AS OUTPUT

AS INPUT

FUNCTION

SRCV11

SRCV10

vertical sync each ﬁeld; default after reset

frame sync (odd/even)

FSEQ

ﬁeld sequence, vertical sync every fourth ﬁeld

(PAL = 0) or eighth ﬁeld (PAL = 1)

not applicable not applicable

−

Table 26 Subaddress 6C and 6D

DATA BYTE

DESCRIPTION

HTRIG

sets the horizontal trigger phase related to signal on RCV1 or RCV2 input

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed

increasing HTRIG decreases delays of all internally generated timing signals

reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used

for triggering at HTRIG = 398H [398H]

Table 27 Subaddress 6D

DATA BYTE

DESCRIPTION

VTRIG

sets the vertical trigger phase related to signal on RCV1 input

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines

variation range of VTRIG = 0 to 31 (1FH)

Table 28 Subaddress 6E

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

SBLBN

−

vertical blanking is deﬁned by programming of FAL and LAL; default after reset

vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)

selects the phase reset mode of the colour subcarrier generator; see Table 29

ﬁeld length control; see Table 30

PHRES

FLC

Table 29 Logic levels and function of PHRES

DATA BYTE

DESCRIPTION

PHRES1

PHRES0

no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset

reset every two lines

reset every eight ﬁelds

reset every four ﬁelds

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 30 Logic levels and function of FLC

DATA BYTE

DESCRIPTION

FLC1

FLC0

interlaced 312.5 lines/ﬁeld at 50 Hz, 262.5 lines/ﬁeld at 60 Hz; default after reset

non-interlaced 312 lines/ﬁeld at 50 Hz, 262 lines/ﬁeld at 60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at 60 Hz

Table 31 Subaddress 6F

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

CCEN

−

enables individual Line 21 encoding; see Table 32

disables teletext insertion

TTXEN

enables teletext insertion

SCCLN

selects the actual line, where closed caption or extended data are encoded

line = (SCCLN + 4) for M-systems

line = (SCCLN + 1) for other systems

Table 32 Logic levels and function of CCEN

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

Line 21 encoding off

enables encoding in ﬁeld 1 (odd)

enables encoding in ﬁeld 2 (even)

enables encoding in both ﬁelds

Table 33 Subaddress 70 to 72

DATA BYTE

DESCRIPTION

RCV2S

start of output signal on pin RCV2

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed

ﬁrst active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at

RCV2S = 11AH [0FDH]

RCV2E

end of output signal on pin RCV2

values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed

last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at

RCV2E = 694H [687H]

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 34 Subaddress 73 and 74

DATA BYTE

DESCRIPTION

TTXHS

TTXHD

start of signal on pin TTXRQ see Fig.7

indicates the delay in clock cycles between rising edge of TTXRQ output and valid data on pin TTX

minimum value has to be TTXHD = 2

Table 35 Subaddress 75

DATA BYTE

DESCRIPTION

VS_S

Vertical Sync. shift between RCV1 and RCV2 (switched to output) in master mode it is possible to shift

H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00)

standard value: VS_S = 3

Table 36 Subaddress 76, 77 and 7C

DATA BYTE

DESCRIPTION

TTXOVS

ﬁrst line of occurrence of signal on pin TTXRQ in odd ﬁeld

line = (TTXOVS + 4) for M-systems

line = (TTXOVS + 1) for other systems

TTXOVE

last line of occurrence of signal on pin TTXRQ in odd ﬁeld

line = (TTXOVE + 3) for M-systems

line = TTXOVE for other systems

Table 37 Subaddress 78, 79 and 7C

DATA BYTE

DESCRIPTION

TTXEVS

ﬁrst line of occurrence of signal on pin TTXRQ in even ﬁeld

line = (TTXEVS + 4) for M-systems

line = (TTXEVS + 1) for other systems

TTXEVE

last line of occurrence of signal on pin TTXRQ in even ﬁeld

line = (TTXEVE + 3) for M-systems

line = TTXEVE for other systems

Table 38 Subaddress 7C

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

TTX60

enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset

enables World Standard Teletext 60 Hz (FISE = 1)

Table 39 Subaddress 7A to 7C

DATA BYTE

DESCRIPTION

FAL

ﬁrst active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0

coincides with the ﬁrst ﬁeld synchronization pulse

LAL

last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides

with the ﬁrst ﬁeld synchronization pulse

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

Table 40 Subaddress 7E and 7F

DATA BYTE

DESCRIPTION

LINE

individual lines in both ﬁelds (PAL counting) can be disabled for insertion of teletext by the respective

bits, disabled line = LINExx (50 Hz ﬁeld rate)

this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE

Slave Transmitter

Table 41 Slave transmitter (slave address 89H or 8DH)

DATA BYTE

D4 D3

SUBADDRESS

FUNCTION

Status byte

−

VER2

VER1

VER0 CCRDO CCRDE

FSEQ

O_E

Table 42 No subaddress

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

VER

−

Version identiﬁcation of the device. It will be changed with all versions of the device that

have different programming models. Current version is 000 binary.

CCRDO

Closed caption bytes of the odd ﬁeld have been encoded.

The bit is reset after information has been written to the subaddresses 67 and 68. It is set

immediately after the data has been encoded.

CCRDE

Closed caption bytes of the even ﬁeld have been encoded.

The bit is reset after information has been written to the subaddresses 69 and 6A. It is set

immediately after the data has been encoded.

FSEQ

O_E

During ﬁrst ﬁeld of a sequence (repetition rate: NTSC = 4 ﬁelds, PAL = 8 ﬁelds).

Not ﬁrst ﬁeld of a sequence.

During even ﬁeld.

During odd ﬁeld.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

CHARACTERISTICS

V_DDD= 3.0 to 3.6 V; T_amb= 0 to +70 °C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS

MIN.

MAX.

UNIT

Supply

V_DDA

V_DDD

I_DDA

analog supply voltage

3.1

3.5

digital supply voltage

analog supply current

digital supply current

3.0

−

3.6

note 1

I_DDD

note 1

−

Inputs

V_IL

LOW level input voltage

(except SDA, SCL, AP, SP and XTALI)

−0.5

+0.8

V_IH

HIGH level input voltage

2.0

V_DDD+ 0.3

(except, SDA, SCL, AP, SP and XTALI)

I_LI

C_i

input leakage current

input capacitance

−

µA

clocks

data

I/Os at high impedance −

Outputs

V_OL

LOW level output voltage

(except SDA and XTALO)

I_OL= 4 mA

I_OH= 4 mA

−

0.4

V_OH

HIGH level output voltage

(except, SDA, and XTALO)

_DDD− 4

−

I²C-bus; SDA and SCL

V_IL

V_IH

I_i

LOW level input voltage

−0.5

2.3

−10

−

V_DDD+ 0.3

HIGH level input voltage

input current

V_DDD+ 0.3

V_i= LOW or HIGH

I_OL= 3 mA

+10

0.4

−

µA

V_OL

I_o

LOW level output voltage (SDA)

output current

during acknowledge

Clock timing (LLC)

T_LLC

cycle time

note 2

note 3

note 2

−

t_r

t_f

duty factor t_HIGH/t_LLC

rise time

fall time

−

Input timing

t_SU;DATinput data set-up time (any pin except

−

SCL, SDA, RESET, AP and SP)

t_HD;DAT

input data hold time (any pin except

SCL, SDA, RESET, AP and SP)

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Crystal oscillator

f_n

nominal frequency (usually 27 MHz)

3^rdharmonic

note 4

−

MHz

∆f/f_n

permissible deviation of nominal frequency

−50 × 10⁻⁶+50 × 10⁻⁶

CRYSTAL SPECIFICATION

T_amb

C_L

operating ambient temperature

−

°C

Ω

load capacitance

R_S

C₁

series resistance

motional capacitance (typical)

parallel capacitance (typical)

1.5 − 20% 1.5 + 20% fF

3.5 − 20% 3.5 + 20% pF

C₀

Data and reference signal output timing

C_L

t_h

output load capacitance

output hold time

7.5

−

t_d

output delay time

−

C, Y and CVBS outputs

V_o(p-p)

R_int

output signal voltage (peak-to-peak value)

note 5

1.20

1.45

internal serial resistance

Ω

R_L

output load resistance

−

300

−

Ω

B_−3dB

ILE

output signal bandwidth of DACs

LF integral linearity error of DACs

LF differential linearity error of DACs

MHz

LSB

±3

±1

DLE

−

Notes

1. At maximum supply voltage with highly active input signals.

2. The data is for both input and output direction.

3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.

4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of

subcarrier frequency and line/field frequency.

5. For full digital range, without load, V_DDA= 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output

voltage (digital zero at DAC) is 0.2 V.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

LLC

handbook, full pagewidth

HIGH

2.6 V

1.5 V

0.6 V

LLC clock output

HD; DAT

LLC

HIGH

2.4 V

1.5 V

0.8 V

LLC clock input

HD; DAT

SU; DAT

2.0 V

valid

input data

valid

not valid

0.8 V

HD; DAT

2.4 V

valid

output data

valid

not valid

0.6 V

MBE742

Fig.8 Clock data timing.

handbook, full pagewidth

LLC

MP(n)

RCV2

Cb(0)

Y(0)

Cr(0)

Y(1)

Cb(2)

MGB699

The data demultiplexing phase is coupled to the internal horizontal phase.

The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).

Fig.9 Functional timing.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

H/L transition

count start

handbook, full pagewidth

5 bits

4 bits

reserved

(7)

reserved

(4)

(7)

(3)

(6)

LOW

HPLL

increment

(2)

(5)

(1)

FSCPLL increment

128

RTCI

time slot:

67 69 72 74

valid

sample sample

invalid

8/LLC

not used in SAA7120/21

MBH789

(1) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before

sequence bit.

(3) Reset bit: only from SAA7111 decoder.

(4) FISE bit: 0 = 50 Hz, 1 = 60 Hz.

(2) Sequence bit

(5) Odd/even bit: odd/even from external.

PAL: 0 = (R−Y) line normal, 1 = (R−Y) line inverted

NTSC: 0 = no change.

(6) Colour detection: 0 = no colour detected, 1 = colour detected.

(7) Reserved bits: 232 with 50 Hz systems, 229 with 60 Hz systems.

Fig.10 RTCI timing.

6. If the colour detection bit is enabled (RTCE = 1;

DECCOL = 1) and no colour was detected (colour

detection bit = 0), the subcarrier frequency is

generated by the ConDENC. In the other case (colour

detection bit = 1) the subcarrier frequency is evaluated

out of FSCPLL increment.

Explanation of RTCI data bits

1. The ConDENC generates the subcarrier frequency out

of the FSCPLL increment if enabled (see item 6.).

2. The PAL bit indicates the line with inverted R - Y

component of colour difference signal.

3. If the reset bit is enabled

If the colour detection bit is disabled (RTCE = 1;

DECCOL = 0), the subcarrier frequency is evaluated

out of FSCPLL increment, independent of the colour

detection bit of RTCI input.

(RTCE = 1; DECPH = 1; PHRES = 00), the phase of

the subcarrier is reset in each line whenever the reset

bit of RTCI input is set to 1.

4. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the

ConDENC takes this bit instead of the FISE bit in

subaddress 61H.

5. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),

the ConDENC ignores its internally generated

odd/even flag and takes the odd/even bit from RTCI

input.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

APPLICATION INFORMATION

BM7H86

h a n d b o o k , f u l l p a g e w i d t h

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

(A )

w M

pin 1 index

detail X

w M

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

10^o

0^o

0.25 1.85

0.05 1.65

0.40 0.25 10.1 10.1

0.20 0.14 9.9 9.9

12.9 12.9

12.3 12.3

0.95 0.85

0.55 0.75

1.2

0.8

1.2

0.8

2.10

0.25

0.8

1.3

0.15 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

92-11-17

95-02-04

SOT307-2

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

If wave soldering cannot be avoided, the following

conditions must be observed:

SOLDERING

Introduction

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering the following packages: QFP52 (SOT379-1),

QFP100 (SOT317-1), QFP100 (SOT317-2),

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011).

QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Reﬂow soldering

Reflow soldering techniques are suitable for all QFP

packages.

The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or

vapour phase heating is used and the large packages are

not absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our “Quality

Reference Handbook” (order code 9397 750 00192).

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1997 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (ConDENC)

SAA7120; SAA7121

NOTES

1997 Jan 06

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Belgium: see The Netherlands

Brazil: see South America

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Colombia: see South America

Czech Republic: see Austria

Slovakia: see Austria

Slovenia: see Italy

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 1949

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580/xxx

South America: Rua do Rocio 220, 5th floor, Suite 51,

04552-903 São Paulo, SÃO PAULO - SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 829 1849

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 481 7730

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874

Indonesia: see Singapore

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

Middle East: see Italy

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Internet: http://www.semiconductors.philips.com

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA53

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

657021/1200/01/pp32

Date of release: 1997 Jan 06

Document order number: 9397 750 01378

Go to Philips Semiconductors' home page

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SAA7120; SAA7121; Digital Video Encoder (ConDENC)

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Description

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Automotive

Consumer Multimedia

Systems

The SAA7120; SAA7121 encodes digital YUV video data to an NTSC or PAL CVBS or S-Video signal.

Communications

PC/PC-peripherals

The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 :2 :2multiplexed formats, for example MPEG decoded

data. It includes a sync/clock generator and on-chip DACs.

Cross reference

Models

Packages

Features

Application notes

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