935243950557 [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQFP100, PLASTIC, SOT-407, LQFP-100, Consumer IC:Other;
| 型号： | 935243950557 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP100, PLASTIC, SOT-407, LQFP-100, Consumer IC:Other 商用集成电路 |
| 文件： | 总12页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7112
Decoder with High-Performance
Scaler (HPS) for Image Port
(PELICAN)
1996 Jun 20
Preliminary specification
File under Integrated Circuits, IC22
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
FEATURES
The PELICAN SAA7112 is a video capture device for
application at the image port of a VGA controller, with
following feature highlights:
Video Decoder
• Six analog inputs, internal analog source selectors,
(e.g. 6 × CVBS or(2 × YC and 2 × CVBS) or
(1 × YC and 4 × CVBS)
• Vertical scaling with linear phase interpolation (6-bit
phase accuracy) and accumulating filter for anti-aliasing
• Horizontal phase correct up- and down-scaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit
phase accuracy
• Two analog preprocessing channels, including built in
analog anti-alias filters
• Fully programmable static gain for the main channels or
Automatic Gain Control (AGC) for the selected
CVBS/Y channel
• Two independent programming sets for scaler part, to
define two ‘ranges’ per field or per frame
• Two 8 bit video CMOS Analog-to-Digital Converters
• Field-wise switching between decoder-part and
(ADCs)
expansion port input
• Automatic Clamp Control (ACC) for CVBS, Y and C
• Switchable white peak control
• Brightness, contrast and saturation controls for scaled
outputs.
• On-chip line locked clock generation in accordance with
CCIR-601
VBI-data decoder and text slicer
• versatile VBI-data decoder, slicer, clock regeneration
and byte synchronization; e.g. for WST, NABST, Close
Caption, WSS, etc.
• Digital PLL for synchronization and clock generation
from all standards and non-standard video sources,
e.g. consumer grade VTR
• Requires only one crystal (32.11 MHz) for all standards
• Horizontal and vertical sync detection
Audio clock generation
• Generation of a field locked audio master clock to
support a constant number of audio clocks per video
field
• Automatic detection of 50/60Hz field frequency, and
automatic switching between standards PAL and NTSC
• Luminance and chrominance signal processing for PAL
BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43
and SECAM
• Generation of an audio serial and left/right (channel)
clock signal.
• User programmable luminance peaking or aperture
Digital I/O interfaces
correction
• Real time signal port (R-port), including continuous line
locked reference clock and real time status information
• Cross-colour reduction for NTSC by chrominance
combination filtering
• Bidirectional expansion port (X-port) with half duplex
functionality (D1), 8-bit YUV
• PAL delay line for correcting PAL phase errors
• Real time status information output (RTCO)
– output from decoder part, real time, or
• Independent Brightness Contrast Saturation (BCS)
adjustment for decoder part.
– input to scaler part, e.g. video from MPEG-decoder
• Video image port (I-port) configurable for 8-bit (16-bit)
data in master mode (own clock), or slave mode
(external clock), with auxiliary timing and hand shake
signals
Video Scaler
• Horizontal and vertical down-scaling and up-scaling to
randomly sized windows
• 8-bit data Host port (H-port) for 16-bit extension of I-port
• Discontinuous data streams supported
• Horizontal and vertical scaling range:
2 (zoom) to 1⁄64 (icon); vertical zoom might be restricted
• 32-word × 4 bytes FIFO register for video output data
• Anti-alias- and accumulating filter for horizontal scaling
1996 Jun 20
2
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
• 16-word × 4 bytes FIFO register for decoded VBI output
data
scaling and a brightness, contrast and saturation control
circuit (see Fig.1).
Scaled 4 : 2 : 2, 4 : 1 : 1 YUV output
• Scaled 8-bit luminance only and raw data output
• Decoded VBI data output.
It is a highly integrated circuit for desktop video
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into CCIR-601
compatible colour component values. The SAA7112
accepts as analog inputs CVBS or S-video (Y−C) from TV
or VCR sources, including weak and distorted signals.
An Expansion port for digital video (bidirectional half
duplex, D1 compatible) is also supported to connect to
MPEG or video phone CODEC. At the so called image port
the SAA7112 supports 8-bit (16-bit) wide output data with
auxiliary reference data for interfacing to VGA controllers
miscellaneous
• Power-on control
• Programming via I2C-bus, or parallel image data port
(full read-back ability by an external controller)
• Chip enable function (reset for the clock generator).
APPLICATIONS
The target application for PELICAN is to capture and scale
video images, to be provided as digital video stream
through the image port of a VGA controller, for display via
VGAs frame buffer, or for capture to system memory.
• Desktop video
• Multimedia
• Digital television
• Image processing
• Video phone.
In parallel the SAA7112 incorporates also provisions for
capturing the serially coded data in the vertical blanking
interval (VBI-data). Two principal functions are available:
to capture raw video samples and a versatile data slicer
(data recovery) unit.
GENERAL DESCRIPTION
The SAA7112 incorporates also a field locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio, during capture or playback.
The PELICAN SAA7112 is a video capture device for
applications at the image port of VGA controllers.
The SAA7112 is a combination of a two channel analog
preprocessing circuit including source-selection,
anti-aliasing filter and ADC, an automatic clamp and gain
control, a Clock Generation Circuit (CGC), a digital
multistandard decoder and a SAA7140B based scaler,
including variable horizontal and vertical up and down
The circuit can be controlled via the I2C-bus or via its fast
parallel programming mode of the image port interface (full
write/read capability).
QUICK REFERENCE DATA
SYMBOL
VDDD
PARAMETER
MIN.
MAX.
3.6
UNIT
digital supply voltage
analog supply voltage
ambient temperature
3.0
3.0
0
V
VDDA
Tamb
3.6
70
V
°C
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA7112
LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
SOT407-1
1996 Jun 20
3
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
BLOCK DIAGRAMS
XPD7
to
XCLK
XRH
XREC
XPD0
XDQ
XRV
XTRI
LLC2
RTS0
LLC
RTCA
RTS1
RT OUT
EXPANSION PORT PIN MAPPING
chroma of 16-bit mode
from host port
D1 OUT
D1 IN
a
RESIN
RESON
CLOCK
GENERATION
AND
POWER ON
CONTROL
CE
XOUT
XTALI
XTAL
X PORT INPUT FORMATTER (SELECT)
data, clock, H, V,
FID and qualifier
to scaler
AI11
AI12
AI21
b
SAA7111A
BASED
DIGITAL
ANALOG
DUAL
ADC
4 : 2 : 2
OUTPUT
INTERFACE
AI22
AI23
DECODER
AI24
AOUT
V
V
ref
ref
AUDIO
MASTER
CLOCK
AMCLK
GENERATION
data, clock, H, V,
FID and qualifier
to text slicer
ALRCLK
ASCLK
AUDIO
BIT BLOCK
WORD SELECT
GENERATION
c
AXMCLK
MGE859
Fig.1 Block diagram (continued in Fig.2).
4
1996 Jun 20
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
HPD7
to
HPD0
HACNSD
HDSNSC
HRWNF
HADP
HCST
HOST PORT PIN MAPPING
chroma of 16-bit
input mode
2
I C-BUS
chroma of 16-bit output mode
a
LPB
PROG
from
event
controller
PROG. PORT CONTROL
PROGRAMMING
REGISTER
ARRAY
A / B
REGISTER
MUX
data, clock, H, V, FID
and qualifier from
scaler input
CLOCK MULTIPLEXER
INCLUDING
TCB
SLEEP MODE REGISTER
selector
IPD7
to
IPD0
HORIZONTAL
PHASE SCALING
LUMINANCE
VERTICAL
SCALING
PROCESSOR
PRESCALING
LUMINANCE
FIR-FILTER
LUMINANCE
INPUT
4 : 2 : 2
BCS
CONTROL
LINE
FIFO
BUFFER
b
ACQUISITION
CONTROL
IMAGE
PORT
PIN
HORIZONTAL
PHASE SCALING
CHROMINANCE
FIR FILTER
CHROMINANCE
PRESCALING
CHROMINANCE
LINE MEMORY
1H * 16 BIT
MAPPING
IRH
IRV
OUTPUT
ACQUISITION
CONTROL
YUV
OUTPUT
FORMAT
VIDEO
FIFO
32 × 32
IDQE
ICRQF
ITRDY
ICLK
ITRI
EVENT
CONTROLLER
32
TO
8 (16)
MUX
FF
IP
OUT
FIFO
CONTROL
FIFO
CONTROL
data, clock and
reference signals
from text input
selector
32
TO
8 (16)
MUX
LPB
VIDEO
OUT
TEXT
FIFO
16 × 32
GENERAL
PURPOSE
TEXTSLICER
TXT
INTERFACE
c
MGE860
VIDEO / TEXT
ARBITER
Fig.2 Block diagram (continued from Fig.1).
5
1996 Jun 20
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
PACKAGE OUTLINE
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
Q
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.5
0.05 1.3
0.28 0.18 14.1 14.1
0.16 0.12 13.9 13.9
16.25 16.25
15.75 15.75
0.75 0.70
0.45 0.57
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
SOT407-1
1996 Jun 20
6
Philips Semiconductors
Preliminary specification
Decoder with High-Performance Scaler
(HPS) for Image Port (PELICAN)
SAA7112
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jun 20
7
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Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
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Tel. +1 800 234 7381, Fax. +1 708 296 8556
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Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
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Tel. +1 800 234 7381, Fax. +1 708 296 8556
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com/ps/
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/01/pp8
Date of release: 1996 Jun 20
Document order number: 9397 750 00923
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Description
Consumer Multimedia
Systems
Communications
The PELICAN SAA7112 is a video capture device for applications at the image port of VGA controllers.
PC/PC-peripherals
The SAA7112 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and ADC, an
automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder and a SAA7140B based scaler,
including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit.
Cross reference
Models
Packages
It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is
able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7112 accepts
as analog inputs CVBS or S-video (Y-C) from TV or VCR sources, including weak and distorted signals. An Expansion port for digital video
(bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone CODEC. At the so called image port the
SAA7112 supports 8-bit (16-bit) wide output data with auxiliary reference data for interfacing to VGA controllers.
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
The target application for PELICAN is to capture and scale video images, to be provided as digital video stream through the image port of a
VGA controller, for display via VGAs frame buffer, or for capture to system memory.
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In parallel the SAA7112 incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two
principal functions are available: to capture raw video samples and a versatile data slicer (data recovery) unit.
The SAA7112 incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio
samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or
playback.
SAA7112
SAA7112
The circuit can be controlled via the I²C-bus or via its fast parallel programming mode of the image port interface (full write/read capability).
Features
The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights:
Video Decoder
l Six analog inputs, internal analog source selectors, (e.g. 6 x CVBS or(2 x YC and 2 x CVBS) or (1x YC and 4 x CVBS)
l Two analog preprocessing channels, including built in analog anti-alias filters
l Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel
l Two 8 bit video CMOS Analog-to-Digital Converters (ADCs)
l Automatic Clamp Control (ACC) for CVBS, Y and C
l Switchable white peak control
l On-chip line locked clock generation in accordance with CCIR-601
l Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR
l Requires only one crystal (32.11 MHz) for all standards
l Horizontal and vertical sync detection
l Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC
l Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM
l User programmable luminance peaking or aperture correction
l Cross-colour reduction for NTSC by chrominance combination filtering
l PAL delay line for correcting PAL phase errors
l Real time status information output (RTCO)
l Independent Brightness Contrast Saturation (BCS) adjustment for decoder part.
Video Scaler
l Horizontal and vertical down-scaling and up-scaling to randomly sized windows
l Horizontal and vertical scaling range: 2 (zoom) to 1/64 (icon); vertical zoom might be restricted
l Anti-alias- and accumulating filter for horizontal scaling
l Vertical scaling with linear phase interpolation (6-bit phase accuracy) and accumulating filter for anti-aliasing
l Horizontal phase correct up- and down-scaling for improved signal quality of scaled data, especially for compression and video
phone applications, with 6-bit phase accuracy
l Two independent programming sets for scaler part, to define two ‘ranges’ per field or per frame
l Field-wise switching between decoder-part and expansion port input
l Brightness, contrast and saturation controls for scaled outputs.
VBI-data decoder and text slicer
l versatile VBI-data decoder, slicer, clock regeneration and byte synchronization; e.g. for WST, NABST, Close Caption, WSS, etc.
Audio clock generation
l Generation of a field locked audio master clock to support a constant number of audio clocks per video field
l Generation of an audio serial and left/right (channel) clock signal.
Digital I/O interfaces
l Real time signal port (R-port), including continuous line locked reference clock and real time status information
l Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV
- output from decoder part, real time, or
- input to scaler part, e.g. video from MPEG-decoder
l Video image port (I-port) configurable for 8-bit (16-bit) data in master mode (own clock), or slave mode (external clock), with
auxiliary timing and hand shake signals
l 8-bit data Host port (H-port) for 16-bit extension of I-port
l Discontinuous data streams supported
l 32-word x 4 bytes FIFO register for video output data
l 16-word x 4 bytes FIFO register for decoded VBI output data
Scaled 4 :2 :2, 4 :1 :1 YUV output
l Scaled 8-bit luminance only and raw data output
l Decoded VBI data output.
miscellaneous
l Power-on control
l Programming via I²C-bus, or parallel image data port (full read-back ability by an external controller)
l Chip enable function (reset for the clock generator).
Applications
l Desktop video
l Multimedia
l Digital television
l Image processing
l Video phone.
Datasheet
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size
(kB)
Publication
release date Datasheet status
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count
Type nr. Title
Datasheet
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SAA7112 Decoder with High-Performance
Scaler (HPS) for Image Port
(PELICAN)
20-Jun-96
Preliminary
Specification
8
81
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Reel Dry Pack,
SMD, 13"
SAA7112H/01
9352 439 50518
9352 439 50551
9352 439 50557
SOT407 Full production
SOT407 Full production
SOT407 Full production
-
Standard Marking * Tray Dry Pack,
Bakeable, Single
SAA7112HBE-S
SAA7112HBE
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
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