935250000112 [NXP]
IC LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP-14, Gate;
| 型号： | 935250000112 |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP-14, Gate 栅 输入元件 光电二极管 |
| 文件： | 总16页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC02A
Quad 2-input NOR gate
Product specification
2002 Mar 05
Supersedes data of 1998 Apr 28
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
FEATURES
DESCRIPTION
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74LVC02A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in
a mixed 3.3 and 5 V environment.
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• Specified from −40 to +85 °C and −40 to +125 °C.
The 74LVC02A provides the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PHL/tPLH
CI
PARAMETER
propagation delay nA, nB to nY
input capacitance
CONDITIONS
TYPICAL
2.1
UNIT
t
CL = 50 pF; VCC = 3.3 V
ns
pF
pF
4.0
10
CPD
power dissipation capacitance per gate
VCC = 3.3 V;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
TYPE NUMBER
.
PACKAGES
TEMPERATURE RANGE
PINS
14
PACKAGE MATERIAL
CODE
74LVC02AD
74LVC02ADB
74LVC02APW
−40 to +125 °C
SO
plastic
plastic
plastic
SOT108-1
SOT337-1
SOT402-1
−40 to +125 °C
14
SSOP
TSSOP
−40 to +125 °C
14
2002 Mar 05
2
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
nA
nB
nY
L
L
L
H
L
H
L
L
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
PINNING
PIN
SYMBOL
DESCRIPTION
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9, 12
7
1Y to 4Y
1A to 4A
1B to 4B
GND
data output
data input
data input
ground (0 V)
14
VCC
supply voltage
handbook, halfpage
1Y
1A
1
2
3
4
5
6
7
V
CC
14
13
12
11
10
9
handbook, halfpage
2
3
1A
1B
1Y
2Y
1
4
4Y
4B
4A
3Y
3B
3A
5
6
2A
2B
1B
2Y
02
8
9
3A
3B
3Y 10
4Y 13
2A
11
12
4A
4B
2B
8
GND
MNA216
MNA214
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2002 Mar 05
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
2
3
handbook, halfpage
≥ 1
≥ 1
≥ 1
≥ 1
1
4
5
6
handbook, halfpage
A
B
Y
8
9
10
13
MNA215
11
12
MNA217
Fig.3 Logic symbol (IEEE/IEC).
Fig.4 Logic diagram (one gate).
2002 Mar 05
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VCC
for maximum speed performance 2.7
V
for low-voltage applications
VCC = 1.2 to 2.7 V
1.2
0
3.6
5.5
VCC
+125
20
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
ns/V
ns/V
VCC = 2.7 to 3.6 V
0
10
LIMITING VALUES
In accordance with the absolute maximum rating system (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
VO
IO
output diode current
output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
−0.5
−
VCC + 0.5
±50
output source or sink current
VO = 0 to VCC
mA
mA
°C
IGND, ICC VCC or GND current
−
±100
+150
Tstg
Ptot
storage temperature
power dissipation per package
SO package
−65
above +70 °C derate linearly with
−
−
500
500
mW
mW
8 mW/K
SSOP and TSSOP packages
above +60 °C derate linearly with
5.5 mW/K
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Mar 05
5
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL PARAMETER
−40 to +85
TYP.(1) MAX.
−40 to +125
MIN. MAX.
VCC V
UNIT
OTHER
VCC (V)
MIN.
VCC
2.7 to 3.6 2.0
VIH
VIL
HIGH-levelinput
voltage
1.2
−
−
−
−
−
−
−
2.0
−
−
V
V
V
LOW-level input
voltage
1.2
−
−
GND
0.8
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level
output voltage
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
VCC − 0.2
VCC − 0.5
VCC − 0.6
VCC − 0.8
−
−
−
−
−
−
−
−
V
V
V
V
CC − 0.3
−
V
V
V
V
CC − 0.65 −
CC − 0.75 −
3.0
3.0
CC − 1
−
VOL
LOW-level
output voltage
2.7 to 3.6
2.7
−
−
−
−
−
0.2
0.4
0.55
±5
−
−
−
−
0.3
0.6
0.8
±20
V
−
V
IO = 24 mA
3.0
−
V
II
input leakage
current
VI = 5.5 V or GND 3.6
±0.1
µA
ICC
∆ICC
quiescent
supply current
VI = VCC or GND; 3.6
IO = 0
−
−
0.1
5
10
−
−
40
µA
additional
VI =VCC−0.6V;
2.7 to 3.6
500
5000 µA
quiescent
IO = 0
supply current
per input pin
Note
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2002 Mar 05
6
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns.
T
amb (°C)
−40 to +85
MIN. TYP.(1) MAX. MIN. MAX.
SYMBOL
PARAMETER
WAVEFORMS
−40 to +125
UNIT
VCC = 1.2 V
tPHL/tPLH
propagation delay nA, nB to nY see Figs 5 and 6
−
14
−
−
−
ns
VCC = 2.7 V
tPHL/tPLH
propagation delay nA, nB to nY see Figs 5 and 6 1.5
2.4
2.1
5.4
1.5
1.0
7.0
ns
VCC = 3.0 to 3.6 V
tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 1.0
tsk(0) skew note 2
4.4
1.0
5.5
1.5
ns
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
AC WAVEFORMS
handbook, halfpage
V
t
nA, nB input
M
t
PHL
PLH
nY output
V
M
MNA213
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 The input nA, nB to output nY propagation delays.
2002 Mar 05
7
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
S1
2 × V
open
GND
CC
V
CC
R
L
500 Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
R
L
L
R
T
500 Ω
MNA368
VCC
VI
tPLH/tPHL
1.2 V
2.7 V
VCC
open
2.7 V open
2.7 V open
3.0 to 3.6 V
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2002 Mar 05
8
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.050
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT108-1
076E06
MS-012
2002 Mar 05
9
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-01-18
99-12-27
SOT337-1
MO-150
2002 Mar 05
10
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-04-04
99-12-27
SOT402-1
MO-153
2002 Mar 05
11
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Mar 05
12
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
not suitable
REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
PLCC(3), SO, SOJ
suitable
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Mar 05
13
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Mar 05
14
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
NOTES
2002 Mar 05
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/03/pp16
Date of release: 2002 Mar 05
Document order number: 9397 750 09443
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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