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74ALVCH16501

18-bit universal bus transceiver; 3-state

Rev. 5 — 10 July 2012

Product data sheet

1. General description

The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is

controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock

(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent

mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a

HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on

the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When

OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.

To ensure the high-impedance state during power-up or power-down, OEBA should be

tied to V_CCthrough a pull-up resistor and OEAB should be tied to GND through a

pull-down resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2. Features and benefits

 Wide supply voltage range from 1.2 V to 3.6 V

 Complies with JEDEC standard JESD8-B

 CMOS low power consumption

 Direct interface with TTL levels

 Current drive 24 mA at V_CC= 3.0 V

 Universal bus transceiver with D-type latches and D-type flip-flops capable of

operating in transparent, latched or clocked mode

 All inputs have bus hold circuitry

 Output drive capability 50  transmission lines at 85 C

 3-state non-inverting outputs for bus-oriented applications

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVCH16501DGG 40 C to +85 C

TSSOP56

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

74ALVCH16501DL 40 C to +85 C

SSOP56

plastic shrink small outline package; 56 leads;

body width 7.5 mm

SOT371-1

4. Functional diagram

1

OEAB

CPAB

LEAB

EN1

2C3

C3

55

2

G2

27

30

28

OEBA

CPBA

LEBA

EN4

5C6

C6

A0

3

B0

B1

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

A1

5

G5

A2

6

B2

A3

B3

3

54

8

A0

3D

4

1

B0

A4

9

B4

6D

A5

B5

5

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

10

A1

A2

B1

A6

12

B6

6

B2

A7

B7

8

13

A3

B3

A8

14

B8

9

A4

B4

A9

B9

10

12

13

14

15

16

17

19

20

21

23

24

26

15

A5

B5

A10

16

B10

B11

B12

B13

B14

B15

B16

B17

A6

B6

A11

17

A7

B7

A12

19

A8

B8

A13

20

A9

B9

A14

21

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

A15

23

A16

24

A17

26

OEAB

LEAB

CPAB

OEBA

LEBA

CPBA

1

2

27

28

30

55

001aal718

001aal717

Fig 1. Logic symbol

Fig 2. IEC logic symbol

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

2 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

V

CC

data input

to internal circuit

001aal733

Fig 3. Bus hold circuit

OEAB

CPBA

LEBA

CPAB

LEAB

OEBA

C1

1D

C1

1D

B1

A1

C1

1D

C1

1D

18 IDENTICAL CHANNELS

001aal719

Fig 4. Logic diagram

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

3 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

5. Pinning information

5.1 Pinning

74ALVCH16501

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A0

GND

CPAB

B0

2

3

4

GND

A1

GND

B1

5

6

A2

B2

7

V

CC

A3

8

B3

9

A4

A5

B4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

B5

GND

A6

GND

B6

A7

B7

A8

B8

A9

B9

A10

A11

GND

A12

A13

A14

B10

B11

GND

B12

B13

B14

V

CC

A15

A16

B15

B16

GND

A17

GND

B17

OEBA

LEBA

CPBA

GND

001aal716

Fig 5. Pin configuration

5.2 Pin description

Table 2.

Symbol

OEAB

LEAB

Pin description

1

Description

output enable A-to-B input

latch enable A-to-B input

data inputs or outputs

ground (0 V)

2

A0 to A17

GND

3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26

4, 11, 18, 25, 29, 32, 39, 46, 53, 56

V_CC

7, 22, 35, 50

positive supply voltage

output enable B-to-A

latch enable B-to-A

OEBA

LEBA

27

28

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

4 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

Table 2.

Symbol

CPBA

Pin description …continued

Description

30

clock input B-to-A

B0 to B17

CPAB

54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs or outputs

55 clock input A-to-B

6. Functional description

6.1 Function table

Table 3.

Function table^[1]

Inputs

Output

Operating mode

OEAB

LEAB

CPAB

An

X

H

L

Bn

Z

L

X

H



L

X

disabled

H

X

H

L

transparent

X

h

H

L

latch data and display

clock data and display

hold data and display

X

l



h

H

L



l

L

H or L

X

H

L

[1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the enable or clock transition;

X = don’t care;

Z = high-impedance OFF-state;

 = HIGH-to-LOW clock transition;

 = LOW-to-HIGH clock transition.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

Unit

V

supply voltage

input clamping current

input voltage

+4.6

V_I< 0 V

-

mA

V

[1]

V_I

control inputs

data inputs

+4.6

V_CC+ 0.5

50

V

I_OK

V_O

I_O

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

mA

V

[1]

0.5

-

V_CC+ 0.5

50

output current

V_O= 0 V to V_CC

mA

I_CC

supply current

-

100

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

5 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

Table 4.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

I_GND

Parameter

Conditions

Min

100

65

Max

-

Unit

mA

C

ground current

T_stg

storage temperature

total power dissipation

+150

P_tot

T_amb= 40 C to +125 C

SSOP package

[2]

[3]

-

850

600

mW

TSSOP package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 55 C the value of P_totderates linearly with 11.3 mW/K.

[3] Above 55 C the value of P_totderates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

maximum speed performance

C_L= 30 pF

2.3

3.0

1.2

0

-

2.7

3.6

V_CC

+85

20

V

C_L= 50 pF

V

low-voltage applications

V

V_I

input voltage

V

V_O

output voltage

0

V

T_amb

t/V

ambient temperature

in free air

40

0

C

ns/V

input transition rise and fall V_CC= 2.3 V to 3.0 V

rate

V_CC= 3.0 V to 3.6 V

0

10

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Product data sheet

Rev. 5 — 10 July 2012

6 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max Unit

T_amb= 40 C to +85 C

V_IH

HIGH-level input voltage

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

1.7

2.0

-

1.2

1.5

1.2

1.5

-

V

-

V_IL

LOW-level input voltage

HIGH-level output voltage

0.7

0.8

-

V_OH

I_O= 100 A;

V_CC 0.2

V_CC

-

V

V_CC= 2.3 V to 3.6 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 12 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC 0.3 V_CC 0.08

V_CC 0.6 V_CC 0.26

V_CC 0.5 V_CC 0.14

V_CC 0.6 V_CC 0.09

V_CC 1.0 V_CC 0.28

-

V

V_OL

LOW-level output voltage

I_O= 100 A;

-

GND

0.20

V

V_CC= 2.3 V to 3.6 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.07

0.15

0.14

0.27

0.1

0.40

0.70

0.40

0.55

5

V

I_I

input leakage current

V_I= V_CCor GND;

A

V_CC= 2.3 V to 3.6 V

I_OZ

OFF-state output current

V_I= V_IHor V_IL;

-

0.1

10 A

V_O= V_CCor GND;

V_CC= 2.7 V to 3.6 V

I_CC

supply current

V_CC= 2.3 V to 3.6 V;

V_I= V_CCor GND; I_O= 0 A

-

0.2

40 A

750 A

I_CC

additional supply current

per data I/O pin; V_CC= 2.3 V

to 3.6 V; V_I= V_CC 0.6 V;

I_O= 0 A

150

[2]

I_BHL

bus hold LOW current

bus hold HIGH current

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

V_CC= 3.6 V

45

75

-

150

-

A

pF

I_BHH

45

75

500

500

-

175

-

I_BHLO

I_BHHO

C_I

bus hold LOW overdrive current

bus hold HIGH overdrive current

input capacitance

V_CC= 3.6 V

-

4.0

8.0

C_I/O

input/output capacitance

-

[1] All typical values are measured at T_amb= 25 C.

[2] Valid for data inputs of bus hold parts only.

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

7 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol

T_amb= 40 C to +85 C

f_maxmaximum frequency

Parameter

Conditions

Min Typ^[1]Max Unit

see Figure 8

[2]

[3]

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

150

333

340

333

-

MHz

[4]

[2]

[3]

t_pd

propagation delay

An to Bn; Bn to An; see Figure 6

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

1.0

-

2.8

3.0

5.1 ns

4.2 ns

4.6 ns

LEAB, LEBA to Bn, An; see Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.1

1.3

-

3.5

3.4

3.6

6.1 ns

4.8 ns

5.3 ns

CPAB, CPBA to Bn, An; see Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[2]

[3]

1.0

1.4

-

3.3

3.4

6.1 ns

4.9 ns

5.6 ns

V_CC= 2.7 V

[4]

[2]

[3]

t_en

enable time

OEBA to An; see Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

1.3

1.1

-

2.8

2.5

3.3

6.3 ns

5.0 ns

6.0 ns

OEAB to Bn; see Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.0

-

2.5

2.4

2.7

5.8 ns

4.6 ns

5.3 ns

[4]

[2]

[3]

t_dis

disable time

OEBA to An; see Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

1.3

-

2.5

3.1

3.3

5.3 ns

4.2 ns

4.6 ns

OEAB to Bn; see Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.5

1.4

-

2.5

2.9

3.6

6.2 ns

5.0 ns

5.7 ns

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

8 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

Table 7.

Dynamic characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol

Parameter

Conditions

Min Typ^[1]Max Unit

t_W

pulse width

LEAB, LEBA HIGH; see Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

3.3

0.8

0.9

0.7

-

ns

CPAB, CPBA HIGH or LOW; see Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

3.3

2.0

1.1

1.4

-

ns

t_su

set-up time

An, Bn to CPAB, CPBA; see Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.7

1.3

1.4

0.1

-

ns

0.3

0.1

An, Bn to LEAB, LEBA; see Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.1

1.0

0.1

0.3

-

ns

0.2

t_h

hold time

An, Bn to CPAB, CPBA; see Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.7

1.3

1.6

0.3

0.4

0.3

-

ns

An, Bn to LEAB, LEBA; see Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.7 V

[2]

[3]

1.6

1.2

1.5

0.3

0.1

-

ns

[5]

C_PD

power dissipation

capacitance

per buffer; V_I= GND to V_CC

outputs enabled

-

21

3

-

pF

outputs disabled

[1] All typical values are measured at T_amb= 25 C.

[2] Typical values are measured at V_CC= 2.5 V.

[3] Typical values are measured at V_CC= 3.3 V.

[4] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N +  (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = total load switching outputs;

 (C_L V_CC² f_o) = sum of outputs.

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

9 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

11. Waveforms

V

I

An, Bn

input

V

t

V

t

M

GND

PHL

PLH

V

OH

Bn, An

output

V

M

001aal734

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An)

V

I

OEAB, OEBA

input

V

M

GND

t

PZL

PLZ

V

CC

An, Bn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

An, Bn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aal721

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 7. 3-state output enable and disable times

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

10 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

1 / f

max

V

LExx

input

CPxx

input

I

V

M

GND

t

W

t

PLH

t

PHL

V

OH

An, Bn

output

V

M

V

OL

001aal720

Measurement points are given in Table 8.

V_OLand V_OHare typical output levels that occur with the output load.

Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output,

and pulse width

V

I

An, Bn

input

V

M

V

M

V

M

GND

t

h

su

h

su

V

I

CPxx, LExx

input

V

M

GND

001aal722

Measurement points are given in Table 8.

Fig 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs)

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

2.3 V to 2.7 V and < 2.3 V V_CC

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH 0.15 V

V_OH 0.3 V

2.7 V

3.0 V to 3.6 V

1.5 V

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

11 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

12. Test information

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

L

mna616

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance includes jig and probe capacitance.

R_T= Termination resistance should be equal to Z_oof pulse generator.

_EXT= External voltage for measuring switching times.

V

Fig 10. Load circuit for measuring switching times

Table 9. Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

2.3 V to 2.7 V

2.7 V

V_CC

 2.0 ns

2.5 ns

30 pF

50 pF

500 

2.7 V

open

GND

3.0 V to 3.6 V

open

GND

74ALVCH16501

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Product data sheet

Rev. 5 — 10 July 2012

12 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

13. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 11. Package outline SOT364-1 (TSSOP56)

74ALVCH16501

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 10 July 2012

13 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

D

E

A

X

c

y

H

v

M

A

E

Z

29

56

Q

A

2

A

(A )

3

1

θ

pin 1 index

L

p

L

28

1

detail X

w M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 18.55

0.13 18.30

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT371-1

MO-118

Fig 12. Package outline SOT371-1 (SSOP56)

74ALVCH16501

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 10 July 2012

14 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

14. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

TTL

Transistor-Transistor Logic

15. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20120710 Product data sheet

• Table 8 corrected (errata).

20111117 Product data sheet

• Legal pages updated.

Change notice Order number Supersedes

74ALVCH16501 v.5

Modifications:

-

74ALVCH16501 v.4

Modifications:

-

74ALVCH16501 v.3

74ALVCH16501 v.2

74ALVCH16501 v.1

20100402

19980929

Product data sheet

-

74ALVCH16501 v.2

Product specification

74ALVCH16501 v.1

-

74ALVCH16501

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 10 July 2012

15 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74ALVCH16501

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 10 July 2012

16 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74ALVCH16501

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 10 July 2012

17 of 18

74ALVCH16501

NXP Semiconductors

18-bit universal bus transceiver; 3-state

18. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

6.1

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 July 2012

Document identifier: 74ALVCH16501


型号：	935262543512
厂家：	NXP
描述：	ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56 光电二极管输出元件逻辑集成电路
文件：	总18页 (文件大小：224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935262543512 [NXP]

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