935262609112 [NXP]
IC 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40, 0.600 INCH, PLASTIC, DIP-40, Microcontroller;
| 型号： | 935262609112 |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40, 0.600 INCH, PLASTIC, DIP-40, Microcontroller 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总35页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
89C51/89C52/89C54/89C58
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
Product specification
1999 Oct 27
Replaces Datasheets 89C51 of 1999 Apr 01 and 89C52/89C54/89C58 of 1999 Apr 01
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DESCRIPTION
FEATURES
The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH
program memory that is parallel programmable. For devices that are
serial programmable (In System Programmable (ISP) with a boot
loader), see the 89C51RC+/89C51RD+ datasheet.
• 80C51 Central Processing Unit
• On-chip FLASH Program Memory
• Speed up to 33 MHz
Both families are Single-Chip 8-bit Microcontrollers manufactured in
advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set
as the 80C51.
• Full static operation
• RAM expandable externally to 64 k bytes
• 4 level priority interrupt
SELECTION TABLE FOR FLASH DEVICES
• 6 interrupt sources
ROM/EPROM
Memory Size
(X by 8)
Programmable
Timer Counter
(PCA)
Hardware
Watchdog
Timer
• Four 8-bit I/O ports
RAM Size
(X by 8)
• Full-duplex enhanced UART
– Framing error detection
Multi-Time Programmable (MTP) devices:
89C51
– Automatic address recognition
• Power control modes
– Clock can be stopped and resumed
– Idle mode
4 k
128
No
No
No
89C52/54/58
8 k/16 k/32 k
256
No
– Power down mode
Serial In-System Programmable devices:
89C51RC+
• Programmable clock out
• Second DPTR register
32 k
512
Yes
Yes
Yes
89C51RD+
64 k
• Asynchronous port reset
• Low EMI (inhibit ALE)
1024
Yes
• 3 16-bit timers
• Wake up from power down by an external interrupt
ORDERING INFORMATION
TEMPERATURE
RANGE °C
AND PACKAGE
MEMORY SIZE MEMORY SIZE MEMORY SIZE MEMORY SIZE
VOLTAGE FREQ.
DWG.
#
4 k × 8
8 k × 8
16 k × 8
32 k × 8
RANGE
(MHz)
0 to +70, Plastic
Leaded Chip Carrier
FLASH
FLASH
FLASH
FLASH
FLASH
P89C51UBA A P89C52UBA A
P89C51UBP N P89C52UBP N
P89C51UBB B P89C52UBB B
P89C51UFA A P89C52UFA A
P89C51UFP N P89C52UFP N
P89C51UFB B P89C52UFB B
P89C54UBA A
P89C54UBP N
P89C54UBB B
P89C54UFA A
P89C54UFP N
P89C54UFB B
P89C58UBA A
P89C58UBP N
P89C58UBB B
5 V
0 to 33 SOT187-2
0 to +70, Plastic
Dual In-line Package
5 V
0 to 33 SOT129-1
0 to +70, Plastic
Quad Flat Pack
2
5 V
0 to 33
QFP44
–40 to +85, Plastic
Leaded Chip Carrier
1
P89C58UFA A
5 V
0 to 33 SOT187-2
–40 to +85, Plastic
Dual In-line Package
1
P89C58UFP N
5 V
0 to 33 SOT129-1
–40 to +85, Plastic
Quad Flat Pack
1
2
FLASH
P89C58UFB B
5 V
0 to 33
QFP44
NOTES:
1. Contact Philips Sales for availability.
2. SOT not assigned for this package outline.
PART NUMBER DERIVATION
DEVICE NUMBER (P89CXX)
OPERATING FREQUENCY, MAX (V)
TEMPERATURE RANGE (B)
PACKAGE (AA, BB, PN)
P89C51 FLASH
P89C52 FLASH
P89C54 FLASH
P89C58 FLASH
AA = PLCC
BB = PQFP
PN = PDIP
B = 0_C to 70_C
U = 33 MHz
F = –40_C to 85_C
2
1999 Oct 27
853–2148 22592
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
V
CC
SS
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
FLASH
RAM
8
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCRE-
MENTER
TIMERS
PSW
8
16
PROGRAM
COUNTER
PSEN
ALE
DPTR’S
MULTIPLE
TIMING
AND
CONTROL
EAV
PP
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU01066
3
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
LOGIC SYMBOL
Ceramic and Plastic Leaded Chip Carrier
Pin Functions
V
V
SS
CC
6
1
40
XTAL1
ADDRESS AND
DATA BUS
7
39
LCC
XTAL2
RST
T2
T2EX
17
29
EA/V
PP
18
28
PSEN
ALE/PROG
Pin Function
Pin Function
Pin Function
RxD
1
2
3
NIC*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
TxD
INT0
P1.0/T2
P1.1/T2EX
P1.2
INT1
T0
T1
WR
RD
4
ADDRESS BUS
SU00830
5
P1.3
6
P1.4
7
P1.5
8
P1.6
9
P1.7
10
11
12
13
14
15
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
V
CC
PIN CONFIGURATIONS
Dual In-Line Package Pin Functions
* NO INTERNAL CONNECTION
SU01062
T2/P1.0
40
39
V
CC
1
2
3
T2EX/P1.1
P0.0/AD0
Plastic Quad Flat Pack Pin Functions
P1.2
P1.3
P1.4
38 P0.1/AD1
37
44
34
4
5
P0.2/AD2
36 P0.3/AD3
35
1
33
23
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
33
PQFP
P0.6/AD6
11
32 P0.7/AD7
DUAL
IN-LINE
PACKAGE
31 EA/V
PP
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
12
Pin Function
22
30 ALE
Pin Function
Pin Function
29
PSEN
28 P2.7/A15
27
1
2
3
P1.5
P1.6
P1.7
RST
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
NIC*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
13
INT1/P3.3
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NIC*
EA/V
P0.7/AD7
4
P2.6/A14
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
5
6
P3.0/RxD
NIC*
26 P2.5/A13
25 P2.4/A12
7
8
9
10
11
12
13
14
15
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
V
CC
NIC*
24
P2.3/A11
23 P2.2/A10
22
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P2.1/A9
21 P2.0/A8
PP
V
20
SS
XTAL1
* NO INTERNAL CONNECTION
SU01064
SU01063
4
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
LCC
22
QFP
16
TYPE NAME AND FUNCTION
V
SS
V
CC
20
40
I
I
Ground: 0 V reference.
44
38
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
39–32 43–36 37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I ). Alternate function for Port 1:
IL
1
2
2
3
40
41
I/O
I
T2 (P1.0): Timer/Counter2 external count input/clockout (see Programmable Clock-Out).
T2EX (P1.1): Timer/Counter2 reload/capture/direction control.
P2.0–P2.7
P3.0–P3.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte
IL
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register.
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
13–19 7–13
(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the
IL
89C51/89C52/89C54/89C58, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
CC
30
33
27
O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
EA/V
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to the
maximum internal memory boundary. If EA is held high, the device executes from internal
program memory unless the program counter contains an address greater than 0FFFH for
4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices.
The value on the EA pin is latched when RST is released and any subsequent changes
PP
have no effect. This pin also receives the 12.00 V programming supply voltage (V ) during
PP
FLASH programming.
XTAL1
XTAL2
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than V ) at any time must not be higher than V + 0.5 V or
PP
CC
V
– 0.5 V, respectively.
SS
5
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Table 1. 89C51/89C52/89C54/89C58 Special Function Registers
DIRECT
ADDRESS MSB
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
DESCRIPTION
LSB
ACC*
AUXR#
AUXR1#
B*
Accumulator
E0H
8EH
A2H
F0H
E7
–
E6
–
E5
–
E4
–
E3
–
E2
–
E1
–
E0
00H
Auxiliary
AO
DPS
F0
xxxxxxx0B
xxxx00x0B
00H
Auxiliary 1
B register
–
–
–
–
GF2
F3
0
–
F7
F6
F5
F4
F2
F1
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
BF
–
AE
–
AD
ET2
BD
AC
ES
BC
PS
B4
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
Interrupt Enable
Interrupt Priority
Interrupt Priority High
Port 0
A8H
B8H
B7H
80H
90H
A0H
0x000000B
xx000000B
xx000000B
FFH
BE
–
IP*
PT2
B5
PT1
B3
PX1
B2
PT0
B1
PX0
B0
B7
–
B6
–
IPH#
P0*
P1*
P2*
P3*
PT2H
85
PSH
84
PT1H
83
PX1H PT0H
PX0H
80
87
86
82
AD2
92
81
AD1
91
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD0
90
Port 1
–
–
–
–
–
–
T2EX
A1
T2
FFH
A7
AD15
B7
RD
A6
AD14
B6
WR
A5
A4
A3
A2
A0
Port 2
AD13
B5
AD12
B4
AD11
B3
AD10
B2
AD9
B1
AD8
B0
FFH
Port 3
B0H
87H
T1
T0
INT1
INT0
TxD
RxD
FFH
1
2
PCON#
Power Control
SMOD1 SMOD0
–
POF
GF1
D3
GF0
D2
PD
D1
–
IDL
D0
P
00xxx000B
D7
CY
D6
AC
D5
F0
D4
PSW*
Program Status Word
D0H
RS1
RS0
OV
000000x0B
RACAP2H# Timer 2 Capture High
RACAP2L# Timer 2 Capture Low
CBH
CAH
00H
00H
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
00H
00H
SBUF
Serial Data Buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SM0/FE
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
TF2
–
8E
TR1
CE
8D
TF0
CD
8C
TR0
CC
8B
IE1
8A
IT1
CA
TR2
–
89
IE0
88
IT0
C8
TCON*
Timer Control
88H
C8H
00H
CB
C9
T2CON*
Timer 2 Control
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
C/T2
T2OE
CP/RL2 00H
T2MOD#
TH0
TH1
TH2#
TL0
TL1
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
C9H
8CH
8DH
CDH
8AH
8BH
CCH
DCEN xxxxxx00B
00H
00H
00H
00H
00H
00H
Timer Low 1
Timer Low 2
TL2#
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
*
SFRs are bit addressable.
#
–
SFRs are modified from or added to the 80C51 SFRs.
Reserved bits.
1. Reset value depends on reset source.
2. Bit will not be affected by reset.
6
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
FLASH EPROM MEMORY
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
General Description
The 89C51/89C52/89C54/89C58 FLASH reliably stores memory
contents even after 100 erase and program cycles. The cell is
designed to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide processing and
low internal electric fields for erase and programming operations
produces reliable cycling.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Features
• FLASH EPROM internal program memory with Chip Erase
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
• Up to 64 k byte external program memory if the internal program
memory is disabled (EA = 0)
• Programmable security bits
• 100 minimum erase/program cycles for each byte
• 10 year minimum data retention
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V (min.) is applied to RESET.
IH1
• Programming support available from many popular vendors
The value on the EA pin is latched when RST is deasserted and has
no further effect.
7
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
LOW POWER MODES
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle Mode
ONCE Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
their values down to 2.0 V and care must be taken to return V to
the minimum specified operating voltages before the Power Down
Mode is terminated.
CC
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a
16MHz operating frequency.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
To properly terminate Power Down the reset or external interrupt
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
should not be executed before V is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
CC
Oscillator Frequency
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
4 (65536 * RCAP2H, RCAP2L)
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
Table 2. External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
Internal
1
1
0
0
1
1
0
0
Data
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
8
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
Auto-Reload Mode (Up or Down Counter)
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter [C/T2* in T2CON]) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
T2CON.6
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
9
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
1
16-bit Capture
Baud rate generator
(off)
X
X
1
0
OSC
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
T2MOD
Symbol
Address = 0C9H
Not Bit Addressable
—
Reset Value = XXXX XX00B
—
6
—
5
—
4
—
3
—
2
T2OE
1
DCEN
0
Bit
7
Function
—
Not implemented, reserved for future use.*
Timer 2 Output Enable bit.
T2OE
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00729
Figure 3. Timer 2 Mode (T2MOD) Control Register
10
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
FFH
FFH
TOGGLE
EXF2
OSC
÷12
C/T2 = 0
OVERFLOW
TL2
TH2
TF2
INTERRUPT
C/T2 = 1
T2 PIN
CONTROL
TR2
COUNT
DIRECTION
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(UP COUNTING RELOAD VALUE)
T2EX PIN
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
11
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“0”
“1”
OSC
÷ 2
C/T2 = 0
C/T2 = 1
SMOD
RCLK
“1”
TL2
(8-bits)
TH2
(8-bits)
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates +
Timer 2
16
Baud Rate
Osc Freq
RCAP2H
RCAP2L
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
375 k
9.6 k
2.8 k
2.4 k
1.2 k
300
110
300
110
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6 MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Modes 1 and 3 Baud Rates =
6 MHz
Oscillator Frequency
[32 [65536 * (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Where: (RCAP2H, RCAP2L) = The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode, in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value
in registers RCAP2H and RCAP2L, which are preset by software.
12
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
If Timer 2 is being clocked internally , the baud rate is:
fOSC
Baud Rate +
[32 [65536 * (RCAP2H, RCAP2L)]]
Where f
= Oscillator Frequency
OSC
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
fOSC
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
RCAP2H, RCAP2L + 65536 * ǒ
Ǔ
32 Baud Rate
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON
do not include the setting of the TR2 bit. Therefore, bit TR2 must be
set, separately, to turn the timer on. see Table 5 for set-up of Timer 2
as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Timer 2 Overflow Rate
Baud Rate +
16
Table 5. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 6. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
13
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Automatic Address Recognition
Slave 0
Slave 1
Slave 2
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
Automatic Address Recognition is a feature which allows the UART to
recognize certain addresses in the serial bit stream by using hardware
to make the comparisons. This feature saves a great deal of software
overhead by eliminating the need for the software to examine every
serial address which passes by the serial port. This feature is enabled
by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2
and mode 3, the Receive Interrupt flag (RI) will be automatically set
when the received byte contains either the “Given” address or the
“Broadcast” address. The 9 bit mode requires that the 9th information
bit is a 1 to indicate that the received information is an address and
not data. Automatic address recognition is shown in Figure 9.
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
14
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
(SMOD0 = 0/1)*
Symbol
FE
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
SM1
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
f /12
OSC
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**f = oscillator frequency
OSC
SU00043
Figure 7. SCON: Serial Port Control Register
15
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
REN
POF
TB8
GF1
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
–
PD
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU01191
Figure 8. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
16
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
There are four interrupt levels rather than two as on the 80C51. An
interrupt will be serviced as long as an interrupt of equal or higher
priority is not already being serviced. If an interrupt of equal or
higher level priority is being serviced, the new interrupt will wait until
it is finished before being serviced. If a lower priority level interrupt is
being serviced, it will be stopped and the new interrupt serviced.
When the new interrupt is finished, the lower priority level interrupt
that was stopped will be completed.
Interrupt Priority Structure
The 89C51/89C52/89C54/89C58 have a 6-source four-level
interrupt structure.
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
Table 7. Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
1
2
X0
T0
X1
T1
SP
T2
1
2
3
4
5
6
IE0
TP0
N (L) Y (T)
03H
0BH
13H
1BH
23H
2BH
Y
IE1
N (L) Y (T)
TF1
Y
N
N
RI, TI
TF2, EXF2
NOTES:
1. L = Level activated
2. T = Transition activated
7
6
5
4
3
2
1
0
IE (0A8H)
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
SU00571
Figure 10. IE Registers
17
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
7
6
5
4
3
2
1
0
IP (0B8H)
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL FUNCTION
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
PT2
PS
PT1
PX1
PT0
PX0
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00572
Figure 11. IP Registers
7
6
5
4
3
2
1
0
IPH (B7H)
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL FUNCTION
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
SU01058
Figure 12. IPH Registers
18
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
DPS
BIT0
AUXR1
Reduced EMI Mode
DPTR1
DPTR0
AUXR (8EH)
DPH
DPL
(83H)
(82H)
EXTERNAL
DATA
MEMORY
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
AO
SU00745A
AUXR.0
AO
Turns off ALE output.
Figure 13.
Dual DPTR
DPTR Instructions
The dual DPTR structure (see Figure 13) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxx00x0B
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
MOVX A, @ DPTR
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
AUXR1 (A2H)
7
–
6
–
5
–
4
–
3
2
0
1
–
0
MOVX @ DPTR , A
JMP @ A + DPTR
Move ACC to external RAM (16-bit
address)
GF2
DPS
Jump indirect relative to DPTR
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF0 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
19
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
0 to +70 or –40 to +85
–65 to +150
0 to +13.0
–0.5 to +6.5
15
UNIT
°C
°C
V
Storage temperature range
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1.5
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted.
SS
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C
CLOCK FREQUENCY
RANGE –f
SYMBOL
PARAMETER
UNIT
MIN
MAX
1/t
CLCL
Oscillator frequency: U (33MHz)
0
33
MHz
20
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C; 5 V ±10%; V = 0 V
SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
MIN
TYP
MAX
0.2 V –0.1
V
V
V
Input low voltage
4.5 V < V < 5.5 V
–0.5
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2 V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7 V
IH1
CC
V
OL
= 4.5 V
= 1.6 mA
CC
8
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
2
I
I
V
CC
= 4.5 V
7, 8
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
2
= 3.2 mA
OL
V
CC
= 4.5 V
= –30 µA
3
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
Output high voltage (port 0 in external bus mode),
V
CC
= 4.5 V
= –3.2 mA
V
OH1
CC
9
3
ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
V
V
= 0.4 V
= 2.0 V
–1
–75
–650
±10
µA
µA
µA
IL
IN
IN
6
TL
See Note 4
I
I
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 21):
Active mode (see Note 5)
See Note 5
CC
Idle mode (see Note 5)
Power-down mode or clock stopped (see Figure 25
for conditions)
T
= 0°C to 70°C
= –40°C to +85°C
3
100
125
µA
µA
amb
T
amb
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2 V.
IN
5. See Figures 22 through 25 for I test conditions and Figure 21 for I vs Freq.
CC
CC
Active mode:
Idle mode:
I
I
= (0.9 × FREQ. + 20)mA
= (0.37 × FREQ. +1.0)mA
CC(MAX)
CC(MAX)
6. This value applies to T
= 0°C to +70°C.
amb
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15 mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26 mA
71 mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
21
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5 V ±10%, V = 0V
CC SS
4
VARIABLE CLOCK
33MHz CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
14
Oscillator frequency
Speed versions:
3.5
33
CLCL
MHz
I;J;U (33 MHz)
3.5
21
5
33
t
t
t
t
t
t
t
t
t
t
t
14
14
14
14
14
14
14
14
14
14
14
ALE pulse width
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
t
–25
5
4t
3t
–65
55
30
CLCL
t
–25
5
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
45
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
CLCL
0
0
t
–25
5
CLCL
5t
–80
70
10
CLCL
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
16
RD pulse width
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
2t
–90
–28
60
CLCL
0
0
Data float after RD
32
90
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
–150
–165
CLCL
CLCL
9t
105
140
AVDV
LLWL
3t
–50
–75
3t
CLCL
+50
40
45
0
CLCL
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
t
t
–30
CLCL
CLCL
CLCL
–25
5
Data valid to WR high
RD low to address float
RD or WR high to ALE high
7t
–130
80
15, 16
15, 16
0
0
t
–25
t
+25
5
55
CLCL
CLCL
External Clock
t
t
t
t
18
18
18
18
High time
Low time
Rise time
Fall time
17
17
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
5
5
Shift Register
t
t
t
t
t
17
17
17
17
17
Serial port clock cycle time
12t
360
167
50
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
–80
0
0
10t
–133
167
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
4. Parts are guaranteed to operate down to 0 Hz.
22
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
D – Input data
H – Logic level high
W– WR signal
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 14. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 15. External Data Memory Read Cycle
23
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 16. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 17. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 18. External Clock Drive
24
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
V
–0.5
CC
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 19. AC Testing Input/Output
Figure 20. Float Waveform
60
50
40
Icc MAX. ACTIVE MODE
I
(mA)
CC
30
Icc MAX ACTIVE MODE (TYP.)
20
10
Icc MAX. IDLE MODE
Icc IDLE MODE (TYP.)
4
8
12
16
20
24
28
32
36
Frequency at XTAL1 (MHz)
SU01056
Figure 21. I vs. FREQ
CC
Valid only within frequency specifications of the device under test
25
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 22. I Test Condition, Active Mode
Figure 23. I Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 24. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
V
RST
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 25. I Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
26
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Security
The security feature protects against software piracy and prevents
the contents of the FLASH from being read. The Security Lock bits
are located in FLASH. The 89C51/89C52/89C54/89C58 has 3
programmable security lock bits that will provide different levels of
protection for the on-chip code and data (see Table 8). Unlike the
ROM and OTP versions, the security lock bits are independent. LB3
includes the security protection of LB1.
Table 8.
1
SECURITY LOCK BITS
PROTECTION DESCRIPTION
Level
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory.
LB1
LB2
LB3
Program verification is disabled
External execution is disabled.
NOTE:
1. The security lock bits are independent.
27
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
28
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
29
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
QFP44: plastic quad flat package; 44 leads
30
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
NOTES
31
1999 Oct 27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-99
Document order number:
9397–750–06613
Philips
Semiconductors
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Information as of 2000-08-23
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Discrete semiconductors
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89C51; 89C52; 89C54; 89C58; 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash
Clocks and Watches
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subscribe to eNews.
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The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH program memory that is parallel programmable. For devices that are serial
programmable (In System Programmable (ISP) with a boot loader), see the 89C51RC+/89C51RD+ datasheet.
PC/PC-peripherals
Both families are Single-Chip 8-bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set as the 80C51.
Cross reference
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
Features
l 80C51 Central Processing Unit
l On-chip FLASH Program Memory
l Speed up to 33 MHz
l Full static operation
l RAM expandable externally to 64 k bytes
l 4 level priority interrupt
l 6 interrupt sources
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89C51; 89C52; 89C54;
89C58
l Four 8-bit I/O ports
l Full-duplex enhanced UART
¡ Framing error detection
¡ Automatic address recognition
l Power control modes
89C51; 89C52; 89C54;
89C58
¡ Clock can be stopped and resumed
¡ Idle mode
¡ Power down mode
l Programmable clock out
l Second DPTR register
l Asynchronous port reset
l Low EMI (inhibit ALE)
l 3 16-bit timers
l Wake up from power down by an external interrupt
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
89C51; 89C52; 89C54; 80C51 8-bit microcontroller family
89C58 4K/8K/16K/32K Flash
Title
Datasheet
Download
27-Oct-99
Product
Specification
32
212
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
P89C51UBAA P89C51UBAA
P89C51UBPN P89C51UBPN
P89C51UFPN P89C51UFPN
P89C52UBAA P89C52UBAA
9352 626 02512 Standard Marking * Tube Dry Pack SOT187 Full production
9352 626 05112 Standard Marking * Tube
9352 626 06112 Standard Marking * Tube
SOT129 Full production
SOT129 Development
9352 625 66512 Standard Marking * Tube Dry Pack SOT187 Full production
Standard Marking * Tray Dry Pack,
P89C52UBBB P89C52UBBB
9352 625 71557
SOT307 Full production
Bakeable, Multiple
P89C52UBPN P89C52UBPN
P89C54UBAA P89C54UBAA
P89C54UBPN P89C54UBPN
P89C54UFAA P89C54UFAA
9352 625 68112 Standard Marking * Tube
SOT129 Full production
9352 626 07512 Standard Marking * Tube Dry Pack SOT187 Full production
9352 626 08112 Standard Marking * Tube SOT129 Full production
9352 626 12512 Standard Marking * Tube Dry Pack SOT187 Development
Standard Marking * Tray Dry Pack,
P89C54UFBB
9352 626 11557
SOT187 Development
-
-
Bakeable, Multiple
P89C54UFPN P89C54UFPN
P89C58UBAA P89C58UBAA
P89C58UBPN P89C58UBPN
P89C58UFAA P89C58UFAA
9352 626 09112 Standard Marking * Tube
SOT129 Development
9352 625 74512 Standard Marking * Tube Dry Pack SOT187 Full production
9352 625 72112 Standard Marking * Tube SOT129 Full production
9352 625 75512 Standard Marking * Tube Dry Pack SOT187 Development
Standard Marking * Tray Dry Pack,
P89C58UFBB
9352 625 77557
SOT307 Development
SOT129 Development
Bakeable, Multiple
P89C58UFPN P89C58UFPN
9352 625 73112 Standard Marking * Tube
Please read information about some discontinued variants of this product.
Find similar products:
89C51; 89C52; 89C54; 89C58 links to the similar products page containing an overview of products that are similar in function or
related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant
selection guides and products from the same functional category.
Copyright © 2000
Royal Philips Electronics
All rights reserved.
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