935269132118_技术文档

INTEGRATED CIRCUITS

PCKV857

70–190 MHz differential 1:10 clock driver

Product data

2002 Sep 13

Supersedes data of 2001 Dec 03

Philips

Semiconductors

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

FEATURES

PIN CONFIGURATION

• ESD classification testing is done to JEDEC Standard JESD22.

Protection exceeds 2000 V to HBM per method A114.

1

2

3

4

5

6

48

47

46

GND

Y

0

5

• Latch-up testing is done to JEDEC Standard JESD78 which

exceeds 100 mA

45

44

V

Y

DDQ

6

• Optimized for clock distribution in DDR (Double Data Rate)

Y

1

SDRAM applications as per JEDEC specifications

Y

1

6

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

GND

7

GND

• 1-to-10 differential clock distribution

8

9

• Very low skew (< 100 ps) and jitter (< 100 ps)

• Operation from 2.2 V to 2.7 V AV and 2.3 V to 2.7 V V

Y

7

Y

2

Y

V

2 10

7

DD

DDQ

V

11

DDQ

• SSTL_2 interface clock inputs and outputs

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

PWRDWN

DDQ 12

CLK 13

CLK 14

FB

IN

V

DDQ

15

16

17

18

19

20

21

22

23

24

DDQ

AV

DD

FB

OUT

FB

AGND

GND

Y

8

Y

3

• Full DDR solution provided when used with SSTL16877 or

Y

3

Y

8

SSTV16857

V

DDQ

• Designed for DDR 200 and 266 DIMM applications

Y

9

Y

4

27

26

25

Y

4

Y

9

• Available in TSSOP-48, TVSOP-48, and VFBGA56

GND

(8 no connects) packages

SW00691

DESCRIPTION

The PCKV857 is a high-performance, low-skew, low-jitter zero delay

buffer designed for 2.5 V V and 2.5 V AV operation and

DD

differential data input and output levels.

The PCKV857 is a zero delay buffer that distributes a differential

clock input pair (CLK, CLK) to ten differential pairs of clock outputs

(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs

(FB , FB

OUT

) . The clock outputs are controlled by the clock

OUT

inputs (CLK, CLK), the feedback clocks (FB , FB ), and the analog

IN

power input (AV ). When PWRDWN is high, the outputs switch in

DD

phase and frequency with CLK. When PWRDWN is low, all outputs

are disabled to high impedance state (3-State), and the PLL is shut

down (low power mode). The device also enters the low power

mode when the input frequency falls below 20 MHz. An input

frequency detection circuit will detect the low frequency condition

and after applying a > 20 MHz input signal, the detection circuit

turns on the PLL again and enables the outputs.

When AV is grounded, the PLL is turned off and bypassed for test

DD

purposes. The PCKV857 is also able to track spread spectrum

clocking for reduced EMI.

The PCKV857 is characterized for operation from 0 to +70 °C.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

0 to +70 °C

ORDER CODE

PCKV857DGG

PCKV857DGV

PCKV857EV

DRAWING NUMBER

SOT362-1

48-Pin Plastic TSSOP

48-Pin Plastic TSSOP (TVSOP)

0 to +70 °C

SOT480-1

1

56-ball Plastic VFBGA

0 to +70 °C

SOT702-1

NOTE:

1. 48 balls are connected, 8 balls are no-connects.

2

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

PIN DESCRIPTION

PINS

SYMBOL

DESCRIPTION

1, 7, 8, 18, 24, 25, 31, 41, 42, 48

GND

SSTL_2 ground pins

2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,

30, 32, 33, 39, 40, 43, 44, 46, 47

Y , Y , FB

, FB

OUT OUT

SSTL_2 differential outputs

n

4, 11, 12, 15, 21, 28, 34, 38, 46

V

SSTL_2 power pins

SSTL_2 differential inputs

Analog power

DDQ

13, 14, 35, 36

CLK , CLK , FB , FB

IN IN IN IN

16

17

37

AV

DD

AGND

Analog ground

PWRDWN

Power-down control input

BALL CONFIGURATION

1

2

3

4

5

6

A

B

GND

NC

GND

Y

0

Y

0

V

Y

5

Y

5

DD

C

D

Y

GND

Y

1

2

1

6

7

GND

Y

GND

2

7

V

PWRDWN

E

F

DD

CLK

FB

IN

AV

DD

AGND

V

FB

OUT

G

DD

OUT

Y

3

Y

3

GND

Y

H

J

8

9

8

9

Y

4

Y

4

V

Y

DD

GND

NC

GND

K

SW00951

3

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

FUNCTION TABLE

INPUTS

OUTPUTS

PLL ON/OFF

PWRDWN

CLK

Y

n

Y

n

FB

OUT

1

L

H

Z

OFF

ON

1

H

L

Z

L

Z

H

L

Z

H

L

H

L

H

Z

H

L

ON

2

1

X

< 20 MHz

Z

OFF

NOTES:

H = HIGH voltage level

L = LOW voltage level

Z = high impedance OFF-state

X = don’t care

1. Subject to change. May cause conflict with FB pins.

IN

2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.

BLOCK DIAGRAM

37 – PWRDWN

3 – Y

2 – Y

0

5 – Y

6 – Y

1

10 – Y

2

9 – Y

2

20 – Y

19 – Y

3

22 – Y

23 – Y

4

13 – CLK

14 – CLK

46 – Y

47 – Y

5

PLL

36 – FB

35 – FB

IN

44 – Y

43 – Y

6

16 – AV

DD

39 – Y

40 – Y

7

29 – Y

30 – Y

8

27 – Y

28 – Y

9

32 – FB

33 – FB

OUT

SW00692

4

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

1

ABSOLUTE MAXIMUM RATINGS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MAX

MIN

0.5

–0.5

—

V

DDQ

Supply voltage range

3.6

V

AV

Supply voltage range

DD

V

I

Input voltage range

see Notes 2 and 3

V

DDQ

V

DDQ

+ 0.5

V

O

Output voltage range

+ 0.5

V

I

IK

Input clamp current

V < 0 or V >V

±50

mA

°C

I

DDQ

I

Output clamp current

V

< 0 or V >V

—

±50

OK

O

DDQ

I

O

Continuous output current

Continuous current to GND or V

Storage temperature range

V

O

= 0 to V

—

±100

+150

DDQ

T

stg

–65

NOTES:

1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 3.6 V maximum.

1

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

2.3

TYP

—

MAX

2.7

V

DDQ

Supply voltage range

V

AV

Supply voltage range

Low level input voltage

2.2

—

2.7

DD

CLK, CLK,

FB , FB

—

V

/2 − 0.18

0.7

DDQ

IN

V

IL

V

PWRDWN

−0.3

CLK, CLK,

V

/2 + 0.18

DDQ

—

FB , FB

IN

V

High level input voltage

IH

ID

PWRDWN

1.7

—

V

+ 0.3

DDQ

DC input signal voltage

Note 2

Note 3

Note 4

−0.3

0.36

0.7

V

DDQ

V

DC differential input signal voltage

AC differential input signal voltage

Output differential cross-voltage

Input differential cross-voltage

High-level output current

CLK, FB

V

+ 0.6

IN

DDQ

V

OX

V

/2 − 0.2

DDQ

V /2

DDQ

V

/2 + 0.2

DDQ

/2 + 0.2

DDQ

V

IX

/2 − 0.2

DDQ

—

V

I

—

1

—

−12

12

4

mA

V/ns

°C

OH

I

OL

Low-level output current

SR

Input slew rate

T

amb

Operating free-air temperature

0

70

NOTES:

1. Unused inputs must be held high or low to prevent them from floating.

2. DC input signal voltage specifies the allowable DC execution of differential input.

3. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and

VCP is the complementary input level.

4. Differential cross-point voltage is expected to track variations of V and is the voltage at which the differential signals must be crossing.

CC

5

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

LIMITS

TYP

—

SYMBOL

PARAMETER

Input voltage, all inputs

High-level output voltage

TEST CONDITIONS

= 2.3 V, I = –18 mA

UNIT

MAX

MIN

V

IK

V

—

−1.2

—

V

DDQ

I

V

= min to max, I = –1 mA

V − 0.1

DDQ

—

DDQ

OH

V

OH

V

= 2.3 V, I = –12 mA

1.7

—

V

DDQ

OH

V

= min to max, I = 1 mA

—

0.1

0.6

±10

V

DDQ

OL

V

OL

Low-level output voltage

V

= 2.3 V, I = 12 mA

—

V

DDQ

OL

I

Input current

V

= 2.7 V, V = 0 V to 2.7 V

—

µA

DDQ

I

High-impedance-state output current

V

= 2.7 V, V = V or GND

DDQ

—

OZ

DDQ

O

CLK and CLK = 0 MHz,

PWRDWN = low;

I

Power-down current on V

+ AV

DD

—

30

100

µA

DDPD

DDQ

Σ of I and AI

DD

I

Dynamic current on V

f

= 67 MHz to 190 MHz

—

2

200

8

300

10

3

mA

pF

DD

DDQ

O

AI

Supply current on AV

DD

O

C

Input capacitance

V

= 2.5 V, V = V or GND

2.8

I

CC

I

CC

NOTE:

1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.

2. All typical values are at respective nominal V

.

DDQ

3. Differential cross-point voltage is expected to track variations of V

and is the voltage at which the differential signals must be crossing.

DDQ

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature.

SYMBOL

PARAMETER

MIN

60

MAX

190

60

UNIT

MHz

%

f

Operating clock frequency

Input clock duty cycle

CK

40

1

Stabilization time

100

—

µs

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.

6

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

AC CHARACTERISTICS

GND = 0 V; t = t ≤ 2.5 ns; C = 50 pF; R = 1 kΩ

r

f

L

LIMITS

TYP

0

SYMBOL

PARAMETER

WAVEFORM

CONDITION

UNIT

MAX

MIN

–150

—

t

Static phase offset

Output clock skew

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

150

75

2

ps

(O)

t

—

SK(O)

t

Output clock skew rate

Jitter (period)

1

—

V/ns

ps

SLR(O)

t

f

= 67 MHz to 200 MHz

–75

–100

—

75

100

JIT(PER)

O

t

Jitter (cycle-to-cycle)

Half-period jitter

—

ps

JIT(CC)

O

t

—

ps

JIT(HPER)

1

Low to high level

propagation delay

Test mode/CLK to any

output

t

—

3.7

—

ns

PLH

High to low level

propagation delay

Test mode/CLK to any

output

1

t

PHL

NOTE:

1. Refers to transition of noninverting output.

FRONT SIDE

SSTL16877

or

SSTL16877

PCKV857

or

SSTV16857

The PLL clock distribution device and SSTL registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

SW00688

7

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

AC WAVEFORMS

CLK

FB

IN

t

(O)n + 1

(O)n

n =N

t

Σ₁

(O)n

t

=

(N is a large number of samples)

SW00882

(O)

N

Figure 1. Static phase offset

Yx

Yx, FB

OUT

t

sk(O)

SW00883

Figure 2. Output skew

80%

V

, V

ID OD

20%

CLOCK INPUTS

AND OUTPUTS

t

, t

t

, t

SLR(I) SLR(O)

SW00886

Figure 3. Input and output slew rates

8

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

Yx, FB

OUT

t

cycle n

Yx, FB

OUT

1

f

O

1

t

= t

–

cycle n

JIT(PER)

f

O

SW00884

Figure 4. Period jitter

t

cycle n + 1

cycle n

Yx, FB

OUT

t

= t

– t

cycle n cycle n+1

JIT(CC)

SW00881

Figure 5. Cycle-to-cycle jitter

Yx, FB

OUT

Yx, FB

t

half period n

half period n + 1

1

f

O

1

2*f

t

= t

–

half period n

JIT(HPER)

O

SW00885

Figure 6. Half-period jitter

skew

ANY TWO OUTPUTS

SW00396

Figure 7. Skew between any two outputs.

9

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

t

1

t

2

t

1

45%

v

v 55%

t

) t

1

2

SW00397

Figure 8. Duty cycle limits and measurement

TEST CIRCUIT

V

/2

DD

PCKV857

SCOPE

–V /2

DD

C = 14 pf

Z = 60 Ω

R = 10 Ω

Z = 50 Ω

R = 50 Ω

V

TT

Z = 60 Ω

R = 10 Ω

Z = 50 Ω

C = 14 pf

–V /2

R = 50 Ω

DD

V

TT

NOTE: V = GND

TT

–V /2

DD

SW00880

Figure 9. Output load test circuit

10

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

11

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

TSSOP48: plastic thin shrink small outline package; 48 leads;

body width 4.4 mm; lead pitch 0.4 mm

SOT480-1

12

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls;

body 4.5 x 7 x 0.65 mm

SOT702-1

13

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

REVISION HISTORY

Rev

Date

Description

_4

2002 Sep 06

Product data (9397 750 10343); fourth version supersedes Product data

2001 Dec 03.

Engineering Change Notice 853-2242 28874 (2002 Sep 09).

Modifications:

Add new package option (VFBGA) to existing product data sheet.

_3

2001 Dec 03

Product data (9397 750 09244); third version

14

2002 Sep 13

Philips Semiconductors

Product data

70–190 MHz differential 1:10 clock driver

PCKV857

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 2002

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 09-02

Document order number:

9397 750 10343

Philips

Semiconductors

15

2002 Sep 13


型号：	935269132118
厂家：	NXP
描述：	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 驱动光电二极管输出元件逻辑集成电路
文件：	总15页 (文件大小：113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935269132118 [NXP]

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