935269144115 [NXP]

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5, Power Management Circuit;
935269144115
型号: 935269144115
厂家: NXP    NXP
描述:

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5, Power Management Circuit

光电二极管
文件: 总12页 (文件大小:122K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
SA56614-XX  
CMOS system reset  
Product data  
2002 Sep 13  
Supersedes data of 2001 Jun 19  
Philips  
Semiconductors  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
GENERAL DESCRIPTION  
The SA56614-XX is a CMOS device designed to generate a reset  
signal for a variety of microprocessor and logic systems. Accurate  
reset signals are generated during momentary power interruptions,  
or whenever power supply voltages sag to intolerable levels.  
Several reset threshold versions of the device are available. A  
totem-pole output topology is incorporated to provide both current  
source and sink capability to the user.  
SA56614-XX is available in the SOT23-5 surface mount package.  
FEATURES  
APPLICATIONS  
10 V maximum operating voltage  
Microcomputer systems  
DC  
Low operating voltage (0.95 V)  
Totem pole CMOS output  
Logic systems  
Battery monitoring systems  
Back-up power supply circuits  
Voltage detection circuits  
Offered in reset thresholds of  
1.85, 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 V  
DC  
Available in SOT23-5 surface mount package  
SIMPLIFIED SYSTEM DIAGRAM  
V
DD  
V
2
DD  
V
DD  
NE56614-XX  
R
CPU  
V
OUT  
1
RESET  
V
REF  
R
R
V
SS  
3
V
SS  
V
SS  
SL01343  
Figure 1. Simplified system diagram.  
2
2002 Sep 13  
853–2248 28914  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
TEMPERATURE  
RANGE  
NAME  
DESCRIPTION  
SA56614-XXGW SOT23-5, SOT25, SO5  
plastic small outline package; 5 leads (see dimensional drawing)  
–40 to +85 °C  
NOTE:  
The device has twelve detection voltage options, indicated by the  
XX on the ‘Type number’.  
XX  
185  
20  
27  
28  
29  
30  
31  
42  
43  
44  
45  
46  
47  
DETECT VOLTAGE (Typical)  
1.85 V  
2.0 V  
2.7 V  
2.8 V  
2.9 V  
3.0 V  
3.1 V  
4.2 V  
4.3 V  
4.4 V  
4.5 V  
4.6 V  
4.7 V  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN  
1
SYMBOL  
DESCRIPTION  
Reset HIGH output.  
V
V
V
OUT  
DD  
V
1
2
3
5
4
N/C  
N/C  
OUT  
2
Positive supply.  
3
Ground. Negative supply.  
No connection.  
SS  
V
SA56614-XX  
DD  
4
N/C  
N/C  
5
No connection.  
V
SS  
SL01360  
Figure 2. Pin configuration.  
MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
MIN.  
MAX.  
UNIT  
V
V
V
Power supply voltage  
Output voltage  
12  
DD  
OUT  
OUT  
V
– 0.3  
V
+ 0.3  
V
SS  
DD  
I
Output current  
50  
mA  
°C  
T
Operating temperature  
Storage temperature  
Power dissipation  
–40  
–40  
85  
oper  
T
stg  
125  
150  
°C  
P
mW  
3
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
DC ELECTRICAL CHARACTERISTICS  
Characteristics measured with T  
= 25 °C, unless otherwise specified.  
amb  
SYMBOL  
PARAMETER  
CONDITIONS  
TEST  
CIRCUIT  
MIN.  
– 2%  
TYP.  
MAX.  
+ 2%  
UNIT  
V
S
Reset detection threshold  
Hysteresis  
V
V
S
V
S
V
V
S
V  
V
DD  
= 0 V V + 1.0 V 0 V  
V
× 0.03  
V
× 0.05  
V × 0.08  
S
S
S
S
S
1
V /T  
S
Threshold voltage temperature  
coefficient  
–40 °C T  
+85 °C  
±0.01  
%/°C  
Fig. 16  
amb  
I
I
Supply current  
V
= V + 1.0 V  
0.25  
1.0  
0.1  
µA  
µA  
CC  
DD  
S
I
leakage current when OFF  
V
DD  
= V = 10 V  
3
OH  
DS  
DS  
Fig. 18  
I
I
N-channel I output sink current 1  
V
V
= 1.2 V; V = 0.5 V  
–0.23  
–1.6  
0.50  
–3.7  
mA  
mA  
NDS1  
DS  
DD  
DS  
N-channel I output sink current 2  
= 0.5 V; V = 2.4 V  
DD  
NDS2  
DS  
DS  
2
(for V > 2.6 V)  
S
Fig. 17  
I
I
I
I
N-channel I output sink current 3  
V
DS  
V
DS  
V
DS  
V
DS  
= 0.5 V; V = 3.6 V  
–3.2  
0.36  
0.46  
0.59  
–7.00  
0.62  
0.75  
0.96  
mA  
mA  
mA  
mA  
NDS3  
PDS1  
PDS2  
PDS3  
DS  
DD  
(for V > 3.9 V)  
S
P-channel I output source current 1  
= 0.5 V; V = 4.8 V  
DS  
DD  
(for V < 4.0 V)  
S
P-channel I output source current 2  
= 0.5 V; V = 6.0 V  
3
DS  
DD  
(for 4.0 V < V < 5.7 V)  
Fig. 18  
S
P-channel I output source current 3  
= 0.5 V; V = 8.4 V  
DS  
DD  
(for V 5.7 V)  
S
4
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
TYPICAL PERFORMANCE CURVES  
0.50  
+0.20  
+0.15  
+0.10  
+0.05  
V
= V + 1.0 V  
S
V
V
FALLING  
NORMALIZED TO 25 °C  
DD  
CC  
0.45  
0.40  
0.35  
NORMALIZED TO 25 °C  
S
V
S
0.30  
0.25  
–0.05  
–0.10  
–0.15  
–0.20  
0.20  
0.15  
0.10  
–50  
–25  
0
25  
50  
75  
100  
125  
–50  
–25  
0
25  
50  
75  
100  
125  
T , TEMPERATURE (°C)  
amb  
T , TEMPERATURE (°C)  
amb  
SL01344  
SL01345  
Figure 3. Supply current versus temperature.  
Figure 4. Detection threshold versus temperature.  
200  
150  
100  
50  
3.0  
2.5  
V
= V – V  
V
= 0.5 V  
DS  
S(HYS)  
SH  
SL  
(V RISING – V FALLING)  
CC  
CC  
2.0  
N-CHANNEL  
1.5  
1.0  
0.5  
0
P-CHANNEL  
0
–50  
–25  
0
25  
50  
75  
100  
125  
–50  
–25  
0
25  
50  
75  
100  
125  
T , TEMPERATURE (°C)  
amb  
T , TEMPERATURE (°C)  
amb  
SL01346  
SL01347  
Figure 5. Detection hysteresis versus temperature.  
Figure 6. Output FET current versus temperature.  
0.6  
0.5  
0.4  
5.0  
T
= 25 °C  
T
AMB  
= 25 °C  
AMB  
TYPICAL CHARACTERISTIC.  
DETECTION AND RELEASE  
VOLTAGE POINTS DEPEND ON  
THE SPECIFIC DEVICE TYPE.  
4.0  
3.0  
2.0  
V
S(HYS)  
0.3  
0.2  
1.0  
0
0.1  
0
0
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
9.0  
10  
0
1.0  
2 .0  
3.0  
4.0  
5.0  
6.0  
V
, SUPPLY VOLTAGE (V)  
V
DD  
, SUPPLY VOLTAGE (V)  
DD  
SL01348  
SL01349  
Figure 7. Output voltage versus supply voltage.  
Figure 8. Supply current versus supply voltage.  
5
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
5
10  
V
+ 2.0 V  
T
AMB  
= 25 °C  
S
(SEE FIGURES 10 AND 11)  
INPUT SIGNAL  
4
3
1.2 V  
10  
10  
V
SS  
t
t
PHL  
7.0 V  
3.5 V  
2
1
10  
10  
OUTPUT SIGNAL  
PLH  
V
SS  
t
PHL  
–5  
–4  
–3  
–2  
–1  
10  
10  
10  
10  
10  
t
PLH  
C , OUTPUT LOAD CAPACITANCE (µF)  
L
SL01350  
SL01351  
Figure 9. Propagation delay versus output load C.  
Figure 10. Propagation delay measurements.  
V
DD  
INPUT  
SIGNAL  
OUTPUT  
SA56614-XX  
C
= 10 pF to 0.1 µF  
L
V
SS  
V
SS  
SL01352  
Figure 11. Propagation delay measurement circuit.  
6
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
TECHNICAL DESCRIPTION  
The SA56614-XX is a CMOS device designed to monitor the  
system’s power source and provide a system reset function in the  
event the supply voltage sags below an acceptable level for the  
system to reliably operate. The SA56614 generates a compatible  
reset signal for a wide variety of microprocessor and logic systems.  
The reset threshold incorporates a typical hysteresis of  
LOW (below V ) and the output HIGH goes to a HIGH voltage state  
S
when the input is HIGH (above V ).  
S
The low side N-Channel FET (TR ) establishes threshold hysteresis  
3
by turning ON whenever the threshold comparator’s output goes to  
a HIGH state (when V sags to or below the threshold level). TR ’s  
DD  
3
turning ON causes additional current to flow through resistors R ,  
1
(V × 0.05) volts to prevent erratic resets from being generated.  
S
and R causing the inverting input of the threshold comparator to be  
2
The SA56614 operates at very low supply currents, typically  
0.25 µA, while offering a high precision of threshold detection (±2%).  
pulled even lower. For the comparator to reverse its output polarity  
and turn OFF TR , the V source voltage must overcome this  
3
DD  
The output of the SA56614 incorporates an active Totem-Pole  
output topology comprised of complimentary P-Channel and  
N-Channel FETs. A P-Channel FET is on the high supply side and  
additional pull-down voltage present on the comparator’s inverting  
input. The differential voltage required to do this establishes the  
hysteresis voltage of the sensed threshold voltage. Typically it is  
when ON pulls the output to or near the V supply voltage from  
(V × 0.05) volts.  
S
DD  
which output source current can be obtained. A complimentary  
N-Channel FET is on the low or ground side, and actively pulls the  
output LOW or to ground with the capability of sinking current into  
the output. Both devices supply system reset signals. The user  
should keep in mind, when connecting the SA56614 to a system, the  
effect of supplying source current from the output of the SA56614 on  
the system. This is of particular importance where the SA56614 is  
operated from a different supply source than the rest of the system.  
When the V voltage sags and is at or below the Detection  
DD  
Threshold (V ), the device will assert a Reset LOW output at or  
SL  
very near ground potential. As the V voltage rises from  
DD  
(V < V ) to V or higher, the reset is released and the output  
DD  
SL  
SH  
follows V . Conversely, decreases in V from (V > V ) to V  
SL  
DD  
DD  
DD  
SL  
or lower cause the output to be pulled to ground.  
Hysteresis Voltage = Release Voltage – Detection Threshold Voltage  
Figure 12 is a functional block diagram of the SA56614. The internal  
V = V – V  
HYS SH SL  
reference source voltage (V  
) is typically 0.8 V over the operating  
REF  
where:  
temperature range. The reference voltage is connected to the  
non-inverting input of the threshold comparator while the inverting  
input monitors the supply voltage through a resistor divider network  
V
SH  
V
SL  
= V + V  
V (R + R ) / R  
REF 1 2 2  
SL  
HYS  
= V  
(R + R + R ) / (R + R )  
REF 1 2 3 2 3  
made up of R , R , and R . The output of the threshold comparator  
1
2
3
drives the totem-pole output stage of the device.  
When V drops below the minimum operating voltage, typically  
DD  
less than 0.95 volts, the output is undefined and output reset low  
When the supply voltage sags to the threshold detection voltage, the  
resistor divider network supplies a voltage to the inverting input of  
assertion is not guaranteed. At this level of V the output will try to  
DD  
rise to V  
.
DD  
the threshold comparator which is less than that of V  
, causing  
REF  
the output of the comparator to adopt a HIGH output state. This  
causes the high side P-Channel FET of the Totem-Pole output stage  
to turn OFF while simultaneously turning the low side N-Channel  
FET from OFF to an active ON state, pulling the output to a LOW  
voltage state. The device adheres to a true input/output logic  
protocol. The output goes to a LOW voltage state when input is  
The V  
voltage is typically 0.8 V. The devices are fabricated using  
REF  
a high resistance CMOS process and utilize high resistance R , R ,  
1
2
and R values requiring very small amounts of current. This  
3
combination achieves very efficient low power performance over the  
full operating temperature.  
V
2
DD  
NE56614-XX  
R
1
TR  
TR  
1
2
V
OUT  
1
V
REF  
R
R
R
2
3
TR  
3
3
V
SS  
SL01353  
Figure 12. Functional diagram  
7
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
TIMING DIAGRAM  
The timing diagram shown in Figure 13 depicts the operation of the  
device. Letters A-J on the TIME axis indicate specific events.  
D-E: Between ‘D’ and ‘E’, V starts rising.  
DD  
E: At ‘E’, V rises to the V . Once again, the device releases  
DD  
SH  
A: At ‘A’, V begins to increase. Also the V  
voltage initially  
the hold on the V  
reset. The Reset output V  
tracks V as it  
OUT DD  
DD  
OUT  
OUT  
increases but abruptly decreases when V reaches the level  
rises above V  
.
SH  
DD  
(approximately 0.8 V) that activates the internal bias circuitry and  
RESET is asserted.  
F-G: At ‘F’, V is above the upper threshold and begins to fall,  
DD  
causing V  
to follow it. As long as V remains above the V  
,
OUT  
DD  
SH  
B: At ‘B’, V reaches the threshold level of V . At this point the  
no reset signal will be triggered. Before V falls to the V , it  
DD SH  
DD  
SH  
device releases the hold on the V  
reset. The Reset output V  
begins to rise, causing V to follow it. At ‘G’, V returns to  
OUT DD  
OUT  
OUT  
tracks V as it rises above V (assuming the reset pull-up resistor  
normal.  
DD  
SH  
R
is connected to V ). In a microprocessor based system these  
DD  
PU  
H: At event ‘H’ V falls until the V undervoltage detection  
DD  
SL  
events release the reset from the microprocessor, allowing the  
microprocessor to function normally.  
threshold point is reached. At this level, a RESET signal is  
generated and V goes LOW.  
OUT  
C-D: At ‘C’, V begins to fall, causing V  
to follow. V  
DD  
DD  
OUT  
J: At ‘J’ the V voltage has decreased until normal internal circuit  
DD  
continues to fall until the V undervoltage detection threshold is  
SL  
bias is unable to maintain a V  
reset. As a result, V may rise to  
DD  
OUT  
reached at ‘D’. This causes a reset signal to be generated (V  
Reset goes LOW).  
OUT  
less than 0.8 V. As V decreases further, V  
reset also  
DD  
OUT  
decreases to zero.  
V  
S
V
SH  
V
SL  
V
DD  
0
V
OUT  
0
A
B
C
D
E
F
G
H
J
TIME  
SL01354  
Figure 13. Timing diagram.  
8
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
APPLICATION INFORMATION  
V
DD  
CURRENT CHANGES  
R
V
11  
DD  
CPU  
RESET  
A
V
DD  
V
OUT  
SA56614-XX  
V
SUPPLY  
OUTPUT  
SA56614-XX  
R
12  
V
SS  
V
SS  
GND  
SL01355  
SL01356  
Figure 14. Conventional reset application  
Figure 15. High impedance supply operating problems  
Small changes in supply current will occur when the SA56614  
asserts or releases a reset. In some cases this can cause  
oscillations of the device. This can present a problem, particularly  
Significant voltage variations of V may occur when the device is  
operated from high impedance power sources. When the device  
DD  
asserts or releases a reset, V variations are produced as a result  
DD  
where high impedance V sources are employed. Figure 15 shows  
of the voltage drop developed across R due to the current  
11  
DD  
how this may occur.  
variations through the resistor R (representing the supply  
11  
impedance). If the V variations are large, such that they exceed  
DD  
the Detection Hysteresis, the output of the device can oscillate from  
a HIGH state to a LOW state. The user should avoid using high  
impedance V sources to prevent such situations.  
DD  
TEST CIRCUITS  
A
V
V
DD  
DD  
V
V
DS  
V
V
V
V
A
DD  
DD  
SA56614-XX  
SA56614-XX  
V
V
OUT  
OUT  
V
V
SS  
SS  
SL01357  
SL01359  
Figure 16. Test Circuit 1  
Figure 18. Test Circuit 3  
V
DD  
V
V
A
DD  
SA56614-XX  
V
OUT  
V
V
DS  
V
SS  
SL01358  
Figure 17. Test Circuit 2  
9
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
PACKING METHOD  
GUARD  
BAND  
TAPE  
TAPE DETAIL  
REEL  
ASSEMBLY  
COVER TAPE  
CARRIER TAPE  
BARCODE  
LABEL  
BOX  
SL01305  
Figure 19. Tape and reel packing method  
10  
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm  
1.2  
1.0  
0.55  
0.41  
0.22  
0.08  
3.00  
2.70  
1.70  
1.50  
0.55  
0.35  
0.025  
1.35  
11  
2002 Sep 13  
Philips Semiconductors  
Product data  
CMOS system reset  
SA56614-XX  
Data sheet status  
Product  
status  
Definitions  
[1]  
Data sheet status  
[2]  
Objective data  
Development  
Qualification  
This data sheet contains data from the objective specification for product development.  
Philips Semiconductors reserves the right to change the specification in any manner without notice.  
Preliminary data  
Product data  
This data sheet contains data from the preliminary specification. Supplementary data will be  
published at a later date. Philips Semiconductors reserves the right to change the specification  
without notice, in order to improve the design and supply the best possible product.  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply.  
Changes will be communicated according to the Customer Product/Process Change Notification  
(CPCN) procedure SNW-SQ-650A.  
[1] Please consult the most recently issued data sheet before initiating or completing a design.  
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL  
http://www.semiconductors.philips.com.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Koninklijke Philips Electronics N.V. 2002  
Contact information  
All rights reserved. Printed in U.S.A.  
For additional information please visit  
http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
Date of release: 09-02  
9397 750 10401  
For sales offices addresses send e-mail to:  
sales.addresses@www.semiconductors.philips.com.  
Document order number:  
Philips  
Semiconductors  

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IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269153115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269154115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5, Power Management Circuit
NXP

935269155115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269161115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269164115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269168115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP

935269171115

IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, PLASTIC, SOT-23, SO-5, Power Management Circuit
NXP