935271209112 [NXP]

IC 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24, Multiplexer/Demultiplexer;


型号：	935271209112
厂家：	NXP
描述：	IC 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24, Multiplexer/Demultiplexer 光电二极管输出元件逻辑集成电路
文件：	总14页 (文件大小：112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

PCA9548

8-channel I²C switch with reset

Product data

2002 Feb 19

File under Inegrated Circuits — ICL03

Philips

Semiconductors

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

PIN CONFIGURATION

SDA

SCL

RESET

21 A2

SC0

SC7

SD1

SC1

SD7

SC6

FEATURES

• 1-of-8 bi-directional translating switches

SD6

SC5

SD2

SC2

• I C interface logic; compatible with SMBus standards

• Active Low Reset Input

SD3

SC3

SD5

SC4

• 3 address pins allowing up to 8 devices on the I C bus

SD4

• Channel selection via I C bus, in any combination

• Power up with all switch channels deselected

SW00361

• Low Rds switches

Figure 1. Pin configuration

• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and

5 V buses

PIN DESCRIPTION

• No glitch on power-up

• Supports hot insertion

• Low stand-by current

• Operating power supply voltage range of 2.3 V to 5.5 V

• 5 V tolerant Inputs

NUMBER

SYMBOL

FUNCTION

Address input 0

Address input 1

RESET

SD0

SC0

SD1

SC1

SD2

SC2

SD3

SC3

Active LOW reset input

Serial data output 0

Serial clock output 1

Serial data output 1

Serial clock output 2

Serial data output 2

Serial clock output 3

Serial data output 3

Serial clock output 4

Supply ground

• 0 to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

150 V MM per JESD22-A115 and 1000 V per JESD22-C101

• Latchup testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Package Offer: SO24, TSSOP24

DESCRIPTION

The PCA9548 is a octal bi-directional translating switch controlled

by the I C bus. The SCL/SDA upstream pair fans out to eight

downstream pairs, or channels. Any individual SCx/SDx channel or

combination of channels can be selected, determined by the

contents of the programmable Control Register.

SD4

SC4

SD5

SC5

SD6

SC6

SD7

SC7

Serial data output 4

Serial clock output 5

Serial data output 5

Serial clock output 6

Serial data output 6

Serial clock output 7

Serial data output 7

Serial clock output 8

Address input 2

An active-LOW reset input allows the PCA9548 to recover from a

situation where one of the downstream I C buses is stuck in a LOW

state. Pulling the RESET pin LOW resets the I2C state machine and

causes all the channels to be deselected as does the internal power

on reset function.

The pass gates of the switches are constructed such that the V

pin can be used to limit the maximum high voltage which will be

passed by the PCA9548. This allows the use of different bus

voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can

communicate with 5 V parts without any additional protection.

External pull-up resistors pull the bus up to the desired voltage level

for each channel. All I/O pins are 5 V tolerant.

SCL

SDA

Serial clock line

Serial data line

Supply voltage

ORDERING INFORMATION

PACKAGES

24-Pin Plastic SO

24-Pin Plastic TSSOP

TEMPERATURE RANGE

–40 to +85 °C

ORDER CODE

PCA9548D

DRAWING NUMBER

SOT137-1

–40 to +85 °C

PCA9548PW

SOT355-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

2002 Feb 19

853-2318 27757

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

BLOCK DIAGRAM

PCA9548

SC0

SC1

SC2

SC3

SC4

SC5

SC6

SC7

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SWITCH CONTROL LOGIC

RESET

CIRCUIT

RESET

SCL

SDA

I C-BUS

INPUT

FILTER

CONTROL

SW00371

Figure 2. Block diagram

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

DEVICE ADDRESSING

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9548 is

shown in Figure 3. To conserve power, no internal pullup resistors

are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

COMMAND

Channel 0

disabled

Channel 0

enabled

Channel 1

disabled

Channel 1

enabled

Channel 2

disabled

Channel 2

enabled

Channel 3

disabled

Channel 3

enabled

Channel 4

disabled

Channel 4

enabled

Channel 5

disabled

Channel 5

enabled

Channel 6

disabled

Channel 6

enabled

Channel 7

disabled

Channel 7

enabled

A2 A1 A0 R/W

FIXED

HARDWARE SELECTABLE

SW00915

Figure 3. Slave address

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9548, which will be stored

in the control register. If multiple bytes are received by the

PCA9548, it will save the last byte received. This register can be

written and read via the I C bus.

CHANNEL SELECTION BITS

(READ/WRITE)

B7 B6 B5 B4 B3

B2 B1 B0

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

NOTE: Several channels can be enabled at the same time.

Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,

means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,

3, and 2 are enabled.

Care should be taken not to exceed the maximum bus capacitance.

SW00932

RESET INPUT

The RESET input is an active-LOW signal which may be used to

Figure 4. Control register

recover from a bus fault condition. By asserting this signal LOW for

a minimum of t , the PCA9548 will reset its registers and I C state

CONTROL REGISTER DEFINITION

machine and will deselect all channels. The RESET input must be

One or several SCx/SDx downstream pair, or channel, is selected

by the contents of the control register. This register is written after

the PCA9548 has been addressed. The 2 LSBs of the control byte

are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a stop

connected to V through a pull-up resistor.

POWER-ON RESET

When power is applied to V , an internal Power On Reset holds

condition has been placed on the I C bus. This ensures that all

the PCA9548 in a reset state until V has reached V

. At this

POR

SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of

connection.

point, the reset condition is released and the PCA9548 registers and

I C state machine are initialized to their default states, all zeroes

causing all the channels to be deselected.

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

Figure 5 shows the voltage characteristics of the pass gate

transistors (note that the PCA9548 is only tested at the points

specified in the DC Characteristics section of this datasheet). In

VOLTAGE TRANSLATION

The pass gate transistors of the PCA9548 are constructed such that

the V voltage can be used to limit the maximum voltage that will

order for the PCA9548 to act as a voltage translator, the V

pass

be passed from one I C bus to another.

voltage should be equal to, or lower than the lowest bus voltage. For

example, if the main bus was running at 5 V, and the downstream

buses were 3.3 V and 2.7 V, then V

should be equal to or below

pass

vs. V

pass

2.7 V to effectively clamp the downstream bus voltages. Looking at

Figure 5, we see that V (max.) will be at 2.7 V when the

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

pass

PCA9548 supply voltage is 3.5 V or lower so the PCA9548 supply

voltage could be set to 3.3 V. Pull-up resistors can then be used to

bring the bus voltages to their appropriate levels (see Figure 12).

MAXIMUM

TYPICAL

More Information can be found in Application Note AN262 PCA954X

pass

family of I C/SMBus multiplexers and switches.

MINIMUM

5.0

2.0

2.5

3.0

3.5

4.0

4.5

5.5

SW00820

Figure 5. V

voltage vs. V

pass

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

Start and stop conditions

CHARACTERISTICS OF THE I C-BUS

Both data and clock lines remain HIGH when the bus is not busy. A

HIGH-to-LOW transition of the data line, while the clock is HIGH is

defined as the start condition (S). A LOW-to-HIGH transition of the

data line while the clock is HIGH is defined as the stop condition (P)

(see Figure 7).

The I C-bus is for 2-way, 2-line communication between different ICs

or modules. The two lines are a serial data line (SDA) and a serial

clock line (SCL). Both lines must be connected to a positive supply

via a pull-up resistor when connected to the output stages of a device.

Data transfer may be initiated only when the bus is not busy.

System configuration

Bit transfer

A device generating a message is a ‘transmitter’, a device receiving

is the ‘receiver’. The device that controls the message is the

‘master’ and the devices which are controlled by the master are the

‘slaves’ (see Figure 8).

One data bit is transferred during each clock pulse. The data on the

SDA line must remain stable during the HIGH period of the clock

pulse as changes in the data line at this time will be interpreted as

control signals (see Figure 6).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

SW00363

Figure 6. Bit transfer

SDA

SCL

START condition

STOP condition

SW00365

Figure 7. Definition of start and stop conditions

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

I C

MASTER

TRANSMITTER

MULTIPLEXER

SLAVE

SW00366

Figure 8. System configuration

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits

is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an

extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock

pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

START condition

SW00368

Figure 9. Acknowledgement on the I C-bus

SLAVE ADDRESS

CONTROL REGISTER

SDA

A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

start condition

R/W acknowledge

from slave

acknowledge

from slave

SW01032

Figure 10. WRITE control register

SLAVE ADDRESS

CONTROL REGISTER

last byte

SDA

A2 A1 A0

B7 B6

B4 B3 B2 B1 B0 NA

start condition

R/W acknowledge

from slave

no acknowledge

from master

stop condition

SW01033

Figure 11. READ control register

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

TYPICAL APPLICATION

= 2.7 – 5.5 V

= 3.3 V

V = 2.7 – 5.5 V

SDA

SCL

SDA

SCL

SD0

SC0

CHANNEL 0

V = 2.7 – 5.5 V

RESET

I2C/SMBus MASTER

SD1

SC1

CHANNEL 1

V = 2.7 – 5.5 V

SD2

SC2

CHANNEL 2

V = 2.7 – 5.5 V

SD3

SC3

CHANNEL 3

V = 2.7 – 5.5 V

SD4

SC4

CHANNEL 4

V = 2.7 – 5.5 V

SD5

SC5

CHANNEL 5

V = 2.7 – 5.5 V

SD6

SC6

CHANNEL 6

V = 2.7 – 5.5 V

SD7

SC7

CHANNEL 7

PCA9548

SW00924

Figure 12. Typical application

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

1, 2

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +7.0

±20

UNIT

DC input voltage

DC input current

°C

DC output current

±25

Supply current

±100

Supply current

±100

tot

total power dissipation

Storage temperature range

Operating ambient temperature

400

stg

–60 to +150

–40 to +85

amb

°C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

DC CHARACTERISTICS

= 2.3 to 3.6 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified. (See page 10 for V = 3.6 to 5.5 V)

amb

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Supply

Supply voltage

Supply current

2.3

—

3.6

Operating mode; V = 3.6 V;

no load; V = V or V ;

100

µA

= 100 kHz

SCL

Standby mode; V = 3.6 V;

Standby current

—

100

2.1

µA

stb

no load; V = V or V

POR

Power-on reset voltage

no load; V = V or V

1.6

Input SCL; input/output SDA

LOW level input voltage

HIGH level input voltage

–0.5

—

0.3 V

0.7 V

= 0.4 V

= 0.6 V

—

LOW level output current

—

Leakage current

Input capacitance

V = V or V

–1

—

µA

V = V

Select inputs A0 to A2 / RESET

LOW level input voltage

HIGH level input voltage

Input leakage current

Input capacitance

–0.5

—

+0.3 V

0.7 V

–1

+ 0.5

pin at V or V

µA

V = V

I SS

—

Pass Gate

= 3.67 V, V = 0.4 V, I = 15 mA

2.2

—

1.5

—

Switch resistance

Ω

= 2.3 to 2.7 V, V = 0.4V, I = 10 mA

swin

= V = 3.3 V; I = –100 µA

swout

—

= V = 3.0 to 3.6 V; I = –100 µA

swout

1.6

—

2.8

—

swin

Pass

Switch output voltage

swin

= V = 2.5 V; I

= –100 µA

swout

= V = 2.3 to 2.7 V; I = –100 µA

swout

1.1

–1

—

2.0

swin

Leakage current

V = V or V

µA

Input/output capacitance

V = V

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

DC CHARACTERISTICS

= 3.6 to 5.5 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified. (See page 9 for V = 2.3 to 3.6 V)

amb DD

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MAX

MIN

TYP

Supply

Supply voltage

Supply current

3.6

—

5.5

Operating mode; V = 5.5 V;

no load; V = V or V ;

575

600

µA

= 100 kHz

SCL

Standby mode; V = 5.5 V;

Standby current

—

250

1.7

300

2.1

µA

stb

no load; V = V or V

POR

Power-on reset voltage

no load; V = V or V

Input SCL; input/output SDA

LOW level input voltage

HIGH level input voltage

–0.5

—

0.3 V

0.7 V

= 0.4 V

= 0.6 V

—

µA

LOW level output current

—

LOW level input current

HIGH level input current

Input capacitance

V = V

–10

—

+10

100

V = V

—

Select inputs A0 to A2 / RESET

LOW level input voltage

HIGH level input voltage

Input leakage current

Input capacitance

–0.5

—

+0.3 V

0.7 V

–1

+ 0.5

pin at V or V

+50

µA

V = V

I SS

—

Pass Gate

Switch resistance

= 4.5 to 5.5 V, V = 0.4 V, I = 15 mA

3.5

—

Ω

= V = 5.0 V; I = –100 µA

swout

—

swin

Pass

Switch output voltage

swin

= V = 4.5 to 5.5 V; I = –100 µA

swout

2.6

–10

—

4.5

+10

Leakage current

V = V or V

µA

Input/output capacitance

V = V

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

AC CHARACTERISTICS

STANDARD-MODE

FAST-MODE I C-BUS

I C-BUS

SYMBOL

PARAMETER

UNIT

MIN

—

MAX

MIN

—

MAX

Propagation delay from SDA to SD or SCL to SC

0.3

kHz

µs

SCL clock frequency

100

—

400

—

SCL

BUF

Bus free time between a STOP and START condition

4.7

1.3

Hold time (repeated) START condition

After this period, the first clock pulse is generated

4.0

—

0.6

—

µs

HD;STA

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Set-up time for STOP condition

Data hold time

4.7

4.0

4.7

4.0

—

1.3

0.6

—

µs

LOW

HIGH

—

SU;STA

SU;STO

—

3.45

—

0.9

—

HD;DAT

Data set-up time

250

—

100

20 + 0.1C

—

SU;DAT

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Capacitive load for each bus line

1000

300

400

300

400

—

Pulse width of spikes which must be suppressed

by the input filter

—

Data valid (HL)

—

0.6

—

0.6

µs

VD:DATL

Data valid (LH)

VD:DATH

Data valid Acknowledge

VD:ACK

RESET

Pulse width low reset

Reset time (SDA clear)

Recovery to Start

500

—

500

—

WL(rst)

rst

REC:STA

NOTES:

1. Pass gate propagation delay is calculated from the 20 Ω typical R and the 15 pF load capacitance.

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH

of the SCL signal) in order to bridge

min

the undefined region of the falling edge of SCL.

3. C = total capacitance of one bus line in pF.

SDA

HD;STA

LOW

BUF

SCL

SU;STO

HD;STA

SU;STA

SU;DAT

HD;DAT

HIGH

SU00645

Figure 13. Definition of timing on the I C-bus

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

2002 Feb 19

Philips Semiconductors

Product data

8-channel I²C switch with reset

PCA9548

Purchase of Philips I C components conveys a license under the Philips’ I C patent

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 02-02

9397 750 09461

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

2002 Feb 19

935271209112 [NXP]

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