935271659125 [NXP]
IC AHCT/VHCT SERIES, 2-INPUT AND GATE, PDSO5, PLASTIC, SC-74A, 5 PIN, Gate;
| 型号： | 935271659125 |
| 厂家： | 
NXP |
| 描述： | IC AHCT/VHCT SERIES, 2-INPUT AND GATE, PDSO5, PLASTIC, SC-74A, 5 PIN, Gate 栅 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC1G08; 74AHCT1G08
2-input AND gate
Product specification
2002 Jun 06
Supersedes data of 2002 Feb 21
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
FEATURES
DESCRIPTION
• Symmetrical output impedance
• High noise immunity
The 74AHC1G/AHCT1G08 is a high-speed Si-gate CMOS
device.
The 74AHC1G/AHCT1G08 provides the 2-input AND
function.
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
AHC1G AHCT1G
tPHL/tPLH propagation delay A and B to Y
CL = 15 pF; VCC = 5 V
3.2
3.6
1.5
19
CI
input capacitance
1.5
17
pF
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
2002 Jun 06
2
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
FUNCTION TABLE
See note 1.
INPUTS
OUTPUT
Y
A
B
L
L
L
H
L
L
L
H
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGES
PACKAGE MATERIAL
TEMPERATURE
RANGE
PINS
CODE
MARKING
74AHC1G08GW
74AHCT1G08GW
74AHC1G08GV
74AHCT1G08GV
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
5
5
5
5
SC-88A
SC-88A
SC-74A
SC-74A
plastic
plastic
plastic
plastic
SOT353
SOT353
SOT753
SOT753
AE
CE
A08
C08
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
B
A
data input B
data input A
ground (0 V)
data output Y
supply voltage
GND
Y
VCC
handbook, halfpage
B
A
1
2
3
5
4
V
Y
CC
handbook, halfpage
1
2
B
A
Y
4
08
GND
MNA113
MNA112
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2002 Jun 06
3
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
handbook, halfpage
A
1
handbook, halfpage
&
4
2
Y
MNA114
B
MNA221
Fig.3 IEC logic symbol.
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
74AHC1G
74AHCT1G
TYP. MAX.
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
UNIT
MIN.
2.0
TYP. MAX. MIN.
5.0
−
5.5
5.5
VCC
4.5
0
5.0
−
5.5
5.5
VCC
V
VI
input voltage
0
V
V
VO
output voltage
0
−
0
−
Tamb
ambient temperature see DC and AC
characteristics per
−40
+25
+125 −40
+25
+125 °C
device
tr, tf (∆t/∆f) input rise and fall
VCC = 3.3 ±0.3 V
CC = 5 ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
ns/V
times
V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage
−0.5
−0.5
−
+7.0
+7.0
−20
±20
±25
±75
V
VI
input voltage
V
IIK
input diode current
VI < −0.5 V
mA
mA
mA
mA
IOK
IO
output diode current
output source or sink current
VCC or GND current
storage temperature
power dissipation per package
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V
−
−
ICC
Tstg
PD
−
−65
−
+150 °C
250 mW
for temperature range from −40 to +125 °C
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Jun 06
4
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
DC CHARACTERISTICS
Family 74AHC1G
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
−40 to +125 UNIT
VCC
(V)
OTHER
VIH
HIGH-level input
voltage
2.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
V
V
V
3.0
5.5
2.0
3.0
5.5
2.0
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
1.9
2.0
1.9
1.9
voltage
IO = −50 µA
VI = VIH or VIL;
IO = −50 µA
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
2.9
4.4
2.58
3.94
−
3.0
4.5
−
−
2.9
4.4
2.48
3.8
−
−
2.9
4.4
2.40
3.70
−
−
V
VI = VIH or VIL;
IO = −50 µA
−
−
−
V
VI = VIH or VIL;
IO = −4.0 mA
−
−
−
V
VI = VIH or VIL;
IO = −8.0 mA
−
−
−
−
V
VOL
LOW-level output VI = VIH or VIL;
0
0.1
0.1
0.1
0.36
0.36
0.1
1.0
10
0.1
0.1
0.1
0.44
0.44
1.0
10
10
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
voltage
IO = 50 µA
VI = VIH or VIL;
IO = 50 µA
−
0
−
−
V
VI = VIH or VIL;
IO = 50 µA
−
0
−
−
V
VI = VIH or VIL;
IO = 4.0 mA
−
−
−
−
V
VI = VIH or VIL;
IO = 8.0 mA
−
−
−
−
V
ILI
input leakage
current
VI = VCC or GND 5.5
−
−
−
−
µA
µA
pF
ICC
CI
quiescent supply VI = VCC or GND; 5.5
−
−
−
−
current
IO = 0
input capacitance
−
1.5
−
−
2002 Jun 06
5
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
Family 74AHCT1G
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
4.5 to 5.5 2.0
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
−
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5
4.5
−
−
0.8
−
−
0.8
−
−
0.8
−
V
VOH
HIGH-leveloutput VI = VIH or VIL;
4.4
3.94
−
4.5
−
4.4
3.8
−
4.4
3.70
−
V
voltage
IO = −50 µA
VI = VIH or VIL;
IO = −8.0 mA
4.5
−
−
−
V
VOL
LOW-level output VI = VIH or VIL;
4.5
0
0.1
0.36
0.1
1.0
1.35
0.1
0.44
1.0
10
1.5
0.1
0.55
2.0
40
1.5
V
voltage
IO = 50 µA
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
−
−
V
ILI
input leakage
current
VI = VIH or VIL
5.5
−
−
−
−
µA
µA
mA
ICC
∆ICC
quiescent supply VI = VCC or GND; 5.5
−
−
−
−
current
IO = 0
additional
VI = 3.4 V;
5.5
−
−
−
−
quiescent supply other inputs at
current per input VCC or GND;
pin
IO = 0
CI
input capacitance
−
1.5
10
−
10
−
10
pF
2002 Jun 06
6
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
AC CHARACTERISTICS
Type 74AHC1G08
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
CL
WAVEFORMS
(pF)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay see Figs 5 and 6 15
−
−
4.6
6.5
8.8
1.0
10.5 1.0
14.0 1.0
12.0 ns
16.0 ns
A and B to Y
50
12.3 1.0
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay see Figs 5 and 6 15
−
−
3.2
4.6
5.9
7.9
1.0
1.0
7.0
9.0
1.0
1.0
8.0
ns
A and B to Y
50
10.5 ns
Notes
1. Typical values are measured at VCC = 3.3 V.
2. Typical values are measured at VCC = 5.0 V.
Type 74AHCT1G08
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
−40 to +125 UNIT
CL
(pF)
WAVEFORMS
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
t
PHL/tPLH propagation delay see Figs 5 and 6 15
−
−
3.6
5.1
6.2
7.9
1.0
1.0
7.1
9.0
1.0
1.0
8.0
ns
A and B to Y
50
10.5 ns
Note
1. Typical values are measured at VCC = 5 V.
2002 Jun 06
7
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
AC WAVEFORMS
handbook, halfpage
V
A, B input
M
t
t
PHL
PLH
V
Y output
M
MNA116
VI INPUT
FAMILY
VM
VM
REQUIREMENTS INPUT OUTPUT
AHC1G
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT1G GND to 3.0 V
Fig.5 The input (A and B) to output (Y) propagation delays.
V
handbook, halfpage
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
L
T
MNA101
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance. (See Chapter “AC characteristics”).
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
8
2002 Jun 06
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
PACKAGE OUTLINES
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
2002 Jun 06
9
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
SOT753
SC-74A
02-04-16
2002 Jun 06
10
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Jun 06
11
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
WAVE
REFLOW(2)
not suitable suitable
PACKAGE(1)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
suitable
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Jun 06
12
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
DATA SHEET STATUS
PRODUCT
STATUS(2)
DATA SHEET STATUS(1)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Product data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Jun 06
13
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
NOTES
2002 Jun 06
14
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
NOTES
2002 Jun 06
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/05/pp16
Date of release: 2002 Jun 06
Document order number: 9397 750 09705
相关型号：
935271753118
IC 8 I/O, PIA-GENERAL PURPOSE, PDSO20, 4.40 MM, PLASTIC, MO-152, SOT-266-1, SSOP-20, Parallel IO Port
NXP
935271788125
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