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P89LV51RB2/RC2/RD2

8-bit 80C51 3 V low power 16/32/64 kB ﬂash microcontroller

with 1 kB RAM

Rev. 05 — 15 December 2009

Product data sheet

1. General description

The P89LV51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB ﬂash and

1024 B of data RAM.

A key feature of the P89LV51RB2/RC2/RD2 is its X2 mode option. The design engineer

can choose to run the application with the conventional 80C51 clock rate (12 clocks per

machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the

throughput at the same clock frequency. Another way to beneﬁt from this feature is to keep

the same performance by reducing the clock frequency by half, thus dramatically reducing

the EMI.

The ﬂash program memory supports both parallel programming and in serial ISP. Parallel

programming mode offers gang-programming at high speed, reducing programming costs

and time to market. ISP allows a device to be reprogrammed in the end product under

software control. The capability to ﬁeld/update the application ﬁrmware makes a wide

range of applications possible.

The P89LV51RB2/RC2/RD2 is also capable of IAP, allowing the ﬂash program memory to

be reconﬁgured even while the application is running.

2. Features

I 80C51 CPU

I 3 V operating voltage from 0 MHz to 33 MHz

I 16/32/64 kB of on-chip ﬂash user code memory with ISP and IAP

I Supports 12-clock (default) or 6-clock mode selection via software or ISP

I SPI and enhanced UART

I PCA with PWM and capture/compare functions

I Four 8-bit I/O ports with three high-current port 1 pins (16 mA each)

I Three 16-bit timers/counters

I Programmable watchdog timer

I Eight interrupt sources with four priority levels

I Second DPTR register

I Low EMI mode (ALE inhibit)

I TTL- and CMOS-compatible logic levels

P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

I Brownout detection

I Low power modes

N Power-down mode with external interrupt wake-up

N Idle mode

I PLCC44 and TQFP44 packages

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

P89LV51RB2BA

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

SOT376-1

SOT187-2

SOT376-1

P89LV51RC2FBC TQFP44

P89LV51RD2FA PLCC44

P89LV51RD2BBC TQFP44

plastic thin quad ﬂat package; 44 leads; body 10 × 10 × 1.0 mm

plastic leaded chip carrier; 44 leads

plastic thin quad ﬂat package; 44 leads; body 10 × 10 × 1.0 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash memory

16 kB

Temperature range

0 °C to +70 °C

Frequency

P89LV51RB2BA

P89LV51RC2FBC

P89LV51RD2FA

P89LV51RD2BBC

0 MHz to 40 MHz

32 kB

−40 °C to +85 °C

0 °C to +70 °C

64 kB

P89LV51RB2_RC2_RD2_5

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

4. Block diagram

P89LV51RB2/RC2/RD2

HIGH PERFORMANCE

80C51 CPU

TXD

RXD

16/32/64 kB

CODE FLASH

UART

internal

bus

T0

T1

TIMER 0

TIMER 1

1 kB

DATA RAM

T2

T2EX

P3[7:0]

P2[7:0]

P1[7:0]

P0[7:0]

PORT 3

PORT 2

PORT 1

PORT 0

TIMER 2

SPI

SPICLK

MOSI

MISO

SS

PCA

CEX[4:0]

PROGRAMMABLE

COUNTER ARRAY

WATCHDOG TIMER

XTAL1

CRYSTAL

OSCILLATOR

OR

RESONATOR

XTAL2

002aaa506

Fig 1. Block diagram

P89LV51RB2_RC2_RD2_5

Product data sheet

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

5. Pinning information

5.1 Pinning

7

39

38

37

36

35

34

33

32

31

30

29

P1.5/MOSI/CEX2

P1.6/MISO/CEX3

P1.7/SPICLK/CEX4

RST

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

8

9

10

11

12

13

14

15

16

17

P3.0/RXD

n.c.

P89LV51RB2BA

P89LV51RD2FA

n.c.

P3.1/TXD

ALE/PROG

PSEN

P3.2/INT0

P3.3/INT1

P3.4/T0

P2.7/A15

P2.6/A14

P2.5/A13

P3.5/T1

002aaa509

Fig 2. PLCC44 pin conﬁguration

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

1

2

33

32

31

30

29

28

27

26

25

24

23

P1.5/MOSI/CEX2

P1.6/MISO/CEX3

P1.7/SPICLK/CEX4

RST

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

3

4

5

P3.0/RXD

n.c.

P89LV51RC2FBC

P89LV51RD2BBC

6

n.c.

7

P3.1/TXD

ALE/PROG

PSEN

8

P3.2/INT0

P3.3/INT1

P3.4/T0

9

P2.7/A15

P2.6/A14

P2.5/A13

10

11

P3.5/T1

002aaa508

Fig 3. TQFP44 pin conﬁguration

P89LV51RB2_RC2_RD2_5

Product data sheet

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

5.2 Pin description

Table 3.

Symbol

P89LV51RB2/RC2/RD2 pin description

Type

Description

TQFP44

PLCC44

P0.0 to P0.7

I/O

Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. Port 0

pins that have ‘1’s written to them ﬂoat, and in this state can be

used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external

code and data memory. In this application, it uses strong internal

pull-ups when transitioning to ‘1’s. Port 0 also receives the code

bytes during the external host mode programming, and outputs

the code bytes during the external host mode veriﬁcation.

External pull-ups are required during program veriﬁcation or as a

general purpose I/O port.

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P1.0 to P1.7

37

36

35

34

33

32

31

30

43

42

41

40

39

38

37

36

I/O

P0.0 — Port 0 bit 0.

AD0 — Address/data bit 0.

P0.1 — Port 0 bit 1.

AD1 — Address/data bit 1.

P0.2 — Port 0 bit 2.

AD2 — Address/data bit 2.

P0.3 — Port 0 bit 3.

AD3 — Address/data bit 3.

P0.4 — Port 0 bit 4.

AD4 — Address/data bit 4.

P0.5 — Port 0 bit 5.

AD5 — Address/data bit 5.

P0.6 — Port 0 bit 6.

AD6 — Address/data bit 6.

P0.7 — Port 0 bit 7.

AD7 — Address/data bit 7.

I/O with

internal

pull-up

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal

pull-ups. The Port 1 pins are pulled high by the internal pull-ups

when ‘1’s are written to them and can be used as inputs in this

state. As inputs, Port 1 pins that are externally pulled LOW will

source current (I_IL) because of the internal pull-ups. P1.5, P1.6,

P1.7 have a high current drive of 16 mA. Port 1 also receives the

low-order address bytes during the external host mode

programming and veriﬁcation.

P1.0/T2

40

41

42

2

3

4

I

P1.0 — Port 1 bit 0.

I/O

T2 — External count input to Timer/counter 2 or Clock-out from

Timer/counter 2.

P1.1/T2EX

P1.2/ECI

I/O

I

P1.1 — Port 1 bit 1.

T2EX: Timer/counter 2 capture/reload trigger and direction

control input.

I/O

I

P1.2 — Port 1 bit 2.

ECI — External clock input. This signal is the external clock input

for the PCA.

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P89LV51RB2/RC2/RD2

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8-bit microcontrollers with 80C51 core

Table 3.

Symbol

P89LV51RB2/RC2/RD2 pin description …continued

Type

Description

TQFP44

43

PLCC44

P1.3/CEX0

5

I/O

P1.3 — Port 1 bit 3.

CEX0 — Capture/compare external I/O for PCA Module 0. Each

capture/compare module connects to a Port 1 pin for external

I/O. When not used by the PCA, this pin can handle standard I/O.

P1.4/SS/CEX1 44

6

7

8

9

I/O

I

P1.4 — Port 1 bit 4.

SS — Slave port select input for SPI.

CEX1 — Capture/compare external I/O for PCA Module 1.

P1.5 — Port 1 bit 5.

I/O

P1.5/MOSI/

CEX2

1

2

3

MOSI — Master Output Slave Input for SPI.

CEX2 — Capture/compare external I/O for PCA Module 2.

P1.6 — Port 1 bit 6.

P1.6/MISO/

CEX3

MISO — Master Input Slave Output for SPI.

CEX3 — Capture/compare external I/O for PCA Module 3.

P1.7 — Port 1 bit 7.

P1.7/SPICLK/

CEX4

SPICLK — Serial clock input/output for SPI.

CEX4 — Capture/compare external I/O for PCA Module 4.

P2.0 to P2.7

I/O with

internal

pull-up

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal

pull-ups. Port 2 pins are pulled HIGH by the internal pull-ups

when ‘1’s are written to them and can be used as inputs in this

state. As inputs, Port 2 pins that are externally pulled LOW will

source current (I_IL) because of the internal pull-ups. Port 2 sends

the high-order address byte during fetches from external

program memory and during accesses to external Data Memory

that use 16-bit address (MOVX@DPTR). In this application, it

uses strong internal pull-ups when transitioning to ‘1’s. Port 2

also receives some control signals and a partial of high-order

address bits during the external host mode programming and

veriﬁcation.

P2.0/A8

18

19

20

21

22

23

24

25

26

27

28

29

30

I/O

O

P2.0 — Port 2 bit 0.

A8 — Address bit 8.

P2.1 — Port 2 bit 1.

A9 — Address bit 9.

P2.2 — Port 2 bit 2.

A10 — Address bit 10.

P2.3 — Port 2 bit 3.

A11 — Address bit 11.

P2.4 — Port 2 bit 4.

A12 — Address bit 12.

P2.5 — Port 2 bit 5.

A13 — Address bit 13.

P2.6 — Port 2 bit 6.

A14 — Address bit 14.

P2.1/A9

I/O

O

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

P89LV51RB2_RC2_RD2_5

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

Table 3.

Symbol

P89LV51RB2/RC2/RD2 pin description …continued

Type

Description

TQFP44

25

PLCC44

P2.7/A15

31

I/O

O

P2.7 — Port 2 bit 7.

A15 — Address bit 15.

P3.0 to P3.7

I/O with

internal

pull-up

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal

pull-ups. Port 3 pins are pulled HIGH by the internal pull-ups

when ‘1’s are written to them and can be used as inputs in this

state. As inputs, Port 3 pins that are externally pulled LOW will

source current (I_IL) because of the internal pull-ups. Port 3 also

receives some control signals and a partial of high-order address

bits during the external host mode programming and veriﬁcation.

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

5

11

13

14

15

16

17

18

19

32

I

P3.0 — Port 3 bit 0.

I

RXD — Serial input port.

7

O

I

P3.1 — Port 3 bit 1.

TXD — Serial output port.

P3.2 — Port 3 bit 2.

8

I

INT0 — External interrupt 0 input.

P3.3 — Port 3 bit 3.

9

I

INT1 — External interrupt 1 input.

P3.4 — Port 3 bit 4.

10

11

12

13

26

I/O

I

T0 — External count input to Timer/counter 0.

P3.5 — Port 3 bit 5.

P3.5/T1

I/O

I

T1 — External count input to Timer/counter 1.

P3.6 — Port 3 bit 6.

P3.6/WR

P3.7/RD

PSEN

O

I/O

WR — External data memory write strobe.

P3.7 — Port 3 bit 7.

RD — External data memory read strobe.

Program Store Enable: PSEN is the read strobe for external

program memory. When the device is executing from internal

program memory, PSEN is inactive (HIGH). When the device is

executing code from external program memory, PSEN is

activated twice each machine cycle, except that two PSEN

activations are skipped during each access to external data

memory. A forced HIGH-to-LOW input transition on the PSEN pin

while the RST input is continually held HIGH for more than 10

machine cycles will cause the device to enter external host mode

programming.

RST

EA

4

10

35

I

Reset: While the oscillator is running, a HIGH logic state on this

pin for two machine cycles will reset the device. If the PSEN pin

is driven by a HIGH-to-LOW input transition while the RST input

pin is held HIGH, the device will enter the external host mode,

otherwise the device will enter the normal operation mode.

29

External Access Enable: EA must be connected to V_SSin order

to enable the device to fetch code from the external program

memory. EA must be strapped to V_DDfor internal program

execution. The EA pin can tolerate a high voltage of 12 V.

P89LV51RB2_RC2_RD2_5

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8-bit microcontrollers with 80C51 core

Table 3.

Symbol

P89LV51RB2/RC2/RD2 pin description …continued

Type

Description

TQFP44

27

PLCC44

ALE/PROG

33

I/O

Address Latch Enable: ALE is the output signal for latching the

low byte of the address during an access to external memory.

This pin is also the programming pulse input (PROG) for ﬂash

programming. Normally the ALE^[1]is emitted at a constant rate of

¹⁄₆the crystal frequency^[2]and can be used for external timing

and clocking. One ALE pulse is skipped during each access to

external data memory. However, if bit AO is set to ‘1’, ALE is

disabled.

n.c.

6, 17, 28,

39

1, 12, 23,

34

I/O

I

not connected

XTAL1

15

21

Crystal 1: Input to the inverting oscillator ampliﬁer and input to

the internal clock generator circuits.

XTAL2

V_DD

14

38

16

20

44

22

O

I

Crystal 2: Output from the inverting oscillator ampliﬁer.

Power supply

Ground

V_SS

I

[1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into

modes other than normal working mode. The solution is to connect a pull-up resistor of 3 kΩ to 50 kΩ from pin ALE to V_DD

.

[2] For 6-clock mode, ALE is emitted at ¹⁄₃of crystal frequency.

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NXP Semiconductors

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6. Functional description

6.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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6.2 Memory organization

The device has separate address spaces for program and data memory.

6.2.1 Flash program memory bank selection

There are two internal ﬂash memory blocks in the device. Block 0 has 16/32/64 kB and is

organized as 128/256/512 sectors, each sector consists of 128 B. Block 1 contains the

IAP/ISP routines and may be enabled such that it overlays the ﬁrst 8 kB of the user code

memory. The overlay function is controlled by the combination of the Software Reset Bit

(SWR) at FCF.1 and the Bank Select Bit (BSEL) at FCF.0. The combination of these bits

and the memory source used for instructions is shown in Table 5.

Table 5.

Code memory bank selection

SWR (FCF.1)

BSEL (FCF.0)

Addresses from

0000H to 1FFFH

Addresses above

1FFFH

0

1

0

1

0

1

boot code (in block 1) user code (in block 0)

user code (in block 0)

Access to the IAP routines in block 1 may be enabled by clearing the BSEL bit (FCF.0),

provided that the SWR bit (FCF.1) is cleared. Following a power-on sequence, the boot

code is automatically executed and attempts to autobaud to a host. If no autobaud occurs

within approximately 400 ms and the SoftICE ﬂag is not set, control will be passed to the

user code. A software reset is used to accomplish this control transfer and as a result the

SWR bit will remain set. Therefore the user's code will need to clear the SWR bit in

order to access the IAP routines in block 1. However, caution must be taken when

dynamically changing the BSEL bit. Since this will cause different physical memory to be

mapped to the logical program address space, the user must avoid clearing the BSEL bit

when executing user code within the address range 0000H to 1FFFH.

6.2.2 Power-on reset code execution

At initial power up, the port pins will be in a random state until the oscillator has started

and the internal reset algorithm has weakly pulled all pins high. Powering up the device

without a valid reset could cause the MCU to start executing instructions from an

indeterminate location. Such undeﬁned states may inadvertently corrupt the code in the

ﬂash. A system reset will not affect the 1 kB of on-chip RAM while the device is running,

however, the contents of the on-chip RAM during power up are indeterminate.

When power is applied to the device, the RST pin must be held high long enough for the

oscillator to start up (usually several milliseconds for a low frequency crystal), in addition

to two machine cycles for a valid power-on reset. An example of a method to extend the

RST signal is to implement a RC circuit by connecting the RST pin to V_DDthrough a 10 µF

capacitor and to V_SSthrough an 8.2 kΩ resistor as shown in Figure 4. Note that if an RC

circuit is used, provision should be made to ensure the V_DDrise time does not exceed

1 ms and the oscillator start-up time does not exceed 10 ms.

For a low frequency oscillator with slow start-up time the reset signal must be extended in

order to account for the slow start-up time. This method maintains the necessary

relationship between V_DDand RST to avoid programming at an indeterminate location,

which may cause corruption in the Flash code. The power-on detection is designed to

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

work during initial power up, before the voltage reaches the brownout detection level. The

POF ﬂag in the PCON register is set to indicate an initial power up condition. The POF

ﬂag will remain active until cleared by software.

Following a power-on or external reset the P89LV51RB2/RC2/RD2 will force the SWR and

BSEL bits (FCF[1:0]) to 00. This causes the boot block to be mapped into the lower 8 kB

of code memory and the device will execute the ISP code in the boot block and attempt to

autobaud to the host. If the autobaud is successful the device will remain in ISP mode. If,

after approximately 400 ms, the autobaud is unsuccessful the boot block code will check

to see if the SoftICE ﬂag is set (from a previous programming operation). If the SoftICE

ﬂag is set the device will enter SoftICE mode. If the SoftICE ﬂag is cleared, the boot code

will execute a software reset causing the device to execute the user code from block 0

starting at address 0000H. Note that an external reset applied to the RST pin has the

same effect as a power-on reset.

V

DD

10 µF

V

DD

RST

8.2 kΩ

C

2

XTAL2

XTAL1

C

1

002aaa543

Fig 4. Power-on reset circuit

6.2.3 Software reset

A software reset is executed by changing the SWR bit (FCF.1) from ‘0’ to ‘1’. A software

reset will reset the program counter to address 0000H and force both the SWR and BSEL

bits (FCF[1:0]) to 10. This will result in the lower 8 kB of the user code memory being

mapped into the user code memory space. Thus the user's code will be executed starting

at address 0000H. A software reset will not change bit WDTC.2 or RAM data. Other SFRs

will be set to their reset values.

6.2.4 Brownout detect reset

The device includes a brownout detection circuit to protect the system from severe supply

voltage ﬂuctuations. The P89LV51RB2/RC2/RD2's brownout detection threshold is 2.35 V.

When V_DDdrops below this voltage threshold, the brownout detect triggers the circuit to

generate a brownout interrupt but the CPU still runs until the supplied voltage returns to

the brownout detection voltage V_bo. The default operation for a brownout detection is to

cause a processor reset.

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Product data sheet

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8-bit microcontrollers with 80C51 core

V_DDmust stay below V_boat least four oscillator clock periods before the brownout

detection circuit will respond.

Brownout interrupt can be enabled by setting the EBO bit (IEN1.3). If EBO bit is set and a

brownout condition occurs, a brownout interrupt will be generated to execute the program

at location 004BH. It is required that the EBO bit is cleared by software after the brownout

interrupt is serviced. Clearing EBO bit when the brownout condition is active will properly

reset the device. If brownout interrupt is not enabled, a brownout condition will reset the

program to resume execution at location 0000H. A brownout detect reset will clear the

BSEL bit (FCF.0) but will not change the SWR bit (FCF.1) and therefore will not change the

banking of the lower 8 kB of user code memory space.

6.2.5 Watchdog reset

Like a brownout detect reset, the watchdog timer reset will clear the BSEL bit (FCF.0) but

will not change the SWR bit (FCF.1) and therefore will not change the banking of the lower

8 kB of user code memory space.

The state of the SWR and BSEL bits after different types of resets is shown in Table 6.

This results in the code memory bank selections as shown.

Table 6.

Effects of reset sources on bank selection

Reset source

SWR bit result

(FCF.1)

BSEL bit result

(FCF.0)

Addresses from 0000H to

1FFFH

Addresses above

1FFFH

External reset

0

Boot code (in block 1)

User code (in block 0)

Power-on reset

Watchdog reset

Brownout detect reset

x

0

Retains state of SWR bit. If

SWR, BSEL = 00 then uses

boot code. If SWR,

BSEL = 10 then uses user

code.

Software reset

1

0

User code (in block 0)

6.2.6 Data RAM memory

The data RAM has 1024 B of internal memory. The device can also address up to 64 kB

for external data memory.

6.2.7 Expanded data RAM addressing

The P89LV51RB2/RC2/RD2 has 1 kB of RAM. See Figure 5 “Internal and external data

memory structure” on page 19.

The device has four sections of internal data memory:

1. The lower 128 B of RAM (00H to 7FH) are directly and indirectly addressable.

2. The higher 128 B of RAM (80H to FFH) are indirectly addressable.

3. The special function registers (80H to FFH) are directly addressable only.

4. The expanded RAM of 768 B (00H to 2FFH) is indirectly addressable by the move

external instruction (MOVX) and clearing the EXTRAM bit (see ‘Auxiliary function

Register’ (AUXR) in Table 4 “Special function registers” on page 11).

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

Since the upper 128 B occupy the same addresses as the SFRs, the RAM must be

accessed indirectly. The RAM and SFRs space are physically separate even though they

have the same addresses.

Table 7.

AUXR - Auxiliary register (address 8EH) bit allocation

Not bit addressable; reset value 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

EXTRAM

AO

Table 8.

Bit

AUXR - Auxiliary register (address 8EH) bit descriptions

Symbol

-

Description

7 to 2

1

Reserved for future use. Should be set to ‘0’ by user programs.

EXTRAM

Internal/External RAM access using MOVX @Ri/@DPTR.

When ‘0’, core attempts to access internal XRAM with address

speciﬁed in MOVX instruction. If address supplied with this instruction

exceeds on-chip available XRAM, off-chip XRAM is going to be

selected and accessed.

When ‘1’, every MOVX @Ri/@DPTR instruction targets external data

memory by default.

0

AO

ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a

constant rate of ¹⁄₂the oscillator frequency. In case of AO = 1, ALE is

active only during a MOVX or MOVC.

When instructions access addresses in the upper 128 B (above 7FH), the MCU

determines whether to access the SFRs or RAM by the type of instruction given. If it is

indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples

below.

Indirect access:

MOV@R0, #data; R0 contains 90H

Register R0 points to 90H which is located in the upper address range. Data in ‘#data’ is

written to RAM location 90H rather than port 1.

Direct access:

MOV90H, #data; write data to P1

Data in ‘#data’ is written to port 1. Instructions that write directly to the address, write to

the SFRs.

To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions

must be used. The extra 768 B of memory is physically located on the chip and logically

occupies the ﬁrst 768 B of external memory (addresses 000H to 2FFH).

When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX

instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.

Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7 (RD), or P2.

With EXTRAM = 0, the expanded RAM can be accessed as in the following example.

Expanded RAM access (indirect addressing only):

MOVX@DPTR, A DPTR contains 0A0H

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DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded RAM

rather than external memory. Access to external memory higher than 2FFH using the

MOVX instruction will access external memory (0300H to FFFFH) and will perform in the

same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7

as write and read timing signals.

When EXTRAM = 1, MOVX@Ri and MOVX@DPTR will be similar to the standard 8051.

Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output

port pins can be used to output higher order address bits. This provides external paging

capabilities. Using MOVX@DPTR generates a 16-bit address. This allows external

addressing up to 64 kB. Port 2 provides the high-order eight address bits (DPH), and

Port 0 multiplexes the low-order eight address bits (DPL) with data. Both MOVX@Ri and

MOVX@DPTR generates the necessary read and write signals (P3.6, - WR and P3.7, -

RD) for external memory use. Table 9 shows external data memory RD, WR operation

with EXTRAM bit.

The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower

128 B and upper 128 B). The stack pointer may not be located in any part of the expanded

RAM.

Table 9.

External data memory RD, WR with EXTRAM bit^[1]

Register AUXR

MOVX @DPTR, A or MOVX A, @DPTR

MOVX @Ri, A or

MOVX A, @Ri

ADDR < 0300H

ADDR ≥ 0300H

RD/WR asserted

ADDR = any

EXTRAM = 0

EXTRAM = 1

RD/WR not asserted

RD/WR asserted

RD/WR not asserted

RD/WR asserted

[1] Access limited to Expanded RAM address within 0 to 0FFH; cannot access 100H to 02FFH.

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2FFH

FFH

EXPANDED

RAM

768 B

(DIRECT

ADDRESSING)

(INDIRECT

ADDRESSING)

SPECIAL

FUNCTION

REGISTERS (SFRs)

UPPER 128 B

INTERNAL RAM

80H

7FH

80H

LOWER 128 B

INTERNAL RAM

(INDIRECT AND

DIRECT

ADDRESSING)

(INDIRECT

ADDRESSING)

00H

000H

FFFFH

(INDIRECT

ADDRESSING)

EXTERNAL

DATA

EXTERNAL

DATA

MEMORY

0300H

2FFH

000H

EXPANDED RAM

0000H

EXTRAM = 0

EXTRAM = 1

002aaa517

Fig 5. Internal and external data memory structure

6.2.8 Dual data pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1

determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is

selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data

pointers can be accomplished by a single INC instruction on AUXR1 (see Figure 6).

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AUXR1 / bit0

DPS

DPTR1

DPTR0

DPS = 0 → DPTR0

DPS = 1 → DPTR1

DPL

82H

DPH

83H

external data memory

002aaa518

Fig 6. Dual data pointer organization

Table 10. AUXR1 - Auxiliary register 1 (address A2H) bit allocation

Not bit addressable; reset value 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

GF2

0

-

DPS

Table 11. AUXR1 - Auxiliary register 1 (address A2H) bit descriptions

Bit

7 to 4

3

Symbol

Description

-

Reserved for future use. Should be set to ‘0’ by user programs.

General purpose user-deﬁned ﬂag.

GF2

0

2

This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by

incrementing AUXR1, without interfering with other bits in the register.

1

0

-

Reserved for future use. Should be set to ‘0’ by user programs.

DPS

Data pointer select. Chooses one of two Data Pointers for use by the

program. See text for details.

6.3 Flash memory IAP

6.3.1 Flash organization

The P89LV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP

capability, in a second 8 kB block, is provided to allow the user code to be programmed

in-circuit through the serial port. There are three methods of erasing or programming of

the ﬂash memory that may be used. First, the ﬂash may be programmed or erased in the

end-user application by calling low-level routines through a common entry point (IAP).

Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call

low-level routines through the same common entry point that can be used by the end-user

application. Third, the ﬂash may be programmed or erased using the parallel method by

using a commercially available EPROM programmer which supports this device.

6.3.2 Boot block (block 1)

When the microcontroller programs its own ﬂash memory, all of the low level details are

handled by code that is contained in block 1. A user program calls the common entry point

in the block 1 with appropriate parameters to accomplish the desired operation. Boot block

operations include erase user code, program user code, program security bits, etc.

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A chip-erase operation can be performed using a commercially available parallel

programer. This operation will erase the contents of this boot block and it will be

necessary for the user to reprogram this boot block (block 1) with the NXP-provided

ISP/IAP code in order to use the ISP or IAP capabilities of this device. Go to

http://www.nxp.com/support for questions or to obtain the hex ﬁle for this device.

6.3.3 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LV51RB2/RC2/RD2 through the serial port. This

ﬁrmware is provided by NXP and embedded within each P89LV51RB2/RC2/RD2 device.

The NXP ISP facility has made in-circuit programming in an embedded application

possible with a minimum of additional expense in components and circuit board area. The

ISP function uses ﬁve pins (V_DD, V_SS, TXD, RXD, and RST). Only a small connector

needs to be available to interface your application to an external circuit in order to use this

feature.

6.3.4 Using ISP

The ISP feature allows for a wide range of baud rates to be used in your application,

independent of the oscillator frequency. It is also adaptable to a wide range of oscillator

frequencies. This is accomplished by measuring the bit-time of a single bit in a received

character. This information is then used to program the baud rate in terms of timer counts

based on the oscillator frequency. The ISP feature requires that an initial character (an

uppercase U) be sent to the P89LV51RB2/RC2/RD2 to establish the baud rate. The ISP

ﬁrmware provides auto-echo of received characters. Once baud rate initialization has

been performed, the ISP ﬁrmware will only accept Intel Hex-type records. Intel Hex

records consist of ASCII characters used to represent hexadecimal values and are

summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The

P89LV51RB2/RC2/RD2 will accept up to 32 data bytes. The ‘AAAA’ string represents the

address of the ﬁrst byte in the record. If there are zero bytes in the record, this ﬁeld is often

set to 0000. The ‘RR’ string indicates the record type. A record type of ‘00’ is a data

record. A record type of ‘01’ indicates the end-of-ﬁle mark. In this application, additional

record types will be added to indicate either commands or data for the ISP facility.

The maximum number of data bytes in a record is limited to 32 (decimal). ISP commands

are summarized in Table 12. As a record is received by the P89LV51RB2/RC2/RD2, the

information in the record is stored internally and a checksum calculation is performed. The

operation indicated by the record type is not performed until the entire record has been

received. Should an error occur in the checksum, the P89LV51RB2/RC2/RD2 will send an

‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to

match the checksum in the record, then the command will be executed. In most cases,

successful reception of the record will be indicated by transmitting a ‘.’ character out the

serial port.

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8-bit microcontrollers with 80C51 core

Table 12. ISP hex record formats

Record type

Command/data function

Program User Code Memory

:nnaaaa00dd..ddcc

Where:

00

nn = number of bytes to program

aaaa = address

dd..dd = data bytes

cc = checksum

Example:

:100000000102030405006070809cc

End of File (EOF), no operation

:xxxxxx01cc

01

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

cc = checksum

Example:

:00000001FF

02

Set SoftICE mode

Following the next reset the device will enter the SoftICE mode. Will erase user

code memory, and erase device serial number.

:00000002cc

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

cc = checksum

Example:

:00000002FE

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Table 12. ISP hex record formats …continued

Record type

03

Command/data function

Miscellaneous Write functions

:nnxxxx03ffssddcc

Where:

nn = number of bytes in the record

xxxx = required ﬁeld but value is a ‘don’t care’

ff = subfunction code

ss = selection code

dd = data (if needed)

cc = checksum

Subfunction code = 01 (Erase block 0)

ff = 01

Subfunction code = 05 (Program security bit, Double Clock)

ff = 05

ss = 01 program security bit

ss = 05 program double clock bit

Subfunction code = 08 (Erase sector, 128 B)

ff = 08

ss = high byte of sector address (A15:8)

dd = low byte of sector address (A7, A6:0 ]= 0)

Example:

:0300000308E000F2 (erase sector at E000H)

Display Device Data or Blank Check

:05xxxx04sssseeeeffcc

04

Where

05 = number of bytes in the record

xxxx = required ﬁeld but value is a ‘don’t care’

04 = function code for display or blank check

ssss = starting address, MSB ﬁrst

eeee = ending address, MSB ﬁrst

ff = subfunction

00 = display data

01 = blank check

cc = checksum

Subfunction codes:

Example:

:0500000400001FFF00D9 (display from 0000H to 1FFFH)

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8-bit microcontrollers with 80C51 core

Table 12. ISP hex record formats …continued

Record type

05

Command/data function

Miscellaneous Read functions

:02xxxx05ffsscc

Where:

02 = number of bytes in the record

xxxx = required ﬁeld but value is a ‘don’t care’

05 = function code for misc read

ffss = subfunction and selection code

0000 = read manufacturer id

0001 = read device id 1

0002 = read boot code version

0700 = read security bit (00 SoftICE serial number match 0 SB 0 Double Clock)

cc = checksum

Example:

:020000050000F9 (display manufacturer id)

Direct load of baud rate

06

:02xxxx06HHLLcc

Where:

02 = number of bytes in the record

xxxx = required ﬁeld but value is a ‘don’t care’

HH = high byte of timer

LL = low byte of timer

cc = checksum

Example:

:02000006FFFFcc (load T2 = FFFF)

Reset serial number, erase user code, clear SoftICE mode

:xxxxxx07cc

07

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

07 = reset serial number function

cc = checksum

Example:

:00000007F9

08

Verify serial number

:nnxxxx08ss..sscc

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

08 = verify serial number function

ss..ss = serial number contents

cc = checksum

Example:

:03000008010203EF (verify serial number = 010203)

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8-bit microcontrollers with 80C51 core

Table 12. ISP hex record formats …continued

Record type

Command/data function

Write serial number

:nnxxxx09ss..sscc

Where:

09

xxxxxx = required ﬁeld but value is a ‘don’t care’

09 = write serial number function

ss..ss = serial number contents

cc = checksum

Example:

:03000009010203EE (write serial number = 010203)

Display serial number

:xxxxxx0Acc

0A

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

0A = display serial number function

cc = checksum

Example:

:0000000AF6

0B

Reset and run user code

:xxxxxx0Bcc

Where:

xxxxxx = required ﬁeld but value is a ‘don’t care’

0B = reset and run user code

cc = checksum

Example:

:0000000BF5

6.3.5 Using the serial number

This device has the option of storing a 31 B serial number along with the length of the

serial number (for a total of 32 B) in a non-volatile memory space. When ISP mode is

entered, the serial number length is evaluated to determine if the serial number is in use.

If the length of the serial number is programmed to either 00H or FFH, the serial number is

considered not in use. If the serial number is in use, reading, programming, or erasing of

the user code memory or the serial number is blocked until the user transmits a ‘verify

serial number’ record containing a serial number and length that matches the serial

number and length previously stored in the device. The user can reset the serial number

to all zeros and set the length to zero by sending the ‘reset serial number' record. In

addition, the ‘reset serial number’ record will also erase all user code.

6.3.6 IAP method

Several IAP calls are available for use by an application program to permit selective

erasing, reading and programming of ﬂash sectors, security bit, conﬁguration bytes, and

device id. All calls are made through a common interface, PGM_MTP. The programming

functions are selected by setting up the microcontroller’s registers before making a call to

PGM_MTP at 1FF0H. The IAP calls are shown in Table 13.

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Table 13. IAP function calls

IAP function

IAP call parameters

Read ID

Input parameters:

R1 = 00H

DPH = 00H

DPL = 00H = mfgr id

DPL = 01H = device id 1

DPL = 02H = boot code version number

Return parameter(s):

ACC = requested parameter

Input parameters:

R1 = 01H

Erase block 0

Return parameter(s):

ACC = 00 = pass

ACC = !00 = fail

Program User Code

Input parameters:

R1 = 02H

DPH = memory address MSB

DPL = memory address LSB

ACC = byte to program

Return parameter(s):

ACC = 00 = pass

ACC = !00 = fail

Read User Code

Input parameters:

R1 = 03H

DPH = memory address MSB

DPL = memory address LSB

Return parameter(s):

ACC = device data

Input parameters:

R1 = 05H

Program Security Bit, Double

Clock

DPL = 01H = security bit

DPL = 05H = Double Clock

Return parameter(s):

ACC = 00 = pass

ACC = !00 = fail

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Table 13. IAP function calls …continued

IAP function

IAP call parameters

Read Security Bit, Double Clock,

SoftICE

Input parameters:

ACC = 07H

Return parameter(s):

ACC = 000 S/N-match 0 SB 0 DBL_CLK

Input parameters:

Read Security Bit, Double Clock,

SoftICE

ACC = 07H

Return parameter(s):

ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK

Input parameters:

Erase sector

R1 = 08H

DPH = sector address high byte

DPL = sector address low byte

Return parameter(s):

ACC = 00 = pass

ACC = !00 = fail

6.4 Timers/counters 0 and 1

The two 16-bit Timer/counter registers: Timer 0 and Timer 1 can be conﬁgured to operate

either as timers or event counters (see Table 14 and Table 15).

In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can

think of it as counting machine cycles. Since a machine cycle consists of six oscillator

periods, the count rate is ¹⁄₆of the oscillator frequency.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once every machine cycle.

When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is

incremented. The new count value appears in the register in the machine cycle following

the one in which the transition was detected. Since it takes two machine cycles (12

oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is ¹⁄₁₂of

the oscillator frequency. There are no restrictions on the duty cycle of the external input

signal, but to ensure that a given level is sampled at least once before it changes, it should

be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection,

Timer 0 and Timer 1 have four operating modes from which to select.

The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function

register TMOD. These two timer/counters have four operating modes, which are selected

by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters.

Mode 3 is different. The four operating modes are described in the following text.

Table 14. TMOD - Timer/counter mode control register (address 89H) bit allocation

Not bit addressable; reset value: 0000 0000B; reset source(s): any source.

Bit

7

6

5

4

3

2

1

0

Symbol T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

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Table 15. TMOD - Timer/counter mode control register (address 89H) bit descriptions

Bit

Symbol

T1/T0

Description

Bits controlling Timer1/Timer0

GATE

Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’

INTx pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’

is enabled whenever ‘TRx’ control bit is set.

C/T

Gating Timer or Counter Selector cleared for Timer operation (input

from internal system clock). Set for Counter operation (input from ‘Tx’

input pin).

Table 16. TMOD - Timer/counter mode control register (address 89H) M1/M0 operating

mode

M1

0

M0

0

Operating mode

0

1

8048 timer ‘TLx’ serves as 5-bit prescaler

0

1

16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded; there

is no prescaler.

1

0

1

2

3

8-bit auto-reload Timer/counter ‘THx’ holds a value which

is to be reloaded into ‘TLx’ each time it overﬂows.

(Timer 0) TL0 is an 8-bit Timer/counter controlled by the

standard Timer 0 control bits. TH0 is an 8-bit timer only

controlled by Timer 1 control bits.

1

3

(Timer 1) Timer/counter 1 stopped.

Table 17. TCON - Timer/counter control register (address 88H) bit allocation

Bit addressable; reset value: 0000 0000B; reset source(s): any reset.

Bit

7

6

5

4

3

2

1

0

Symbol

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Table 18. TCON - Timer/counter control register (address 88H) bit descriptions

Bit

Symbol

Description

7

TF1

Timer 1 overﬂow ﬂag. Set by hardware on Timer/counter overﬂow.

Cleared by hardware when the processor vectors to Timer 1 Interrupt

routine, or by software.

6

5

TR1

TF0

Timer 1 Run control bit. Set/cleared by software to turn Timer/counter 1

on/off.

Timer 0 overﬂow ﬂag. Set by hardware on Timer/counter overﬂow.

Cleared by hardware when the processor vectors to Timer 0 Interrupt

routine, or by software.

4

3

TR0

IE1

Timer 0 Run control bit. Set/cleared by software to turn Timer/counter 0

on/off.

Interrupt 1 Edge ﬂag. Set by hardware when external interrupt 1

edge/low level is detected. Cleared by hardware when the interrupt is

processed, or by software.

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Table 18. TCON - Timer/counter control register (address 88H) bit descriptions …continued

Bit

Symbol

Description

2

IT1

Interrupt 1 Type control bit. Set/cleared by software to specify falling

edge/low level that triggers external interrupt 1.

1

IE0

IT0

Interrupt 0 Edge ﬂag. Set by hardware when external interrupt 0

edge/low level is detected. Cleared by hardware when the interrupt is

processed, or by software.

0

Interrupt 0 Type control bit. Set/cleared by software to specify falling

edge/low level that triggers external interrupt 0.

6.4.1 Mode 0

Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit

counter with a ﬁxed divide-by-32 prescaler. Figure 7 shows mode 0 operation.

overflow

C/T = 0

osc/6

TLn

THn

interrupt

TFn

Tn pin

(5-bits) (8-bits)

control

C/T = 1

TRn

TnGate

INTn pin

002aaa519

Fig 7. Timer/counter 0 or 1 in mode 0 (13-bit counter)

In this mode, the Timer register is conﬁgured as a 13-bit register. As the count rolls over

from all 1s to all 0s, it sets the Timer interrupt ﬂag TFn. The count input is enabled to the

Timer when TRn = 1 and either GATE = 0 or INTn = 1. Setting GATE = 1 allows the Timer

to be controlled by external input INTn, to facilitate pulse width measurements. TRn is a

control bit in the Special Function Register TCON (Figure 6). The GATE bit is in the TMOD

register.

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper

3 bits of TLn are indeterminate and should be ignored. Setting the run ﬂag (TRn) does not

clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 7). There are two

different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

6.4.2 Mode 1

Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)

are used. See Figure 8.

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overflow

C/T = 0

C/T = 1

TLn

THn

osc/6

Tn pin

interrupt

TFn

(8-bits) (8-bits)

control

TRn

TnGate

INTn pin

002aaa520

Fig 8. Timer/counter 0 or 1 in mode 1 (16-bit counter)

6.4.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter (TLn) with automatic reload, as

shown in Figure 9. Overﬂow from TLn not only sets TFn, but also reloads TLn with the

contents of THn, which must be preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 and Timer 1.

C/T = 0

overflow

osc/6

TLn

interrupt

TFn

(8-bits)

Tn pin

control

C/T = 1

reload

TRn

TnGate

THn

(8-bits)

INTn pin

002aaa521

Fig 9. Timer/counter 0 or 1 in mode 2 (8-bit auto-reload)

6.4.4 Mode 3

When timer 1 is in mode 3 it is stopped (holds its count). The effect is the same as setting

TR1 = 0.

Timer 0 in mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for

mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T,

T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the

‘Timer 1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in mode

3, the P89LV51RB2/RC2/RD2 can look like it has an additional Timer.

Note: When Timer 0 is in mode 3, Timer 1 can be turned on and off by switching it into

and out of its own mode 3. It can still be used by the serial port as a baud rate generator,

or in any application not requiring an interrupt.

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C/T = 0

C/T = 1

overflow

TL0

(8-bits)

osc/6

interrupt

TF0

T0 pin

control

TR0

TnGate

INT0 pin

overflow

TH0

(8-bits)

osc/2

TF1

interrupt

control

TR1

002aaa522

Fig 10. Timer/counter 0 mode 3 (two 8-bit counters)

6.5 Timer 2

Timer 2 is a 16-bit Timer/counter which can operate as either an event timer or an event

counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four

operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate

Generator which are selected according to Table 19 using T2CON (Table 20 and

Table 21) and T2MOD (Table 22 and Table 23).

Table 19. Timer 2 operating mode

RCLK + TCLK CP/RL2

TR2

1

T2OE

Mode

0

1

X

0

1

0

X

0

1

0

X

16-bit auto reload

16-bit capture

programmable clock-out

baud rate generator

off

1

0

Table 20. T2CON - Timer/counter 2 control register (address C8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Table 21. T2CON - Timer/counter 2 control register (address C8H) bit descriptions

Bit

Symbol

Description

7

TF2

Timer 2 overﬂow ﬂag set by a Timer 2 overﬂow and must be cleared by

software. TF2 will not be set when either RCLK or TCLK = 1 or when

Timer 2 is in Clock-out mode.

6

5

EXF2

RCLK

Timer 2 external ﬂag is set when Timer 2 is in capture, reload or

baud-rate mode, EXEN2 = 1 and a negative transition on T2EX occurs.

If Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to

the Timer 2 interrupt routine. EXF2 must be cleared by software.

Receive clock ﬂag. When set, causes the UART to use Timer 2

overﬂow pulses for its receive clock in modes 1 and 3. RCLK = 0

causes Timer 1 overﬂow to be used for the receive clock.

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Table 21. T2CON - Timer/counter 2 control register (address C8H) bit descriptions

Bit

Symbol

Description

4

TCLK

Transmit clock ﬂag. When set, causes the UART to use Timer 2

overﬂow pulses for its transmit clock in modes 1 and 3. TCLK = 0

causes Timer 1 overﬂows to be used for the transmit clock.

3

EXEN2

Timer 2 external enable ﬂag. When set, allows a capture or reload to

occur as a result of a negative transition on T2EX if Timer 2 is not being

used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore

events at T2EX.

2

1

TR2

Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.

Timer or counter select. (Timer 2)

C/T2

0 = internal timer (f_osc/ 6)

1 = external event counter (falling edge triggered; external clock’s

maximum rate = f_osc/12

0

CP/RL2

Capture/Reload ﬂag. When set, captures will occur on negative

transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will

occur either with Timer 2 overﬂows or negative transitions at T2EX

when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is

ignored and the timer is forced to auto-reload on Timer 2 overﬂow.

Table 22. T2MOD - Timer 2 mode control register (address C9H) bit allocation

Not bit addressable; Reset value: XX00 0000B.

Bit

7

6

5

4

3

2

1

0

Symbol

-

T2OE

DCEN

Table 23. T2MOD - Timer 2 mode control register (address C9H) bit descriptions

Bit

7 to 2

1

Symbol

-

Description

Reserved for future use. Should be set to ‘0’ by user programs.

T2OE

DCEN

Timer 2 Output Enable bit. Used in programmable clock-out mode only.

0

Down Count Enable bit. When set, this allows Timer 2 to be conﬁgured

as an up/down counter.

6.5.1 Capture mode

In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If

EXEN2 = 0, Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which

upon overﬂowing sets bit TF2, the Timer 2 overﬂow bit.

The capture mode is illustrated in Figure 11.

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OSC

÷6

C/T2 = 0

C/T2 = 1

TL2

TH2

TF2

(8-bits) (8-bits)

control

T2 pin

TR2

capture

timer 2

transition

detector

interrupt

RCAP2L RCAP2H

T2EX pin

EXF2

control

EXEN2

002aaa523

Fig 11. Timer 2 in Capture mode

This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the

IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added

feature that a 1-to-0 transition at external input T2EX causes the current value in the

Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H,

respectively.

In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like

TF2 can generate an interrupt (which vectors to the same location as Timer 2 overﬂow

interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to

determine which event caused the interrupt.

There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs

from T2EX, the counter keeps on counting T2 pin transitions or f_osc/ 6 pulses. Since once

loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2

interrupt is signalled it has to be serviced before a new capture event on T2EX pin occurs.

Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from

TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to

the previously reported interrupt.

6.5.2 Auto-reload mode (up or down counter)

In the 16-bit auto-reload mode, Timer 2 can be conﬁgured as either a timer or counter (via

C/T2 in T2CON), then programmed to count up or down. The counting direction is

determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register

(see Table 22 and Table 23). When reset is applied, DCEN = 0 and Timer 2 will default to

counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value

of the T2EX pin.

Figure 12 shows Timer 2 counting up automatically (DCEN = 0).

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OSC

÷6

C/T2 = 0

C/T2 = 1

TL2

TH2

TF2

(8-bits) (8-bits)

control

T2 pin

TR2

reload

timer 2

transition

detector

interrupt

RCAP2L RCAP2H

T2EX pin

EXF2

control

EXEN2

002aaa524

Fig 12. Timer 2 in auto-reload mode (DCEN = 0)

In this mode, there are two options selected by bit EXEN2 in T2CON register. If

EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overﬂow Flag) bit upon

overﬂow. This causes the Timer 2 registers to be reloaded with the 16-bit value in

RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software

means.

Auto reload frequency when Timer 2 is counting up can be determined from this formula:

Supply Frequency

(65536 (RCAP2H, RCAP2L))

(1)

--------------------------------------------------------------------------------

Where Supply frequency is either f_osc(C/T2 = 0) or frequency of signal on T2 pin

(C/T2 = 1).

If EXEN2 = 1, a 16-bit reload can be triggered either by an overﬂow or by a 1-to-0

transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if

enabled, can be generated when either TF2 or EXF2 is ‘1’.

Microcontroller’s hardware will need three consecutive machine cycles in order to

recognize the falling edge on T2EX and to set EXF2 = 1: in the ﬁrst machine cycle pin

T2EX has to be sampled as ‘1’; in the second machine cycle it has to be sampled as ‘0’,

and in the third machine cycle EXF2 will be set to ‘1’.

In Figure 13, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin

T2EX to control the direction of count. When a logic ‘1’ is applied at pin T2EX Timer 2 will

count up. Timer 2 will overﬂow at 0FFFFH and sets the TF2 ﬂag, which can then generate

an interrupt, if the interrupt is enabled. This timer overﬂow also causes the 16-bit value in

RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

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toggle

(down-counting reload value)

EXF2

FFH

OSC

÷6

C/T2 = 0

C/T2 = 1

underflow

overflow

TL2

TH2

timer 2

interrupt

TF2

(8-bits) (8-bits)

control

T2 pin

TR2

count direction

1 = up

0 = down

RCAP2L RCAP2H

(up-counting reload value)

T2EX pin

002aaa525

Fig 13. Timer 2 in Auto Reload mode (DCEN = 1)

A logic 0 applied at pin T2EX causes Timer 2 to count down. The timer will underﬂow

when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2

underﬂow sets the TF2 ﬂag and causes 0FFFFH to be reloaded into the timer registers

TL2 and TH2. The external ﬂag EXF2 toggles when Timer 2 underﬂows or overﬂows. This

EXF2 bit can be used as a 17th bit of resolution if needed.

6.5.3 Programmable clock-out

A 50 % duty cycle clock can be programmed to come out on pin T2 (P1.0). This pin,

besides being a I/O pin, has two additional functions. It can be programmed:

• To input the external clock for Timer/counter 2, or

• To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz

operating frequency.

To conﬁgure the Timer/counter 2 as a clock generator, bit C/T2 (in T2CON) must be

cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start

the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of

Timer 2 capture registers (RCAP2H, RCAP2L) as shown in Equation 2:

Oscillator Frequency

2 × (65536 (RCAP2H, RCAP2L))

-------------------------------------------------------------------------------------

(2)

Where (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit

unsigned integer.

In the Clock-Out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to

when it is used as a baud-rate generator.

6.5.4 Baud rate generator mode

Bits TCLK and/or RCLK in T2CON allow the UART transmit and receive baud rates to be

derived from either Timer 1 or Timer 2 (See Section 6.6 “UART” on page 37 for details).

When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When

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TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same

effect for the UART receive baud rate. With these two bits, the serial port can have

different receive and transmit baud rates – Timer 1 or Timer 2.

Figure 14 shows Timer 2 in baud rate generator mode.

OSC

÷2

C/T2 = 0

TL2

TH2

TX/RX baud rate

(8-bits) (8-bits)

control

C/T2 = 1

T2 pin

reload

TR2

transition

detector

RCAP2L RCAP2H

timer 2

interrupt

T2EX pin

EXF2

control

EXEN2

002aaa526

Fig 14. Timer 2 in Baud Rate Generator mode

The baud rate generation mode is like the auto-reload mode, when a rollover in TH2

causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and

RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2’s overﬂow rate given below:

Modes 1 and 3 baud rates = Timer 2 Overﬂow Rate / 16

The timer can be conﬁgured for either ‘timer’ or ‘counter’ operation. In many applications,

it is conﬁgured for ‘timer' operation (C/T2 = 0). Timer operation is different for Timer 2

when it is being used as a baud rate generator.

Usually, as a timer it would increment every machine cycle (i.e., ¹⁄₆the oscillator

frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the

baud rate formula is as follows:

Modes 1 and 3 baud rates =

Oscillator Frequency

(16 × (65536–(RCAP2H, RCAP2L)))

(3)

-----------------------------------------------------------------------------------------------

Where: (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit

unsigned integer.

The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in

T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an

interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the

baud rate generator mode. Also if the EXEN2 (T2 external enable ﬂag) is set, a 1-to-0

transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external ﬂag) but will

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not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is in

use as a baud rate generator, T2EX can be used as an additional external interrupt, if

needed.

When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2

and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The

RCAP2 registers may be read, but should not be written to, because a write might overlap

a reload and cause write and/or reload errors. The timer should be turned off (clear TR2)

before accessing the Timer 2 or RCAP2 registers. Table 24 shows commonly used baud

rates and how they can be obtained from Timer 2.

6.5.5 Summary of baud rate equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0)

the baud rate is:

Baud rate = Timer 2 overﬂow rate / 16

If Timer 2 is being clocked internally, the baud rate is:

Baud rate = f_osc/ (16 × (65536 − (RCAP2H, RCAP2L)))

Where f_osc= oscillator frequency

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten

as:

RCAP2H, RCAP2L = 65536 − f_osc/ (16 × baud rate)

Table 24. Timer 2 generated commonly used baud rates

Rate

Oscillator frequency Timer 2

RCAP2H

RCAP2L

FF

750 kBd

19.2 kBd

9.6 kBd

4.8 kBd

2.4 kBd

600 Bd

220 Bd

600 Bd

220 Bd

12 MHz

6 MHz

FF

FE

FB

F2

FD

F9

D9

B2

64

C8

1E

AF

8F

6 MHz

57

6.6 UART

The UART operates in all standard modes. Enhancements over the standard 80C51

UART include Framing Error detection, and automatic address recognition.

6.6.1 Mode 0

Serial data enters and exits through RXD, and TXD outputs the shift clock. Only 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₆of the CPU clock frequency.

The UART is conﬁgured to operate in this mode and outputs serial clock on TXD line no

matter whether it sends or receives data on the RXD line.

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6.6.2 Mode 1

8-bit microcontrollers with 80C51 core

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8

data bits (LSB ﬁrst), and a stop bit (logical 1). When data is received, the stop bit is stored

in RB8 in Special Function Register SCON. The baud rate is variable and is determined

by the Timer ¹⁄₂overﬂow rate.

6.6.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the

parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data

bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The

baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of the CPU clock frequency, as determined

by the SMOD1 bit in PCON.

6.6.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical 1). In fact, mode 3

is the same as mode 2 in all respects except baud rate. The baud rate in mode 3 is

variable and is determined by the Timer ¹⁄₂overﬂow rate.

Table 25. SCON - Serial port control register (address 98H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

Table 26. SCON - Serial port control register (address 98H) bit descriptions

Bit

Symbol

Description

7

SM0/FE

The usage of this bit is determined by SMOD0 in the PCON register. If

SMOD0 = 0, this bit is SM0, which with SM1, deﬁnes the serial port

mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the

receiver when an invalid stop bit is detected. Once set, this bit cannot

be cleared by valid frames but can only be cleared by software. (Note:

It is recommended to set up UART mode bits SM0 and SM1 before

setting SMOD0 to ‘1’.)

6

5

SM1

SM2

With SM0, deﬁnes the serial port mode (see Table 27).

Enables the multiprocessor communication feature in modes 2 and 3.

In mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if the

received 9th data bit (RB8) is ‘0’. In mode 1, if SM2 = 1 then RI will not

be activated if a valid stop bit was not received. In mode 0, SM2 should

be ‘0’.

4

3

REN

TB8

Enables serial reception. Set by software to enable reception. Clear by

software to disable reception.

The 9th data bit that will be transmitted in modes 2 and 3. Set or clear

by software as desired.

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Table 26. SCON - Serial port control register (address 98H) bit descriptions …continued

Bit

Symbol

Description

2

RB8

In modes 2 and 3, is the 9th data bit that was received. In mode 1, if

SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is

undeﬁned.

1

0

TI

Transmit interrupt ﬂag. Set by hardware at the end of the 8th bit time in

mode 0, or at the stop bit in the other modes, in any serial transmission.

Must be cleared by software.

RI

Receive interrupt ﬂag. Set by hardware at the end of the 8th bit time in

mode 0, or approximately halfway through the stop bit time in all other

modes. (See SM2 for exceptions). Must be cleared by software.

Table 27. SCON - Serial port control register (address 98H) SM0/SM1 mode deﬁnitions

SM0, SM1

0 0

UART mode

0: shift register

1: 8-bit UART

2: 9-bit UART

Baud rate

CPU clock / 6

variable

0 1

1 0

CPU clock / 32 or CPU

clock / 16

1 1

3: 9-bit UART

variable

6.6.5 Framing error

Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,

SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0

is set to ‘1’.

6.6.6 More about UART mode 1

Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is

sampled at a rate of 16 times whatever baud rate has been established. When a transition

is detected, the divide-by-16 counter is immediately reset to align its rollovers with the

boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th

counter states of each bit time, the bit detector samples the value of RXD. The value

accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise

rejection. If the value accepted during the ﬁrst bit time is not 0, the receive circuits are

reset and the unit goes back to looking for another 1-to-0 transition. This is to provide

rejection of false start bits. If the start bit proves valid, it is shifted into the input shift

register, and reception of the rest of the frame will proceed.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the

following conditions are met at the time the ﬁnal shift pulse is generated: (a) RI = 0, and

(b) either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If both

conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is

activated.

6.6.7 More about UART modes 2 and 3

Reception is performed in the same manner as in mode 1.

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The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the

following conditions are met at the time the ﬁnal shift pulse is generated: (a) RI = 0, and

(b) either SM2 = 0, or the received 9th data bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not

set. If both conditions are met, the received 9th data bit goes into RB8, and the ﬁrst 8 data

bits go into SBUF.

6.6.8 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In

these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is

stored in RB8. The UART can be programmed so that when the stop bit is received, the

serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit

SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it

ﬁrst sends out an address byte which identiﬁes the target slave. An address byte differs

from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte.

With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’.

However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each

slave can examine the received byte and see if it is being addressed or not. The

addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that

follow. The slaves that weren’t being addressed leave their SM2 bits set and ignore the

subsequent data bytes.

SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop

bit, although this is better done with the Framing Error ﬂag. When the UART receives data

in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is

received.

6.6.9 Automatic address recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain

addresses in the serial bit stream by using hardware to make the comparisons. This

feature saves a great deal of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This feature is enabled for

the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3,

the Receive Interrupt ﬂag (RI) will be automatically set when the received byte contains

either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th

information bit is a ‘1’ to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively

communicate with one or more slaves by invoking the Given slave address or addresses.

All of the slaves may be contacted by using the Broadcast address. Two Special Function

Registers are used to deﬁne the slave’s address, SADDR, and the address mask,

SADEN. SADEN is used to deﬁne which bits in the SADDR are to be used and which bits

are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the

‘Given’ address which the master will use for addressing each of the slaves. Use of the

Given address allows multiple slaves to be recognized while excluding others.

This device uses the methods presented in Figure 15 to determine if a ‘Given’ or

‘Broadcast’ address has been received or not.

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rx_byte(7)

saddr(7)

saden(7)

.

given_address_match

rx_byte(0)

saddr(0)

saden(0)

logic used by UART to detect 'given address' in received data

saddr(7)

saden(7)

rx_byte(7)

.

broadcast_address_match

.

saddr(0)

saden(0)

rx_byte(0)

logic used by UART to detect 'given address' in received data

002aaa527

Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor

communications is enabled

The following examples help to show the versatility of this scheme.

Example 1, slave 0:

SADDR = 1100 0000

SADEN = 1111 1101

---------------------------------------------------

Given = 1100 00X0

(4)

(5)

Example 2, slave 1:

SADDR = 1100 0000

SADEN = 1111 1110

---------------------------------------------------

Given = 1100 000X

In the above example value SADDR is the same and the SADEN data is used to

differentiate between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1.

Slave 1 requires a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be

1100 0010 since slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100

0001 since a ‘1’ in bit 0 will exclude slave 0. Both slaves can be selected at the same time

by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could

be addressed with 1100 0000.

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In a more complex system the following could be used to select slaves 1 and 2 while

excluding slave 0:

Example 1, slave 0:

SADDR = 1100 0000

SADEN = 1111 1001

---------------------------------------------------

Given = 1100 0XX0

(6)

(7)

(8)

Example 2, slave 1:

SADDR = 1110 0000

SADEN = 1111 1010

---------------------------------------------------

Given = 1110 0X0X

Example 3, slave 2:

SADDR = 1100 0000

SADEN = 1111 1100

---------------------------------------------------

Given = 1100 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits.

Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1

requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude

Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and

SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the

don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR

and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well

as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic

Addressing mode and allows the microcontroller to use standard UART drivers which do

not make use of this feature.

6.7 SPI

6.7.1 SPI features

• Master or slave operation

• 10 MHz bit frequency (maximum)

• LSB ﬁrst or MSB ﬁrst data transfer

• Four programmable bit rates

• End of transmission (SPIF)

• Write collision ﬂag protection (WCOL)

• Wake-up from Idle mode (slave mode only)

6.7.2 SPI description

The SPI allows high-speed synchronous data transfer between the

P89LV51RB2/RC2/RD2 and peripheral devices or between several

P89LV51RB2/RC2/RD2 devices. Figure 16 shows the correspondence between master

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and slave SPI devices. The SPICLK pin is the clock output and input for the master and

slave modes, respectively. The SPI clock generator will start following a write to the

master devices SPI data register. The written data is then shifted out of the MOSI pin on

the master device into the MOSI pin of the slave device. Following a complete

transmission of one byte of data, the SPI clock generator is stopped and the SPIF ﬂag is

set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and

the Serial Port Interrupt Enable bit (ES) are both set.

An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI

module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not

active and the MOSI/P1[5] port can also be used as an input port pin.

CPHA and CPOL control the phase and polarity of the SPI clock. Figure 17 and Figure 18

show the four possible combinations of these two bits.

MSB master LSB

MSB slave LSB

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPICLK

SS

SPICLK

SS

SPI

CLOCK GENERATOR

V

DD

V

SS

002aaa528

Fig 16. SPI master-slave interconnection

Table 28. SPCTL - SPI control register (address D5H) bit allocation

Bit addressable; reset source(s): any reset; reset value: 0000 0000B.

Bit

7

6

5

4

3

2

1

0

Symbol

SPIE

SPEN

DORD

MSTR

CPOL

CPHA

PSC1

PSC0

Table 29. SPCTL - SPI control register (address D5H) bit descriptions

Bit

7

Symbol

SPIE

Description

If both SPIE and ES are set to one, SPI interrupts are enabled.

SPI enable bit. When set enables SPI.

6

SPEN

DORD

5

Data transmission order. 0 = MSB ﬁrst; 1 = LSB ﬁrst in data

transmission.

4

3

MSTR

CPOL

Master/slave select. 1 = master mode, 0 = slave mode.

Clock polarity. 1 = SPICLK is high when idle (active LOW), 0 = SPICLK

is low when idle (active HIGH).

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Table 29. SPCTL - SPI control register (address D5H) bit descriptions …continued

Bit

Symbol

Description

2

CPHA

Clock Phase control bit. 1 = shift triggered on the trailing edge of the

clock; 0 = shift triggered on the leading edge of the clock.

1

0

PSC1

PSC0

SPI Clock Rate Select bit 1. Along with PSC0 controls the SPICLK rate

of the device when a master. PSC1 and PSC0 have no effect on the

slave. See Table 30.

SPI Clock Rate Select bit 0. Along with PSC1 controls the SPICLK rate

of the device when a master. PSC1 and PSC0 have no effect on the

slave. See Table 30.

Table 30. SPCTL - SPI control register (address D5H) clock rate selection

PSC1

PSC0

SPICLK = f_oscdivided by

0

1

0

1

0

1

4

16

64

128

Table 31. SPCFG - SPI status register (address AAH) bit allocation

Bit addressable; reset source(s): any reset; reset value: 0000 0000B.

Bit

7

6

5

4

3

2

1

0

Symbol

SPIF

WCOL

-

Table 32. SPCFG - SPI status register (address AAH) bit descriptions

Bit

Symbol

Description

7

SPIF

SPI interrupt ﬂag. Upon completion of data transfer, this bit is set to ‘1’.

If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is

cleared by software.

6

WCOL

-

Write Collision Flag. Set if the SPI data register is written to during data

transfer. This bit is cleared by software.

5 to 0

Reserved for future use. Should be set to ‘0’ by user programs.

SPICLK cycle #

(for reference)

1

2

3

4

5

6

7

8

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI

(from master)

MSB

6

5

4

3

2

1

LSB

MISO

(from slave)

6

5

4

3

2

1

SS (to slave)

002aaa529

Fig 17. SPI transfer format with CPHA = 0

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SPICLK cycle #

(for reference)

1

2

3

4

5

6

7

8

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI

(from master)

MSB

6

5

4

3

2

1

LSB

MISO

6

5

4

3

2

1

LSB

(from slave)

SS (to slave)

002aaa530

Fig 18. SPI transfer format with CPHA = 1

6.8 Watchdog timer

The device offers a programmable Watchdog Timer (WDT) for fail safe protection against

software deadlock and automatic recovery.

To protect the system against software deadlock, the user software must refresh the WDT

within a user-deﬁned time period. If the software fails to do this periodical refresh, an

internal hardware reset will be initiated if enabled (WDRE = 1). The software can be

designed such that the WDT times out if the program does not work properly.

The WDT in the device uses the system clock (XTAL1) as its time base. So strictly

speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment

every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used

as the reload register of the WDT.

The WDTS ﬂag bit is set by WDT overﬂow and is not changed by WDT reset. User

software can clear WDTS by writing ‘1' to it.

Figure 19 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control

WDT operation. During Idle mode, WDT operation is temporarily suspended, and

resumes upon an interrupt exit from idle.

The time-out period of the WDT is calculated as follows:

Period = (255 − WDTD) × 344064 × 1 / f_{CLK (XTAL1)}

where WDTD is the value loaded into the WDTD register and f_oscis the oscillator

frequency.

344064

clks

WDT reset

WDT

UPPER BYTE

CLK (XTAL1)

external reset

COUNTER

internal reset

WDTC

WDTD

002aaa531

Fig 19. Block diagram of programmable WDT

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Table 33. WDTC - Watchdog control register (address COH) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

WDOUT

WDRE

WDTS

WDT

SWDT

Table 34. WDTC - Watchdog control register (address COH) bit descriptions

Bit

7 to 5

4

Symbol

-

Description

Reserved for future use. Should be set to ‘0’ by user programs.

WDOUT

Watchdog output enable. When this bit and WDRE are both set, a

Watchdog reset will drive the reset pin active for 32 clocks.

3

2

WDRE

WDTS

Watchdog timer reset enable. When set enables a watchdog timer

reset.

Watchdog timer reset ﬂag, when set indicates that a WDT reset

occurred. Reset in software.

1

0

WDT

Watchdog timer refresh. Set by software to force a WDT reset.

SWDT

Start watchdog timer, when set starts the WDT. When cleared, stops

the WDT.

6.9 PCA

The PCA includes a special 16-bit Timer that has ﬁve 16-bit capture/compare modules

associated with it. Each of the modules can be programmed to operate in one of four

modes: rising and/or falling edge capture, software timer, high-speed output, or PWM.

Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0),

module 1 to P1.4 (CEX1), etc. Registers CH and CL contain the current values of the free

running up counting 16-bit PCA timer. The PCA timer is a common time base for all ﬁve

modules and can be programmed to run at: ¹⁄₆the oscillator frequency, ¹⁄₂the oscillator

frequency, the Timer 0 overﬂow, or the input on the ECI pin (P1.2). The timer count source

is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 35 and

Table 36).

16 bits

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

MODULE0

MODULE1

MODULE2

MODULE3

MODULE4

16 bits

PCA TIMER/COUNTER

time base for PCA modules

Module functions:

- 16-bit capture

- 16-bit timer

- 16-bit high speed output

- 8-bit PWM

- watchdog timer (module 4 only)

002aaa532

Fig 20. Programmable counter array

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In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL

which allows the PCA to stop during Idle mode, WDTE which enables or disables the

Watchdog function on module 4, and ECF which when set causes an interrupt and the

PCA overﬂow ﬂag CF (in the CCON SFR) to be set when the PCA timer overﬂows.

The watchdog timer function is implemented in module 4 of PCA.

The CCON SFR contains the run control bit (CR) for the PCA and the ﬂags for the PCA

timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set

by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the

PCA counter overﬂows and an interrupt will be generated if the ECF bit in the CMOD

register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON

register are the ﬂags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are

set by hardware when either a match or a capture occurs. These ﬂags can only be cleared

by software. All the modules share one interrupt vector. The PCA interrupt system is

shown in Figure 21.

Each module in the PCA has a special function register associated with it. These registers

are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that

control the mode that each module operates in.

The ECCFn bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)

enables the CCFn ﬂag in the CCON SFR to generate an interrupt when a match or

compare occurs in the associated module (see Figure 21).

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOGn bit (CCAPMn.2) when set causes the CEX output associated with the module

to toggle when there is a match between the PCA counter and the module’s

capture/compare register.

The match bit MATn (CCAPMn.3) when set will cause the CCFn bit in the CCON register

to be set when there is a match between the PCA counter and the module’s

capture/compare register.

The next two bits CAPNn (CCAPMn.4) and CAPPn (CCAPMn.5) determine the edge that

a capture input will be active on. The CAPN bit enables the negative edge, and the

CAPPn bit enables the positive edge. If both bits are set, both edges will be enabled and a

capture will occur for either transition.

The last bit in the register ECOMn (CCAPMn.6) when set enables the comparator

function.

There are two additional registers associated with each of the PCA modules. They are

CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a

capture occurs or a compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output.

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CCON

CF

CR

-

CCF4 CCF3 CCF2 CCF1 CCF0

(D8H)

PCA TIMER/COUNTER

MODULE0

MODULE1

MODULE2

IE.6

EC

IE.7

EA

to

interrupt

priority

decoder

MODULE3

MODULE4

CMOD.0

CCAPMn.0

ECCFn

ECF

002aaa533

Fig 21. PCA interrupt system

Table 35. CMOD - PCA counter mode register (address D9H) bit allocation

Not bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

CIDL

WDTE

-

CPS1

CPS0

ECF

Table 36. CMOD - PCA counter mode register (address D9H) bit descriptions

Bit

Symbol

Description

7

CIDL

Counter Idle Control: CIDL = 0 programs the PCA Counter to continue

functioning during Idle mode. CIDL = 1 programs it to be gated off

during idle.

6

WDTE

-

Watchdog Timer Enable: WDTE = 0 disables watchdog timer function

on module 4. WDTE = 1 enables it.

5 to 3

2 to 1

Reserved for future use. Should be set to ‘0’ by user programs.

PCA Count Pulse Select (see Table 37 below).

CPS1,

CPS0

0

ECF

PCA Enable Counter Overﬂow Interrupt: ECF = 1 enables CF bit in

CCON to generate an interrupt. ECF = 0 disables that function.

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Table 37. CMOD - PCA counter mode register (address D9H) count pulse select

CPS1

CPS0

Select PCA input

0

1

0

1

0

1

0 Internal clock, f_osc/ 6

1 Internal clock, f_osc/ 2

2 Timer 0 overﬂow

3 External clock at ECI/P1.2 pin (maximum rate = f_osc/ 4)

Table 38. CCON - PCA counter control register (address 0D8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

Table 39. CCON - PCA counter control register (address 0D8H) bit descriptions

Bit

Symbol

Description

7

CF

PCA Counter Overﬂow Flag. Set by hardware when the counter rolls

over. CF ﬂags an interrupt if bit ECF in CMOD is set. CF may be set by

either hardware or software but can only be cleared by software.

6

CR

PCA Counter Run Control Bit. Set by software to turn the PCA counter

on. Must be cleared by software to turn the PCA counter off.

5

4

-

Reserved for future use. Should be set to ‘0’ by user programs.

CCF4

PCA Module 4 Interrupt Flag. Set by hardware when a match or

capture occurs. Must be cleared by software.

3

2

1

0

CCF3

CCF2

CCF1

CCF0

PCA Module 3 Interrupt Flag. Set by hardware when a match or

capture occurs. Must be cleared by software.

PCA Module 2 Interrupt Flag. Set by hardware when a match or

capture occurs. Must be cleared by software.

PCA Module 1 Interrupt Flag. Set by hardware when a match or

capture occurs. Must be cleared by software.

PCA Module 0 Interrupt Flag. Set by hardware when a match or

capture occurs. Must be cleared by software.

Table 40. CCAPMn - PCA modules compare/capture register (address CCAPM0: 0DAH,

CCAPM1: 0DBH, CCAPM2: 0DCH, CCAPM3: 0DDH, CCAPM4: 0DEH) bit

allocation

Not bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

ECOMn CAPPn CAPNn

MATn

TOGn

PWMn

ECCFn

Table 41. CCAPMn - PCA modules compare/capture register (address CCAPM0: 0DAH,

CCAPM1: 0DBH, CCAPM2: 0DCH, CCAPM3: 0DDH, CCAPM4: 0DEH) bit

descriptions

Bit

7

Symbol

-

Description

Reserved for future use. Should be set to ‘0’ by user programs.

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

6

ECOMn

CAPPn

CAPNn

5

4

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Table 41. CCAPMn - PCA modules compare/capture register (address CCAPM0: 0DAH,

CCAPM1: 0DBH, CCAPM2: 0DCH, CCAPM3: 0DDH, CCAPM4: 0DEH) bit

descriptions …continued

Bit

Symbol

Description

3

MATn

Match. When MATn = 1 a match of the PCA counter with this module’s

compare/capture register causes the CCFn bit in CCON to be set,

ﬂagging an interrupt.

2

1

0

TOGn

Toggle. When TOGn = 1, a match of the PCA counter with this

module’s compare/capture register causes the CEXn pin to toggle.

PWMn

ECCFn

Pulse Width Modulation mode. PWMn = 1 enables the CEXn pin to be

used as a pulse-width modulated output.

Enable CCF Interrupt. Enables compare/capture ﬂag CCFn in the

CCON register to generate an interrupt.

Table 42. PCA module modes (CCAPMn register)

ECOMn CAPPn

CAPNn MATn

TOGn

PWMn

ECCFn

Module function

0

1

0

no operation

X

16-bit capture by a positive-edge trigger on

CEXn

X

0

1

0

X

16-bit capture by a negative-edge trigger on

CEXn

X

1

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

16-bit capture by any transition on CEXn

16-bit software timer

16-bit high-speed output

8-bit PWM

X

Watchdog timer

6.9.1 PCA capture mode

To use one of the PCA modules in the capture mode (Figure 22) either one or both of the

CCAPM bits CAPNn and CAPPn for that module must be set. The external CEX input for

the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA

hardware loads the value of the PCA counter registers (CH and CL) into the module’s

capture registers (CCAPnL and CCAPnH).

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CCON

(D8H)

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

PCA

interrupt

(to CCFn)

PCA timer/counter

CH

CL

capture

CEXn

CCAPnH CCAPnL

CCAPMn, n = 0 to 4

(DAH to DEH)

-

ECOMn

0

CAPPn

CAPNn

MATn

0

TOGn

0

PWMn

0

ECCFn

002aaa538

Fig 22. PCA capture mode

If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR

are set then an interrupt will be generated.

6.9.2 16-bit software timer mode

The PCA modules can be used as software timers (Figure 23) by setting both the ECOMn

and MATn bits in the modules CCAPMn register. The PCA timer will be compared to the

module’s capture registers and when a match occurs an interrupt will occur if the CCFn

(CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

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CCON

(D8H)

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

write to

CCAPnH reset

(to CCFn)

PCA

CCAPnH

CCAPnL

interrupt

write to

CCAPnL

enable

match

0

1

16-BIT COMPARATOR

CH

CL

PCA timer/counter

CCAPMn, n = 0 to 4

(DAH to DEH)

-

ECOMn

CAPPn

0

CAPNn

0

MATn

1

TOGn

0

PWMn

0

ECCFn

002aaa539

Fig 23. PCA compare mode

6.9.3 High-speed output mode

In this mode (Figure 24) the CEX output (on port 1) associated with the PCA module will

toggle each time a match occurs between the PCA counter and the module’s capture

registers. To activate this mode the TOGn, MATn, and ECOMn bits in the module’s

CCAPMn SFR must be set.

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CCON

(D8H)

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

write to

CCAPnH reset

(to CCFn)

PCA

interrupt

CCAPnH

CCAPnL

write to

CCAPnL

enable

match

0

1

16-BIT COMPARATOR

CH

CL

PCA timer/counter

toggle

CEXn

CCAPMn, n = 0 to 4

(DAH to DEH)

-

ECOMn

CAPPn

0

CAPNn

0

MATn

1

TOGn

0

PWMn

0

ECCFn

002aaa540

Fig 24. PCA high-speed output mode

6.9.4 PWM mode

All of the PCA modules can be used as PWM outputs (Figure 25). Output frequency

depends on the source for the PCA timer.

CCAPnH

CCAPnL

0

CL < CCAPnL

enable

CEXn

8-BIT COMPARATOR

CL ≥ CCAPnL

CL

1

PCA timer/counter

CCAPMn, n = 0 to 4

(DAH to DEH)

-

ECOMn

1

CAPPn

CAPNn

MATn

0

TOGn

PWMn

1

ECCFn

1

0

002aaa541

Fig 25. PCA PWM mode

All of the modules will have the same frequency of output because they all share only one

PCA timer. The duty cycle of each module is independently variable using the module’s

capture register CCAPnL. When the value of the PCA CL SFR is less than the value in the

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module’s CCAPnL SFR the output will be LOW, when it is equal to or greater than, the

output will be HIGH. When CL overﬂows from FF to 00, CCAPnL is reloaded with the

value in CCAPnH. This allows updating the PWM without glitches. The PWMn and

ECOMn bits in the module’s CCAPMn register must be set to enable the PWM mode.

6.9.5 PCA watchdog timer

An on-board watchdog timer is available with the PCA to improve the reliability of the

system without increasing chip count. Watchdog timers are useful for systems that are

susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA

module that can be programmed as a Watchdog. However, this module can still be used

for other modes if the Watchdog is not needed. Figure 25 shows a diagram of how the

Watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the

other compare modes, this 16-bit value is compared to the PCA timer value. If a match is

allowed to occur, an internal reset will be generated. This will not cause the RST pin to be

driven HIGH.

User’s software then must periodically change (CCAP4H, CCAP4L) to keep a match from

occurring with the PCA timer (CH, CL). This code is given in the WATCHDOG routine

shown below.

In order to hold off the reset, the user has three options:

• Periodically change the compare value so it will never match the PCA timer.

• Periodically change the PCA timer value so it will never match the compare values.

• Disable the Watchdog by clearing the WDTE bit before a match occurs and then

re-enable it.

The ﬁrst two options are more reliable because the watchdog timer is never disabled as in

option #3. If the program counter ever goes astray, a match will eventually occur and

cause an internal reset. The second option is also not recommended if other PCA

modules are being used. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most

applications the ﬁrst solution is the best option.

;CALL the following WATCHDOG subroutine periodically.

CLR

MOV

EA

;Hold off interrupts

;Next compare value is within 255 counts of

current PCA timer value

CCAP4L,#00

MOV

SETB

RET

CCAP4H,CH

EA

;Re-enable interrupts

This routine should not be part of an interrupt service routine, because if the program

counter goes astray and gets stuck in an inﬁnite loop, interrupts are still serviced and the

Watchdog continues to reset. Thus, the purpose of the Watchdog would be defeated.

Instead, call this subroutine from the main program within 2¹⁶count of the PCA timer.

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6.10 Security bit

The Security Bit protects against software piracy and prevents the contents of the ﬂash

from being read by unauthorized parties in Parallel Programmer mode. It also protects

against code corruption resulting from accidental erasing and programming to the internal

ﬂash memory.

When the Security Bit is activated, all parallel programming commands except for

Chip-Erase are ignored (thus the device cannot be read). However, ISP reading, writing,

or erasing of the user’s code can still be performed if the serial number and length has not

been programmed. Therefore, when a user requests to program the Security Bit, the

programmer should prompt the user and program a serial number into the device.

6.11 Interrupt priority and polling sequence

The device supports eight interrupt sources under a four level priority scheme. Table 43

summarizes the polling sequence of the supported interrupts. Note that the SPI serial

interface and the UART share the same interrupt vector. (See Figure 26).

Table 43. Interrupt polling sequence

Description

Interrupt ﬂag

Vector address Interrupt

enable bit

Interrupt

priority bit

Service

priority

Wake-up

power-down

External

IE0

0003H

EX0

PX0/H

1 (highest)

yes

interrupt 0

Brownout

T0

-

004BH

000BH

0013H

EBO

ET0

EX1

PBO/H

PT0/H

PX1/H

2

3

4

no

TF0

IE1

no

External

yes

interrupt 1

T1

TF1

001BH

0033H

0023H

002BH

ET1

EC

PT1/H

PPCH

PS/H

5

6

7

8

no

PCA

UART/SPI

T2

CF/CCFn

TI/RI/SPIF

TF2, EXF2

ES

ET2

PT2/H

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highest

priority

interrupt

IP/IPH/IPA/IPAH

registers

IE and IEA

registers

0

INT0#

IT0

IE0

1

brownout

interrupt

polling

sequence

TF0

0

1

INT1#

IT1

IE1

TF1

ECF

CF

CCFn

ECCFn

SPIE

RI

TI

SPIF

TF2

EXF2

lowest

priority

interrupt

global

disable

individual

enables

002aaa544

Fig 26. Interrupt structure

Table 44. IEN0 - Interrupt enable register 0 (address A8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

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Table 45. IEN0 - Interrupt enable register 0 (address A8H) bit descriptions

Bit

Symbol

Description

7

EA

Interrupt Enable Bit: EA = 1 interrupt(s) can be serviced, EA = 0

interrupt servicing disabled.

6

5

4

3

2

1

0

EC

PCA Interrupt Enable bit.

ET2

ES

Timer 2 Interrupt Enable.

Serial Port Interrupt Enable.

Timer 1 Overﬂow Interrupt Enable.

External Interrupt 1 Enable.

Timer 0 Overﬂow Interrupt Enable.

External Interrupt 0 Enable.

ET1

EX1

ET0

EX0

Table 46. IEN1 - Interrupt enable register 1 (address E8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

EBO

-

Table 47. IEN1 - Interrupt enable register 1 (address E8H) bit descriptions

Bit

Symbol

Description

7 to 4

3

-

Reserved for future use. Should be set to ‘0’ by user programs.

Brownout Interrupt Enable. 1 = enable, 0 = disable.

EBO

-

2 to 0

Reserved for future use. Should be set to ‘0’ by user programs.

Table 48. IP0 - Interrupt priority 0 low register (address B8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

PPC

PT2

PS

PT1

PX1

PT0

PX0

Table 49. IP0 - Interrupt priority 0 low register (address B8H) bit descriptions

Bit

7

Symbol

-

Description

Reserved for future use. Should be set to ‘0’ by user programs.

PCA interrupt priority LOW bit.

6

PPC

PT2

PS

5

Timer 2 interrupt priority LOW bit.

Serial Port interrupt priority LOW bit.

Timer 1 interrupt priority LOW bit.

External interrupt 1 priority LOW bit.

Timer 0 interrupt priority LOW bit.

External interrupt 0 priority LOW bit.

4

3

PT1

PX1

PT0

PX0

2

1

0

Table 50. IP0H - Interrupt priority 0 high register (address B7H) bit allocation

Not bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

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Table 51. IP0H - Interrupt priority 0 high register (address B7H) bit descriptions

Bit

7

Symbol

-

Description

Reserved for future use. Should be set to ‘0’ by user programs.

PCA interrupt priority HIGH bit.

6

PPCH

PT2H

PSH

5

Timer 2 interrupt priority HIGH bit.

Serial Port interrupt priority HIGH bit.

Timer 1 interrupt priority HIGH bit.

External interrupt 1 priority HIGH bit.

Timer 0 interrupt priority HIGH bit.

External interrupt 0 priority HIGH bit.

4

3

PT1H

PX1H

PT0H

PX0H

2

1

0

Table 52. IP1 - Interrupt priority 1 register (address F8H) bit allocation

Bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

PBO

-

Table 53. IP1 - Interrupt priority 1 register (address F8H) bit descriptions

Bit

Symbol

Description

7 to 5

4

-

Reserved for future use. Should be set to ‘0’ by user programs.

Brownout interrupt priority bit.

PBO

-

3 to 0

Reserved for future use. Should be set to ‘0’ by user programs.

Table 54. IP1H - Interrupt priority 1 high register (address F7H) bit allocation

Not bit addressable; reset value: 00H.

Bit

7

6

5

4

3

2

1

0

Symbol

-

PBOH

-

Table 55. IP1H - Interrupt priority 1 high register (address F7H) bit descriptions

Bit

Symbol

Description

7 to 5

4

-

Reserved for future use. Should be set to ‘0’ by user programs.

Brownout interrupt priority bit.

PBOH

-

3 to 0

Reserved for future use. Should be set to ‘0’ by user programs.

6.12 Power-saving modes

The device provides two power saving modes of operation for applications where power

consumption is critical. The two modes are Idle and Power-down, see Table 56.

6.12.1 Idle mode

Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the Program

Counter (PC) is stopped. The system clock continues to run and all interrupts and

peripherals remain active. The on-chip RAM and the special function registers hold their

data during this mode.

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The device exits Idle mode through either a system interrupt or a hardware reset. When

exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits

Idle mode. After exiting the Interrupt Service Routine, the interrupted program resumes

execution beginning at the instruction immediately following the instruction which invoked

the Idle mode. A hardware reset starts the device similar to a power-on reset.

6.12.2 Power-down mode

The Power-down mode is entered by setting the PD bit in the PCON register. In the

Power-down mode, the clock is stopped and external interrupts are active for level

sensitive interrupts only. SRAM contents are retained during Power-down mode, and the

minimum V_DDlevel is 2.0 V.

The device exits Power-down mode through either an enabled external level sensitive

interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits

Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must

hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon

interrupt signal restored to logic V_IH, the interrupt service routine program execution

resumes beginning at the instruction immediately following the instruction which invoked

Power-down mode. A hardware reset starts the device similar to power-on reset.

To exit properly out of Power-down mode, the reset or external interrupt should not be

executed before the V_DDline is restored to its normal operating voltage. Be sure to hold

V_DDvoltage long enough at its normal operating level for the oscillator to restart and

stabilize (normally less than 10 ms).

Table 56. Power-saving modes

Mode

Initiated by

State of MCU

Exited by

Idle mode

Software (Set IDL bit in

Clock is running. Interrupts,

Enabled interrupt or hardware reset. Start of

PCON) MOV PCON, #01H serial port and timers/counters interrupt clears IDL bit and exits Idle mode,

are active. Program Counter is after the ISR (Interrupt Service Routine)

stopped. ALE and PSEN

signals are HIGH level during

Idle. All registers remain

unchanged.

RETI (Return from Interrupt) instruction,

program resumes execution beginning at

the instruction following the one that invoked

Idle mode. A user could consider placing

two or three NOP (No Operation)

instructions after the instruction that invokes

Idle mode to eliminate any problems. A

hardware reset restarts the device similar to

a power-on reset.

Power-down

mode

Software (Set PD bit in

Clock is stopped. On-chip

Enabled external level sensitive interrupt or

hardware reset. Start of interrupt clears PD

bit and exits Power-down mode, after the

ISR RETI instruction program resumes

execution beginning at the instruction

PCON) MOV PCON, #02H SRAM and SFR data is

maintained. ALE and PSEN

signals are LOW level during

power-down. External

Interrupts are only active for

level sensitive interrupts, if

enabled.

following the one that invoked Power-down

mode. A user could consider placing two or

three NOP instructions after the instruction

that invokes Power-down mode to eliminate

any problems. A hardware reset restarts the

device similar to a power-on reset.

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6.13 System clock and clock options

6.13.1 Clock input options and recommended capacitor values for oscillator

Shown in Figure 27 are the input and output (XTAL1, XTAL2) of an internal inverting

ampliﬁer, which can be conﬁgured for use as an on-chip oscillator.

When driving the device from an external clock source, XTAL2 should be left disconnected

and XTAL1 should be driven.

At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to

interaction between the ampliﬁer and its feedback capacitance. However, the capacitance

will not exceed 15 pF once the external signal meets the V_ILand V_IHspeciﬁcations.

Crystal manufacturer, supply voltage, and other factors may cause circuit performance to

differ from one application to another. C1 and C2 should be adjusted appropriately for

each design. Table 57 shows the typical values for C1 and C2 vs. crystal type for various

frequencies.

Table 57. Recommended values for C1 and C2 by crystal type

Crystal

Quartz

C1 = C2

20 pF to 30 pF

40 pF to 50 pF

Ceramic

More speciﬁc information about on-chip oscillator design can be found in the FlashFlex51

Oscillator Circuit Design Considerations application note.

6.13.2 Clock doubling option

By default, the device runs at 12 clocks per machine cycle (X1 mode). The device has a

clock doubling option to speed up to 6 clocks per machine cycle (see Table 58). Clock

double mode can be enabled either by an external programmer or using IAP. When set,

the EDC bit in FST register will indicate 6-clock mode.

The clock double mode is only for doubling the internal system clock and the internal ﬂash

memory, i.e. EA = 1. To access the external memory and the peripheral devices, careful

consideration must be taken. Also note that the crystal output (XTAL2) frequency will not

be doubled.

C

2

n.c.

XTAL2

XTAL1

XTAL2

XTAL1

external

oscillator

signal

C

1

V

SS

002aaa545

002aaa546

On-chip oscillator

External clock drive

Fig 27. Oscillator characteristics

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Table 58. Clock doubling features

Device Standard mode (X1)

Clocks per Maximum

Clock double mode (X2)

Clocks per Maximum

machine cycle external clock

frequency (MHz)

machine cycle external clock

frequency (MHz)

P89LV51RB2/RC2/RD2 12

33

6

16

Table 59. FST - Flash status register (address B6) bit allocation

Not Bit addressable; reset value: xxxx x0xxB.

Bit

7

6

5

4

3

2

1

0

Symbol

-

SB

-

EDC

-

Table 60. FST - Flash status register (address B6) bit descriptions

Bit

Symbol

Description

7

-

Reserved for future use. Should be set to ‘0’ by user programs.

Security bit.

6

SB

5 to 4

3

-

Reserved for future use. Should be set to ‘0’ by user programs.

Enable double clock.

EDC

-

2 to 0

Reserved for future use. Should be set to ‘0’ by user programs.

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7. Limiting values

Table 61. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

−55

−65

−0.5

Max

Unit

°C

V

bias ambient temperature

storage temperature

input voltage

+125

+150

V_I

on EA pin to V_SS

+14

V_n

voltage on any other pin

except V_SS; with respect to

V_DD

V_DD+ 0.5

V

I_OL(I/O)

LOW-level output current per

input/output pin

pins P1.5, P1.6, P1.7

all other pins

-

20

15

1.5

mA

W

P_tot(pack)

total power dissipation per package

based on package heat

transfer, not device power

consumption

8. Static characteristics

Table 62. Static characteristics

T_amb= 0 °C to +70 °C or −40 °C to +85 °C; V_DD= 2.7 V to 3.6 V; V_SS= 0 V.

Symbol

n_endu(ﬂ)

t_ret(ﬂ)

I_latch

Parameter

Conditions

Min

Max

Unit

cycles

years

mA

V

[1]

endurance of ﬂash memory

ﬂash memory retention time

I/O latch-up current

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard 78

2.7 V < V_DD< 3.6 V

XTAL1, RST

10000

-

100

-

100 + I_DD

−0.5

-

V_IL

LOW-level input voltage

HIGH-level input voltage

+0.7

V_IH

0.2V_DD+ 0.9

0.7V_DD

V_DD+ 0.5

V

V_OL

LOW-level output voltage

V_DD= 2.7 V; ports 1.5, 1.6,

1.7

I_OL= 16 mA

-

1.0

V

[2][3][4]

V_DD= 2.7 V; ports 1, 2, 3,

except PSEN, ALE

I_OL= 100 µA

I_OL= 1.6 mA

I_OL= 3.5 mA

-

0.3

V

0.45

1.0

V_DD= 2.7 V; port 0, PSEN,

ALE

I_OL= 200 µA

-

0.3

V

I_OL= 3.2 mA

0.45

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Table 62. Static characteristics …continued

T_amb= 0 °C to +70 °C or −40 °C to +85 °C; V_DD= 2.7 V to 3.6 V; V_SS= 0 V.

Symbol

Parameter

Conditions

Min

Max

Unit

[5]

V_OH

HIGH-level output voltage

V_DD= 2.7 V; ports 1, 2, 3,

ALE, PSEN

I_OH= −10 µA

I_OH= −30 µA

I_OH= −60 µA

V

_DD− 0.3

-

V

_DD− 0.7

_DD− 1.5

V_DD= 2.7 V; port 0 in

External Bus mode

I_OH= −200 µA

I_OH= −3.2 mA

V

_DD− 0.3

_DD− 0.7

-

V

-

V

V_bo

I_IL

brownout trip voltage

2.35

2.55

−75

−650

±10

V

LOW-level input current

HIGH-LOW transition current

input leakage current

V_I= 0.4 V; ports 1, 2, 3

V_I= 2 V; ports 1, 2, 3

-

µA

[6]

[7]

I_THL

I_LI

0.45 V < V_I< V_DD− 0.3 V;

port 0

R_pd

pull-down resistance

input capacitance

on pin RST

-

225

15

kΩ

C_iss

1 MHz; T_amb= 25 °C

f_osc= 12 MHz

pF

I_DD(oper)

operating supply current

11.5

30

mA

f_osc= 33 MHz

I_DD(idle)

Idle mode supply current

f_osc= 12 MHz

8.5

21

f_osc= 33 MHz

I_DD(pd)

Power-down mode supply

current

minimum V_DD= 2 V

T_amb= 0 °C to +70 °C

T_amb= −40 °C to +85 °C

-

45

55

µA

[1] This parameter is measured only for initial qualiﬁcation and after a design or process change that could affect this parameter.

[2] Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

a) Maximum I_OLper 8-bit port: 26 mA

b) Maximum I_OLtotal for all outputs: 71 mA

c) If I_OLexceeds the test condition, V_OHmay exceed the related speciﬁcation. Pins are not guaranteed to sink current greater than the

listed test conditions.

[3] Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V_OLof ALE and Ports 1 and 3. The noise due

to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to

qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.

[4] Load capacitance for Port 0, ALE and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[5] Capacitive loading on Ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the V_DD− 0.7 V speciﬁcation when

the address bits are stabilizing.

[6] Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V_Iis approximately 2 V.

[7] Pin capacitance is characterized but not tested. Pin EA = 25 pF (max).

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001aak852

30

(1)

I

DD

(mA)

20

(2)

10

(3)

(4)

0

5

10

15

20

25

30

35

internal clock frequency (MHz)

(1) Maximum I_DD(oper)

(2) Maximum I_DD(idle)

(3) Typical I_DD(oper)

(4) Typical I_DD(idle)

Fig 28. Supply current versus frequency

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9. Dynamic characteristics

Table 63. Dynamic characteristics

Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF; T_amb= 0 °C to +70 °C or −40 °C to +85 °C; V_DD= 2.7 V to 3.6 V at 33 MHz; V_SS= 0 V.^[1][2]

Symbol Parameter

Conditions

X1 mode

X2 mode

IAP

Min

Typ

Max

Unit

MHz

ns

f_osc

oscillator frequency

0

-

33

0

16

0.25

33

t_LHLL

t_AVLL

t_LLAX

t_LLIV

ALE pulse width

2T_cy(clk)− 15

-

address valid to ALE LOW time

address hold after ALE LOW time

ALE LOW to valid instruction in time

ALE LOW to PSEN LOW time

PSEN pulse width

T

-

_cy(clk)− 25

-

ns

_cy(clk)− 25

-

ns

4T_cy(clk)− 65

ns

t_LLPL

t_PLPH

t_PLIV

T

-

_cy(clk)− 25

-

ns

_cy(clk)− 25

-

ns

PSEN LOW to valid instruction in time

input instruction hold after PSEN time

input instruction ﬂoat after PSEN time

PSEN to address valid time

address to valid instruction in time

PSEN LOW to address ﬂoat time

RD LOW pulse width

3T_cy(clk)− 55

ns

t_PXIX

0

-

ns

t_PXIZ

T

-

_cy(clk)− 5

ns

t_PXAV

t_AVIV

T_cy(clk)− 8

ns

-

5T_cy(clk)− 80

ns

t_PLAZ

t_RLRH

t_WLWH

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_WHQX

t_QVWH

t_RLAZ

t_WHLH

-

10

ns

6T_cy(clk)− 40

-

ns

WR LOW pulse width

6T_cy(clk)− 40

-

ns

RD LOW to valid data in time

data hold after RD time

-

5T_cy(clk)− 90

ns

0

-

ns

data ﬂoat after RD time

-

2T_cy(clk)− 25

ns

ALE LOW to valid data in time

address to valid data in time

ALE LOW to RD or WR LOW time

address to RD or WR LOW time

data hold after WR time

-

8T_cy(clk)− 90

ns

-

9T_cy(clk)− 90

ns

3T_cy(clk)− 25

4T_cy(clk)− 75

3T_cy(clk)+ 25

ns

-

ns

T_cy(clk)− 27

-

ns

data output valid to WR HIGH time

RD LOW to address ﬂoat time

RD or WR HIGH to ALE HIGH time

7T_cy(clk)− 70

-

ns

-

0

ns

T_cy(clk)− 25

T_cy(clk)+ 25

ns

[1] T_cy(clk)= 1 / f_osc

.

[2] Calculated values are for 6-clock mode only.

P89LV51RB2_RC2_RD2_5

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

9.1 Explanation of symbols

Each timing symbol has 5 characters. The ﬁrst character is always a ‘T’ (stands for time).

The other characters, depending on their positions, stand for the name of a signal or the

logical status of that signal. The characters are described below:

A — Address

C — Clock

D — Input data

H — Logic level HIGH

I — Instruction (program memory contents)

L — Logic level LOW or ALE

P — PSEN

Q — Output data

R — RD signal

T — Time

V — Valid

W — WR signal

X — No longer a valid logic level

Z — High impedance (Float)

Example:

t_AVLL= Address valid to ALE LOW time

t_LLPL= ALE LOW to PSEN LOW time

t

LHLL

ALE

t

PLPH

t

AVLL

LLIV

t

LLPL

t

PLIV

PSEN

t

PXAV

t

PLAZ

t

PXIZ

PXIX

INSTR IN

t

LLAX

t

A0 to A7

port 0

port 2

A0 to A7

t

AVIV

A8 to A15

002aaa548

Fig 29. External program memory read cycle

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Product data sheet

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

ALE

t

WHLH

PSEN

t

LLDV

t

RLRH

LLWL

RD

t

LLAX

RHDZ

t

AVLL

t

RLAZ

t

RHDX

RLDV

A0 to A7

from RI to DPL

port 0

port 2

DATA IN

A0 to A7 from PCL

A0 to A15 from PCH

INSTR IN

t

AVWL

t

AVDV

P2.0 to P2.7 or A8 to A15 from DPH

002aaa549

Fig 30. External data memory read cycle

t

LHLL

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

t

QVWH

A0 to A7 from RI or DPL

DATA OUT

A0 to A7 from PCL

INSTR IN

port 0

port 2

t

AVWL

P2[7:0] or A8 to A15 from DPH

A8 to A15 from PCH

002aaa550

Fig 31. External data memory write cycle

P89LV51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 15 December 2009

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

Table 64. External clock drive

Symbol

Parameter

Oscillator

Unit

12 MHz

Variable

Min

Max

Min

Max

f_osc

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

-

0

33

MHz

ns

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

83

-

0.35T_cy(clk)

0.65T_cy(clk)

ns

-

0.35T_cy(clk)

0.65T_cy(clk)

ns

-

20

-

ns

clock fall time

-

ns

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 32. External clock drive waveform

Table 65. Serial port timing

Symbol Parameter

Oscillator

12 MHz

Min

Unit

Variable

Min

Max

T_XLXL

t_QVXH

serial port clock cycle time

1.0

-

12T_cy(clk)

-

µs

output data set-up to clock rising edge 700

time

10T_cy(clk)− 133

ns

t_XHQX

t_XHDX

t_XHDV

output data hold after clock rising

edge time

50

-

2T_cy(clk)− 50

-

ns

input data hold after clock rising edge

time

0

-

0

-

input data valid to clock rising edge

time

-

700

10T_cy(clk)− 133 ns

P89LV51RB2_RC2_RD2_5

Product data sheet

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

instruction

ALE

0

1

2

3

4

5

6

7

8

T

XLXL

clock

t

XHQX

1

t

QVXH

output data

write to SBUF

input data

0

2

3

4

5

6

7

t

XHDX

set TI

valid

t

XHDV

valid

clear RI

set RI

002aaa552

Fig 33. Shift register mode timing waveforms

to tester

to DUT

C

L

002aaa555

Fig 34. Test load example

V

DD

I

DD

V

DD

8

P0

EA

V

RST

DD

DUT

XTAL2

XTAL1

(n.c.)

clock

signal

V

SS

002aaa556

All other pins disconnected

Fig 35. I_DDtest condition, Active mode

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Product data sheet

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NXP Semiconductors

8-bit microcontrollers with 80C51 core

V

DD

I

DD

V

DD

8

V

P0

DD

RST

EA

DUT

XTAL2

XTAL1

(n.c.)

clock

signal

V

SS

002aaa557

All other pins disconnected

Fig 36. I_DDtest condition, Idle mode

V

DD

= 2 V

V

DD

I

DD

V

DD

P0

8

V

DD

RST

EA

DUT

XTAL2

XTAL1

(n.c.)

V

SS

002aaa558

All other pins disconnected

Fig 37. I_DDtest condition, Power-down mode

P89LV51RB2_RC2_RD2_5

Product data sheet

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

10. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 38. Package outline SOT187-2 (PLCC44)

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Product data sheet

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P89LV51RB2/RC2/RD2

NXP Semiconductors

8-bit microcontrollers with 80C51 core

TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm

SOT376-1

c

y

X

A

33

23

34

Z

22

E

e

H

E

A

2

(A )

3

A

1

w M

p

θ

b

pin 1 index

L

p

L

detail X

12

44

11

1

Z

D

v M

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.05

0.05 0.95

0.45 0.18 10.1 10.1

0.30 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.2

0.8

1.2

0.8

mm

1.2

0.25

0.8

1

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

02-03-14

SOT376-1

137E08

MS-026

Fig 39. Package outline SOT376-1 (TQFP44)

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Product data sheet

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NXP Semiconductors

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11. Abbreviations

Table 66. Abbreviations

Acronym

DUT

EMI

Description

Device Under Test

Electro-Magnetic Interference

In-Application Programming

In-System Programming

IAP

ISP

MCU

PCA

PWM

RC

Microcontroller Unit

Programmable Counter Array

Pulse Width Modulator

Resistance-Capacitance

SFR

SPI

Special Function Register

Serial Peripheral Interface

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

TTL

UART

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Product data sheet

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12. Revision history

Table 67. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

P89LV51RB2_RC2_RD2_5 20091215

Product data sheet

-

P89LV51RB2_RC2_RD2-04

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 3: Removed sentence “However, Security lock level 4 will disable EA...” for EA

description.

• Table 37: Second row, changed “f_osc/ 6” to “f_osc/ 2”.

• Figure 30: Updated ﬁgure.

• Figure 31: Updated ﬁgure.

P89LV51RB2_RC2_RD2-04 20041202

(9397 750 14342)

Product data

-

P89LV51RB2_RC2_RD2-03

P89LV51RB2_RC2_RD2-02

P89LV51RB2_RC2_RD2-01

-

P89LV51RB2_RC2_RD2-03 20041011

(9397 750 14101)

P89LV51RB2_RC2_RD2-02 20031113

(9397 750 11783)

P89LV51RB2_RC2_RD2-01 20030630

(9397 750 11669)

ECN 853-2432 30075

dated 27 June 2003

P89LV51RB2_RC2_RD2_5

Product data sheet

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13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

13.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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NXP Semiconductors

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15. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.7

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SPI description. . . . . . . . . . . . . . . . . . . . . . . . 42

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 45

PCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PCA capture mode. . . . . . . . . . . . . . . . . . . . . 50

16-bit software timer mode. . . . . . . . . . . . . . . 51

High-speed output mode . . . . . . . . . . . . . . . . 52

PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PCA watchdog timer . . . . . . . . . . . . . . . . . . . 54

Security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interrupt priority and polling sequence. . . . . . 55

Power-saving modes . . . . . . . . . . . . . . . . . . . 58

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Power-down mode . . . . . . . . . . . . . . . . . . . . . 59

System clock and clock options . . . . . . . . . . . 60

Clock input options and recommended

6.7.1

6.7.2

6.8

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

4

6.9

6.9.1

6.9.2

6.9.3

6.9.4

6.9.5

6.10

6.11

6.12

6.12.1

6.12.2

6.13

6.13.1

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6

6.1

6.2

Functional description . . . . . . . . . . . . . . . . . . 10

Special function registers . . . . . . . . . . . . . . . . 10

Memory organization . . . . . . . . . . . . . . . . . . . 14

Flash program memory bank selection. . . . . . 14

Power-on reset code execution. . . . . . . . . . . . 14

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 15

Brownout detect reset. . . . . . . . . . . . . . . . . . . 15

Watchdog reset. . . . . . . . . . . . . . . . . . . . . . . . 16

Data RAM memory. . . . . . . . . . . . . . . . . . . . . 16

Expanded data RAM addressing . . . . . . . . . . 16

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . 19

Flash memory IAP . . . . . . . . . . . . . . . . . . . . . 20

Flash organization . . . . . . . . . . . . . . . . . . . . . 20

Boot block (block 1) . . . . . . . . . . . . . . . . . . . . 20

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Using ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Using the serial number . . . . . . . . . . . . . . . . . 25

IAP method. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Timers/counters 0 and 1. . . . . . . . . . . . . . . . . 27

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Capture mode. . . . . . . . . . . . . . . . . . . . . . . . . 32

Auto-reload mode (up or down counter) . . . . . 33

Programmable clock-out. . . . . . . . . . . . . . . . . 35

Baud rate generator mode . . . . . . . . . . . . . . . 35

Summary of baud rate equations . . . . . . . . . . 37

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 39

More about UART mode 1 . . . . . . . . . . . . . . . 39

More about UART modes 2 and 3 . . . . . . . . . 39

Multiprocessor communications . . . . . . . . . . . 40

Automatic address recognition . . . . . . . . . . . . 40

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.6

capacitor values for oscillator. . . . . . . . . . . . . 60

Clock doubling option. . . . . . . . . . . . . . . . . . . 60

6.13.2

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 62

Static characteristics . . . . . . . . . . . . . . . . . . . 62

Dynamic characteristics. . . . . . . . . . . . . . . . . 65

Explanation of symbols . . . . . . . . . . . . . . . . . 66

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 71

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 73

Revision history . . . . . . . . . . . . . . . . . . . . . . . 74

8

9

9.1

10

11

12

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 75

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 75

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 75

13.1

13.2

13.3

13.4

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 75

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

6.6.6

6.6.7

6.6.8

6.6.9

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2009

Document identifier: P89LV51RB2_RC2_RD2_5


型号：	935277744512
厂家：	NXP
描述：	8-BIT, FLASH, 33MHz, MICROCONTROLLER, PQCC44, PLASTIC, MS-018, SOT-187-2, LCC-44 时钟外围集成电路
文件：	总76页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935277744512 [NXP]

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