935278201112 [NXP]
SERIAL INPUT LOADING, 24-BIT DAC, PDSO16, 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16;
| 型号： | 935278201112 |
| 厂家： | 
NXP |
| 描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO16, 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 输入元件 光电二极管 |
| 文件： | 总22页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UDA1334ATS
Low power audio DAC with PLL
Product specification
2000 Jul 31
Supersedes data of 2000 Feb 09
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
CONTENTS
9
LIMITING VALUES
HANDLING
10
11
12
13
14
1
FEATURES
THERMAL CHARACTERISTICS
QUALITY SPECIFICATION
DC CHARACTERISTICS
AC CHARACTERISTICS
1.1
1.2
1.3
1.4
1.5
General
Multiple format data interface
DAC digital features
Advanced audio configuration
PLL system clock generation
14.1
14.2
Analog
Timing
2
3
4
5
6
7
8
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
15
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
16
17
17.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
PINNING
17.2
17.3
17.4
17.5
FUNCTIONAL DESCRIPTION
8.1
System clock
8.1.1
8.1.2
8.2
Audio mode
Video mode
Interpolation filter
Noise shaper
Suitability of surface mount IC packages for
wave and reflow soldering methods
18
19
DATA SHEET STATUS
DISCLAIMERS
8.3
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
Filter stream DAC
Power-on reset
Feature settings
Digital interface format select
De-emphasis control
Mute control
2000 Jul 31
2
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
1
FEATURES
General
1.1
• 2.4 to 3.6 V power supply voltage
• On-board PLL to generate the internal system clock:
– Operates as an asynchronous DAC, regenerating the
internal clock from the WS signal (called audio mode)
– Generates audio related system clock (output) based
on 32, 48 or 96 kHz sampling frequency (called video
mode).
2
APPLICATIONS
• Integrated digital filter plus DAC
This audio DAC is excellently suitable for digital audio
portable application, specially in applications in which an
audio related system clock is not present.
• Supports sample frequencies from 16 to 100 kHz in
asynchronous DAC mode
• No analog post filtering required for DAC
• Easy application
3
GENERAL DESCRIPTION
• SSOP16 package.
The UDA1334ATS is a single chip 2 channel
digital-to-analog converter employing bitstream
conversion techniques, including an on-board PLL.
The extremely low power consumption and low voltage
requirements make the device eminently suitable for use in
low-voltage low-power portable digital audio equipment
which incorporates a playback function.
1.2
Multiple format data interface
• I2S-bus and LSB-justified format compatible
• 1fs input data rate.
1.3
DAC digital features
The UDA1334ATS supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
• Digital de-emphasis for 44.1 kHz sampling frequency
• Mute function.
The UDA1334ATS has basic features such as
de-emphasis (44.1 kHz sampling frequency, only
supported in audio mode) and mute.
1.4
Advanced audio configuration
• High linearity, wide dynamic range and low distortion.
1.5
PLL system clock generation
• Integrated low jitter PLL for use in applications in which
there is digital audio data present but the system cannot
provide an audio related system clock. This mode is
called audio mode.
• The PLL can generate 256 × 48 kHz and 384 × 48 kHz
from a 27 MHz input clock. This mode is called video
mode.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UDA1334ATS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2000 Jul 31
3
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
5
QUICK REFERENCE DATA
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
VDDA
VDDD
IDDA
DAC analog supply voltage
digital supply voltage
2.4
3.0
3.0
3.5
3.5
2.5
4.5
−
3.6
3.6
−
V
2.4
−
V
DAC analog supply current
audio mode
mA
mA
mA
mA
°C
video mode
audio mode
video mode
−
−
IDDD
digital supply current
−
−
−
−
Tamb
ambient temperature
−40
+85
Digital-to-analog converter (VDDA = VDDD = 3.0 V)
Vo(rms)
output voltage (RMS value)
at 0 dB (FS) digital input;
note 1
−
900
−
mV
(THD+N)/S
total harmonic distortion-plus-noise to fs = 44.1 kHz; at 0 dB
−
−
−90
−40
−
−
dB
dB
signal ratio
fs = 44.1 kHz; at −60 dB;
A-weighted
fs = 96 kHz; at 0 dB
−
−
−85
−38
−
−
dB
dB
fs = 96 kHz; at −60 dB;
A-weighted
S/N
signal-to-noise ratio
channel separation
fs = 44.1 kHz; code = 0;
A-weighted
−
−
−
100
98
−
−
−
dB
dB
dB
fs = 96 kHz; code = 0;
A-weighted
αCS
100
Power dissipation (at fs = 44.1 kHz)
P
power dissipation
audio mode
video mode
−
−
18
24
−
−
mW
mW
Note
1. The output voltage of the DAC scales proportionally to the power supply voltage.
2000 Jul 31
4
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
6
BLOCK DIAGRAM
V
V
PLL0
10
SSD
5
DDD
4
1
2
3
BCK
WS
DIGITAL INTERFACE
DE-EMPHASIS
PLL
DATAI
UDA1334ATS
6
7
SYSCLK/PLL1
MUTE
SFOR1
SFOR0
8
9
11
INTERPOLATION FILTER
NOISE SHAPER
DEEM/CLKOUT
DAC
DAC
14
16
VOUTR
VOUTL
13
15
12
ref(DAC)
MGL973
V
V
V
DDA
SSA
Fig.1 Block diagram.
2000 Jul 31
5
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
7
PINNING
SYMBOL
PIN
PAD TYPE
DESCRIPTION
BCK
1
2
3
4
5
6
5 V tolerant digital input pad
5 V tolerant digital input pad
5 V tolerant digital input pad
digital supply pad
bit clock input
WS
word select input
serial data input
digital supply voltage
digital ground
DATAI
VDDD
VSSD
digital ground pad
SYSCLK/PLL1
5 V tolerant digital input pad
system clock input in video mode/PLL
mode control 1 input in audio mode
SFOR1
7
8
9
5 V tolerant digital input pad
5 V tolerant digital input pad
5 V tolerant digital input/output pad
serial format select 1 input
mute control input
MUTE
DEEM/CLKOUT
de-emphasis control input in audio
mode/clock output in video mode
PLL0
10
11
12
13
14
15
16
3-level input pad; note 1
digital input pad; note 1
analog pad
PLL mode control 0 input
serial format select 0 input
DAC reference voltage
DAC analog supply voltage
DAC output left
SFOR0
Vref(DAC)
VDDA
analog supply pad
analog output pad
analog ground pad
analog output pad
VOUTL
VSSA
DAC analog ground
VOUTR
DAC output right
Note
1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at
a maximum of 0.5 V above that level.
handbook, halfpage
BCK
WS
1
2
3
4
5
6
7
8
16
15
VOUTR
V
SSA
DATAI
14 VOUTL
V
V
V
13
12
DDD
DDA
UDA1334ATS
V
SSD
ref(DAC)
SYSCLK/PLL1
SFOR1
11 SFOR0
10 PLL0
MUTE
9
DEEM/CLKOUT
MGL972
Fig.2 Pin configuration.
2000 Jul 31
6
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
8
FUNCTIONAL DESCRIPTION
System clock
Table 2 Clock output selection in video mode
8.1
PLL0
MID
SELECTION
12.228 MHz clock; note 1
18.432 MHz clock; note 2
audio mode
The UDA1334ATS incorporates a PLL capable of
generating the system clock. The UDA1334ATS can
operate in 2 modes:
HIGH
LOW
• It operates as an asynchronous DAC, which means the
device regenerates the internal clocks using a PLL from
the incoming WS signal. This mode is called audio
mode.
Notes
1. The supported sampling frequencies are:
96, 48 and 24 kHz or 64, 32 and 16 kHz.
• It generates the internal clocks from a 27 MHz clock
input, based on 32, 48 and 96 kHz sampling
frequencies. This mode is called video mode.
2. The supported sampling frequencies are:
96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.
8.2
Interpolation filter
In video mode, the digital audio input is slave, which
means that the system must generate the BCK and
WS signals from the output clock available at pin CLKOUT
of the UDA1334ATS. The digital audio signals should be
frequency locked to the CLKOUT signal.
The interpolation digital filter interpolates from 1fs to 64fs
by cascading FIR filters (see Table 3).
Table 3 Interpolation filter characteristics
Remarks:
ITEM
CONDITION
VALUE (dB)
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
Pass-band ripple
Stop band
0fs to 0.45fs
>0.55fs
±0.02
−50
Dynamic range
0fs to 0.45fs
>114
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
8.3
Noise shaper
8.1.1
AUDIO MODE
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
Audio mode is enabled by setting pin PLL0 to LOW.
De-emphasis can be activated via pin DEEM/CLKOUT
according to Table 5.
In audio mode, pin SYSCLK/PLL1 is used to set the
sampling frequency range as given in Table 1.
Table 1 Sampling frequency range in audio mode
SYSCLK/PLL1
LOW
SELECTION
fs = 16 to 50 kHz
fs = 50 to 100 kHz
HIGH
8.1.2
VIDEO MODE
In video mode, the master clock is a 27 MHz external clock
(as is available in video environment). A clock-out signal is
generated at pin DEEM/CLKOUT. The output frequency
can be selected using pin PLL0. The output frequency is
either 12.228 MHz (256 × 48 kHz) with pin PLL0 being at
MID level or 18.432 MHz (384 × 48 kHz) with pin PLL0
being HIGH, as given in Table 2.
2000 Jul 31
7
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
8.4
Filter stream DAC
8.5
Power-on reset
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. No post filter is needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The UDA1334ATS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 μs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
The output voltage of the FSDAC scales proportionally to
the power supply voltage.
3.0
handbook, halfpage
V
DDD
(V)
1.5
0
t
handbook, halfpage
V
DDA
13
12
3.0 V
3.0
V
50 kΩ
50 kΩ
DDA
(V)
RESET
CIRCUIT
V
ref(DAC)
1.5
C1 >
10 μF
0
UDA1334ATS
t
MGT015
3.0
V
ref(DAC)
(V)
1.5
1.25
0.75
0
t
>1 μs
MGL984
Fig.3 Power-on reset circuit.
Fig.4 Power-on reset timing.
2000 Jul 31
8
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
8.6
Feature settings
8.6.2
DE-EMPHASIS CONTROL
This function is only available in audio mode. In that case,
pin DEEM/CLKOUT can be used to activate the digital
de-emphasis for 44.1 kHz as given in Table 5.
8.6.1
DIGITAL INTERFACE FORMAT SELECT
The digital audio interface formats (see Fig.5) can be
selected via pins SFOR1 and SFOR0 as shown in
Table 4.
Table 5 De-emphasis control (audio mode)
For the digital audio interface holds that the
BCK frequency can be maximum 64 times WS frequency.
DEEM/CLKOUT
LOW
FUNCTION
de-emphasis off
de-emphasis on
The WS signal must change at the negative edge of the
BCK signal for all digital audio formats.
HIGH
8.6.3
MUTE CONTROL
Table 4 Data format selection
The output signal can be soft muted by setting pin MUTE
to HIGH as given in Table 6.
SFOR1
SFOR0
INPUT FORMAT
I2S-bus input
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
Table 6 Mute control
LSB-justified 16 bits input
LSB-justified 20 bits input
LSB-justified 24 bits input
MUTE
LOW
FUNCTION
mute off
mute on
HIGH
2000 Jul 31
9
RIGHT
LEFT
WS
1
2
3
> = 8
1
2
3
> = 8
BCK
DATA
MSB B2
MSB B2
MSB
2
I S-BUS FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
15
2
1
BCK
DATA
B15 LSB
B15 LSB
MSB B2
MSB B2
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
20
RIGHT
20
19
18
17
16
15
2
1
19
18
17
16
15
2
1
BCK
DATA
B19 LSB
B19 LSB
MSB B2
B3
B4
B5
B6
MSB B2
B3
B4
B5
B6
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
20
RIGHT
20
24
23
22
21
19
18
17
16
15
2
1
24
23
22
21
19
18
17
16
15
2
1
BCK
DATA
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MGS752
LSB-JUSTIFIED FORMAT 24 BITS
Fig.5 Digital audio formats.
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS
VDD supply voltage
MIN.
MAX.
4.0
UNIT
note 1
−
−
V
Txtal(max)
maximum crystal
temperature
150
°C
Tstg
Tamb
Ves
storage temperature
ambient temperature
−65
+125
+85
°C
°C
V
−40
electrostatic handling voltage human body model; note 2
machine model; note 2
−2000
−250
+2000
+250
V
Isc(DAC)
short-circuit current of DAC
note 3
output short-circuited to VSSA
output short-circuited to VDDA
−
−
450
300
mA
mA
Notes
1. All supply connections must be made to the same power supply.
2. ESD behaviour is tested according to JEDEC II standard.
3. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
145
K/W
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”.
13 DC CHARACTERISTICS
VDDD = VDDA = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
VDDD
IDDA
DAC analog supply voltage
digital supply voltage
note 1
2.4
3.0
3.6
3.6
−
V
V
note 1
2.4
−
3.0
3.5
3.5
2.5
4.5
DAC analog supply current
audio mode
video mode
audio mode
video mode
mA
mA
mA
mA
−
−
IDDD
digital supply current
−
−
−
−
2000 Jul 31
11
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pins: TTL compatible
VIH
VIL
⎪ILI⎪
Ci
HIGH-level input voltage
LOW-level input voltage
input leakage current
input capacitance
2.0
−
−
−
−
5.0
V
V
−0.5
−
+0.8
1
μA
−
10
pF
3-level input: pin PLL0
VIH
VIM
VIL
HIGH-level input voltage
0.9VDDD
0.4VDDD
−0.5
−
−
−
VDDD + 0.5
0.6VDDD
+0.5
V
V
V
MID-level input voltage
LOW-level input voltage
Digital output pins
VOH
VOL
HIGH-level output voltage
IOH = −2 mA
0.85VDDD
−
−
−
V
V
LOW-level output voltage
IOL = 2 mA
−
0.4
DAC
Vref(DAC)
Ro(ref)
reference voltage
with respect to VSSA
0.45VDD 0.5VDD 0.55VDD
V
output resistance on
pin Vref(DAC)
−
25
−
kΩ
Io(max)
maximum output current
(THD + N)/S < 0.1%;
−
1.6
−
mA
RL = 5 kΩ
RL
CL
load resistance
3
−
−
−
kΩ
load capacitance
note 2
−
50
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
14 AC CHARACTERISTICS
14.1 Analog
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
TYP.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
at 0 dB (FS) digital input; note 1
900
mV
ΔVo
0.1
dB
dB
dB
dB
dB
(THD + N)/S
total harmonic
distortion-plus-noise to signal
ratio
fs = 44.1 kHz; at 0 dB
−90
−40
−85
−38
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
fs = 96 kHz; at −60 dB; A-weighted
2000 Jul 31
12
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
SYMBOL
S/N
PARAMETER
CONDITIONS
fs = 44.1 kHz; code = 0; A-weighted
fs = 96 kHz; code = 0; A-weighted
TYP.
100
UNIT
dB
signal-to-noise ratio
98
dB
dB
dB
αCS
channel separation
100
60
PSRR
power supply rejection ratio
fripple = 1 kHz; Vripple = 30 mV (p-p)
Note
1. The output voltage of the DAC scales proportionally to the analog power supply voltage.
14.2 Timing
VDDD = VDDA = 2.4 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Output clock timing in video mode (see Fig.6)
Tsys
output clock cycle
fo = 12.228 MHz
fo = 18.432 MHz
fo = 12.228 MHz
fo = 18.432 MHz
fo = 12.228 MHz
fo = 18.432 MHz
−
−
81.38
−
−
ns
54.25
ns
ns
ns
ns
ns
tCWL
output clock LOW time
output clock HIGH time
0.3Tsys
0.4Tsys
0.3Tsys
0.4Tsys
−
−
−
−
0.7Tsys
0.6Tsys
0.7Tsys
0.6Tsys
tCWH
Serial input data timing (see Fig.7)
fBCK
bit clock frequency
bit clock HIGH time
bit clock LOW time
rise time
−
−
−
−
−
−
−
−
−
−
64fs
−
Hz
ns
ns
ns
ns
ns
ns
ns
ns
tBCKH
tBCKL
tr
50
50
−
−
20
20
−
tf
fall time
−
tsu(DATAI)
th(DATAI)
tsu(WS)
th(WS)
set-up time data input
hold time data input
set-up time word select
hold time word select
20
0
−
20
10
−
−
Note
1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz.
2000 Jul 31
13
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
t
CWH
MGR984
t
CWL
T
sys
Fig.6 Output clock timing.
WS
t
h(WS)
t
BCKH
t
su(WS)
t
t
f
r
BCK
t
su(DATAI)
t
BCKL
T
t
cy(BCK)
h(DATAI)
DATAI
MGL880
Fig.7 Serial interface timing.
2000 Jul 31
14
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
15 APPLICATION INFORMATION
analog
digital
supply voltage
supply voltage
R7
1 Ω
R6
1 Ω
C9
C5
47 μF
(16 V)
47 μF
(16 V)
C10
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
SYSCLK/PLL1
6
C3
R3
VOUTL
left
output
100 Ω
BCK
WS
47 μF
1
R1
220 kΩ
(16 V)
C1
10 nF
(63 V)
2
DATAI
SFOR1
SFOR0
3
7
C4
R4
100 Ω
VOUTR
right
output
16
12
11
UDA1334ATS
47 μF
(16 V)
R2
220 kΩ
10 nF
(63 V)
C2
MUTE
DEEM/CLKOUT
PLL0
8
V
ref(DAC)
9
C8
100 nF
(63 V)
C7
47 μF
(16 V)
10
MGL971
In audio mode, the system does not need to supply a system clock.
Fig.8 Audio mode application diagram.
2000 Jul 31
15
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
analog
digital
supply voltage
supply voltage
R7
1 Ω
R6
1 Ω
C9
C5
47 μF
(16 V)
47 μF
(16 V)
C10
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
R5
SYSCLK/PLL1
27 MHz
clock
6
47 Ω
C3
R3
100 Ω
VOUTL
left
output
BCK
WS
47 μF
(16 V)
1
R1
220 kΩ
C1
10 nF
(63 V)
2
DATAI
3
2
SFOR1
SFOR0
I S-bus
7
C4
R4
100 Ω
VOUTR
right
output
(master)
16
12
11
UDA1334ATS
47 μF
(16 V)
MPEG
R2
220 kΩ
DECODER
10 nF
(63 V)
C2
MUTE
8
V
DEEM/CLKOUT
ref(DAC)
9
audio clock
PLL0
C8
100 nF
(63 V)
C7
47 μF
(16 V)
10
MGL974
In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is
slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.
Fig.9 Video mode application diagram.
2000 Jul 31
16
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
16 PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.3
5.1
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1
1.5
0.65
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT369-1
MO-152
2000 Jul 31
17
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
17 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
17.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
17.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
17.4 Manual soldering
17.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Jul 31
18
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Jul 31
19
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
18 DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
19 DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2000 Jul 31
20
NXP Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Semiconductors’ product specifications.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2000 Jul 31
21
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/02/pp22
Date of release: 2000 Jul 31
Document order number: 9397 750 07238
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