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935278229118 [NXP]

LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 7.50 MM, PLASTIC, MS-013, SOT-137-1, SOP-24;
935278229118
型号： 935278229118
厂家： NXP    NXP
描述：

LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 7.50 MM, PLASTIC, MS-013, SOT-137-1, SOP-24

光电二极管 输出元件 逻辑集成电路
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74LVC4245A  
Octal dual supply translating transceiver; 3-state  
Rev. 10 — 18 December 2012  
Product data sheet  
1. General description  
The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting  
3-state bus compatible outputs in both send and receive directions. It is designed to  
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.  
The device features an output enable input (pin OE) for easy cascading and a  
send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the  
buses are effectively isolated.  
In suspend mode, when VCC(A) is zero, there will be no current flow from one supply to the  
other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be  
smaller than Vdiode (typical 0.7 V).  
VCC(A) VCC(B), except in suspend mode.  
2. Features and benefits  
5 V tolerant inputs/outputs, for interfacing with 5 V logic  
Wide supply voltage range:  
3 V bus (VCC(B)): 1.5 V to 3.6 V  
5 V bus (VCC(A)): 1.5 V to 5.5 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Inputs accept voltages up to 5.5 V  
High-impedance when VCC(A) = 0 V  
Complies with JEDEC standard no. JESD8B/JESD36  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC4245AD  
40 C to +125 C  
SO24  
plastic small outline package; 24 leads;  
body width 7.5 mm  
SOT137-1  
74LVC4245ADB  
40 C to +125 C  
SSOP24  
TSSOP24  
plastic shrink small outline package; 24 leads;  
body width 5.3 mm  
SOT340-1  
74LVC4245APW 40 C to +125 C  
74LVC4245ABQ 40 C to +125 C  
plastic thin shrink small outline package; 24 leads; SOT355-1  
body width 4.4 mm  
DHVQFN24 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 24 terminals;  
body 3.5 5.5 0.85 mm  
SOT815-1  
4. Functional diagram  
DIR  
2
OE  
22  
A0  
3
B0  
21  
20  
19  
18  
17  
16  
15  
14  
A1  
4
22  
B1  
G3  
3EN1  
A2  
5
2
3EN2  
B2  
A3  
6
1
B3  
21  
3
2
A4  
7
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
B4  
A5  
8
B5  
A6  
9
B6  
A7  
10  
B7  
10  
mna452  
mna453  
Fig 1. IEC Logic symbol  
Fig 2. Logic diagram  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
2 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
5. Pinning information  
5.1 Pinning  
74LVC4245A  
terminal 1  
index area  
74LVC4245A  
2
3
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
DIR  
A0  
V
CC(B)  
V
1
2
3
4
5
6
7
8
9
24  
23  
V
V
CC(A)  
CC(B)  
OE  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
DIR  
CC(B)  
4
A1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
22 OE  
21 B0  
20 B1  
19 B2  
18 B3  
17 B4  
16 B5  
15 B6  
14 B7  
13 GND  
5
A2  
6
A3  
7
A4  
8
A5  
9
A6  
(1)  
GND  
10  
11  
A7  
GND  
A7 10  
GND 11  
GND 12  
001aah087  
Transparent top view  
001aaa349  
(1) This is not a supply pin. The substrate is attached to this  
pad using conductive die attach material. There is no  
electrical or mechanical requirement to solder this pad.  
However, if it is soldered, the solder land should remain  
floating or be connected to GND.  
Fig 3. Pin configuration SO24 and (T)SSOP24  
Fig 4. Pin configuration DHVQFN24  
5.2 Pin description  
Table 2.  
Symbol  
VCC(A)  
VCC(B)  
GND  
Pin description  
Pin  
Description  
1
supply voltage (5 V bus)  
supply voltage (3 V bus)  
ground (0 V)  
23, 24  
11, 12, 13  
DIR  
2
direction control  
A[0:7]  
B[0:7]  
OE  
3, 4, 5, 6, 7, 8, 9, 10  
data input or output  
21, 20, 19, 18, 17, 16, 15, 14  
22  
data input or output  
output enable input (active LOW)  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
3 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
6. Functional description  
Table 3.  
Functional table[1]  
Input  
OE  
L
Input/output  
DIR  
L
An  
Bn  
A = B  
input  
Z
input  
B = A  
Z
L
H
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC(A)  
VCC(B)  
IIK  
Parameter  
Conditions  
Min  
0.5  
0.5  
50  
0.5  
-
Max  
+6.5  
+4.6  
-
Unit  
V
supply voltage A  
supply voltage B  
input clamping current  
input voltage  
V
VI < 0 V  
mA  
V
[1]  
[3]  
[1]  
[1]  
[3]  
VI  
+6.5  
50  
VCC + 0.5  
+6.5  
50  
100  
-
IOK  
output clamping current  
output voltage  
VO > VCCO or VO < 0 V  
output HIGH or LOW state  
output 3-state  
mA  
V
VO  
0.5  
0.5  
-
V
IO  
output current  
VO = 0 V to VCCO  
mA  
mA  
mA  
C  
mW  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
500  
[2]  
Tamb = 40 C to +125 C  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] For SO24 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.  
For (T)SSOP24 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.  
For DHVQFN24 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.  
[3] VCCO is the supply voltage associated with the output.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC(A)  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
supply voltage A  
VCC(A) VCC(B)  
see Figure 5 for maximum  
speed performance  
;
1.5  
-
-
-
5.5  
3.6  
5.5  
V
V
V
VCC(B)  
supply voltage B  
input voltage  
VCC(A) VCC(B)  
see Figure 5 for low-voltage  
applications  
;
1.5  
0
VI  
for control inputs  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
4 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
Table 5.  
Symbol  
VO  
Recommended operating conditions …continued  
Parameter  
Conditions  
Min  
Typ  
Max  
VCC  
5.5  
+125  
20  
Unit  
V
output voltage  
output HIGH or LOW state  
output 3-state  
0
-
-
-
-
-
-
-
0
V
Tamb  
ambient temperature  
40  
C  
t/V  
input transition rise and fall rate  
VCC(B) = 2.7 V to 3.0 V  
VCC(B) = 3.0 V to 3.6 V  
VCC(A) = 3.0 V to 4.5 V  
VCC(A) = 4.5 V to 5.5 V  
-
-
-
-
ns/V  
ns/V  
ns/V  
ns/V  
10  
20  
10  
9. Static characteristics  
Table 6.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
Tamb = 40 C to +85 C  
VIH  
HIGH-level input voltage VCC(B) = 2.7 V to 3.6 V  
VCC(A) = 4.5 V to 5.5 V  
2.0  
2.0  
-
-
-
-
-
-
V
V
V
V
-
VIL  
LOW-level input voltage  
VCC(B) = 2.7 V to 3.6 V  
VCC(A) = 4.5 V to 5.5 V  
0.8  
0.8  
-
VOH  
HIGH-level output voltage VI = VIH or VIL  
VCC(B) = 2.7 V to 3.6 V; IO = 100 A  
VCC(B) 0.2  
VCC(B) 0.5  
VCC(B) 0.8  
VCC(A) 0.2  
VCC(A) 0.5  
VCC(A) 0.8  
VCC(B) -  
V
V
V
V
V
V
VCC(B) = 2.7 V; IO = 12 mA  
VCC(B) = 3.0 V; IO = 24 mA  
VCC(A) = 4.5 V to 5.5 V; IO = 100 A  
VCC(A) = 4.5 V; IO = 12 mA  
VCC(A) = 4.5 V; IO = 24 mA  
-
-
-
-
VCC(A) -  
-
-
-
-
VOL  
LOW-level output voltage VI = VIH or VIL  
VCC(B) = 2.7 V to 3.6 V; IO = 100 A  
VCC(B) = 2.7 V; IO = 12 mA  
VCC(B) = 3.0 V; IO = 24 mA  
VCC(A) = 4.5 V to 5.5 V; IO = 100 A  
VCC(A) = 4.5 V; IO = 12 mA  
VCC(A) = 4.5 V; IO = 24 mA  
VI = 5.5 V or GND  
-
-
-
-
-
-
-
-
0.20  
0.40  
0.55  
0.20  
0.40  
0.55  
5  
V
-
V
-
V
-
V
-
V
-
V
II  
input leakage current  
OFF-state output current VI = VIH or VIL  
VCC(B) = 3.6 V; VO = VCC(B) or GND  
VCC(A) = 5.5 V; VO = VCC(A) or GND  
supply current IO = 0 A  
0.1  
A  
[2]  
IOZ  
-
-
0.1  
0.1  
5  
5  
A  
A  
ICC  
VCC(B) = 3.6 V;  
other inputs at VCC(B) or GND  
-
-
0.1  
0.1  
10  
10  
A  
A  
VCC(A) = 5.5 V;  
other inputs at VCC(A) or GND  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
5 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
Table 6.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
[3]  
ICC  
additional supply current per control pin; IO = 0 A  
VCC(B) = 2.7 V to 3.6 V;  
VI = VCC(B) 0.6 V;  
other inputs at VCC(B) or GND  
-
5
5
500  
500  
A  
VCC(A) = 4.5 V to 5.5 V;  
VI = VCC(A) 0.6 V;  
-
A  
other inputs at VCC(A) or GND  
CI  
input capacitance  
-
-
4.0  
5.0  
-
-
pF  
pF  
CI/O  
input/output capacitance An and Bn  
Tamb = 40 C to +125 C  
VIH  
HIGH-level input voltage VCC(B) = 2.7 V to 3.6 V  
2.0  
2.0  
-
-
-
-
-
-
V
V
V
V
VCC(A) = 4.5 V to 5.5 V  
VCC(B) = 2.7 V to 3.6 V  
VCC(A) = 4.5 V to 5.5 V  
-
VIL  
LOW-level input voltage  
0.8  
0.8  
-
VOH  
HIGH-level output voltage VI = VIH or VIL  
VCC(B) = 2.7 V to 3.6 V; IO = 100 A  
VCC(B) 0.3  
VCC(B) 0.65  
VCC(B) 1.0  
VCC(A) 0.3  
VCC(A) 0.65  
VCC(A) 1.0  
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC(B) = 2.7 V; IO = 12 mA  
VCC(B) = 3.0 V; IO = 24 mA  
VCC(A) = 4.5 V to 5.5 V; IO = 100 A  
VCC(A) = 4.5 V; IO = 12 mA  
VCC(A) = 4.5 V; IO = 24 mA  
VOL  
LOW-level output voltage VI = VIH or VIL  
VCC(B) = 2.7 V to 3.6 V; IO = 100 A  
VCC(B) = 2.7 V; IO = 12 mA  
VCC(B) = 3.0 V; IO = 24 mA  
VCC(A) = 4.5 V to 5.5 V; IO = 100 A  
VCC(A) = 4.5 V; IO = 12 mA  
VCC(A) = 4.5 V; IO = 24 mA  
VI = 5.5 V or GND  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.30  
0.60  
0.80  
0.30  
0.60  
0.80  
20  
V
V
V
V
V
V
II  
input leakage current  
OFF-state output current VI = VIH or VIL  
VCC(B) = 3.6 V; VO = VCC(B) or GND  
VCC(A) = 5.5 V; VO = VCC(A) or GND  
supply current IO = 0 A  
A  
[2]  
IOZ  
-
-
-
-
20  
20  
A  
A  
ICC  
VCC(B) = 3.6 V;  
other inputs at VCC(B) or GND  
-
-
-
-
40  
40  
A  
A  
V
CC(A) = 5.5 V;  
other inputs at VCC(A) or GND  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
6 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
Table 6.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
[3]  
ICC  
additional supply current per control pin; IO = 0 A  
VCC(B) = 2.7 V to 3.6 V;  
VI = VCC(B) 0.6 V;  
other inputs at VCC(B) or GND  
-
-
-
5000 A  
VCC(A) = 4.5 V to 5.5 V;  
VI = VCC(A) 0.6 V;  
-
5000 A  
other inputs at VCC(A) or GND  
[1] All typical values are measured at VCC(A) = 5.0 V, VCC(B) = 3.3 V and Tamb = 25 C.  
[2] For transceivers, the parameter IOZ includes the input leakage current.  
[3]  
V
CC(B) = 2.7 V to 3.6 V: other inputs at VCC(B) or GND.  
VCC(A) = 4.5 V to 5.5 V: other inputs at VCC(A) or GND.  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V). VCC(A) = 4.5 V to 5.5 V; tr = tf 2.5 ns. For test circuit see Figure 8.  
Symbol Parameter  
Conditions  
VCC(B  
)
40 C to +85 C  
Min Max  
40 C to +125 C Unit  
Min Max  
1.0 8.0  
Typ[1]  
3.6  
3.3  
3.4  
3.4  
3.3  
2.8  
3.0  
3.0  
4.5  
4.5  
4.4  
3.8  
4.5  
4.5  
4.3  
3.2  
2.9  
2.9  
3.9  
3.5  
2.8  
2.8  
3.3  
2.9  
tPHL  
HIGH to LOW An to Bn;  
2.7 V  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
6.3  
6.3  
6.1  
6.1  
6.7  
6.5  
5.0  
5.0  
9.0  
9.0  
8.7  
8.1  
8.1  
8.1  
8.7  
8.1  
7.0  
7.0  
7.7  
7.7  
5.8  
5.8  
7.8  
7.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
propagation  
delay  
see Figure 6  
3.0 V to 3.6 V  
2.7 V  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
8.0  
Bn to An;  
see Figure 6  
8.0  
3.0 V to 3.6 V  
2.7 V  
8.0  
tPLH  
LOW to HIGH An to Bn;  
8.5  
propagation  
delay  
see Figure 6  
3.0 V to 3.6 V  
2.7 V  
8.5  
Bn to An;  
see Figure 6  
6.5  
3.0 V to 3.6 V  
2.7 V  
6.5  
tPZL  
OFF-state to  
LOW  
OE to An;  
see Figure 7  
11.5  
11.5  
11.0  
10.5  
10.5  
10.5  
11.0  
10.5  
9.0  
3.0 V to 3.6 V  
2.7 V  
propagation  
delay  
OE to Bn;  
see Figure 7  
3.0 V to 3.6 V  
2.7 V  
tPZH  
OFF-state to  
HIGH  
OE to An;  
see Figure 7  
3.0 V to 3.6 V  
2.7 V  
propagation  
delay  
OE to Bn;  
see Figure 7  
3.0 V to 3.6 V  
2.7 V  
tPLZ  
LOW to  
OE to An;  
see Figure 7  
OFF-state  
propagation  
delay  
3.0 V to 3.6 V  
2.7 V  
9.0  
OE to Bn;  
see Figure 7  
10.0  
10.0  
7.5  
3.0 V to 3.6 V  
2.7 V  
tPHZ  
HIGH to  
OFF-state  
propagation  
delay  
OE to An;  
see Figure 7  
3.0 V to 3.6 V  
2.7 V  
7.5  
OE to Bn;  
see Figure 7  
10.0  
10.0  
3.0 V to 3.6 V  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
7 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
Table 7.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V). VCC(A) = 4.5 V to 5.5 V; tr = tf 2.5 ns. For test circuit see Figure 8.  
Symbol Parameter  
Conditions  
VCC(B  
)
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
[3]  
tsk(o)  
CPD  
output skew  
time  
-
-
1.0  
-
1.5  
ns  
power  
dissipation  
capacitance  
5 V bus: Bn to An;  
VI = GND to VCC(A);  
VCC(A) = 5.0 V  
outputs enabled  
outputs disabled  
-
-
-
-
17  
5
-
-
-
-
-
-
pF  
pF  
[3]  
3 V bus: An to Bn;  
VI = GND to VCC(B);  
VCC(B) = 3.3 V  
outputs enabled  
outputs disabled  
-
-
-
-
17  
5
-
-
-
-
-
-
pF  
pF  
[1] Typical values are measured at Tamb = 25 C, VCC(A) = 5.0 V, and VCC(B) = 2.7 V and 3.3 V respectively.  
[2] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.  
[3] PD is used to determine the dynamic power dissipation (PD in W).  
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in Volts  
N = number of inputs switching  
(CL VCC2 fo) = sum of the outputs  
11. AC waveforms  
mna454  
3.9  
3.6  
3.3  
3.0  
2.7  
2.4  
2.1  
1.8  
1.5  
1.2  
0.9  
V
V
³ V  
CC(A) CC(B)  
CC(B)  
(V)  
1.5  
2.1  
2.7  
3.3  
3.9  
4.5  
5.1  
5.7  
V
(V)  
CC(A)  
Full operation  
Complies with TTL levels  
Fig 5. Supply operation area  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
8 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
V
I
An, Bn  
input  
V
M
GND  
t
t
PHL  
PLH  
V
OH  
Bn, An  
output  
V
M
mna366  
V
OL  
VM = 1.5 V at 2.7 V VCC(B) 3.6 V;  
VM = 0.5 VCC(A) at VCC(A) 4.5 V.  
V
OL and VOH are typical output voltage drops that occur with the output load.  
Fig 6. Input (An, Bn) to output (Bn, An) propagation delays  
V
I
OE input  
V
M
GND  
t
t
PZL  
PLZ  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PHZ  
PZH  
V
OH  
V
Y
output  
HIGH-to-OFF  
OFF-to-HIGH  
V
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
mna367  
VM = 1.5 V at 2.7 V VCC(B) 3.6 V;  
V
M = 0.5 VCC(A) at VCC(A) 4.5 V.  
VX = VOL + 0.3 V at VCC(B) 2.7 V;  
VY = VOH 0.3 V at VCC(B) 2.7 V.  
VOL and VOH are typical output voltage drops that occur with the output load.  
Fig 7. 3-state enable and disable times  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
9 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Test data is given in Table 8. Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
Fig 8. Load circuitry for switching times  
Table 8.  
Test data  
Supply voltage  
VCC(A)  
Input  
Load  
CL  
VEXT  
[1]  
[2]  
VCC(B)  
VI  
RL  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ  
2 VCCO  
2 VCCO  
2 VCCO  
< 2.7 V  
< 2.7 V  
VCCI  
50 pF  
50 pF  
50 pF  
500   
500   
500   
-
2.7 V to 3.6 V  
-
2.7 V  
3.0 V  
open  
GND  
4.5 V to 5.5 V  
open  
GND  
[1] VCCI is the supply voltage associated with the data input port.  
[2] CCO is the supply voltage associated with the output port.  
V
74LVC4245A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
10 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
12. Package outline  
SO24: plastic small outline package; 24 leads; body width 7.5 mm  
SOT137-1  
D
E
A
X
c
H
v
M
A
E
y
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
mm  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3  
0.1  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
15.6  
15.2  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
2.65  
0.1  
0.25  
0.01  
1.27  
0.05  
1.4  
0.25 0.25  
0.01  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.61  
0.014 0.009 0.60  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT137-1  
075E05  
MS-013  
Fig 9. Package outline SOT137-1 (SO24)  
74LVC4245A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
11 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm  
SOT340-1  
D
E
A
X
v
c
H
M
A
y
E
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
8.4  
8.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
0.8  
0.4  
mm  
2
0.65  
1.25  
0.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT340-1  
MO-150  
Fig 10. Package outline SOT340-1 (SSOP24)  
74LVC4245A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
12 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm  
SOT355-1  
D
E
A
X
c
H
v
M
A
y
E
Z
13  
24  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
7.9  
7.7  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.5  
0.2  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT355-1  
MO-153  
Fig 11. Package outline SOT355-1 (TSSOP24)  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
13 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;  
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm  
SOT815-1  
D
B
A
A
A
E
1
c
detail X  
terminal 1  
index area  
C
e
1
terminal 1  
index area  
y
y
v
M
C
C
A B  
C
1
e
b
w
M
2
11  
L
12  
13  
1
e
E
h
2
24  
23  
14  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.  
0.05 0.30  
0.00 0.18  
5.6  
5.4  
4.25  
3.95  
3.6  
3.4  
2.25  
1.95  
0.5  
0.3  
mm  
1
0.2  
0.5  
4.5  
1.5  
0.1  
0.05 0.05  
0.1  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
03-04-29  
SOT815-1  
- - -  
- - -  
- - -  
Fig 12. Package outline SOT815-1 (DHVQFN24)  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
14 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
13. Abbreviations  
Table 9.  
Acronym  
ESD  
Abbreviations  
Description  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
HBM  
MM  
TTL  
Transistor-Transistor Logic  
14. Revision history  
Table 10. Revision history  
Document ID  
Release date  
20121218  
Data sheet status  
Change notice  
Supersedes  
74LVC4245A v.10  
Modifications:  
Product data sheet  
-
74LVC4245A v.9  
• VCC(A) and VCC(B) changed into VCC(A) and VCC(B) (errata)  
20121120 Product data sheet  
• Figure 4: Pin configuration drawing corrected for DHVQFN24 package  
74LVC4245A v.9  
Modifications:  
-
74LVC4245A v.8  
74LVC4245A v.8  
74LVC4245A v.7  
74LVC4245A v.6  
74LVC4245A v.5  
74LVC4245A v.4  
74LVC4245A v.3  
74LVC4245A v.2  
74LVC4245A v.1  
20111122  
20110812  
20080118  
20040330  
20040211  
19990615  
19980729  
19980729  
Product data sheet  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
Product specification  
Product specification  
Product specification  
-
-
-
-
-
-
-
-
74LVC4245A v.7  
74LVC4245A v.6  
74LVC4245A v.5  
74LVC4245A v.4  
74LVC4245A v.3  
74LVC4245A v.2  
74LVC4245A v.1  
-
74LVC4245A  
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Product data sheet  
Rev. 10 — 18 December 2012  
15 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
15.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
74LVC4245A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
16 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74LVC4245A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 18 December 2012  
17 of 18  
74LVC4245A  
NXP Semiconductors  
Octal dual supply translating transceiver; 3-state  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
6
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 17  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2012.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 18 December 2012  
Document identifier: 74LVC4245A  

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