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SC68C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte

FIFOs, IrDA encoder/decoder, and 68 mode µP interface

Rev. 02 — 2 November 2009

Product data sheet

1. General description

The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides

enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data

transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled

by the FIFO trigger levels and the TXRDYn and RXRDYn signals. On-board status

registers provide the user with error indications and operational status. System interrupts

and modem control features may be tailored by software to meet speciﬁc user

requirements. An internal loopback capability allows on-board diagnostics. Independent

programmable baud rate generators are provided to select transmit and receive baud

rates.

The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in the plastic LQFP48 package.

2. Features

I 2 channel UART with 68 mode (Motorola) µP interface

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range (−40 °C to +85 °C)

I Software compatible with industry standard 16C450, 16C550, and SC16C650

I Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

I 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 32-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I Independent transmit and receive UART control

I Four selectable receive and transmit FIFO interrupt trigger levels

I Automatic software (Xon/Xoff) and hardware (RTSn/CTSn) ﬂow control

I Programmable Xon/Xoff characters

I Software selectable baud rate generator

I Standard modem interface or infrared IrDA encoder/decoder interface

I Supports IrDA version 1.0 (up to 115.2 kbit/s)

I Sleep mode

1. For data bus pins D7 to D0, see Table 27 “Limiting values”.

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

I Transmit, Receive, Line Status, and Data Set interrupts independently controlled

I Fully programmable character formatting:

N 5, 6, 7, or 8-bit characters

N Even, odd, or no parity formats

N 1, 1¹⁄₂, or 2 stop bit generation

N Baud generation (DC to 5 Mbit/s)

I False start bit detection

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC68C652BIB48

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT313-2

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

2 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

4. Block diagram

SC68C652B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTER

DATA BUS

AND

D0 to D7

R/W

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A3

CS

DTRA, DTRB

RTSA, RTSB

OP2A, OP2B

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

IRQ

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aab323

XTAL1

XTAL2

Fig 1. Block diagram of SC68C652B

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

3 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

5. Pinning information

5.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D5

D6

RESET

DTRB

DTRA

RTSA

OP2A

RXRDYA

IRQ

3

D7

4

RXB

RXA

TXRDYB

TXA

TXB

OP2B

CS

5

6

SC68C652BIB48

7

8

n.c.

9

A0

10

11

12

A1

A3

A2

n.c.

002aab324

Fig 2. Pin conﬁguration for LQFP48

5.2 Pin description

Table 2.

Symbol

Pin description

Pin Type Description

28

A0

A1

A2

A3

I

Address 0 select bit. Internal registers address selection.

Address 1 select bit. Internal registers address selection.

Address 2 select bit. Internal registers address selection.

27

26

11

Address 3 select bit. A3 is used to select Channel A or

Channel B. A logic LOW selects Channel A, and a logic HIGH

selects Channel B. (See Table 3.)

CDA

CDB

40

16

I

Carrier Detect (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 on these pins

indicates that a carrier has been detected by the modem for that

channel.

CS

10

I

Chip Select (active LOW). This pin enables data transfers

between the user CPU and the SC68C652B for the channel(s)

addressed. Individual UART sections (A, B) are addressed by A3.

See Table 3.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

4 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Pin description …continued

Symbol

CTSA

38

Type Description

I

Clear to Send (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 (LOW) on the CTSn

pins indicates the modem or data set is ready to accept transmit

data from the SC68C652B. Status can be tested by reading

MSR[4]. These pins have no effect on the UART’s transmit or

receive operation.

CTSB

23

D0

44

45

46

47

48

1

I/O

I

Data bus (bidirectional). These pins are the 8-bit, 3-state data

bus for transferring information to or from the controlling CPU. D0 is

the least signiﬁcant bit and the ﬁrst data bit in a transmit or receive

serial data stream.

D1

D2

D3

D4

D5

D6

2

D7

3

DSRA

DSRB

39

20

Data Set Ready (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 (LOW) on these pins

indicates the modem or data set is powered-on and is ready for

data exchange with the UART. These pins have no effect on the

UART’s transmit or receive operation.

I

DTRA

DTRB

34

35

O

Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels A and B. A logic 0

(LOW) on these pins indicates that the SC68C652B is powered-on

and ready. These pins can be controlled via the modem control

register. Writing a logic 1 to MCR[0] will set the DTRn output pin to

logic 0 (LOW), enabling the modem. The output of these pins will

be a logic 1 after writing a logic 0 to MCR[0], or after a reset. These

pins have no effect on the UART’s transmit or receive operation.

GND

IRQ

17, 24

30

I

Signal and power ground

O

Interrupt Request. Interrupts from UART channels A-B are

wire-ORed internally to function as a single IRQ interrupt. This pin

transitions to a logic 0 (if enabled by the interrupt enable register)

whenever a UART channel(s) requires service. Individual channel

interrupt status can be determined by addressing each channel

through its associated internal register, using CS and A3. An

external pull-up resistor must be connected between this pin and

V_CC

.

R/W

n.c.

15

I

A logic LOW on this pin will transfer the contents of the data bus

(D[7:0]) from an external CPU to an internal register that is deﬁned

by address bits A[2:0]. A logic HIGH on this pin will load the

contents of an internal register deﬁned by address bits A[2:0] on

the SC68C652B data bus (D[7:0]) for access by an external CPU.

12, 25,

29, 37

-

not connected

OP2A

OP2B

32

9

O

Output 2 (user-deﬁned). This function is associated with

individual channels A and B. The state of these pins is deﬁned by

the user through the software settings of MCR[3]. OP2A/OP2B is a

logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1

when MCR[3] is set to a logic 0. The output of these two pins is

HIGH after reset.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

5 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Pin description …continued

Symbol

Type Description

RESET

36

I

Reset (active LOW). This pin will reset the internal registers and

all the outputs. The UART transmitter output and the receiver input

will be disabled during reset time. See Section 7.11 “SC68C652B

external reset condition” for initialization details.

RIA

RIB

41

21

I

Ring Indicator (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 on these pins

indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on these input pins generates an

interrupt.

RTSA

RTSB

33

22

O

Request to Send (active LOW). These outputs are associated

with individual UART channels, A and B. A logic 0 on the RTSn pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register MCR[1] will set this

pin to a logic 0, indicating data is available. After a reset these pins

are set to a logic 1. These pins have no effect on the UART’s

transmit or receive operation.

RXA

RXB

5

4

I

Receive data input. These inputs are associated with individual

serial channel data to the SC68C652B receive input circuits A and

B. The RXn pin will be a logic 1 during reset, idle (no data), or when

the transmitter is disabled. During the local loopback mode, these

RXn input pins are disabled and transmit data is connected to the

UART receive input internally.

RXRDYA

31

O

Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW

when the trigger level has been reached or the FIFO has at least

one character. It goes HIGH when the receive FIFO is empty.

RXRDYB 18

TXA

TXB

7

8

O

Transmit data A, B. These outputs are associated with individual

serial transmit channel data from the SC68C652B. The TXn pin will

be a logic 1 during reset, idle (no data), or when the transmitter is

disabled. During the local loopback mode, the TXn output pins are

disabled and transmit data is internally connected to the UART

receive input.

TXRDYA

TXRDYB

43

6

O

Transmit Ready A, B (active LOW). These outputs provide the

transmit FIFO/THR status for individual transmit channels A and B.

TXRDYn is primarily intended for monitoring DMA mode 1 transfers

for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, that is, at least

one location is empty and available in the FIFO or THR. This pin

goes to a logic 1 (DMA mode 1) when there are no more empty

locations in the FIFO or THR. This signal can also be used for

single mode transfers (DMA mode 0).

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

6 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Pin description …continued

Symbol

V_CC

Type Description

19, 42

13

I

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as

an external clock input. A crystal can be connected between this

pin and XTAL2 to form an internal oscillator circuit (see Figure 3).

This conﬁguration requires an external 1 MΩ resistor between the

XTAL1 and XTAL2 pins. Alternatively, an external clock can be

connected to this pin to provide custom data rates. See Section 6.8

“Programmable baud rate generator”.

XTAL2

14

O

Output of the crystal oscillator or buffered clock. (See also

XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered

clock output. Should be left open if an external clock is connected

to XTAL1. For extended frequency operation, this pin should be tied

to V_CCvia a 2 kΩ resistor.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

7 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6. Functional description

The SC68C652B UART is pin-compatible with the SC68C2550B UART. It provides more

enhanced features. All additional features are provided through a special enhanced

feature register.

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC68C652B

UART can be read at any time during functional operation by the processor.

The SC68C652B can be placed in an alternate mode (FIFO mode) relieving the processor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.

The SC68C652B has selectable hardware ﬂow control and software ﬂow control.

Hardware ﬂow control signiﬁcantly reduces software overhead and increases system

efﬁciency by automatically controlling serial data ﬂow using the RTSn output and CTSn

input signals. Software ﬂow control automatically controls data ﬂow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (2¹⁶− 1).

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC68C652B package, and an external serial device. A

logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to conﬁgure, send

data, and/or receive data via UART channels A and B. Individual channel select functions

are shown in Table 3.

Table 3.

Channel selection using CS pin

CS

1

A3

-

UART channel

none

0

channel A

channel B

0

1

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.2 Internal registers

The SC68C652B provides two sets of internal registers (A and B) consisting of

17 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a

user accessible scratchpad register (SPR), along with advanced feature registers EFR

and Xon1, Xon2, Xoff1 and Xoff2.

Table 4.

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon1, Xon2, Xoff1, Xoff2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, Xon2, and Xoff1, Xoff2 are accessible only when the LCR is set to ‘BFh’.

6.3 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). With SC68C2550B devices, the user can set the receive trigger level, but

not the transmit trigger level. The SC68C652B provides independent trigger levels for both

receiver and transmitter. To remain compatible with SC68C2550B, the transmit interrupt

trigger level is set to 16 following a reset. It should be noted that the user can set the

transmit trigger levels by writing to the FCR register, but activation will not take place until

EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure

data is delivered to the external CPU. An interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

9 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 5.

Flow control mechanism

Selected trigger level

(characters)

IRQ pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

RX

8

TX

16

8

0

16

24

28

16

24

28

16

24

28

7

24

30

15

23

6.4 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC68C652B monitors the CTSn pin

for a remote buffer overﬂow indication and controls the RTSn pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTSn transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend

TXn transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTSn input returns to a logic 0, indicating more data

may be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTSn pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTSn pin will return

to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the

programmed trigger level. However, under the above described conditions, the

SC68C652B will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC68C652B compares one or two sequential

receive data characters with the programmed Xon or Xoff character value(s). If received

character(s) match the programmed Xoff values, the SC68C652B will halt transmission

as soon as the current character(s) has completed transmission. When a match occurs,

the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt output pin

(if receive interrupt is enabled) will be activated. Following a suspension due to a match of

the Xoff characters’ values, the SC68C652B will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC68C652B will

resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters are selected, the SC68C652B

compares two consecutive receive characters with two software ﬂow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TXn transmissions accordingly. Under the above

described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the

user accessible receive data buffer or FIFO. When using a software ﬂow control, the

Xon/Xoff characters cannot be used for data transfer.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed, the

SC68C652B automatically sends an Xoff message (when enabled) via the serial TXn

output to the remote modem. The SC68C652B sends the Xoff1/Xoff2 characters as soon

SC68C652B_2

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Rev. 02 — 2 November 2009

10 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

as received data passes the programmed trigger level. To clear this condition, the

SC68C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data

drops below the programmed trigger level.

6.6 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit

character is detected, wit will be placed on the user-accessible data stack along with

normal incoming receive data. This condition is selected in conjunction with EFR[3:0].

Note that software ﬂow control should be turned off when using this special mode by

setting EFR[3:0] to a logic 0.

The SC68C652B compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 9 “SC68C652B internal registers” shows

each X-register with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne the

number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determine the number of bits that will be used for the special

character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive

character.

6.7 Hardware/software and time-out interrupts

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C652B

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR register provides the current singular highest priority

interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority.

A condition can exist where a higher priority interrupt may mask the lower priority

CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower

priority CTS/RTS interrupt(s) be reﬂected in the status register. Servicing the interrupt

without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC68C652B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the receive holding register (RHR) is read.

The actual time-out value is 4 character time, including data information length, start bit,

parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

11 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.8 Programmable baud rate generator

The SC68C652B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

The SC68C652B can support a standard data rate of 921.6 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent transmit/receive channel control. The programmable baud rate generator is

capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is

necessary to use full rail swing on the clock input. The SC68C652B can be conﬁgured for

internal or external clock operation. For internal clock oscillator operation, an industry

standard microprocessor crystal is connected externally between the XTAL1 and XTAL2

pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 6).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC68C652B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is conﬁgured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 6 shows the

selectable baud rate table available when using a 1.8432 MHz external clock input.

XTAL1

XTAL2

X1

1.8432 MHz

C1

22 pF

C2

33 pF

002aab325

Fig 3. Crystal oscillator connection

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

12 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 6.

Baud rate generator programming table using a 1.8432 MHz clock

Output

DLM

DLL

baud rate

16× clock divisor

(decimal)

16× clock divisor

(HEX)

program value

(HEX)

program value

(HEX)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

03

02

01

75

110

150

300

600

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

6.9 DMA operation

The SC68C652B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYn and TXRDYn

output pins. Table 7 and Table 8 show this.

Table 7.

Effect of DMA mode on state of RXRDYn pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,

or time-out occurs

Table 8.

Effect of DMA mode on state of TXRDYn pin

Non-DMA mode

1 = at least 1 byte in FIFO

0 = FIFO empty

DMA mode

0-to-1 transition when FIFO becomes full

1-to-0 transition when FIFO goes below trigger level

6.10 Loopback mode

The internal loopback capability allows on-board diagnostics. In the loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)

are disconnected from their associated interface pins, and instead are connected together

internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal

modem control inputs pins, and instead are connected internally to MCR[1] RTS,

SC68C652B_2

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

MCR[0] DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the

transmit holding register via the user data bus interface, D0 to D7. The transmit UART

serializes the data and passes the serial data to the receive UART via the internal

loopback connection. The receive UART converts the serial data back into parallel data

that is then made available at the user data interface D0 to D7. The user optionally

compares the received data to the initial transmitted data for verifying error-free operation

of the UART transmit/receive circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational.

SC68C652B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

DATA BUS

AND

D0 to D7

R/W

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A3

CS

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

MODEM

CONTROL

LOGIC

DSRA, DSRB

(OP1A, OP1B)

IRQ

TXRDYA, TXRDYB

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA, RIB

(OP2A, OP2B)

CDA, CDB

002aab326

XTAL1 XTAL2

Fig 4. Internal loopback mode diagram

SC68C652B_2

Product data sheet

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7. Register descriptions

Table 9 details the assigned bit functions for the SC68C652B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 9.

SC68C652B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General register set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

Sleep

modem

status

interrupt

RX

receive transmit receive

line

status

interrupt interrupt

interrupt interrupt interrupt mode^[3]

holding

register register

holding

[3]

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)^[3](LSB)^[3]

TX

trigger

DMA

mode

select

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFOs

enable

FIFOs

INT

priority

bit 3

INT

priority

bit 2

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled priority

bit 4

LCR

divisor

latch

enable

set break set parity even

parity

enable

stop bits word

length

word

length

bit 0

parity

bit 1

1

0

1

MCR

LSR

00

60

clock

IRDA

0

loopback OP2

control

(OP1)

RTS

DTR

select^[3]enable

FIFO

data

error

THR and THR

TSR

empty

break

framing

parity

error

overrun receive

error

empty

interrupt error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special register set^[4]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced register set^[5]

0

1

0

EFR

00

Auto-

CTS

Auto-

RTS

Special

Enable

Cont-3

Cont-2

TX, RX TX, RX

Control Control

Cont-1

Cont-0

TX, RX

Control

character IER[4:7], TX, RX

detect

ISR[4:5], Control

FCR[4:5],

MCR[5:7]

1

0

1

0

1

0

1

Xon1

Xon2

Xoff1

Xoff2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown in represents the register’s initialized hexadecimal value; X = not applicable.

[2] Accessible only when LCR[7] is logic 0.

[3] These bits are only accessible when EFR[4] is set.

[4] Baud rate registers accessible only when LCR[7] is logic 1.

[5] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.

SC68C652B_2

Product data sheet

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the

TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag in the

LSR register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and

receive FIFO by reading the RHR register. The receive section provides a mechanism to

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled, and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the IRQ output pin.

Table 10. Interrupt Enable Register bits description

Bit

Symbol

Description

7

IER[7]

CTS interrupt

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC68C652B issues an interrupt

when the CTSn pin transitions from a logic 0 to a logic 1.

6

5

IER[6]

IER[5]

RTS interrupt

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC68C652B issues an interrupt

when the RTSn pin transitions from a logic 0 to a logic 1.

Xoff interrupt

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the software ﬂow control, receive Xoff interrupt

Sleep mode

4

3

IER[4]

IER[3]

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

SC68C652B_2

Product data sheet

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 10. Interrupt Enable Register bits description …continued

Bit

Symbol

Description

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a

receive data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default

condition)

logic 1 = enable the receiver line status interrupt

1

0

IER[1]

IER[0]

Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will

be issued whenever the THR is empty, and is associated with LSR[5]. In

the FIFO modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

Receive Holding Register. In the 16C450 mode, this interrupt will be

issued when the RHR has data, or is cleared when the RHR is empty. In

the FIFO mode, this interrupt will be issued when the FIFO has reached

the programmed trigger level or is cleared when the FIFO drops below the

trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt

(normal default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register, or by loading the THR with new data characters.

SC68C652B_2

Product data sheet

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC68C652B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for transmit and/or receive data status. Since the receiver and transmitter

have separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C450 mode. Transmit Ready pin (TXRDYn) will go to a logic 0 whenever the FIFO

(THR, if FIFO is not enabled) is empty. Receive Ready pin (RXRDYn) will go to a logic 0

whenever the Receive Holding Register (RHR) is loaded with a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. The receive interrupt is set when

the receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

regardless of the programmed level until the FIFO is full. RXRDYn remains a logic 0 as

long as the FIFO ﬁll level is above the programmed trigger level.

SC68C652B_2

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.3.2 FIFO mode

Table 11. FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6]

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO equals

the programmed trigger level. However, the FIFO will continue to be loaded

until it is full. Refer to Table 12.

5:4

3

FCR[5:4]

FCR[3]

TX trigger. Logic 0 or cleared is the default condition; TX trigger level = 16.

These bits are used to set the trigger level for the transmit FIFO interrupt.

The SC68C652B will issue a transmit empty interrupt when the number of

characters in FIFO drops below the selected trigger level. Refer to Table 13.

DMA mode select

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC68C652B is in the 16C450

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs

enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no

characters in the transmit FIFO or transmit holding register, the TXRDYn pin

will be a logic 0. Once active, the TXRDYn pin will go to a logic 1 after the

ﬁrst character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC68C652B is in 16C450 mode,

or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at

least one character in the receive FIFO, the RXRDYn pin will be a logic 0.

Once active, the RXRDYn pin will go to a logic 1 when there are no more

characters in the receiver.

Transmit operation in mode ‘1’: When the SC68C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when

the transmit FIFO is completely full. It will be a logic 0 when the trigger level

has been reached.

Receive operation in mode ‘1’: When the SC68C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,

or a Receive Time-Out has occurred, the RXRDYn pin will go to a logic 0.

Once activated, it will go to a logic 1 after there are no more characters in

the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset

logic 0 = no FIFO receive reset (normal default condition).

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

FIFO enable

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to, or they will not be programmed.

SC68C652B_2

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 12. RCVR trigger levels

FCR[7]

FCR[6]

Receive FIFO trigger level (bytes)

0

1

0

1

0

1

8

16

24

28

Table 13. TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes)

0

1

0

1

0

1

16

8

24

30

SC68C652B_2

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.4 Interrupt Status Register (ISR)

The SC68C652B provides six levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. A lower level interrupt may be seen after servicing the higher level

interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the

data values (bit 0 to bit 5) for the six prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 14. Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding

Register Empty)

4

5

0

1

0

MSR (Modem Status Register)

RXRDY (received Xoff signal)/

special character

6

1

0

CTS, RTS change-of-state

Table 15. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not

being used in the 16C450 mode. They are set to a logic 1 when the

FIFOs are enabled in the SC68C652B mode.

logic 0 or cleared = default condition

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a

logic 1. ISR[4] indicates that matching Xoff character(s) have been

detected. ISR[5] indicates that CTS, RTS have been generated. Note

that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon

character(s) are received.

logic 0 or cleared = default condition

3:1

0

ISR[3:1]

ISR[0]

INT priority bits 2:0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 14).

logic 0 or cleared = default condition

INT status

logic 0 = an interrupt is pending and the ISR contents may be used

as a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

SC68C652B_2

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 16. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TXn output pin is forced to a logic 0

state). This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no break condition (normal default condition)

logic 1 = forces the transmitter output pin (TXn) to a logic 0 for

alerting the remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Set parity; even parity; parity enable. Programs the parity conditions

(see Table 17).

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see Table 18).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 19).

logic 0 or cleared = default condition

Table 17. LCR[5:3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 18. LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1¹⁄₂

6, 7, 8

2

Table 19. LCR[1:0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

SC68C652B_2

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 20. Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

IR enable (see Figure 16)

6

MCR[6]

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While

in this mode, the TXn/RXn output/inputs are routed to the infrared

encoder/decoder. The data input and output levels will conform to the

IrDA infrared interface requirement. As such, while in this mode, the

infrared TXn output will be a logic 0 during idle data conditions.

5

4

MCR[5]

MCR[4]

reserved; set to ‘0’

Loopback. Enable the local loopback mode (diagnostics). In this mode the

transmitter output (TXn) and the receiver input (RXn), CTSn, DSRn, CDn,

and RIn pins are disconnected from the SC68C652B I/O pins. Internally

the modem data and control pins are connected into a loopback data

conﬁguration (see Figure 4). In this mode, the receiver and transmitter

interrupts remain fully operational. The Modem Control Interrupts are also

operational, but the interrupts’ sources are switched to the lower four bits of

the Modem Control. Interrupts continue to be controlled by the IER

register.

logic 0 = disable loopback mode (normal default condition)

logic 1 = enable local loopback mode (diagnostics)

OP2 control

3

2

MCR[3]

MCR[2]

logic 0 = forces OP2n output pin to HIGH state

logic 1 = forces OP2n output pin to LOW state. In loopback mode,

controls MSR[7].

(OP1). OP1A/OP1B are not available as an external signal in the

SC68C652B. This bit is instead used in the loopback mode only. In the

loopback mode, this bit is used to write the state of the modem RIn pin

interface signal.

1

0

MCR[1]

MCR[0]

RTS

logic 0 = force RTSn output pin to a logic 1 (normal default condition)

logic 1 = force RTSn output pin to a logic 0

DTR

logic 0 = force DTRn output pin to a logic 1 (normal default condition)

logic 1 = force DTRn output pin to a logic 0

SC68C652B_2

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SC68C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC68C652B and the CPU.

Table 21. Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit

FIFO and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RXn pin was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s).

In the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error

logic 0 = no parity error (normal default condition

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with

the character at the top of the FIFO.

Overrun error

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready

logic 0 = no data in receive holding register or FIFO (normal default

condition).

logic 1 = data has been received and is saved in the receive holding register

or FIFO.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

24 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC68C652B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 22. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD. During normal operation, this bit is the complement of the CDn input pin.

Reading this bit in the loopback mode produces the state of MCR[3] (OP2).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

RI. During normal operation, this bit is the complement of the RIn input pin.

Reading this bit in the loopback mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSRn input

pin. During the loopback mode, this bit is equivalent to the state of MCR[0].

CTS. During normal operation, this bit is the complement of the CTSn input

pin. During the loopback mode, this bit is equivalent to the state of MCR[1].

∆CD ^[1]

logic 0 = no change of state on CDn pin (normal default condition)

logic 1 = the CDn input pin to the SC68C652B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no change of state on RIn pin (normal default condition)

logic 1 = the RIn input pin to the SC68C652B has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no change of state on DSRn pin (normal default condition)

logic 1 = the DSRn input pin to the SC68C652B has changed state since

the last time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no change of state on CTSn pin (normal default condition)

logic 1 = the CTSn input pin to the SC68C652B has changed state since

the last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC68C652B provides a temporary data register to store 8 bits of user information.

SC68C652B_2

Product data sheet

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 23. Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic CTS ﬂow control. Transmission will stop when

CTSn goes to a logic 1. Transmission will resume when the CTSn pin returns

to a logic 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTSn will go to a logic 1 at the next trigger level. RTSn will return to a logic 0

when data is unloaded below the next lower trigger level (programmed trigger

level 1). The state of this register bit changes with the status of the hardware

ﬂow control. RTSn functions normally when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic RTS ﬂow control.

5

EFR[5]

Special character detect

logic 0 = Special character detect disabled (normal default condition)

logic 1 = Special character detect enabled. The SC68C652B compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit-0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC68C652B

enhanced functions.

logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4],

FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554

mode. (Normal default condition.)

logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all

enhanced features of the SC68C652B are enabled and user settings stored

during a reset will be restored.

3:0

EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 24.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

26 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 24. Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

no transmit ﬂow control

transmit Xon1/Xoff1

transmit Xon2/Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

no receive ﬂow control

receiver compares Xon1/Xoff1

receiver compares Xon2/Xoff2

transmit Xon1/Xoff1

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

transmit Xon2/Xoff2

0

1

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC68C652B external reset condition

Table 25. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

ISR

FCR[7:0] = 0

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

SFR[7:0] = 1

MSR

SPR

DLL

DLL[7:0] = X

DLM

DLM[7:0] = X

Table 26. Reset state for outputs

Output

Reset state

logic 1

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

IRQ

logic 1

3-state condition

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

27 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

8. Limiting values

Table 27. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage on any other pin

at D7 to D0 pins

at input only pins

operating

GND − 0.3 V_CC+ 0.3

GND − 0.3 5.3

V

T_amb

ambient temperature

storage temperature

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot/pack

total power dissipation

per package

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

28 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

9. Static characteristics

Table 28. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

−0.3

1.8

Max

0.45

V_CC

0.65

-

Min

−0.3

2.4

Max

0.6

V_CC

0.8

-

Min

−0.5

3.0

Max

0.6

V_CC

0.8

-

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

V

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

except X1 clock

on all outputs

−0.3

1.6

−0.3

2.0

−0.5

2.2

V_IH

[1]

V_OL

I_OL= 5 mA

(data bus)

-

0.4

V

I_OL= 4 mA

(other outputs)

-

0.4

-

0.4

-

I_OL= 2 mA

(data bus)

-

I_OL= 1.6 mA

(other outputs)

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(data bus)

-

2.4

I_OH= −1 mA

(other outputs)

-

2.0

-

I_OH= −800 µA

(data bus)

1.85

-

I_OH= −400 µA

(other outputs)

-

I_LIL

LOW-level input leakage

current

±10

±10 µA

±30 µA

I_L(clk)

I_CC

clock leakage current

supply current

-

±30

3.5

200

5

-

±30

4.5

200

5

-

4.5

200 µA

pF

mA

I_CC(sleep)sleep mode supply current

C_iinput capacitance

5

[1] Except XTAL2; V_OL= 1 V typical.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

29 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

10. Dynamic characteristics

Table 29. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless speciﬁed otherwise.

Symbol Parameter

Conditions

V_CC= 2.5 V

Min Max

V_CC= 3.3 V and 5 V

Unit

Min

10

20

-

Max

-

t_d1

t_d2

t_d3

t_d4

t_d6

t_d7

t_d8

R/W to chip select

10

20

-

ns

read cycle delay

25 pF load

-

delay from CS to data

data disable time

77

15

-

26

15

-

write cycle delay

25

-

25

-

delay from write to output

25 pF load

100

33

24

delay to set interrupt from modem 25 pF load

input

-

t_d9

delay to reset interrupt from read

delay from stop to set interrupt

delay from read to reset interrupt

delay from start to set interrupt

delay from write to transmit start

delay from write to reset interrupt

delay from stop to set RXRDY

delay from read to reset RXRDY

delay from write to set TXRDY

delay from start to reset TXRDY

R/W hold time from CS

data hold time

25 pF load

-

100

1T_RCLK

100

-

24

1T_RCLK

29

ns

MHz

ns

[1]

t_d10

t_d11

t_d12

t_d13

t_d14

t_d15

t_d16

t_d17

t_d18

t_h2

-

25 pF load

-

100

-

100

[1]

8T_RCLK

24T_RCLK

100

8T_RCLK

24T_RCLK

70

-

[1]

1T_RCLK

-

100

-

75

-

100

-

70

[1]

-

16T_RCLK

-

16T_RCLK

10

15

10

-

10

15

6

-

t_h3

t_h4

address hold time

-

t_WH

t_WL

f_XTAL

t_(RESET)

t_su1

t_su2

t_w1

pulse width HIGH

-

pulse width LOW

-

6

-

[2][3]

[4]

clock speed

48

-

80

-

RESET pulse width

200

10

16

77

200

10

16

30

address set-up time

-

data set-up time

-

CS strobe width

-

[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[2] Applies to external clock; crystal oscillator max 24 MHz.

1

[3] f _XTAL

=

--------------

t_w(clk)

[4] Reset pulse must happen when CS is inactive.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

30 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

10.1 Timing diagrams

A0 to A3

valid address

t

h4

t

w1

su1

t

d2

CS

t

d4

d1

R/W

t

d3

D0 to D7

valid data

002aab087

Fig 5. General read timing

A0 to A3

valid address

t

h4

su1

w1

CS

R/W

t

d6

d1

h2

t

h3

t

su2

D0 to D7

valid data

002aab088

Fig 6. General write timing

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

31 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

(1)

active

CS (write)

t

d7

RTSA, RTSB

DTRA, DTRB

change of state

CDA, CDB

CTSA, CTSB

DSRA, DSRB

change of state

t

d8

IRQ

active

t

d9

(2)

CS (read)

active

t

d8

change of state

RIA, RIB

002aab089

(1) CS timing during a write cycle. See Figure 6.

(2) CS timing during a read cycle. See Figure 5.

Fig 7. Modem input/output timing

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL

=

--------------

t_w(clk)

Fig 8. External clock timing

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

32 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Start

bit

parity Stop Start

bit

data bits (0 to 7)

RXA, RXB

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d10

active

IRQ

t

d11

CS (read)

active

16 baud rate clock

002aab090

Fig 9. Receive timing

Start

bit

parity Stop Start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

t

d15

active data

ready

RXRDYA,

RXRDYB

t

d16

CS (read)

active

002aab091

Fig 10. Receive ready timing in non-FIFO mode

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

33 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Start

bit

parity Stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

first byte that

reaches the

trigger level

t

d15

active data

ready

RXRDYA,

RXRDYB

t

d16

CS (read)

active

002aab092

Fig 11. Receive ready timing in FIFO mode

Start

bit

parity Stop Start

bit bit bit

data bits (0 to 7)

D0

D1

D2

D3

D4

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

active

transmitter ready

IRQ

t

d12

t

d14

t

d13

active

CS (write)

16 baud rate clock

002aab093

Fig 12. Transmit timing

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

34 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Start

bit

parity Stop Start

bit

data bits (0 to 7)

D3 D4

TXA,

TXB

D0

D1

D2

D5

D6

D7

active

CS (write)

D0 to D7

byte #1

t

d18

t

d17

active

transmitter ready

TXRDYA,

TXRDYB

transmitter

not ready

002aab094

Fig 13. Transmit ready timing in non-FIFO mode

Start

bit

parity Stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA,

TXB

5 data bits

6 data bits

7 data bits

CS (write)

D0 to D7

active

t

d18

byte #32

t

d17

TXRDYA,

TXRDYB

trigger

lead

002aab095

Fig 14. Transmit ready timing in FIFO mode

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

35 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 15. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 16. Infrared receive timing

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

36 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

11. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 17. Package outline SOT313-2 (LQFP48)

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC68C652B_2

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SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 30 and 31

Table 30. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 31. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 18.

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

39 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 18. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 32. Abbreviations

Acronym

CPU

Description

Central Processing Unit

DMA

FIFO

IrDA

Direct Memory Access

First In, First Out

Infrared Data Association

Integrated Service Digital Network

Least Signiﬁcant Bit

ISDN

LSB

MSB

Most Signiﬁcant Bit

UART

Universal Asynchronous Receiver and Transmitter

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

40 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

14. Revision history

Table 33. Revision history

Document ID

SC68C652B_2

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20091102

Product data sheet

-

SC68C652B_1

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Data sheet title modiﬁed from “... and Motorola µP interface” to “... and 68 mode µP interface”

• Section 2 “Features”, 3^rdbullet item re-written; added Footnote 1

• Table 10 “Interrupt Enable Register bits description”, description of bit 0: changed from “In the

68C450 mode” to “In the 16C450 mode”

• Table 11 “FIFO Control Register bits description”, description of bit 3: changed from “in the

68C450 mode” to “in the 16C450 mode” (in 2 places)

• Table 27 “Limiting values”:

–

Symbol V_nsplit to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”

Symbol “P_tot(pack)” changed to “P_tot/pack”

Parameter for T_ambchanged from “operating temperature” to “ambient temperature”;

“operating” moved to Conditions column

• Table 28 “Static characteristics”:

–

Descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %” to

“tolerance of V_CC± 10 %”

Symbol/parameter changed from “V_IL(CK), LOW-level clock input voltage” to “V_IL(clk), clock

LOW-level input voltage”

Symbol/parameter changed from “V_IH(CK), HIGH-level clock input voltage” to “V_IH(clk), clock

HIGH-level input voltage”

–

Symbol changed from “I_CL” to “I_L(clk)

”

Parameter for I_CC(sleep)changed from “sleep current” to “sleep mode supply current”

• Table 29 “Dynamic characteristics”:

–

Descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %” to

“tolerance of V_CC± 10 %”

–

Symbol/parameter “t_1w, t_2w, clock cycle period” is split into “t_WH, pulse width HIGH” and

“t_WL, pulse width LOW”

–

Table note [3]: denominator in equation changed from “t_3w” to “t_w(clk)

added Table note [4] and its reference at t_(RESET)

”

• Figure 8 “External clock timing”:

–

“t_w2” changed to “t_WL

“t_w1” changed to “t_WH

“t_w3” changed to “t_w(clk)

”

• Updated soldering information

20050425 Product data sheet

SC68C652B_1

-

(9397 750 14657)

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

41 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

42 of 43

SC68C652B

NXP Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

12.2

12.3

12.4

Wave and reﬂow soldering . . . . . . . . . . . . . . . 38

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 38

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 39

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 42

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

15.1

15.2

15.3

15.4

6

Functional description . . . . . . . . . . . . . . . . . . . 8

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 8

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 9

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 10

Software ﬂow control . . . . . . . . . . . . . . . . . . . 10

Special feature software ﬂow control . . . . . . . 11

Hardware/software and time-out interrupts. . . 11

Programmable baud rate generator . . . . . . . . 12

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 42

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 15

Transmit Holding Register (THR) and

Receive Holding Register (RHR) . . . . . . . . . . 16

Interrupt Enable Register (IER) . . . . . . . . . . . 16

IER versus Transmit/Receive FIFO interrupt

7.2

7.2.1

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 18

FIFO Control Register (FCR) . . . . . . . . . . . . . 18

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 18

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 18

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Status Register (ISR) . . . . . . . . . . . . 21

Line Control Register (LCR) . . . . . . . . . . . . . . 22

Modem Control Register (MCR) . . . . . . . . . . . 23

Line Status Register (LSR). . . . . . . . . . . . . . . 24

Modem Status Register (MSR). . . . . . . . . . . . 25

Scratchpad Register (SPR) . . . . . . . . . . . . . . 25

Enhanced Feature Register (EFR) . . . . . . . . . 26

SC68C652B external reset condition . . . . . . . 27

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28

Static characteristics. . . . . . . . . . . . . . . . . . . . 29

Dynamic characteristics . . . . . . . . . . . . . . . . . 30

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 31

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37

Soldering of SMD packages . . . . . . . . . . . . . . 38

Introduction to soldering . . . . . . . . . . . . . . . . . 38

9

10

10.1

11

12

12.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 November 2009

Document identifier: SC68C652B_2


型号：	935278766157
厂家：	NXP
描述：	2 CHANNEL(S), 5Mbps, SERIAL COMM CONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件：	总43页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935278766157 [NXP]

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