935279244118 [NXP]

I2C BUS CONTROLLER, PDSO20;


型号：	935279244118
厂家：	NXP
描述：	I2C BUS CONTROLLER, PDSO20 时钟光电二极管外围集成电路
文件：	总92页 (文件大小：676K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9665; PCA9665A

Fm+ parallel bus to I²C-bus controller

Rev. 4 — 29 September 2011

Product data sheet

1. General description

The PCA9665/PCA9665A serves as an interface between most standard parallel-bus

microcontrollers/microprocessors and the serial I²C-bus and allows the parallel bus

system to communicate bidirectionally with the I²C-bus. The PCA9665/PCA9665A can

operate as a master or a slave and can be a transmitter or receiver. Communication with

the I²C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake.

The PCA9665/PCA9665A controls all the I²C-bus specific sequences, protocol, arbitration

and timing with no external timing element required.

The PCA9665 and PCA9665A have the same footprint as the PCA9564 with additional

features:

• 1 MHz transmission speeds

• Up to 25 mA drive capability on SCL/SDA

• 68-byte buffer

• I²C-bus General Call

• Software reset on the parallel bus

2. Features and benefits

 Parallel-bus to I²C-bus protocol converter and interface

 Both master and slave functions

 Multi-master capability

 Internal oscillator trimmed to 15 % accuracy reduces external components

 1 Mbit/s and up to 25 mA SCL/SDA I_OL(Fast-mode Plus (Fm+)) capability

 I²C-bus General Call capability

 Software reset on parallel bus

 68-byte data buffer

 Operating supply voltage: 2.3 V to 3.6 V

 5 V tolerant I/Os

 Standard-mode and Fast-mode I²C-bus capable and compatible with SMBus

 PCA9665A ‘glitch-free’ restart is suitable for use with buffer drivers

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Packages offered:

 PCA9665: SO20, TSSOP20, HVQFN20

 PCA9665A: TSSOP20

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

3. Applications

 Add I²C-bus port to controllers/processors that do not have one

 Add additional I²C-bus ports to controllers/processors that need multiple I²C-bus ports

 Converts 8 bits of parallel data to serial data stream to prevent having to run a large

number of traces across the entire printed-circuit board

4. Ordering information

Table 1.

Ordering information

T_amb= 40 C to +85 C.

Type number

Topside

mark

Package

Name

Description

Version

PCA9665BS

9665

HVQFN20

plastic thermal enhanced very thin quad flat package; no leads; SOT662-1

20 terminals; body 5  5  0.85 mm

PCA9665D

PCA9665D SO20

plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

SOT360-1

PCA9665PW

PCA9665

TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

PCA9665APW

CA9665A

TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

2 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

5. Block diagram

data

PCA9665/PCA9665A

BUS BUFFER

SDA

direct registers

FILTER

SD7

SD6

–

SD5

SD4

SD3

SD2

SD1

IP1

SD0

SDA CONTROL

68-BYTE

BUFFER

I2CDAT – data register – read/write

–

IP2

IP0

INDPTR – indirect address pointer – write only

AA ENSIO STA STO SI

ST5

ST4

ST3

ST2

ST1

ST0

–

FILTER

SCL

I2CSTA – status register – read only

–

AA ENSIO STA

STO

MODE

SCL CONTROL

I2CCON – control register – read/write

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

INDIRECT – indirect register access – read/write

ENSIO STA STO SI

indirect registers

INDPTR

BC6

BC5

BC4

BC3

BC2

BC1

BC0

00h

I2CCOUNT – byte count – read/write

AD7

AD6

AD5

AD4

AD3

AD2

AD1

I2CADR – own address – read/write

01h

02h

03h

04h

05h

06h

I2CSCLL – SCL LOW period – read/write

IR7

–

I2CSCLH – SCL HIGH period – read/write

BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

I2CTO – TIMEOUT register – read/write

IR6

IR5

IR4

IR3

IR2

IR1

IR0

I2CPRESET – software reset register – write only

–

AC1

AC0

I2CMODE – I C-bus mode register – read/write

CONTROL BLOCK

INTERRUPT CONTROL

CLOCK SELECTOR

OSCILLATOR

POWER-ON

RESET

002aab023

INT

RESET

control signals

Fig 1. Block diagram of PCA9665/PCA9665A

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

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PCA9665; PCA9665A

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Fm+ parallel bus to I²C-bus controller

6. Pinning information

6.1 Pinning

i.c.

SDA

SCL

RESET

INT

SDA

SCL

RESET

INT

PCA9665PW

PCA9665APW

PCA9665D

002aab020

002aab021

Fig 2. Pin configuration for SO20

Fig 3. Pin configuration for TSSOP20

terminal 1

index area

SCL

RESET

INT

PCA9665BS

002aab022

Transparent top view

Fig 4. Pin configuration for HVQFN20

PCA9665_PCA9665A

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Product data sheet

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4 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

6.2 Pin description

Table 2.

Symbol Pin

SO20,

Pin description

Type

Description

HVQFN20

TSSOP20

i.c.

I/O

Data bus: Bidirectional 3-state data bus used to

transfer commands, data and status between the bus

controller and the CPU. D0 is the least significant bit.

internally connected: must be left floating (pulled

LOW internally)

V_SS

7^[1]

power Supply ground

Write strobe: When LOW and CE is also LOW, the

content of the data bus is loaded into the addressed

WR or CE.

Read strobe: When LOW and CE is also LOW,

causes the contents of the addressed register to be

presented on the data bus. The read cycle begins on

the falling edge of RD.

Chip Enable: Active LOW input signal. When LOW,

data transfers between the CPU and the bus

controller are enabled on D0 to D7 as controlled by

the WR, RD and A0 to A1 inputs. When HIGH,

places the D0 to D7 lines in the 3-state condition.

Data are written into the addressed register on rising

edge of either CE or WR.

Address inputs: Selects the bus controller’s internal

registers and ports for read/write operations.

INT

Interrupt request: Active LOW, open-drain, output.

This pin requires a pull-up device.

RESET 17

Reset: Active LOW input. A LOW level clears

internal registers and resets the I²C-bus state

machine.

SCL

SDA

V_DD

I/O

I²C-bus serial clock input/output (open-drain).

This pin requires a pull-up device.

I²C-bus serial data input/output (open-drain). This pin

requires a pull-up device.

power Power supply: 2.3 V to 3.6 V

[1] HVQFN20 package die supply ground is connected to both the V_SSpin and the exposed center pad. The

V_SSpin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

5 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

7. Functional description

7.1 General

The PCA9665/PCA9665A acts as an interface device between standard high-speed

parallel buses and the serial I²C-bus. On the I²C-bus, it can act either as a master or

slave. Bidirectional data transfer between the I²C-bus and the parallel-bus microcontroller

is carried out on a byte or buffered basis, using either an interrupt or polled handshake.

7.2 Internal oscillator

The PCA9665/PCA9665A contains an internal oscillator which is used for all I²C-bus

timing. Typical oscillator frequency is 28.5 MHz for the PCA9665 and 32 MHz for the

PCA9665A. The oscillator requires up to 550 s to start-up after ENSIO bit is set to ‘1’.

7.3 Registers

The PCA9665/PCA9665A contains eleven registers which are used to configure the

operation of the device as well as to send and receive serial data. There are four registers

that can be accessed directly and seven registers that are accessed indirectly by setting a

The four direct registers are selected by setting pins A0 and A1 to the appropriate logic

levels before a read or write operation is executed on the parallel bus.

The seven indirect registers require that the INDPTR (indirect register pointer, one of the

four direct registers described above) is initially loaded with the address of the register in

the indirect address space before a read or write is performed to the INDIRECT data field.

For example, in order to write to the indirectly addressed I2CSCLL register, the INDPTR

(A1 = 0, A0 = 0). Then the I2CSCLL register can be programmed by writing to the

INDIRECT data field (A1 = 1, A0 = 0) in the direct address space. Register mapping is

described in Table 3, Table 4 and Figure 5.

Remark: Do not write to any I²C-bus registers while the I²C-bus is busy and the

PCA9665/PCA9665A is in master or addressed slave mode.

Table 3.

Direct register selection by setting A0 and A1

I2CSTA

status

Read/Write

Default

F8h

INDPTR

indirect register pointer

data

00h

I2CDAT

R/W

00h

00h^[1]

I2CCON

control

INDIRECT

indirect data field

access

00h

[1] See Section 8.10 “Power-on reset” for more detail.

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

Table 4.

Indirect register selection by setting A1 = 1 and A0 = 0

I2CCOUNT

I2CADR

byte count

INDPTR

00h

Read/Write

R/W

Default

01h

own address

01h

R/W

E0h

9Dh

86h

I2CSCLL

SCL LOW period

SCL HIGH period

time-out

02h

R/W

I2CSCLH

I2CTO

03h

R/W

04h

R/W

FFh

00h

I2CPRESET

I2CMODE

parallel software reset

I²C-bus mode

05h

06h

R/W

00h

yes

A1 A0 = 00

read?

I2CSTA REGISTER

INDPTR REGISTER

yes

A1 A0 = 00

write?

yes

A1 A0 = 10

read/write?

I2CCOUNT REGISTER

I2CADR REGISTER

INDPTR = 00h

INDPTR = 01h

yes

A1 A0 = 01

read/write?

I2CDAT REGISTER

yes

I2CSCLL REGISTER

INDPTR = 02h

A1 A0 = 11

read/write?

I2CCON REGISTER

yes

I2CSCLH REGISTER

I2CTO REGISTER

INDPTR = 03h

INDPTR = 04h

I2CPRESET REGISTER

(write only)

INDPTR = 05h

I2CMODE REGISTER

INDPTR = 06h

RESERVED

002aab459

Fig 5. Register mapping flowchart

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

7 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

7.3.1 Direct registers

7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0)

I2CSTA is an 8-bit read-only register. The two least significant bits are always zero. The

six most significant bits contain the status code. There are 30 possible status codes.

When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is

requested. All other I2CSTA values correspond to defined states. When each of these

states is entered, a serial interrupt is requested (SI = 1 and INT asserted LOW).

Remark: Data in I2CSTA is valid only when a serial interrupt occurs (SI = 1 and INT

asserted LOW). Reading the register when SI = 0 and INT is HIGH may cause wrong

values to be read.

Table 5.

I2CSTA - Status register (A1 = 0, A0 = 0) bit allocation

ST5

ST4

ST3

ST2

ST1

ST0

Table 6.

Bit

I2CSTA - Status register (A1 = 0, A0 = 0) bit description

Symbol

ST[5:0]

Description

7:2

status code corresponding to the different I²C-bus states

1:0

always at zero

7.3.1.2 The Indirect Pointer register, INDPTR (A1 = 0, A0 = 0)

Table 7.

INDPTR - Indirect Register Pointer (A1 = 0, A0 = 0) bit allocation

IP2

IP1

IP0

Table 8.

Bit

INDPTR - Indirect Pointer register (A1 = 0, A0 = 0) bit description

Symbol

Description

7:3

reserved; must be written with zeroes

address of the indirect register

2:0

IP2 to IP0

INDPTR is an 8-bit write-only register. It contains a pointer to a register in the indirect

address space (IP[2:0]). The value in the register will determine what indirect register will

be accessed when the INDIRECT register is read or written, as defined in Table 4.

7.3.1.3 The I²C-bus Data register, I2CDAT (A1 = 0, A0 = 1)

I2CDAT is an 8-bit read/write register. It contains a byte of serial data to be transmitted or

a byte which has just been received. In master mode, this includes the slave address that

the master wants to send out on the I²C-bus, with the most significant bit of the slave

address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU

can read from and write to this 8-bit register while the PCA9665/PCA9665A is not in the

process of shifting a byte. This occurs when PCA9665/PCA9665A is in a defined state

and the serial interrupt flag is set. Data in I2CDAT remains stable as long as SI is set.

Whenever the PCA9665/PCA9665A generates an interrupt, the I2CDAT register contains

the data byte that was just transferred on the I²C-bus.

PCA9665_PCA9665A

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Product data sheet

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the

CPU can read or write up to 68 bytes at a time. See Section 8.1 “Configuration modes” for

more detail.

Remark: The I2CDAT register will capture the serial address as data when addressed via

the serial bus.

Remark: In Byte mode only, the data register will capture data from the serial bus during

38h (arbitration lost in slave address + R/W or data bytes causing this data in I2CDAT to

be changed), so the I2CDAT register will need to be reloaded when the bus becomes free.

In Buffered mode, the data is not written in the data register when arbitration is lost, which

keeps the buffer intact.

Table 9.

I2CDAT - Data register (A1 = 0, A0 = 1) bit allocation

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Table 10. I2CDAT - Data register (A1 = 0, A0 = 1) bit description

Bit

Symbol Description

7:0

SD[7:0]

Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to

a HIGH level on the I²C-bus. A logic 0 corresponds to a LOW level on the bus.

7.3.1.4 The Control register, I2CCON (A1 = 1, A0 = 1)

I2CCON is an 8-bit read/write register. Two bits are affected by the bus controller

hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared

when a STOP condition is present on the I²C-bus. A Write to the I2CCON register via the

parallel interface automatically clears the SI bit, which causes the Serial Interrupt line to

be de-asserted and the next clock pulse on the SCL line to be generated.

Remark: Since none of the registers should be written to via the parallel interface once

the Serial Interrupt line has been de-asserted, all the other registers that need to be

modified should be written to before the content of the I2CCON register is modified.

Table 11. I2CCON - Control register (A1 = 1, A0 = 1) bit allocation

ENSIO

STA

STO

MODE

PCA9665_PCA9665A

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Product data sheet

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PCA9665; PCA9665A

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Fm+ parallel bus to I²C-bus controller

Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description

Bit Symbol Description

The Assert Acknowledge flag.

AA = 1: If the AA flag is set, an acknowledge (LOW level on SDA) will be returned

during the acknowledge clock pulse on the SCL line when:

• ‘Own slave address’ has been received (as defined in I2CADR register).

• A data byte has been received while the bus controller is in the Master

Receiver mode.

• A data byte has been received while the bus controller is in the addressed

Slave Receiver mode.

AA = 0: if the AA flag is reset, a not acknowledge (HIGH level on SDA) will be

returned during the acknowledge clock pulse on SCL when:

• ‘Own slave address’ has been received (as defined in I2CADR register).

• A data byte has been received while the PCA9665/PCA9665A is in the

Master Receiver mode.

• A data byte has been received while the PCA9665/PCA9665A is in the

addressed Slave Receiver mode.

When the bus controller is in the addressed Slave Transmitter mode, state C8h

will be entered after the last data byte is transmitted and an ACK is received from

the Master Receiver (see Figure 9 and Figure 13). When SI is cleared, the

PCA9665/PCA9665A enters the not addressed Slave Receiver mode, and the

SDA line remains at a HIGH level. In state C8h, the AA flag can be set again for

future address recognition.

When the PCA9665/PCA9665A is in the not addressed slave mode, its own slave

address is ignored. Consequently, no acknowledge is returned, and a serial

interrupt is not requested. Thus, the bus controller can be temporarily released

from the I²C-bus while the bus status is monitored. While the bus controller is

released from the bus, START and STOP conditions are detected, and serial data

is shifted in. Address recognition can be resumed at any time by setting the AA

flag.

ENSIO The bus controller enable bit.

ENSIO = 0: When ENSIO is ‘0’, the SDA and SCL outputs are in a

high-impedance state. SDA and SCL input signals are ignored, the

PCA9665/PCA9665A is in the ‘not addressed’ slave state. Internal oscillator is off.

ENSIO = 1: When ENSIO is ‘1’, the PCA9665/PCA9665A is enabled.

After the ENSIO bit is set to ‘1’, it takes 550 s enable time for the internal

oscillator to start up and the serial interface to initialize. The PCA9665/PCA9665A

will enter either the master or the slave mode after this time. ENSIO should not be

used to temporarily release the PCA9665/PCA9665A from the I²C-bus since,

when ENSIO is reset, the I²C-bus status is lost. The AA flag should be used

instead (see description of the AA flag above).

In the following text, it is assumed that ENSIO = ‘1’ for Normal mode operation.

For power-up behavior, please refer to Section 8.10 “Power-on reset”.

PCA9665_PCA9665A

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Product data sheet

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PCA9665; PCA9665A

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Fm+ parallel bus to I²C-bus controller

Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description …continued

Bit Symbol Description

STA

The START flag.

STA = 1: When the STA bit is set to enter a master mode, the bus controller

hardware checks the status of the I²C-bus and generates a START condition if the

bus is free. If the bus is not free, then the bus controller waits for a STOP condition

(which will free the bus) and generates a START condition after the minimum

buffer time (t_BUF) has elapsed.

If STA is set while the bus controller is already in a master mode and one or more

bytes are transmitted or received, the bus controller transmits a repeated START

condition. STA may be set at any time. STA may also be set when the bus

controller is an addressed slave. A START condition will then be generated after a

STOP condition and the minimum buffer time (t_BUF) has elapsed.

STA = 0: When the STA bit is reset, no START condition or repeated START

condition will be generated.

STO

The STOP flag.

STO = 1: When the STO bit is set while the bus controller is in a master mode, a

STOP condition is transmitted on the I²C-bus. When a STOP condition is detected

on the bus, the hardware clears the STO flag.

If the STA and STO bits are both set and the PCA9665/PCA9665A is in master

mode, then a STOP condition is transmitted on the I²C-bus. The bus controller

then transmits a START condition after the minimum buffer time (t_BUF) has

elapsed.

STO = 0 : When the STO bit is reset, no STOP condition will be generated.

The Serial Interrupt flag.

SI = 1: When the SI flag is set, and, if the ENSIO bit is also set, a serial interrupt is

requested. SI is set by hardware when one of 29 of the 30 possible states of the

bus controller states is entered. The only state that does not cause SI to be set is

state F8h, which indicates that no relevant state information is available.

While SI is set, the LOW period of the serial clock on the SCL line is stretched,

and the serial transfer is suspended. A HIGH level on the SCL line is unaffected

by the serial interrupt flag. SI is automatically cleared when the I2CCON register is

written. The SI bit cannot be set by the user.

SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no

stretching of the serial clock on the SCL line.

2:1

Reserved. When I2CCON is read, zeroes are read. Must be written with zeroes.

MODE The Mode flag.

MODE = 0; Byte mode. See Section 8.1.1 “Byte mode” for more detail.

MODE = 1; buffered mode. See Section 8.1.2 “Buffered mode” for more detail.

Remark: ENSIO bit value must be changed only when the I²C-bus is idle.

7.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0 = 0)

The registers in the indirect address space can be accessed using the INDIRECT data

field. Before writing or reading such a register, the INDPTR register should be written with

the address of the indirect register that needs to be accessed. Once the INDPTR register

contains the appropriate value, reads and writes to the INDIRECT data field will actually

read and write the selected indirect register.

PCA9665_PCA9665A

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Product data sheet

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

7.3.2 Indirect registers

7.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h)

The I2CCOUNT register is an 8-bit read/write register. It contains the number of bytes that

have been stored in Master/Slave Buffered Receiver mode, and the number of bytes to be

sent in Master/Slave Buffered Transmitter mode. Bit 7 is the last byte control bit and

applies to the Master/Slave Buffered Receiver mode only. The data in the I2CCOUNT

written) in Byte mode (MODE = 0).

Table 13. I2CCOUNT - Byte Count register (indirect address 00h) bit allocation

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Table 14. I2CCOUNT - Byte Count register (indirect address 00h) bit description

Bit Symbol Description

Last Byte control bit. Master/Slave Buffered Receiver mode only.

LB = 1: PCA9665/PCA9665A does not acknowledge the last received byte.

LB = 0: PCA9665/PCA9665A acknowledges the last received byte. A future

bus transaction must complete the read sequence by not acknowledging the

last byte.

6:0 BC[6:0]

Number of bytes to be read or written (up to 68 bytes). If BC[6:0] is equal to 0 or

greater than 68 (44h), no bytes will be read or written and an interrupt is

immediately generated after writing to the I2CCON register (in Buffered mode

only).

7.3.2.2 The Own Address register, I2CADR (indirect address 01h)

I2CADR is an 8-bit read/write register. It is not affected by the bus controller hardware.

The content of this register is unused when the controller is in a master mode. A master

should never transmit its own slave address. In the slave modes, the seven most

significant bits must be loaded with the microcontroller's own slave address and the least

significant bit determines if the General Call address will be recognized or not.

Remark: AD[7:1] must be different from the General Call address (000 0000) for proper

device operation.

Remark: The I2CADR default value is E0h.

Table 15. I2CADR - Address register (indirect address 01h) bit allocation

AD7

AD6

AD5

AD4

AD3

AD2

AD1

Table 16. I2CADR - Address register (indirect address 01h) bit description

Bit

Symbol Description

7:1

AD[7:1]

Own slave address. The most significant bit corresponds to the first bit received

from the I²C-bus after a START condition. A logic 1 in I2CADR corresponds to a

HIGH level on the I²C-bus, and a logic 0 corresponds to a LOW level on the bus.

General Call.

GC = 1: General Call address (00h) is recognized.

GC = 0: General Call address (00h) is ignored.

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Product data sheet

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PCA9665; PCA9665A

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Fm+ parallel bus to I²C-bus controller

7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)

I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the

PCA9665/PCA9665A when used as a bus master. The actual frequency is determined by

t_HIGH(time where SCL is HIGH), t_LOW(time where SCL is LOW), t_r(rise time), t_f(fall time)

and t_d(delay time) values.

t_HIGHand t_LOWare calculated based on the values that are programmed into I2CSCLH

and I2CSCLL registers and the internal oscillator frequency. t_rand t_fare

system/application dependent. t_dfor the PCA9665 is approximately 175 ns and the

PCA9665A is approximately 300 ns.

------------------------------------------------------------------------------------------------------

f_SCL

(1)

T_oscI2CSCLL + I2CSCLH + t_r+ t_f+ t_d

with T_osc= internal oscillator period = 35 ns  5 ns for the PCA9665 and 33 ns  5 ns for

the PCA9665A

The delay time ‘t_d’ is the sum of the time between the oscillator edge of the SCLL terminal

count until the SCL is up to 0.3V_DDand the oscillator edge of the SCLH terminal count

until the SCL is down to 0.7V_DD

Remark: The I2CMODE register needs to be programmed before programming the

I2CSCLL and I2CSCLH registers in order to know which I²C-bus mode is selected. See

Section 7.3.2.6 “The I²C-bus mode register, I2CMODE (indirect address 06h)” for more

detail.

Standard-mode is the default selected mode at power-up or after reset.

Table 17. I2CSCLL - Clock Rate Low register (indirect address 02h) bit allocation

Table 18. I2CSCLL - Clock Rate Low register (indirect address 02h) bit description

Bit

Symbol

Description

7:0

L[7:0]

Eight bits defining the LOW state of SCL.

Table 19. I2CSCLH - Clock Rate High register (indirect address 03h) bit allocation

Table 20. I2CSCLH - Clock Rate High register (indirect address 03h) bit description

Bit

Symbol

Description

7:0

H[7:0]

Eight bits defining the HIGH state of SCL.

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7.3.2.4 The Time-out register, I2CTO (indirect address 04h)

I2CTO is an 8-bit read/write register. It is used to determine the maximum time that SCL is

allowed to be in a LOW logic state before the I²C-bus state machine is reset or the

PCA9665/PCA9665A initiates a forced action on the I²C-bus.

When the I²C-bus interface is operating, I2CTO is loaded in the time-out counter at every

LOW SCL transition.

Table 21. I2CTO - Time-out register (indirect register 04h) bit allocation

TO6

TO5

TO4

TO3

TO2

TO1

TO0

Table 22. I2CTO - Time-out register (indirect register 04h) bit description

Bit

Symbol

Description

Time-out enable/disable

TE = 1: Time-out function enabled

TE = 0: Time-out function disabled

6:0

TO[6:0]

Time-out value. The time-out value may vary some, and is an

approximate value.

PCA9665 typical time-out period = (I2CTO[6:0] + 1)  143 s.

PCA9665A typical time-out period = (I2CTO[6:0] + 1)  134 s.

The Time-out register can be used in the following cases:

• When the bus controller, in the master mode, wants to send a START condition and

the SCL line is held LOW by some other device. Then the bus controller waits a time

period equivalent to the time-out value for the SCL to be released. In case it is not

released, the bus controller concludes that there is a bus error, loads 78h in the

I2CSTA register, generates an interrupt signal and releases the SCL and SDA lines.

After the microcontroller reads the status register, it needs to send a reset in order to

reset the bus controller.

• In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL

stays LOW for a time period equal to or greater than the time-out value, the bus

controller concludes there is a bus error and behaves in the manner described above.

When the I²C-bus interface is operating, I2CTO is loaded in the time-out counter at

every SCL transition. See Section 8.11 “Reset” for more information.

• In case of a forced access to the I²C-bus. (See more details in Section 8.9.3 “Forced

access to the I²C-bus”.)

7.3.2.5 The Parallel Software Reset register, I2CPRESET (indirect address 05h)

I2CPRESET is an 8-bit write-only register. Programming the I2CPRESET register allows

the user to reset the PCA9665/PCA9665A under software control. The software reset is

achieved by writing two consecutive bytes to this register. The first byte must be A5h while

the second byte must be 5Ah. The writes must be consecutive and the values must match

A5h and 5Ah. If this sequence is not followed as described, the reset is aborted.

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7.3.2.6 The I²C-bus mode register, I2CMODE (indirect address 06h)

I2CMODE is an 8-bit read/write register. It contains the control bits that select the correct

timing parameters when the device is used in master mode (AC[1:0]). Timing parameters

involved with AC[1:0] are t_BUF, t_HD;STA, t_SU;STA, t_SU;STO, t_HIGH, t_LOW

Table 23. I2CMODE - I²C-bus Mode register (indirect address 06h) bit allocation

AC1

AC0

Table 24. I2CMODE - I²C-bus Mode register (indirect address 06h) bit description

Bit

Symbol

Description

7:2

Reserved. When I2CMODE is read, zeroes are read. Must be written

with zeroes.

1:0

AC[1:0]

I²C-bus mode selection to ensure proper timing parameters (see

Table 25 and Table 51).

AC[1:0] = 00: Standard-mode AC parameters selected.

AC[1:0] = 01: Fast-mode AC parameters selected.

AC[1:0] = 10: Fast-mode Plus AC parameters selected.

AC[1:0] = 11: Turbo mode. In this mode, the user is not limited to a

maximum frequency of 1 MHz.

Remark: Change from an I²C-bus mode to a slower one (Fast-mode to Standard-mode,

for example) will cause the HIGH and LOW timings of SCL to be violated. It is then

required to program the I2CSCLL and I2CSCLH registers with values in accordance with

the selected mode.

Table 25. I²C-bus mode selection example^[1]

I2CSCLL

I2CSCLH

I²C-bus frequency (kHz)

AC[1:0] Mode

(hexadecimal)

PCA9665^[2]

PCA9665A^[3]

98.0

103.3

371.4

788.6

932.8

Standard

371.1

Fast

836.8

Fast-mode Plus

Turbo mode

1015

[1] I2CSCLL and I2CSCLH values in the table also represents the minimum values that can be used for the

corresponding I²C-bus mode. Use of lower values will cause the minimum values to be loaded.

------------------------------------------------------------------------------------------------------

[2] Using the formula f_SCL

with T_oscat 30 ns

T_oscI2CSCLL + I2CSCLH + t_r+ t_f+ t_d

(minimum pulse width), t_d= 175 ns, and t_rand t_fat maximum data sheet values for the mode.

------------------------------------------------------------------------------------------------------

[3] Using the formula f_SCL

with T_oscat 28 ns

T_oscI2CSCLL + I2CSCLH + t_r+ t_f+ t_d

(minimum pulse width), t_d= 300 ns, and t_rand t_fat maximum data sheet values for the mode.

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8. PCA9665/PCA9665A modes

8.1 Configuration modes

Byte mode and Buffered mode are selected using the MODE bit in I2CCON register:

MODE = 0: Byte mode

MODE = 1: Buffered mode

8.1.1 Byte mode

The Byte mode allows communication on a single command basis. Only one specific

command is executed at a time and the Status Register is updated once this single

command has been performed. A command can be a START, a STOP, a Byte Write, a

Byte Read, and so on.

8.1.2 Buffered mode

The Buffered mode allows several instructions to be executed before an Interrupt is

generated and before the I2CSTA register is updated. This allows the microcontroller to

request a sequence, up to 68 bytes in a single transmission and lets the

PCA9665/PCA9665A perform it without having to access the Status Register and the

Control Register each time a single command is performed. The microcontroller can then

perform other tasks while the PCA9665/PCA9665A performs the requested sequence.

The number of bytes that needs to be sent from the internal buffer (Transmitter mode) or

received into the internal buffer (Receiver mode) is defined in the indirectly addressed

I2CCOUNT Register (BC[6:0]). Up to 68 bytes can be sent or received.

8.2 Operating modes

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave Receiver

• Slave Transmitter

Each mode can be used on a byte basis (Byte mode) or in an up to 68-byte buffer basis

(Buffered mode).

Data transfers in each mode of operation are shown in Figure 6 through Figure 9. These

figures contain the following abbreviations:

S — START condition

SLA — 7-bit slave address

R — Read bit (HIGH level at SDA)

W — Write bit (LOW level at SDA)

A — Acknowledge bit (LOW level at SDA)

A — Not acknowledge bit (HIGH level at SDA)

Data — 8-bit data byte

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P — STOP condition

In Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12 and Figure 13,

circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not

generated when I2CSTA = F8h. This happens on a STOP condition or when an external

reset is generated (at power-up, when RESET pin is going LOW or during a software

reset on the parallel bus). The numbers in the circles show the status code held in the

I2CSTA register. At these points, a service routine must be executed to continue or

complete the serial transfer. These service routines are not critical since the serial transfer

is suspended until the serial interrupt flag is cleared by software.

When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to

the appropriate service routine. For each status code, the required software action and

details of the following serial transfer are given in Table 27, Table 28, Table 31, Table 32,

Table 35, Table 36, Table 40, and Table 41.

8.3 Byte mode

8.3.1 Master Transmitter Byte mode

In the Master Transmitter Byte mode, a number of data bytes are transmitted to a slave

receiver (see Figure 6). Before the Master Transmitter Byte mode can be entered,

I2CCON must be initialized as shown in Table 26.

Table 26. I2CCON initialization (Byte mode)

Bit

ENSIO

STA

STO

Symbol

Value

reserved reserved MODE

ENSIO must be set to logic 1 to enable the PCA9665/PCA9665A. If the AA bit is reset, the

PCA9665/PCA9665A will not acknowledge its own slave address in the event of another

device becoming master of the bus. (In other words, if AA is reset, PCA9665/PCA9665A

cannot enter a slave mode.) STA, STO, and SI must be reset. Once ENSIO has been set

to 1, it takes about 550 s for the oscillator to start up.

The Master Transmitter Byte mode may now be entered by setting the STA bit. The

I²C-bus state machine will first test the I²C-bus and generate a START condition as soon

as the bus becomes free. When a START condition is transmitted, the serial interrupt flag

(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register

(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service

routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). A

write to I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the

serial transfer to continue.

When the slave address with the direction bit have been transmitted, the Serial Interrupt

flag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is loaded with

the following possible codes:

• 18h if an acknowledgment bit (ACK) has been received

• 20h if an no acknowledgment bit (NACK) has been received

• 38h if the PCA9665/PCA9665A lost the arbitration

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• B0h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

transmitter (slave mode enabled with AA = 1)

• 68h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver (slave mode enabled with AA = 1)

• D8h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver during a General Call sequence (slave mode enabled with AA = 1 and

General Call address enabled with GC = 1 in I2CADR register)

The appropriate action to be taken for each of these status codes is detailed in Table 27.

ENSIO is not affected by the serial transfer and is not referred to in Table 27.

After a repeated START condition (state 10h), the PCA9665/PCA9665A may switch to the

Master Receiver mode by loading I2CDAT with SLA+R.

Remark: A master should not transmit its own slave address.

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successful

transmission

to a Slave Receiver

SLA

F8h

DATA

28h

(2)

08h

18h

next transfer started with a

repeated START condition

SLA

10h

Not Acknowledge received after

the slave address

20h

F8h

to Master Receiver

mode entry = MR

Not Acknowledge received after

a data byte

(4)

30h

(3)

F8h

arbitration lost in slave address

or data byte

other MST

continues

other MST

continues

A or A

38h

A or A

38h

other MST

continues

arbitration lost and addressed as slave

B0h

68h

D8h

to corresponding states in Slave Transmitter mode

to corresponding states in Slave Receiver mode

from master to slave

from slave to master

to corresponding states in Slave Receiver mode (General Call)

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

002aab024

(1) See Table 27

(2) Defined state when a single byte is sent and an ACK is received.

(3) Defined state when a single byte is sent and a NACK is received.

(4) Master Receiver Byte mode is entered when MODE = 0. Master Receiver Buffered mode is entered when MODE = 1.

Fig 6. Format and states in the Master Transmitter Byte mode (MODE = 0)

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Table 27. Master Transmitter Byte mode (MODE = 0)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCON

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

STA STO SI AA MODE

08h

10h

A START condition

has been transmitted

Load SLA+W

Load SLA+W or

Load SLA+R

SLA+W will be transmitted;

ACK/NACK will be received

SLA+W will be transmitted;

ACK/NACK will be received

SLA+R will be transmitted;

A repeated START

condition has been

transmitted

PCA9665/PCA9665A will be

switched to Master Receiver Byte

mode

18h

20h

28h

SLA+W has been

transmitted; ACK has

been received

Load data byte or 0

Data byte will be transmitted;

ACK/NACK will be received

no I2CDAT action 1

Repeated START will be transmitted;

no I2CDAT action 0

STOP condition will be transmitted;

STO flag will be reset

no I2CDAT action 1

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

SLA+W has been

transmitted; NACK

has been received

Load data byte or 0

Data byte will be transmitted;

ACK/NACK will be received

Repeated START will be transmitted;

no I2CDAT action 1

no I2CDAT action 0

STOP condition will be transmitted;

STO flag will be reset

no I2CDAT action 1

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

Data byte in I2CDAT Load data byte or 0

has been transmitted;

Data byte will be transmitted;

ACK/NACK will be received

Repeated START will be transmitted;

ACK has been

no I2CDAT action 1

received

no I2CDAT action 0

STOP condition will be transmitted;

STO flag will be reset

no I2CDAT action 1

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

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Table 27. Master Transmitter Byte mode (MODE = 0) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCON

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

STA STO SI AA MODE

30h

Data byte in I2CDAT Load data byte or 0

Data byte will be transmitted;

ACK/NACK will be received

has been transmitted;

NACK has been

received

no I2CDAT action 1

Repeated START will be transmitted;

no I2CDAT action 0

STOP condition will be transmitted;

STO flag will be reset

no I2CDAT action 1

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

I²C-bus will be released;

38h

Arbitration lost in

No I2CDAT

SLA+W or Data bytes action or

PCA9665/PCA9665A will enter

Slave mode.

I²C-bus will be released;

No I2CDAT

action or

PCA9665/PCA9665A will enter the

Slave mode.

No I2CDAT

action

A START condition will be

transmitted when the bus becomes

free

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8.3.2 Master Receiver Byte mode

In the Master Receiver Byte mode, a number of data bytes are received from a slave

transmitter one byte at a time (see Figure 7). The transfer is initialized as in the Master

Transmitter Byte mode.

The Master Receiver Byte mode may now be entered by setting the STA bit. The I²C-bus

state machine will first test the I²C-bus and generate a START condition as soon as the

bus becomes free. When a START condition is transmitted, the Serial Interrupt flag (SI) is

set, the Interrupt line (INT) goes LOW and the status code in the status register (I2CSTA)

will be 08h. This status code must be used to vector to an interrupt service routine that

loads I2CDAT with the slave address and the data direction bit (SLA+R). A write to

I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the serial

transfer to continue.

When the slave address and the data direction bit have been transmitted, the serial

interrupt flag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is

loaded with the following possible codes:

• 40h if an acknowledgment bit (ACK) has been received for the slave address with

direction bit

• 48h if a no acknowledgment bit (NACK) has been received for the slave address with

direction bit

• 38h if the PCA9665/PCA9665A lost the arbitration

• B0h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

transmitter (slave mode enabled with AA = 1)

• 68h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver (slave mode enabled with AA = 1)

• D8h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver during a General Call sequence (slave mode enabled with AA = 1 and

General Call address enabled with GC = 1 in I2CADR register).

The appropriate action to be taken for each of these status codes is detailed in Table 28.

ENSIO is not affected by the serial transfer and is not referred to in Table 28.

After a repeated START condition (state 10h), the PCA9665/PCA9665A may switch to the

Master Transmitter mode by loading I2CDAT with SLA+W.

Remark: A master should not transmit its own slave address.

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successful

reception from

a Slave Transmitter

SLA

DATA

F8h

DATA

50h

(2)

58h

(3)

08h

40h

next transfer started with a

repeated START condition

SLA

10h

Not Acknowledge received after

the slave address

48h

F8h

to Master Transmitter mode

(4)

entry = MT

arbitration lost in slave address

or Acknowledge bit

other MST

continues

other MST

continues

A or A

38h

other MST

continues

arbitration lost and addressed as slave

B0h

68h

D8h

to corresponding states in Slave Transmitter mode

to corresponding states in Slave Receiver mode

from master to slave

from slave to master

to corresponding states in Slave Receiver mode (General Call)

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

002aab025

(1) See Table 28.

(2) Defined state when a single byte is received and an ACK is sent (AA = 1).

(3) Defined state when a single byte is received and a NACK is sent (AA = 0).

(4) Master Transmitter Byte mode is entered when MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.

Fig 7. Format and states in the Master Receiver Byte mode (MODE = 0)

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Table 28. Master Receiver Byte mode (MODE = 0)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

To/from I2CDAT

To I2CCON

STA STO SI AA MODE

08h

10h

A START condition

has been

transmitted

Load SLA+R

SLA+R will be transmitted;

ACK/NACK bit will be received

A repeated START

condition has been

transmitted

Load SLA+R or

Load SLA+W

SLA+R will be transmitted;

ACK/NACK bit will be received

SLA+W will be transmitted;

PCA9665/PCA9665A will be

switched to Master Transmitter Byte

mode

38h

Arbitration lost in

NACK bit

No I2CDAT action

I²C-bus will be released;

PCA9665/PCA9665A will enter a

slave mode

no I2CDAT action

A START condition will be

transmitted when the bus becomes

free

40h

48h

SLA+R has been

transmitted; ACK

has been received

No I2CDAT action

Data byte will be received;

NACK bit will be returned

Data byte will be received;

ACK bit will be returned

no I2CDAT action

SLA+R has been

transmitted; NACK

has been received

No I2CDAT action

Repeated START condition will be

transmitted

no I2CDAT action

STOP condition will be transmitted;

STO flag will be reset

no I2CDAT action

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

50h

58h

Data byte has been Read data byte or

received; ACK has

Data byte will be received;

NACK bit will be returned

Data byte will be received;

ACK bit will be returned

been returned

read data byte

Data byte has been Read data byte or

received; NACK has

Repeated START condition will be

transmitted

been returned

read data byte or

STOP condition will be transmitted;

STO flag will be reset

read data byte

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

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8.3.3 Slave Receiver Byte mode

In the Slave Receiver Byte mode, a number of data bytes are received from a master

transmitter one byte at a time (see Figure 8). To initiate the Slave Receiver mode, I2CADR

and I2CCON must be loaded as shown in Table 29 and Table 30.

Table 29. I2CADR initialization

Bit

Symbol

Value

AD7

AD6

AD5

AD4

AD3

AD2

AD1

own slave address

The upper 7 bits are the I²C-bus address to which PCA9665/PCA9665A will respond

when addressed by a master. GC is the control bit that allows the PCA9665/PCA9665A to

respond or not to the General Call address (00h).

When programmed to logic 1, the PCA9665/PCA9665A will acknowledge the General

Call address.

When programmed to logic 0, the PCA9665/PCA9665A will not acknowledge the General

Call address.

Table 30. I2CCON initialization

Bit

ENSIO

STA

STO

MODE

Symbol

Value

ENSIO must be set to logic 1 to enable the I²C-bus interface. The AA bit must be set to

enable PCA9665/PCA9665A to acknowledge its own slave address, STA, STO, and SI

must be reset.

When I2CADR and I2CCON have been initialized, the PCA9665/PCA9665A waits until it

is addressed by its own slave address followed by the data direction bit which must be ‘0’

(W) to operate in the Slave Receiver mode. After its own slave address and the W bit have

been received, the Serial Interrupt flag (SI) is set, the Interrupt line (INT) goes LOW, and

I2CSTA is loaded with 60h. This status code is used to vector to an interrupt service

routine, and the appropriate action to be taken is detailed in Table 31.

The Slave Receiver Buffered mode may also be entered when:

• The arbitration is lost while the PCA9665/PCA9665A is in the master mode. See

status 68h and D8h.

• The General Call Address (00h) has been received (General Call address enabled

with GC = 1). See status D0h.

If the AA bit is reset during a transfer, the PCA9665/PCA9665A will return a not

acknowledge (logic 1) on SDA after the next received data byte. While AA is reset, the

I²C-bus state machine does not respond to its own slave address. However, the I²C-bus is

still monitored and address recognition may be resumed at any time by setting AA. This

means that the AA bit may be used to temporarily isolate PCA9665/PCA9665A from the

I²C-bus.

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

reception of

own slave address

and one or more

data bytes;

SLA

DATA

P or S

A0h

DATA

80h

(2)

80h

(2)

60h

all are Acknowledged.

last data byte received is

Not Acknowledged

P or S

88h

(3)

F8h

arbitration lost as MST and

addressed as slave

on STOP

68h

P or S

on STOP

F8h

reception of the

GENERAL

CALL = 00h

General Call address

and one or more

data bytes

DATA

P or S

A0h

DATA

E0h

(2)

E0h

(2)

D0h

last data byte received is

Not Acknowledged

P or S

arbitration lost as MST and

addressed as slave by

General Call

E8h

(3)

F8h

on STOP

D8h

from master to slave

from slave to master

P or S

F8h

on STOP

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

002aab026

(1) See Table 31.

(2) Defined state when a single byte is received and an ACK is sent (AA = 1).

(3) Defined state when a single byte is received and a NACK is sent (AA = 0).

Fig 8. Format and states in the Slave Receiver Byte mode (MODE = 0)

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

Table 31. Slave Receiver Byte mode (MODE = 0)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCON

STA STO SI

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

AA MODE

60h

Own SLA+W has

been received; ACK or

has been returned

No I2CDAT action

Data byte will be received and

NACK will be returned

no I2CDAT action

Data byte will be received and ACK

will be returned

68h

Arbitration lost in

SLA+R/W as

master; Own

SLA+W has been

received, ACK has

been returned

No I2CDAT action

Data byte will be received and

NACK will be returned

no I2CDAT action

Data byte will be received and ACK

will be returned

D0h

D8h

General Call

No I2CDAT action

Data byte will be received and

NACK will be returned.

address (00h) has

been received; ACK

has been returned.

no I2CDAT action

Data byte will be received and ACK

will be returned.

Arbitration lost in

SLA = R/W as

master; General Call

address has been

received; ACK bit

has been returned.

No I2CDAT action

Data byte will be received and

NACK will be returned.

no I2CDAT action

Data byte will be received and ACK

will be returned.

80h

88h

Previously

Read data byte or

read data byte

Data byte will be received and

NACK will be returned

addressed with own

slave address; DATA

has been received;

ACK has been

returned

Data byte will be received and ACK

will be returned

Previously

Read data byte or

read data byte or

Switched to not addressed slave

mode; no recognition of own SLA or

General Call address

addressed with own

slave address; DATA

byte has been

received; NACK has

been returned

Switched to not addressed slave

mode; Own slave address will be

recognized; General Call address

will be recognized if GC = 1.

read data byte or

read data byte

Switched to not addressed slave

mode; no recognition of own slave

address or General Call address. A

START condition will be transmitted

when the bus becomes free

Switched to not addressed slave

mode; Own slave address will be

recognized; General Call will be

recognized if GC = 1. A START

condition will be transmitted when

the bus becomes free.

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

Table 31. Slave Receiver Byte mode (MODE = 0) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCON

STA STO SI

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

AA MODE

E0h

Previously

Read data byte or

Data byte will be received and

NACK will be returned.

addressed with

General Call; Data

has been received;

ACK has been

returned

read data byte

Data byte will be received and ACK

will be returned.

E8h

Previously

Read data byte or

read data byte or

Switched to not addressed slave

mode; no recognition of own slave

address or General Call address.

addressed with

General Call; Data

has been received;

NACK has been

returned

Switched to not addressed slave

mode; own slave address will be

recognized; General Call address

will be recognized if GC = 1.

read data byte or

read data byte

Switched to not addressed slave

mode; no recognition of own slave

address or General Call address. A

START condition will be transmitted

when the bus becomes free.

Switched to not addressed slave

mode; own slave address will be

recognized; General Call address

will be recognized if GC = 1. A

START condition will be transmitted

when the bus becomes free.

A0h

A STOP condition or No I2CDAT action

Switched to not addressed slave

mode; no recognition of own slave

address or General Call address.

repeated START

condition has been

received while still

addressed as Slave

Receiver

No I2CDAT action

Switched to not addressed slave

mode; Own slave address will be

recognized; General Call will be

recognized if GC = 1.

No I2CDAT action

Switched to not addressed slave

mode; no recognition of own slave

address or General Call. A START

condition will be transmitted when

the bus becomes free

No I2CDAT action

Switched to not addressed slave

mode; Own slave address will be

recognized; General Call will be

recognized if GC = 1. A START

condition will be transmitted when

the bus becomes free.

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.3.4 Slave Transmitter Byte mode

In the Slave Transmitter Byte mode, a number of data bytes are transmitted to a master

receiver one byte at a time (see Figure 9). Data transfer is initialized as in the Slave

Receiver Byte mode. When I2CADR and I2CCON have been initialized, the

PCA9665/PCA9665A waits until it is addressed by its own slave address followed by the

data direction bit which must be ‘1’ (R) for the PCA9665/PCA9665A to operate in the

Slave Transmitter mode. After its own slave address and the R bit have been received,

the Serial Interrupt flag (SI) is set, the Interrupt line (INT) goes LOW and I2CSTA is loaded

with A8h. This status code is used to vector to an interrupt service routine, and the

appropriate action to be taken is detailed in Table 32.

The Slave Transmitter Byte mode may also be entered if arbitration is lost while the

PCA9665/PCA9665A is in the master mode. See state B0h and appropriate actions in

Table 32.

If the AA bit is reset during a transfer, the PCA9665/PCA9665A will transmit the last byte

of the transfer and enter state C8h. The PCA9665/PCA9665A is switched to the not

addressed slave mode and will ignore the master receiver if it continues the transfer. Thus

the master receiver receives all ‘1’s as serial data. While AA is reset, the

PCA9665/PCA9665A does not respond to its own slave address. However, the I²C-bus is

still monitored, and address recognition may be resumed at any time by setting AA. This

means that the AA bit may be used to temporarily isolate SIO from the I²C-bus.

reception of own

slave address and

transmission of one

or more data bytes

SLA

DATA

P or S

DATA

B8h

(2)

C0h

(3)

F8h

A8h

on STOP

arbitration lost as MST and

addressed as slave

B0h

from master to slave

from slave to master

last data byte transmitted;

switched to Not Addressed slave

(AA bit in I2CCON = 0)

P or S

ALL '1's

C8h

(4)

F8h

any number of data bytes and

their associated Acknowledge bits

on STOP

DATA

002aab027

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

(1) See Table 31.

(2) Defined state when a single byte is transmitted and an ACK is received.

(3) Defined state when a single byte is transmitted and a NACK is received.

(4) Defined state when a single byte is transmitted and the PCA9665/PCA9665A goes to the non-addressed mode (AA = 0) and an

ACK is received.

Fig 9. Format and states in the Slave Transmitter Byte mode (MODE = 0)

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

Table 32. Slave Transmitter Byte mode (MODE = 0)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCON

Next action taken by

PCA9665/PCA9665A

I²C-bus and the

STA STO SI AA MODE

A8h

Own SLA+R has

been received; ACK or

has been returned

Load data byte

Last data byte will be transmitted and

ACK/NACK bit will be received

load data byte

Data byte will be transmitted;

ACK/NACK will be received

B0h

Arbitration lost in

SLA+R/W as

master; Own SLA+R

has been received,

ACK has been

returned

Load data byte

Last data byte will be transmitted and

ACK/NACK bit will be received

load data byte

Data byte will be transmitted;

ACK bit will be received

B8h

C0h

Data byte in I2CDAT Load data byte

Last data byte will be transmitted and

ACK/NACK bit will be received

has been

transmitted; ACK

has been received

load data byte

Data byte will be transmitted;

ACK/NACK bit will be received

Data byte in I2CDAT No I2CDAT

Switched to not addressed slave mode;

no recognition of own slave address.

General Call address recognized if

GC = 1.

has been

action or

transmitted; NACK

has been received

no I2CDAT

action or

Switched to slave mode; Own slave

address will be recognized. General

Call address recognized if GC = 1.

no I2CDAT

action or

Switched to not addressed slave mode;

no recognition of own slave address.

General Call address recognized if

GC = 1. A START condition will be

transmitted when the bus becomes free

no I2CDAT

action

Switched to slave mode; Own slave

address will be recognized. General

Call address recognized if GC = 1. A

START condition will be transmitted

when the bus becomes free.

C8h

Last data byte in

I2CDAT has been

transmitted (AA = 0);

ACK has been

received

No I2CDAT

action or

Switched to not addressed slave mode;

no recognition of own slave address.

General Call address recognized if

GC = 1.

no I2CDAT

action or

Switched to slave mode; Own slave

address will be recognized. General

Call address recognized if GC = 1.

no I2CDAT

action or

Switched to not addressed slave mode;

no recognition of own slave address.

General Call address recognized if

GC = 1. A START condition will be

transmitted when the bus becomes free

no I2CDAT

action

Switched to slave mode; Own slave

address will be recognized. General

Call address recognized if GC = 1. A

START condition will be transmitted

when the bus becomes free.

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.4 Buffered mode

8.4.1 Master Transmitter Buffered mode

In the Master Transmitter Buffered mode, a number of data bytes are transmitted to a

slave receiver several bytes at a time (see Figure 10). Before the Master Transmitter

Buffered mode can be entered, I2CCON must be initialized as shown in Table 33.

Table 33. I2CCON initialization (Buffered mode)

Bit

ENSIO

STA

STO

Symbol

Value

reserved reserved MODE

Table 34. I2CCOUNT programming

Bit

Symbol

Value

BC6

BC5

BC4

BC3

BC2

BC1

BC0

number of bytes received in a single sequence (1 byte to 68 bytes)

ENSIO must be set to logic 1 to enable the PCA9665/PCA9665A. If the AA bit is reset, the

PCA9665/PCA9665A will not acknowledge its own slave address in the event of another

device becoming master of the bus (in other words, if AA is reset, the

PCA9665/PCA9665A cannot enter a slave mode). STA, STO, and SI must be reset. Once

ENSIO has been set to logic 1, it takes about 550 s for the oscillator to start up.

The Master Transmitter Buffered mode may now be entered by setting the STA bit. The

I²C-bus state machine will first test the I²C-bus and generate a START condition as soon

as the bus becomes free. When a START condition is transmitted, the Serial Interrupt flag

(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register

(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service

routine that loads I2CDAT with the slave address and the data direction bit (SLA+W)

followed by the number of data bytes to be sent. The byte count register (I2CCOUNT) has

been previously programmed with the number of bytes that need to be sent in a single

sequence (BC[6:0]) as shown in Table 34. LB bit is only used for the Receiver Buffered

modes and can be programmed to either logic 0 or logic 1. The total number of bytes

loaded in I2CDAT (slave address with direction bit plus data bytes) must be equal to the

value programmed in I2CCOUNT. A write to I2CCON resets the SI bit, clears the Interrupt

(INT goes HIGH) and allows the serial transfer to continue.

When the slave address with the direction bit and part of or all the following bytes have

been transmitted, the Serial Interrupt flag (SI) is set again, the Interrupt line (INT) goes

LOW again and I2CSTA is loaded with the following possible codes:

• 18h if an acknowledgment bit (ACK) has been received for the slave address with

direction bit (happens only if I2CCOUNT = 1; no data bytes have been sent).

• 20h if a no acknowledgment bit (NACK) has been received for the slave address with

direction bit (no data bytes have been sent).

• 28h if the slave address with direction bit and all the data bytes have been transmitted

and an acknowledgement bit has been received for each of them (number of bytes

sent is equal to value in I2CCOUNT).

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Fm+ parallel bus to I²C-bus controller

• 30h if the slave address with direction bit has been successfully sent and no

acknowledgement (NACK) has been received while transmitting the data bytes

(number of total bytes sent is lower than or equal to value in I2CCOUNT).

• 38h if the PCA9665/PCA9665A lost the arbitration when sending the slave address

with the direction bit or when sending data bytes.

• B0h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

transmitter (slave mode enabled with AA = 1).

• 68h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver (slave mode enabled with AA = 1).

• D8h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver during a General Call sequence (slave mode enabled with AA = 1 and

General Call address enabled with GC = 1 in I2CADR register).

The appropriate action to be taken for each of these status codes is detailed in Table 35.

ENSIO is not affected by the serial transfer and is not referred to in Table 35.

After a repeated START condition (state 10h), the PCA9665/PCA9665A may switch to the

Master Receiver mode by loading I2CDAT with SLA+R).

Remark: A master should not transmit its own slave address.

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

successful

transmission

to a Slave Receiver

SLA

F8h

DATA

18h

(2)

28h

(3)

08h

next transfer started with a

repeated START condition

SLA

10h

Not Acknowledge received after

the slave address

20h

F8h

to MST/REC mode

Not Acknowledge received after

a data byte

(5)

entry = MR

30h

(4)

F8h

arbitration lost in slave address

or data byte

other MST

continues

other MST

continues

A or A

38h

A or A

38h

other MST

continues

arbitration lost and addressed as slave

B0h

68h

D8h

to corresponding states in Slave Transmitter mode

to corresponding states in Slave Receiver mode

from master to slave

from slave to master

to corresponding states in Slave Receiver mode (General Call)

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

002aab659

(1) See Table 35

(2) Serial interrupt that occurs when BC[6:0] = 01. No serial interrupt if BC[6:0] > 01.

(3) Defined state when the number of bytes sent is equal to the value in I2CCOUNT register and an ACK has been received for all

the bytes sent.

(4) Defined state when a NACK received while number of bytes sent is lower than or equal to value in I2CCOUNT register.

(5) Master Receiver Byte mode is entered when MODE = 0. Master Receiver Buffered mode is entered when MODE = 1.

Remark: The master should never transmit its own slave address.

Fig 10. Format and states in the Master Transmitter Buffered mode (MODE = 1)

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

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Table 35. Master Transmitter Buffered mode (MODE = 1)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCOUNT

LB BC[6:0]

Next action taken by the PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

08h

A START condition Load SLA+W and X

Total number of bytes

SLA+W will be transmitted. If ACK bit received,

data bytes will be transmitted until all of them

have been sent and an ACK has been received

for each of them or until a NACK bit is received.

has been

the data bytes

to be transmitted

(= SLA+W + number

of data bytes)

transmitted

10h

A repeated START Load SLA+W and X

condition has been the data bytes or

transmitted

Total number of bytes

to be transmitted

(= SLA+W + number

of data bytes)

SLA+W will be transmitted. If ACK bit received,

data bytes will be transmitted until all of them

have been sent and an ACK has been received

for each of them or until a NACK bit is received.

Load SLA+R

Total number of bytes

to be received

SLA+R will be transmitted.

PCA9665/PCA9665A will be switched to Master

Receiver Buffered mode.

18h

SLA+W has been

transmitted; ACK

has been received

Load the data

bytes or

Total number of data

bytes to be

transmitted

Up to BC[6:0] data bytes will be transmitted (until

all of them have been sent and an ACK has

been received for each of them or until a NACK

bit is received).

no I2CDAT action X

Repeated START will be transmitted.

no I2CDAT action X

STOP condition will be transmitted.

STO flag will be reset.

no I2CDAT action X

STOP condition followed by a START condition

will be transmitted.

STO flag will be reset.

20h

SLA+W has been

Load the data

Total number of data

bytes to be

transmitted

Up to BC[6:0] data bytes will be transmitted (until

all of them have been sent and an ACK has

been received for each of them or until a NACK

bit is received).

transmitted; NACK bytes or

has been received

no I2CDAT action 1

Repeated START will be transmitted.

no I2CDAT action 0

STOP condition will be transmitted;.

STO flag will be reset.

no I2CDAT action 1

STOP condition followed by a START condition

will be transmitted.

STO flag will be reset.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 35. Master Transmitter Buffered mode (MODE = 1) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To I2CCOUNT

LB BC[6:0]

Next action taken by the PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

28h

30h

38h

BC[6:0] bytes in

I2CDAT have been bytes or

transmitted; ACK

has been received

for all of them

Load the data

Total number of data

bytes to be

transmitted

Up to BC[6:0] data bytes will be transmitted (until

all of them have been sent and an ACK has

been received for each of them or until a NACK

bit is received).

no I2CDAT action X

Repeated START will be transmitted.

no I2CDAT action X

STOP condition will be transmitted.

STO flag will be reset.

no I2CDAT action X

TOP condition followed by a START condition

will be transmitted.

STO flag will be reset.

Up to BC[6:0] bytes Load the data

in I2CDAT have

been transmitted;

Total number of data

bytes to be

transmitted

Up to BC[6:0] data bytes will be transmitted (until

all of them have been sent and an ACK has

been received for each of them or until a NACK

bit is received).

bytes or

NACK has been

received for the last

byte

no I2CDAT action X

Repeated START will be transmitted.

no I2CDAT action X

STOP condition will be transmitted.

STO flag will be reset.

no I2CDAT action X

STOP condition followed by a START condition

will be transmitted.

STO flag will be reset.

I²C-bus will be released; PCA9665/PCA9665A

will enter the not addressed slave mode.

I²C-bus will be released; PCA9665/PCA9665A

will enter the slave mode.

Arbitration lost in

SLA+W or

Data bytes

No I2CDAT

action or

No I2CDAT

action or

No I2CDAT

action

A START condition will be transmitted when the

bus becomes free.

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.4.2 Master Receiver Buffered mode

In the Master Receiver Buffered mode, a number of data bytes are received from a slave

transmitter several bytes at a time (see Figure 11). The transfer is initialized as in the

Master Transmitter Byte mode.

The Master Receiver Buffered mode may now be entered by setting the STA bit. The

I²C-bus state machine will first test the I²C-bus and generate a START condition as soon

as the bus becomes free. When a START condition is transmitted, the Serial Interrupt flag

(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register

(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service

routine that loads I2CDAT with the slave address and the data direction bit (SLA+R). The

byte count register (I2CCOUNT) needs to be programmed with the number of bytes that

need to be received in a single sequence (BC[6:0]). LB bit is programmed with logic 0 if

the last received byte needs to be acknowledged (read operation still ongoing) or with

logic 1 if the last received byte needs to be not acknowledged (read operation ends so the

PCA9665/PCA9665A can issue a STOP or Re-START condition). A write to I2CCON

resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the serial transfer to

continue.

When the slave address and the data direction bit have been transmitted and all the data

bytes have been received, the Serial Interrupt flag (SI) is set again, the Interrupt line (INT)

goes LOW again and I2CSTA is loaded with the following possible codes:

• 48h if a no acknowledgment bit (NACK) has been received for the slave address with

direction bit

• 50h when all the bytes have been received and an acknowledgement bit (ACK) has

been returned for all the bytes

• 58h when all the bytes have been received and an acknowledgement bit (ACK) has

been returned for all the bytes except the last one

• 38h if the PCA9665/PCA9665A lost the arbitration

• B0h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

transmitter (slave mode enabled with AA = 1)

• 68h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver (slave mode enabled with AA = 1)

• D8h if the PCA9665/PCA9665A lost the arbitration and is addressed as a slave

receiver during a General Call sequence (slave mode enabled with AA = 1 and

General Call address enabled with GC = 1 in I2CADR register).

The appropriate action to be taken for each of these status codes is detailed in Table 36.

ENSIO is not affected by the serial transfer and is not referred to in Table 36.

After a repeated START condition (state 10h), the PCA9665 may switch to the Master

Transmitter mode by loading I2CDAT with SLA+W.

Remark: A master should not transmit its own slave address.

PCA9665_PCA9665A

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Product data sheet

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36 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

successful

reception

from a Slave

Transmitter

SLA

DATA

F8h

DATA

(2)

50h

(3)

58h

(4)

08h

next transfer

started with a

repeated START

condition

SLA

10h

Not Acknowledge

received after

the slave address

48h

F8h

to Master Transmitter mode

(5)

entry = MT

arbitration lost in

slave address

or Acknowledge bit

other MST

continues

other MST

continues

A or A

38h

other MST

continues

arbitration lost and

addressed as slave

B0h

68h

D8h

to corresponding states in Slave Transmitter mode

to corresponding states in Slave Receiver mode

from master to slave

to corresponding states in Slave Receiver mode (General Call)

from slave to master

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

to a defined state of the I C-bus.

002aab660

(1) See Table 28.

(2) No serial interrupt.

(3) Defined state when LB = 0 and the number of bytes received is equal to the value in I2CCOUNT register.

(4) Defined state when LB = 1 and the number of bytes received is equal to the value in I2CCOUNT register.

(5) Master Transmitter Byte mode is entered with MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.

Fig 11. Format and states in the Master Receiver Buffered mode (MODE = 1)

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

37 of 92

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Table 36. Master Receiver Buffered mode (MODE = 1)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

08h

A START condition

has been transmitted

Load SLA+R

Total number of bytes

to be received

SLA+R will be transmitted.

If ACK bit received, BC[6:0] data bytes will be

received, ACK bit will be returned for all of

them.

Total number of bytes

to be received

SLA+R will be transmitted.

If ACK bit received, BC[6:0] data bytes will be

received, ACK bit will be returned for all of

them, except for the last one where NACK bit

will be returned.

10h

A repeated START

condition has been

transmitted

Load SLA+R or

Total number of bytes

to be received

SLA+R will be transmitted.

If ACK bit received, BC[6:0] data bytes will be

received, ACK bit will be returned for all of

them.

Total number of bytes

to be received

SLA+R will be transmitted.

If ACK bit received, BC[6:0] data bytes will be

received, ACK bit will be returned for all of

them, except for the last one where NACK bit

will be returned.

Load SLA+W and

the data bytes

Total number of bytes

to be transmitted

(= SLA+W + number

of data bytes)

SLA+W will be transmitted;

PCA9665/PCA9665A will be switched to

Master Transmitter Buffered mode.

38h

48h

Arbitration lost in

NACK bit

No I2CDAT action X

I²C-bus will be released;

PCA9665/PCA9665A will enter slave mode.

No I2CDAT action X

A START condition will be transmitted when

the bus becomes free.

SLA+R has been

transmitted;

No I2CDAT action X

Repeated START condition will be

transmitted.

NACK has been

received

No I2CDAT action X

STOP condition will be transmitted;

STO flag will be reset.

No I2CDAT action X

STOP condition followed by a START

condition will be transmitted;

STO flag will be reset.

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Table 36. Master Receiver Buffered mode (MODE = 1) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

50h

58h

BC[6:0] data bytes

have been received; or

ACK has been

returned for all the

bytes

Read data bytes

Total number of bytes

to be received

BC[6:0] data bytes will be received, ACK bit

will be returned for all of them

Read data bytes

Total number of bytes

to be received

BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the

last one where NACK bit will be returned

BC[6:0] data bytes

have been received; or

ACK has been

returned for all the

bytes, except for the

Read data bytes

Repeated START condition will be transmitted

Read data bytes

STOP condition will be transmitted;

STO flag will be reset.

last one where NACK Read data bytes

bit has been returned

STOP condition followed by a START

condition will be transmitted;

STO flag will be reset.

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.4.3 Slave Receiver Buffered mode

In the Slave Receiver Buffered mode, a number of data bytes are received from a master

transmitter several bytes at a time (see Figure 12). To initiate the Slave Receiver Byte

mode, I2CADR and I2CCON must be loaded as shown in Table 37 and Table 38.

Table 37. I2CADR initialization

Bit

Symbol

Value

AD7

AD6

AD5

AD4

AD3

AD2

AD1

own slave address

The upper 7 bits are the I²C-bus address to which PCA9665/PCA9665A will respond

when addressed by a master. GC is the control bit that allows the PCA9665/PCA9665A to

respond or not to the General Call address (00h).

When programmed to logic 1, the PCA9665/PCA9665A will acknowledge the General

Call address.

When programmed to logic 0, the PCA9665/PCA9665A will not acknowledge the General

Call address.

Table 38. I2CCON initialization

Bit

ENSIO

STA

STO

MODE

Symbol

Value

Table 39. I2CCOUNT programming

Bit

Symbol

Value

BC6

BC5

BC4

BC3

BC2

BC1

BC0

number of bytes received in a single sequence (1 byte to 68 bytes)

ENSIO must be set to logic 1 to enable the I²C-bus interface. The AA bit must be set to

enable the PCA9665/PCA9665A to acknowledge its own slave address; STA, STO, and

SI must be reset.

When I2CADR and I2CCON have been initialized, the PCA9665/PCA9665A waits until it

is addressed by its own slave address followed by the data direction bit which must be ‘0’

(W) to operate in the Slave Receiver mode. After its own slave address and the W bit have

been received, the Serial Interrupt flag (SI) is set, the Interrupt line (INT) goes LOW and

I2CSTA is loaded with 60h. This status code is used to vector to an interrupt service

routine, and the appropriate action to be taken is detailed in Table 40.

The Slave Receiver Buffered mode may also be entered when:

• The arbitration is lost while the PCA9665/PCA9665A is in the master mode. See

status 68h and D8h.

• The General Call Address (00h) has been received (General Call address enabled

with GC = 1). See status D0h.

Appropriate actions to be taken from these status codes are also detailed in Table 40.

The byte count register (I2CCOUNT) is programmed with the number of bytes that need

to be sent in a single sequence (BC[6:0]) as shown in Table 39.

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Product data sheet

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PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

If the LB bit is reset (logic 0), the PCA9665/PCA9665A will return an acknowledge for all

the bytes that will be received. The maximum number of bytes that are received in a single

sequence is defined by BC[6:0] in I2CCOUNT register as shown in Table 39.

If the LB bit is set (logic 1) during a transfer, the PCA9665/PCA9665A will return a not

acknowledge (logic 1) on SDA after receiving the last byte. If the AA bit is reset, the

I²C-bus state machine does not respond to its own slave address. However, the I²C-bus is

still monitored and address recognition may be resumed at any time by setting AA. This

means that the AA bit may be used to temporarily isolate the PCA9665/PCA9665A from

the I²C-bus.

(4)

reception of

own slave address

and one or more

data bytes;

SLA

DATA

P or S

A0h

80h

(2)

80h

(2)

60h

all are Acknowledged

last data byte received is

Not Acknowledged

P or S

arbitration lost as MST and

addressed as slave

88h

(3)

F8h

on STOP

68h

P or S

F8h

(4)

on STOP

reception of the

GENERAL

CALL = 00h

General Call address

and one or more

data bytes

DATA

P or S

A0h

D0h

E0h

(2)

E0h

(2)

last data byte received is

Not Acknowledged

P or S

arbitration lost as MST and

addressed as slave by

General Call

E8h

(3)

F8h

on STOP

D8h

from master to slave

from slave to master

P or S

F8h on STOP

any number of data bytes and

their associated Acknowledge bits

DATA

This number (contained in I2CSTA) corresponds

(1)

002aab661

to a defined state of the I C-bus.

(1) See Table 40.

(2) Defined state when the number of bytes received is equal to the value in I2CCOUNT register and LB = 0.

(3) Defined state when the number of bytes received is equal to the value in I2CCOUNT register and LB = 1.

(4) Number of bytes received is lower than I2CCOUNT.

Fig 12. Format and states in the Slave Receiver Buffered mode (MODE = 1)

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

41 of 92

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Table 40. Slave Receiver Buffered mode (MODE = 1)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

60h

68h

D0h

D8h

Own SLA+W has

been received;

No I2CDAT action 0

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them.

ACK has been

returned

No I2CDAT action 1

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the last

one where NACK bit will be returned (unless

master transmitter sends a STOP or Repeated

START condition before).

Arbitration lost in

SLA+R/W as master; or

No I2CDAT action 0

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them.

Own SLA+W has

been received;

No I2CDAT action 1

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the last

one where NACK bit will be returned (unless

master transmitter sends a STOP or Repeated

START condition before).

ACK has been

returned

General Call address No I2CDAT action 0

(00h) has been

received;

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them.

ACK has been

returned.

No I2CDAT action 1

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the last

one where NACK bit will be returned (unless

master transmitter sends a STOP or Repeated

START condition before).

Arbitration lost in

SLA = R/W as

master;

No I2CDAT action 0

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them.

General Call address

has been received;

No I2CDAT action 1

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the last

one where NACK bit will be returned (unless

master transmitter sends a STOP or Repeated

START condition before).

ACK bit has been

returned.

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Table 40. Slave Receiver Buffered mode (MODE = 1) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

80h

Previouslyaddressed Read data bytes

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them.

with own slave

address;

BC[6:0] data bytes

have been received;

ACK has been

returned for all the

bytes

Read data bytes

Total number of

bytes to be

received

Up to BC[6:0] data bytes will be received, ACK bit

will be returned for all of them, except for the last

one where NACK bit will be returned (unless

master transmitter sends a STOP or Repeated

START condition before).

88h

Previouslyaddressed Read data bytes

Switched to not addressed slave mode;

No recognition of own slave address; General

Call address will be recognized if GC = 1.

with own slave

address;

BC[6:0] data bytes

have been received;

ACK has been

Read data bytes

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1.

returned for all the

bytes, except for the

last one where NACK

bit has been returned

Read data bytes

Switched to not addressed slave mode;

No recognition of own slave address; General

Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

Read data bytes

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

E0h

Previouslyaddressed Read data bytes

Total number of

bytes to be

received

BC[6:0] data bytes will be received, ACK bit will

be returned for all of them.

with General Call;

BC[6:0] data bytes

have been received;

ACK has been

returned for all the

bytes

Read data bytes

Total number of

bytes to be

received

BC[6:0] data bytes will be received, ACK bit will

be returned for all of them, except for the last one

where NACK bit will be returned (unless master

transmitter sends a STOP or Repeated START

condition before).

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Table 40. Slave Receiver Buffered mode (MODE = 1) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

E8h

Previouslyaddressed Read data bytes

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if GC = 1

with General Call;

BC[6:0] data bytes

have been received;

ACK has been

returned for all the

bytes, except for the

last one where NACK

bit has been returned

Read data bytes

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1

Read data bytes

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

Read data bytes

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

A0h

A STOP condition or No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if GC = 1

repeated START

condition has been

received while still

addressed as slave

receiver

No I2CDAT action X

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1

No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

No I2CDAT action X

Switched to not addressed slave mode;

Own slave address will be recognized;

General Call address will be recognized if GC = 1;

A START condition will be transmitted when the

bus becomes free.

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.4.4 Slave Transmitter Buffered mode

In the Slave Transmitter Buffered mode, a number of data bytes are transmitted to a

master receiver several bytes at a time (see Figure 13). Data transfer is initialized as in

the Slave Receiver Buffered mode. When I2CADR and I2CCON have been initialized, the

PCA9665/PCA9665A waits until it is addressed by its own slave address followed by the

data direction bit which must be ‘1’ (R) for the PCA9665/PCA9665A to operate in the

Slave Transmitter mode. After its own slave address and the R bit have been received,

the Serial Interrupt flag (SI) is set, the Interrupt line (INT) goes LOW and I2CSTA is loaded

with A8h. This status code is used to vector to an interrupt service routine, and the

appropriate action to be taken is detailed in Table 41.

The Slave Transmitter Buffered mode may also be entered if arbitration is lost while the

PCA9665/PCA9665A is in the master mode. See state B0h and appropriate actions in

Table 41.

The byte count register (I2CCOUNT) is programmed with the number of bytes that need

to be sent in a single sequence (BC[6:0]) as shown in Table 39. LB bit is only used for the

Receiver Buffered modes and can be programmed to either logic 0 or logic 1.

If the AA bit is reset during a transfer, the PCA9665/PCA9665A will transmit all the bytes

of the transfer (values defined by BC[6:0]) and enter state C8h. The PCA9665/PCA9665A

is switched to the not addressed slave mode and will ignore the master receiver if it

continues the transfer. Thus the master receiver receives all ‘1’s as serial data. While AA

is reset, the PCA9665/PCA9665A does not respond to its own slave address. However,

the I²C-bus is still monitored, and address recognition may be resumed at any time by

setting AA. This means that the AA bit may be used to temporarily isolate the

PCA9665/PCA9665A from the I²C-bus.

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

45 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

reception of own

slave address and

transmission of one

or more data bytes

SLA

DATA

P or S

DATA

A8h

B8h

(2)

C0h

(3)

F8h

on STOP

arbitration lost as MST and

addressed as slave

B0h

from master to slave

from slave to master

last data byte transmitted;

switched to Not Addressed slave

(AA bit in I2CCON = 0)

P or S

ALL '1's

C8h

(4)

F8h

any number of data bytes and

their associated Acknowledge bits

DATA

on STOP

This number (contained in I2CSTA) corresponds

002aab662

(1)

to a defined state of the I C-bus.

(1) See Table 31.

(2) Defined state when the number of bytes sent is equal to the value in I2CCOUNT register.

(3) Defined state when a NACK is received. The number of bytes transmitted is lower than or equal to the value in the I2CCOUNT

(4) Defined state after the last byte has been transmitted and the PCA9665/PCA9665A goes to the non-addressed mode (AA = 0)

and an ACK is received. The number of bytes that are transmitted is equal to the value in I2CCOUNT register.

Fig 13. Format and states in the Slave Transmitter Buffered mode (MODE = 1)

PCA9665_PCA9665A

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Product data sheet

Rev. 4 — 29 September 2011

46 of 92

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Table 41. Slave Transmitter Buffered mode (MODE = 1)

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

A8h

B0h

B8h

C0h

Own SLA+R has

been received;

ACK has been

returned

Load data bytes

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

PCA9665/PCA9665A switches to the not

addressed mode after BC[6:0] bytes have

been transmitted.

Load data bytes

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

Arbitration lost in

SLA+R/W as

master; Own SLA+R

has been received,

ACK has been

returned

Load data bytes

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

PCA9665/PCA9665A switches to the not

addressed mode after BC[6:0] bytes have

been transmitted

Load data bytes

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

BC[6:0] bytes in

I2CDAT have been or

transmitted;

ACK has been

received

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

PCA9665/PCA9665A switches to the not

addressed mode after BC[6:0] bytes have

been transmitted

Load data bytes

Total number of data

bytes to be transmitted

Up to BC[6:0] bytes will be transmitted.

Up to BC[6:0] bytes No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address recognized if GC = 1

in I2CDAT have

been transmitted;

NACK has been

received

No I2CDAT action X

Switched to slave mode; Own slave address

will be recognized; General Call address

recognized if GC = 1

No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if

GC = 1; A START condition will be

transmitted when the bus becomes free

No I2CDAT action X

Switched to slave mode; Own slave address

will be recognized; General Call address will

be recognized if GC = 1; A START condition

will be transmitted when the bus becomes

free

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Table 41. Slave Transmitter Buffered mode (MODE = 1) …continued

Status

code

(I2CSTA) PCA9665/65A

Status of the

Application software response

To/from I2CDAT To/from I2CCOUNT

LB BC[6:0]

Next action taken by the

PCA9665/PCA9665A

I²C-bus and the

To I2CCON

STA STO SI AA MODE

C8h BC[6:0] bytes in

No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address recognized if GC = 1.

I2CDAT have been or

transmitted

(AA = 0);

ACK has been

received

No I2CDAT action X

Switched to slave mode; Own slave address

will be recognized; General Call address

recognized if GC = 1.

No I2CDAT action X

Switched to not addressed slave mode;

No recognition of own slave address;

General Call address will be recognized if

GC = 1; A START condition will be

transmitted when the bus becomes free.

No I2CDAT action X

Switched to slave mode; Own slave address

will be recognized; General Call address will

be recognized if GC = 1; A START condition

will be transmitted when the bus becomes

free.

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

8.5 Buffered mode examples

8.5.1 Buffered Master Transmitter mode of operation

1. Program the I2CCOUNT register with the number of bytes that need to be sent to the

I²C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver mode only

and can be set to 0 or 1.

2. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in

the PCA9665/PCA9665A buffer. There is no protection against writing over a buffer’s

boundary. If more than 68 bytes are written to the buffer, the data at address 00h will

be overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to

BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],

therefore, if the number of data bytes loaded is greater than BC[6:0], the additional

data will not be sent. If the number of data bytes written to the buffer is less than

BC[6:0], the PCA9665/PCA9665A will still send out BC[6:0] data bytes.

3. Program I2CCON register to initiate the Master Transmitter Buffered sequence. In

Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and

the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA

a write to the I2CCON register is performed.

4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.

That clears the previous Interrupt. If a START command has been previously sent, the

first byte loaded into the buffer and sent to the I²C-bus is interpreted as the

I²C-bus address + R/W operation. In transmitter mode, R/W = 0 and the following

bytes that are sent to the I²C-bus are interpreted as data bytes.

5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set

in the I2CCON register. The I2CSTA register contains the status of the transmission

and the I2CCOUNT register contains the number of bytes that have been sent to the

I²C-bus as described in Table 42.

6. More sequence (program I2CCOUNT register, load data bytes in I2CDAT buffer, write

the I2CCON register to send the data to the I²C-bus, read the I2CSTA register when

the sequence has been executed) can be performed as long as a STOP or Repeated

START command has not been sent. Master Transmitter Buffered mode ends when

the I2CCOUNT register is programmed with STO = 1.

8.5.2 Buffered Master Receiver mode of operation

1. Program the I2CCOUNT register with the number of bytes that need to be read from a

slave device in the I²C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in

Receiver mode to let the PCA9665/PCA9665A know if the last byte received must be

acknowledged or not.

LB = 0: Last received byte is acknowledged and another sequence can be executed.

LB = 1: Last received byte is not acknowledged. The last sequence before sending a

STOP or Repeated START must be executed with LB = 1.

2. Load the I²C-bus address + R/W = 1 in I2CDAT buffer.

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3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In

Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and

the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA

a write to the I2CCON register is performed.

4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.

That clears the previous Interrupt. If a START command has been previously sent, the

I²C-bus address + R/W = 1 byte that has been loaded into the buffer is sent to the

I²C-bus, the PCA9665/PCA9665A then becomes a master receiver device and starts

receiving data from the addressed slave device.

Remark: The PCA9665/PCA9665A is already a master receiver device if a buffered

sequence has been previously executed.

5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set

in the I2CCON register. The I2CSTA register contains the status of the transmission

and the I2CCOUNT register contains the number of bytes that have been received.

I2CDAT buffer contains all the data that has been received and can be read by the

microcontroller.

6. More sequences (program the I2CCOUNT register, write to the I2CCON register, read

the I2CSTA register when sequence has been executed, read the I2CDAT buffer) can

be performed as long as a STOP or a Repeated START command has not been sent.

To be able to end the reception, the last buffered sequence must be performed with

LB = 1. Master Receiver Buffered mode ends when the I2CCOUNT register is

programmed with STO = 1.

8.5.3 Buffered Slave Transmitter mode

1. An interrupt is asserted and the SI bit is set in the I2CCON register when the

PCA9665/PCA9665A’s own slave address has been detected on the I²C-bus (AA = 1,

own slave address defined in the I2CADR register). In Slave Transmitter mode,

R/W = 1.

2. Program the I2CCOUNT register with the number of bytes that need to be sent to the

I²C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver Buffered

mode only.

3. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in

the PCA9665/PCA9665A buffer. There is no protection against writing over a buffer’s

boundary. If more than 68 bytes are written to the buffer, the data at address 00h will

be overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to

BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],

therefore, if the number of data bytes loaded is greater than BC[6:0], the additional

data will not be sent. If the number of data bytes written to the buffer is less than

BC[6:0], the PCA9665/PCA9665A will still send out BC[6:0] data bytes.

4. The I2CCON is programmed to clear the previous Interrupt. The bytes loaded into the

buffer are sent to the I²C-bus. MODE bits must be set to ‘1’ each time a write to the

I2CCON register is performed.

5. When the sequence has been executed (BC[6:0] bytes sent or the master sent a

NACK), an Interrupt is asserted and the SI bit is set in the I2CCON register. The

I2CSTA register contains the status of the transmission and the I2CCOUNT register

contains the number of bytes that have been sent to the I²C-bus.

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6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer,

write the I2CCON register to send the data to the I²C-bus, read the I2CSTA register

when sequence has been executed) can be performed as long as the master

acknowledges the bytes sent by the PCA9665/PCA9665A and AA = 1. Slave

Transmitter Buffered mode ends when the I²C-bus master does not acknowledge a

byte or when the PCA9665/PCA9665A goes to Non-addressed Slave mode.

8.5.4 Buffered Slave Receiver mode

1. An interrupt is asserted and the SI bit is set in the I2CCON register when the

PCA9665/PCA9665A‘s own slave address has been detected in the I²C-bus (AA = 1,

own slave address defined in the I2CADR register). In Slave Receiver mode,

R/W = 0.

2. Program the I2CCOUNT register with the number of bytes that needs to be read from

a master device in the I²C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in

Receiver mode to let the PCA9665/PCA9665A know if the last byte received must be

acknowledged or not.

LB = 0: Last received byte is acknowledged and another sequence can be executed.

LB = 1: Last received byte is not acknowledged.

3. The I2CCON is programmed to clear the previous Interrupt. The

PCA9665/PCA9665A receives data from the I²C-bus master. MODE bit must be set to

‘1’ each time a write to the I2CCON register is performed.

4. When the sequence has been executed (BC[6:0] bytes have been received or the

master sent a STOP or Repeated START command), an Interrupt is asserted and the

SI bit is set in the I2CCON register. The I2CSTA register contains the status of the

transmission and the I2CCOUNT register contains the number of bytes that have

been received. I2CDAT buffer contains all the data that has been received and can be

read by the microcontroller.

5. More sequence (program the I2CCOUNT register, write to the I2CCON register, read

the I2CDAT buffer) can be performed as long as a STOP or a Repeated START

command has not been sent by the I²C-bus master. Slave Receiver Buffered mode

ends when the I²C-bus master sends a STOP or Repeated START command, or

when the PCA9665/PCA9665A does not acknowledge the received bytes any more.

8.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM

(I²C-bus address = A0h for write operations and A1h for read operations)

starting at Location 08h

1. Program I2CCOUNT = 02h (2 bytes to be sent): I²C-bus slave address and memory

allocation.

2. Write A0h (I²C-bus slave address and write command) and 08h (Location) into the

I2CDAT register.

3. Program I2CCON with STA = 1, STO = SI = 0, MODE = 1.

– the PCA9665/PCA9665A sends a START command

– the PCA9665/PCA9665A sends an interrupt, sets SI = 1 and updates I2CSTA

– I2CSTA reads 08h

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4. Program I2CCON with STA = STO = SI = 0, MODE = 1.

– I²C-bus slave address A0h, then EEPROM sub address 08h is sent on the bus

– the SCL line is held LOW by the PCA9665/PCA9665A after the 2 bytes have been

sent

– the PCA9665/PCA9665A sends an Interrupt, sets SI = 1 and updates I2CSTA

– I2CSTA reads 28h

5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged).

6. Load I2CDAT with A1h (I²C-bus slave address and Read command).

7. Program I2CCON with STA = 1, SI = 0, MODE = 1.

– the PCA9665/PCA9665A sends a ReSTART command

– an interrupt is asserted and the I2CSTA register is updated

– the I2CSTA register reads 10h

8. Program I2CCON with STA = STO = SI = 0, MODE = 1.

– address A1h is sent followed by a read of 64 data bytes

– the last data byte is acknowledged

– the SCL line is held LOW by the PCA9665/PCA9665A after the data is read

– the PCA9665/PCA9665A sends an interrupt and updates I2CSTA register

– I2CSTA reads 50h

9. The microcontroller reads the 64 data bytes from the PCA9665/PCA9665A.

10. Program I2CCOUNT = C0h (64 bytes and Last byte is not acknowledged).

11. Program I2CCON with STA = STO = SI = 0, MODE = 1.

12. The PCA9665/PCA9665A reads 64 bytes and does not acknowledge the last byte.

– the PCA9665/PCA9665A sends an Interrupt and updates I2CSTA register

– the I2CSTA reads 58h

– the SCL line is held LOW by the PCA9665/PCA9665A

– the slave should release the SDA line

13. The microcontroller reads the 64 bytes from the PCA9665/PCA9665A.

14. Program I2CCON with SI = STA = 0, ST0 = 1, MODE = X.

– the PCA9665/PCA9665A sends a STOP condition

– no interrupt is generated by the PCA9665/PCA9665A

– the I2CSTA register contains F8h

8.6 I2CCOUNT register

When a write to the I2CCOUNT register is requested, the buffer pointer is reset and points

at the first byte. Loading of the data in the I2CDAT buffer then starts at the first byte.

Once an operation has been performed (SI = 1 and an interrupt is generated), the

I2CCOUNT register contains the number of bytes that have been received (Receiver

mode) or the number of bytes that have been sent (Transmitter mode). See Table 42 for

more information.

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In Buffered Transmitter mode, the first byte that is sent to the I²C-bus is always the first

byte that has been loaded in the I2CDAT buffer.

In Buffered Receiver mode, when an interrupt is generated and SI is set to 1 (after a

STOP command or a buffer full condition), the buffer pointer is reset and points at the first

received data byte. Reading the I2CCOUNT register then indicates the number of bytes

that have been sent or received (BC[6:0]). Reading of the data from I2CDAT buffer can

then be initiated starting with the first received byte.

Table 42. I2CCOUNT register value based on the performed operation

Operation performed

I2CCOUNT register value

Master Transmitter Buffered mode

After START condition

don’t care

After Slave Address Sent + ACK bit received and interrupt received

After Slave Address Sent + NACK bit received

After Slave Address Sent + ‘n’ data bytes sent, ACK bit received, both

address and ‘n’ data

n + 1

After Slave Address Sent + ‘n’ data bytes sent, last byte

After STOP

n + 1

don’t care

After losing arbitration in Slave Address + W and addressed as slave

After losing arbitration in slave address + W and not addressed as slave

After losing arbitration in data at n^thbyte

n (if there was no interrupt after slave address

was sent)

n  1 (if there was an interrupt after slave

address was sent)

Master Receiver Buffered mode

After START condition

don't care

After Slave Address Sent + ACK bit received

After Slave Address Sent + NACK bit received

don't care (because no interrupt received here)

After Slave Address Sent + ‘n’ data bytes received, ACK bit received for

address and ACK bit returned for ‘n’ data bytes

After Slave Address Sent + ‘n’ data bytes received, NACK bit returned for

the last byte

After STOP

don't care

After losing arbitration in Slave Address + R bit and addressed as slave

After losing arbitration in slave address + R and not addressed as slave

After losing arbitration in ACK of n^thbyte

Slave Receiver Buffered mode (regular slave mode and General Call response

After Slave Address + W and ACK bit returned for slave address (both in

regular mode and when PCA9665/PCA9665A loses arbitration and is

addressed as slave)

After receiving ‘n’ bytes, ACK bit returned for the ‘n’ bytes

After receiving ‘n’ bytes, NACK bit returned for the last byte

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Table 42. I2CCOUNT register value based on the performed operation …continued

Operation performed

I2CCOUNT register value

Slave Transmitter Buffered mode

After Slave Address + R and ACK bit returned for slave address (both in

regular mode and when PCA9665/PCA9665A loses arbitration and is

addressed as slave)

After ‘n’ data bytes transmitted and ACK bit received for ‘n’ bytes

After ‘n’ data bytes transmitted and NACK bit received for the last byte

Remark: Request to send or receive a number of bytes equal to 0 or higher than 68

(BC[6:0] = 000 0000 or BC[6:0] > 100 0100) will cause no data to be transferred and an

interrupt to be generated after writing to the I2CCON register. I2CSTA status register is

loaded with FCh that indicates that an invalid value was requested to be loaded in

I2CCOUNT.

8.7 Acknowledge management (I²C-bus addresses and data) in Byte and

Buffered modes

Data acknowledge/not acknowledge management can be controlled on a byte basis (Byte

mode) or on a sequence basis (Buffered mode). The PCA9665/PCA9665A can be

programmed to respond (ACK) or not (NACK) to two different I²C-bus addresses.

Table 43 shows how this is performed based on the different control bits (AA, GC, LB and

MODE) and the different modes.

Table 43. Own slave address, General Call address, and Data acknowledge management

MODE

Address

Data received^[1]

Master mode: the PCA9665/65A generates a START command and controls the I²C-bus

not applicable

data (each byte) = NACK

data (each byte) = ACK

all the bytes (BC[6:0] bytes) = ACK

all the bytes except the last one

(BC[6:0] bytes  1) = ACK;

last byte = NACK

Slave mode: I²C-bus message starting with the PCA9665/65A’s Own Slave address

Own address = NACK data (each byte) = NACK

Own address = ACK data (each byte) = ACK

Own address = NACK all the bytes ( BC[6:0] bytes) = ACK

Own address = NACK all the bytes except the last one

(BC[6:0] bytes - 1) = ACK; last

byte = NACK^[2]

Own address = ACK

all the bytes ( BC[6:0] bytes) = ACK

all the bytes except the last one

(BC[6:0] bytes - 1) = ACK;

last byte = NACK^[2]

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Table 43. Own slave address, General Call address, and Data acknowledge management

AA GC LB MODE Address

Data received^[1]

Slave mode: I²C-bus message starting with the General Call address

GC address = NACK

GC address = ACK

GC address = NACK

GC address = ACK

data (each byte) = NACK

data (each byte) = ACK

data (each byte) = NACK

all the bytes ( BC[6:0] bytes) = ACK

all the bytes except the last one

(BC[6:0] bytes - 1) = ACK;

last byte = NACK^[2]

[1] Assumption is that Data Received follows the address (as defined in column “Address”); valid for slave

mode only.

[2] Unless the master sends a STOP command before.

Table 44. Unbuffered Mode (MODE = 0)

Control

bits

LB = x

Master Receiver mode

AA = 0

Master Transmitter mode

• address/data are transmitted on a byte basis

• address is transmitted and data are received on a

byte basis

• NACK returned after one byte received

Slave Receiver mode

Slave Transmitter mode

• NACK returned after own slave address received

• NACK returned after one byte received

• switch to not addressed slave mode any time

during an I²C-bus sequence

AA = 1

Master Transmitter mode

Master Receiver mode

• address/data are transmitted on a byte basis

• data are received on a byte basis

• ACK returned after one byte received

Slave Receiver mode

Slave Transmitter mode

• ACK returned after own slave address received

• always addressed during an I²C-bus sequence

• ACK returned after own slave address received

• ACK returned after one byte received

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Table 45. Buffered Mode (MODE = 1)

Control

bits

LB = 0

LB = 1

AA = 0 Master Transmitter

mode

Master Receiver mode

Master Transmitter

mode

Master Receiver mode

• address is transmitted

and data are received on

a multiple byte basis

= BC[6:0] value

• address is transmitted

and data are received on

a multiple byte basis

= BC[6:0] value

• address/data are

transmitted on a

multiple byte basis

= BC[6:0] value

• address/data are

transmitted on a

multiple byte basis

= BC[6:0] value

• ACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

• NACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

Slave Transmitter

mode

Slave Receiver mode

Slave Transmitter mode Slave Receiver mode

• NACK returned after own

• NACK returned after

own slave address

received

• NACK returned after

own slave address

received

• NACK returned

after own slave

slave address received

• in addressed mode, data

are received on a multiple

byte basis = BC[6:0]

value

address received

• in addressed mode,

data are transmitted

on a multiple byte

basis = BC[6:0]

value

• in addressed mode, data

are received on a

• in addressed

mode, data are

transmitted on a

multiple byte basis

= BC[6:0] value

multiple byte basis

= BC[6:0] value

• in addressed mode, ACK

returned after the last

byte of a buffered

• in addressed mode,

NACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

• in addressed mode,

switch to non

• in addressed

mode, switch to

non addressed

mode after the last

byte of a buffered

sequence is

sequence received (after

bytes received = BC[6:0]

value)

addressed mode

after the last byte of

a buffered

• in addressed mode,

switch to non-addressed

mode after the last byte of

a buffered sequence is

received (after bytes

sequence is

• in addressed mode,

switch to non-addressed

mode after the last byte

of a buffered sequence

is received (after bytes

received = BC[6:0]

value)

transmitted (after

bytes sent = BC[6:0]

value)

transmitted (after

bytes sent

= BC[6:0] value)

received = BC[6:0] value)

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Table 45. Buffered Mode (MODE = 1) …continued

Control

bits

LB = 0

LB = 1

AA = 1 Master Transmitter

mode

Master Receiver mode

Master Transmitter

mode

Master Receiver mode

• address is transmitted

and data are received on

a multiple byte basis

= BC[6:0] value

• address is transmitted

and data are received on

a multiple byte basis

= BC[6:0] value

• address/data are

transmitted on a

multiple byte basis

= BC[6:0] value

• address/data are

transmitted on a

multiple byte basis

= BC[6:0] value

• ACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

• NACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

Slave Transmitter

mode

Slave Receiver mode

Slave Transmitter mode Slave Receiver mode

• ACK returned after own

• ACK returned after

own slave address

received

• ACK returned after own

• ACK returned after

own slave address

received

slave address received

• in addressed mode, data

are received on a multiple

byte basis = BC[6:0]

value

• in addressed mode, data

are received on a

• in addressed mode,

data are transmitted

on a multiple byte

basis = BC[6:0]

value

• in addressed

mode, data are

transmitted on a

multiple byte basis

= BC[6:0] value

multiple byte basis

= BC[6:0] value

• in addressed mode, ACK

returned after the last

byte of a buffered

• in addressed mode,

NACK returned after the

last byte of a buffered

sequence received (after

bytes received = BC[6:0]

value)

• always addressed

during a buffered

sequence

• always addressed

during a buffered

sequence

sequence received (after

bytes received = BC[6:0]

value)

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8.8 Miscellaneous states

There are four I2CSTA codes that do not correspond to a defined PCA9665/PCA9665A

state (see Table 46). These are discussed in Section 8.8.1 through Section 8.8.4.

Table 46. Miscellaneous states

Status

code

(I2CSTA) PCA9665/65A

Status of the I²C-bus Application software response

Next action taken by

PCA9665/PCA9665A

and the

To/from I2CDAT To I2CCON

STA STO SI

AA MODE

F8h

On hardware or

software reset or

STOP

No I2CDAT action 1

No I2CDAT action 0

Go into master mode; send START

No recognition of own slave

address. General Call address will

be recognized if GC = 1.

No I2CDAT action 0

Will recognize own slave address.

General Call address will be

recognized if GC = 1.

70h

78h

FCh

00h

Bus error

No I2CDAT action No I2CCON action

Hardware or software reset of the

PCA9665/PCA9665A (requires

reset to return to state F8h)

SDA stuck LOW

Bus error

Hardware or software reset of the

PCA9665/PCA9665A (requires

reset to return to state F8h)

SCL stuck LOW

Illegal value in

I2CCOUNT

Program a valid value in

I2CCOUNT: BC[6:0] between 1 and

68.

Bus error during

master or slave

mode, due to illegal

START or STOP

condition

Hardware or software reset of the

PCA9665/PCA9665A (requires

reset to return to state F8h)

8.8.1 I2CSTA = F8h

This status code indicates that the PCA9665/PCA9665A is in an idle state and that no

relevant information is available because the serial interrupt flag, SI, is not yet set. This

occurs on a STOP condition or during a hardware or software reset event and when the

PCA9665/PCA9665A is not involved in a serial transfer.

8.8.2 I2CSTA = 00h

This status code indicates that a bus error has occurred during a serial transfer. A bus

error is caused when a START or STOP condition occurs at an illegal position in the

format frame. Examples of such illegal positions are during the serial transfer of an

address byte, a data byte, or an acknowledge bit. A bus error may also be caused when

external interference disturbs the internal PCA9665/PCA9665A signals. When a bus error

occurs, SI is set. To recover from a bus error, the microcontroller must send an external

hardware or software reset signal to reset the PCA9665/PCA9665A.

8.8.3 I2CSTA = 70h

This status code indicates that the SDA line is stuck LOW when the PCA9665/PCA9665A,

in master mode, is trying to send a START condition.

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8.8.4 I2CSTA = 78h

This status code indicates that the SCL line is stuck LOW.

8.9 Some special cases

The PCA9665/PCA9665A has facilities to handle the following special cases that may

occur during a serial transfer.

8.9.1 Simultaneous repeated START conditions from two masters

A repeated START condition may be generated in the Master Transmitter or Master

Receiver modes. A special case occurs if another master simultaneously generates a

repeated START condition (see Figure 14). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

If the PCA9665/PCA9665A detects a repeated START condition on the I²C-bus before

generating a repeated START condition itself, it will use the repeated START as its own

and continue with the sending of the slave address.

both masters continue

with SLA transmission

SLA

DATA

08h

28h

18h

other master sends

repeated START condition earlier

002aab028

Fig 14. Simultaneous repeated START conditions from 2 masters

8.9.2 Data transfer after loss of arbitration

Arbitration may be lost in the Master Transmitter and Master Receiver modes. Loss of

arbitration is indicated by the following states in I2CSTA; 38h, 68h, and B0h (see Figure 6,

Figure 10, Figure 7, and Figure 11).

Remark: In order to exit state 38h, a Time-out, Reset, or external STOP are required.

If the STA flag in I2CCON is set by the routines which service these states, then, if the bus

is free again, a START condition (state 08h) is transmitted without intervention by the

CPU, and a retry of the total serial transfer can commence.

8.9.3 Forced access to the I²C-bus

In some applications, it may be possible for an uncontrolled source to cause a bus

hang-up. In such situations, the problem may be caused by interference, temporary

interruption of the bus or a temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superfluous START or masks a STOP condition,

then the I²C-bus stays busy indefinitely. If the STA flag is set and bus access is not

obtained within a reasonable amount of time, then a forced access to the I²C-bus is

possible. If the I²C-bus stays idle for a time period equal to the time-out period, then the

PCA9665/PCA9665A concludes that no other master is using the bus and sends a

START condition.

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Fm+ parallel bus to I²C-bus controller

time-out

STA flag

SDA line

SCL line

START condition

002aab029

Fig 15. Forced access to a busy I²C-bus

8.9.4 I²C-bus obstructed by a LOW level on SCL or SDA

An I²C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the

SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is

possible, and the PCA9665/PCA9665A cannot resolve this type of problem. When this

occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW.

When the SCL line stays LOW for a period equal to the time-out value, the

PCA9665/PCA9665A concludes that this is a bus error and behaves in a manner

described in Section 7.3.2.4 “The Time-out register, I2CTO (indirect address 04h)”.

If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit

synchronization), the problem can be solved by transmitting additional clock pulses on the

SCL line (see Figure 16). The PCA9665/PCA9665A sends out nine clock pulses followed

by the STOP condition. If the SDA line is released by the slave pulling it LOW, a normal

START condition is transmitted by the PCA9665/PCA9665A, state 08h is entered and the

serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then

the PCA9665/PCA9665A concludes that there is a bus error, loads 70h in I2CSTA,

generates an interrupt signal, and releases the SCL and SDA lines. After the

microcontroller reads the status register, it needs to send a reset signal (hardware through

the RESET pin, or software through the parallel port) in order to reset the

PCA9665/PCA9665A. See Section 8.11 “Reset” for more information.

If a forced bus access occurs or a repeated START condition is transmitted while SDA is

obstructed (pulled LOW), the PCA9665/PCA9665A performs the same action as

described above. In each case, state 08h is entered after a successful START condition is

transmitted and normal serial transfer continues. Note that the CPU is not involved in

solving these bus hang-up problems.

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STA flag

SDA line

SCL line

STOP

START

condition

002aab030

Fig 16. Recovering from a bus obstruction caused by a LOW level on SDA

8.9.5 Bus error

A bus error occurs when a START or STOP condition is present at an illegal position in the

format frame. Examples of illegal positions are during the serial transfer of an address

byte, a data or an acknowledge bit.

The PCA9665/PCA9665A only reacts to a bus error when it is involved in a serial transfer

either as a master or an addressed slave. When a bus error is detected,

PCA9665/PCA9665A releases the SDA and SCL lines, sets the interrupt flag, and loads

the status register with 00h. This status code may be used to vector to a service routine

which either attempts the aborted serial transfer again or simply recovers from the error

condition as shown in Table 46 “Miscellaneous states”. The microcontroller must send an

external hardware or software reset signal to reset the PCA9665/PCA9665A.

8.10 Power-on reset

When power is applied to V_DD, an internal Power-On Reset holds the

PCA9665/PCA9665A in a reset condition until V_DDhas reached V_POR. At this point, the

reset condition is released and the PCA9665/PCA9665A goes to the power-up

initialization phase where the following operations are performed:

1. ENSIO bit is set to 1 to enable the internal oscillator.

2. Internal register initialization is performed.

3. ENSIO bit is set to 0 to disable the internal oscillator and go to the non-addressed low

power mode.

The complete power-up initialization phase takes 550 s to be performed. During this

time, write to the PCA9665/PCA9665A through the parallel port is not permitted. However,

the parallel port can be read. This allows the device connected to the parallel port of the

PCA9665/PCA9665A to poll the I2CCON register and read the ENSIO state bit. When

ENSIO bit is equal to 1, this means that the power-up initialization is in progress. When

ENSIO is set to 0, this means that the power-up initialization is done and that the

PCA9665/PCA9665A is initialized and ready to be used.

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8.11 Reset

Fm+ parallel bus to I²C-bus controller

Reset of the PCA9665/PCA9665A to its default state can be performed in 2 different

ways:

• By holding the RESET pin LOW for a minimum of t_w(rst)

• By using the Parallel Software Reset sequence as described in Figure 17.

access to INDPTR

Indirect Register pointer

access to the INDIRECT

Indirect Data field

A[1:0]

D[7:0]

I2CPRESET register selected

05h

SWRST data byte 1

SWRST data byte 2

5Ah

A5h

If D[7:0] ≠ 5Ah, reset is aborted.

If SWRST Data 1 = A5h and

SWRST Data 2 = 5Ah, PCA9665

is reset to its default state.

If D[7:0] ≠ A5h,

following byte is ignored

and reset is aborted.

internal

reset

signal

002aab966

Fig 17. Parallel Software Reset sequence

The RESET hardware pin and software reset function only resets the internal registers

and control logic, and does not re-initialize the internal oscillator because the oscillator

initialization is performed only on power-up. If the device hangs up and does not respond

to a normal RESET input or software reset command, the only way to recover is by

powering down and then powering the device back up.

A simple way to implement this circuit without actually having to de-power the entire

system is by using a dual gate buffer such as the 74LVC2G125 to control the V_DDof

PCA9665/PCA9665A as shown in Figure 18. Now, instead of powering the V_DDof the

PCA9665/PCA9665A directly from the supply rail, it is powered by the output of the

74LVC2G125 with its input connected to the supply rail. Ganging up the two buffers

provides twice the drive and minimizes the voltage drop. The 74LVC2G125 enable pins

(1OE, 2OE) are now used to power cycle and recover the PCA9665.

A 100 pF capacitor is used for filtering the supply of PCA9665/PCA9665A and averaging

the dynamic current (typically, maximum peak current is 24 mA). Do not size the capacitor

too large as the larger capacitor could discharge during power-down, and possibly

damage the output of the buffer.

The enable pins are pulled down to ground by a 10 k resistor. During normal operation,

the enable pins are held LOW and the buffer is turned on, powering the

PCA9665/PCA9665A. An external signal (either from a controller or processor) controls

the 74LVC2G125 enable pins to switch on or switch off the supply voltage of the

PCA9665/PCA9665A. A HIGH logic level places the buffer in a high-impedance state and

turns off the supply to the PCA9665/PCA9665A, which discharges through the 100 pF

capacitor. When the enable pins are once again pulled LOW, the PCA9665 powers up and

re-initializes to an operation state.

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DD(3V3)

74LVC2G125

1OE

2OE

input control signal

= ON HIGH: V = OFF

LOW: V

10 kΩ

100 pF

PCA9665

002aac920

Fig 18. Schematic to power-on/power-off PCA9665/PCA9665A

8.12 I²C-bus timing diagrams, Unbuffered mode

The diagrams (Figure 19 through Figure 22) illustrate typical timing diagrams for the

PCA9665/PCA9665A in master/slave functions.

SCL

SDA

INT

7-bit address

interrupt

first byte

n byte

interrupt

R/W = 0

STOP

condition

START

condition

ACK

002aab031

from slave receiver

Master PCA9665/PCA9665A writes data to slave transmitter.

Fig 19. Bus timing diagram; Unbuffered Master Transmitter mode

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SCL

SDA

INT

7-bit address

interrupt

first byte

n byte

R/W = 1

STOP

condition

START

condition

ACK

no ACK

from master receiver

002aab032

from slave

Master PCA9665/PCA9665A reads data from slave transmitter.

Fig 20. Bus timing diagram; Unbuffered Master Receiver mode

SCL

SDA

INT

(1)

7-bit address

interrupt

first byte

interrupt

n byte

interrupt

R/W = 1

STOP

condition

START

condition

ACK

no ACK

from master receiver

002aab033

from slave PCA9665

External master receiver reads data from PCA9665/PCA9665A.

(1) As defined in I2CADR register.

Fig 21. Bus timing diagram; Unbuffered Slave Transmitter mode

SCL

SDA

INT

(1)

7-bit address

interrupt

first byte

n byte

interrupt

R/W = 0

(after STOP)

START

condition

ACK

STOP

condition

from slave PCA9665

002aab034

Slave PCA9665/PCA9665A is written to by external master transmitter.

(1) As defined in I2CADR register.

Fig 22. Bus timing diagram; Unbuffered Slave Receiver mode

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Fm+ parallel bus to I²C-bus controller

8.13 I²C-bus timing diagrams, Buffered mode

The diagrams (Figure 23 through Figure 26) illustrate typical timing diagrams for the

PCA9665/PCA9665A in master/slave functions.

SCL

SDA

INT

(1)

7-bit address

(1)

first byte

n byte

interrupt

R/W = 0

STOP

condition

START

condition

ACK

002aab267

from slave receiver

Master PCA9665/PCA9665A writes data to slave transmitter.

(1) 7-bit address + R/W = 0 byte and number of bytes sent = value programmed in I2CCOUNT register (BC[6:0]  68).

Fig 23. Bus timing diagram; Buffered Master Transmitter mode

SCL

SDA

INT

7-bit address

(1)

first byte

n byte

R/W = 1

STOP

condition

START

condition

ACK

no ACK

from master receiver

002aab268

from slave

Master PCA9665/PCA9665A reads data from slave transmitter.

(1) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]  68).

Fig 24. Bus timing diagram; Buffered Master Receiver mode

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Fm+ parallel bus to I²C-bus controller

SCL

SDA

INT

(1)

7-bit address

interrupt

(2)

first byte

n byte

interrupt

R/W = 1

STOP

condition

START

condition

ACK

no ACK

from master receiver

002aab269

from slave PCA9665

External master receiver reads data from PCA9665/PCA9665A.

(1) As defined in I2CADR register.

(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]  68).

Fig 25. Bus timing diagram; Buffered Slave Transmitter mode

SCL

SDA

INT

(1)

7-bit address

interrupt

(2)

first byte

n byte

interrupt

R/W = 0

(after STOP)

START

condition

ACK

STOP

condition

from slave PCA9665

002aab270

Slave PCA9665/PCA9665A is written to by external master transmitter.

(1) As defined in I2CADR register.

(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]  68).

Fig 26. Bus timing diagram; Buffered Slave Receiver mode

SCL

SDA

INT

7-bit SWRST

Call address

interrupt

first byte = 0xA5

second byte = 0x5A

interrupt

(after STOP)

R/W = 0

START

condition

ACK

STOP

condition

from slave PCA9665

002aab488

Fig 27. Bus timing diagram; Software Reset Call

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Fm+ parallel bus to I²C-bus controller

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 28).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 28. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 29).

SDA

SCL

STOP condition

START condition

mba608

Fig 29. Definition of START and STOP conditions

9.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 30).

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Fm+ parallel bus to I²C-bus controller

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 30. System configuration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 31. Acknowledgement on the I²C-bus

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10. Application design-in information

address bus

PCA9665

DECODER

ALE

SCL

80C51

D0 to D7

SDA

SLAVE

INT

SLAVE

RESET

INT

RESET

002aab035

Fig 32. Application diagram using the 80C51

10.1 Specific applications

The PCA9665/PCA9665A is a parallel bus to I²C-bus controller that is designed to allow

‘smart’ devices to interface with I²C-bus or SMBus components, where the ‘smart’ device

does not have an integrated I²C-bus port and the designer does not want to ‘bit-bang’ the

I²C-bus port. The PCA9665/PCA9665A can also be used to add more I²C-bus ports to

‘smart’ devices, provide a higher frequency, lower voltage migration path for the PCF8584

and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across

the printed-circuit board.

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10.2 Add I²C-bus port

As shown in Figure 33, the PCA9665/PCA9665A converts 8-bits of parallel data into a

multiple master capable I²C-bus port for microcontrollers, microprocessors, custom

ASICs, DSPs, etc., that need to interface with I²C-bus or SMBus components.

control signals

SDA

SCL

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

PCA9665

8 bits data

002aab036

Fig 33. Adding I²C-bus port application

10.2.1 Add I²C-bus port with ‘hot swap bus buffers’

The PCA9665A should be used when incremental offset hot swap buffers like the

PCA9511A are included in the system such as shown in Figure 34 since the PCA9665 is

susceptible to producing a LOW-going spike on a HIGH SDA line during a repeated

START as shown in Figure 35 spike labeled ‘A’.

PCA9511A

SDA

SDAIN SDAOUT

SCLIN

SCLOUT

SCL

µC

PCA9665A

PCA9511A

SDAIN SDAOUT

SCLIN

SCLOUT

SLAVE

002aag267

Fig 34. Adding I²C-bus port with ‘hot swap bus buffers’

B (with buffer present)

SDA

SCL

repeated START

interrupt serviced on the

parallel port of the PCA9665

002aag268

Fig 35. Stretching duration of spike

The spike varies in depth and width, and will return HIGH greater than a data set-up time

(t_SU;DAT) before the SCL rises, so the spike is not a violation of the I²C-bus specification.

An incremental offset hot swap buffer (e.g., PCA9511A) however may interact with the

spike in such a way as to stretch the duration of the spike (see Figure 35 spike labeled ‘B’)

and possibly violate the data set-up time. It is therefore recommended to use the

PCA9665A in these types of applications since the PCA9665A eliminates the spike on

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repeated START conditions. The differences between PCA9665 and PCA9665A are

timing related. Section 7.3.2.3 “The Clock Rate registers, I2CSCLL and I2CSCLH (indirect

addresses 02h and 03h)” and Section 7.3.2.6 “The I²C-bus mode register, I2CMODE

(indirect address 06h)” outline these timing differences. There are no functional or

operational differences between the two bus controllers so a PCA9665A can be a drop-in

replacement for the PCA9665 with only a small sacrifice in the serial data rate.

Figure 36 shows the glitch-free SDA output of the PCA9665A during a repeated START.

SDA

SCL

repeated START

interrupt serviced on the

parallel port of the PCA9665A

002aag457

Fig 36. Glitch-free repeated START on PCA9665A

10.3 Add additional I²C-bus ports

The PCA9665/PCA9665A can be used to convert 8-bit parallel data into additional

multiple master capable I²C-bus port as shown in Figure 37. It is used if the

microcontroller, microprocessor, custom ASIC, DSP, etc., already have an I²C-bus port

but need one or more additional I²C-bus ports to interface with more I²C-bus or SMBus

components or components that cannot be located on the same bus (e.g., 100 kHz and

400 kHz slaves on different buses so that each bus can operate at its maximum potential).

SDA

SCL

MICROCONTROLLER,

MICROPROCESSOR,

control signals

OR ASIC

SDA

SCL

PCA9665

8 bits data

002aab037

Fig 37. Adding additional I²C-bus ports application

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10.4 Convert 8 bits of parallel data into I²C-bus serial data stream

Functioning as a slave transmitter, the PCA9665/PCA9665A can convert 8-bit parallel

data into a two-wire I²C-bus data stream as is shown in Figure 38. This would prevent

having to run 8 traces across the entire width of the printed-circuit board.

control signals

8 bits data

SDA

SCL

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

PCA9665

MASTER

002aab039

Fig 38. Converting parallel to serial data application

11. Limiting values

Table 47. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

0.3

0.8

10

Max

+4.6

+6.0

+10

300

Unit

supply voltage

[1]

input voltage

any input

any output

I_I

input current

C

I_O

output current

P_tot

P/out

T_stg

T_amb

T_j

total power dissipation

power dissipation per output

storage temperature

ambient temperature

junction temperature

65

40

+150

+85

125

operating

C

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

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Fm+ parallel bus to I²C-bus controller

12. Static characteristics

Table 48. Static characteristics

V_DD= 2.3 V to 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply

V_DD

supply voltage

supply current

2.3

3.6

3.0

8.0

2.2

I_DD

standby mode

0.1

operating mode; no load

V_POR

power-on reset voltage

1.8

Inputs WR, RD, A0, A1, CE, RESET

V_IL

V_IH

I_L

LOW-level input voltage

HIGH-level input voltage

leakage current

0.8

5.5

[1]

2.0

1

input; V_I= 0 V or 5.5 V

V_I= V_SSor V_DD

A

C_i

input capacitance

2.0

Inputs/outputs D0 to D7

V_IL

V_IH

I_OH

I_OL

I_L

LOW-level input voltage

0.8

5.5

[1]

HIGH-level input voltage

HIGH-level output current

LOW-level output current

leakage current

2.0

4.0

4.0

1

V_OH= V_DD 0.4 V

V_OL= 0.4 V

7.0

8.0

A

input; V_I= 0 V or 5.5 V

V_I= V_SSor V_DD

C_io

input/output capacitance

2.8

SDA and SCL

V_IL

V_IH

I_L

LOW-level input voltage

0.3V_DD

[1]

HIGH-level input voltage

leakage current

0.7V_DD

5.5

+10

input/output; V_I= 0 V or 3.6 V

input/output; V_I= 5.5 V

V_OL= 0.4 V

1

A

I_OL

C_io

LOW-level output current

input/output capacitance

V_I= V_SSor V_DD

5.6

Outputs INT

I_OLLOW-level output current

I_L

V_OL= 0.4 V

6.0

1

A

leakage current

V_O= 0 V or 3.6 V

V_I= V_SSor V_DD

C_o

output capacitance

3.8

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

PCA9665_PCA9665A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 September 2011

73 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

13. Dynamic characteristics

Table 49. Dynamic characteristics (3.3 volt)^[1][2][3]

V_CC= 3.3 V  0.3 V; T_amb= 40 C to +85 C; unless otherwise specified. (See Table 50 on page 75 for 2.5 V)

Symbol Parameter

Initialization timing

Conditions

Min

Typ

Max

550

Unit

s

t_init(po)

power-on initialization time

Serial interface initialization timing

t_init(sintf)

RESET timing (see Figure 39)

serial interface initialization time^[4]

from ENSIO bit HIGH

s

t_w(rst)

t_rst

reset pulse width

reset time

250

[5][6]

t_rec(rst)

reset recovery time

INT timing (see Figure 40)

t_as(int)

interrupt assert time

500

t_das(int)

interrupt de-assert time

Bus timing (see Figure 41 and Figure 43)

t_su(A)

t_h(A)

address set-up time

address hold time

to RD, WR LOW

from RD, WR LOW

to RD, WR LOW

from RD, WR LOW

t_{su(CE_N)}CE set-up time

t_{h(CE_N)}

t_w(RDL)

t_w(WRL)

t_d(DV)

CE hold time

RD LOW pulse width

WR LOW pulse width

data valid delay time

data output float delay time

data output set-up time

data output hold time

RD HIGH pulse width

WR HIGH pulse width

after RD and CE LOW

after RD or CE HIGH

t_d(QZ)

t_su(Q)

before WR or CE HIGH (write cycle)

after WR HIGH

t_h(Q)

t_w(RDH)

t_w(WRH)

[1] Parameters are valid over specified temperature and voltage range.

[2] All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of

5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 41 and Figure 43.

[3] Test conditions for outputs: C_L= 50 pF; R_L= 500 , except open-drain outputs.

Test conditions for open-drain outputs: C_L= 50 pF; R_L= 1 k pull-up to V_DD

[4] Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.

[5] Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

[6] Upon reset, the full delay will be the sum of t_rstand the RC time constant of the SDA and SCL bus.

PCA9665_PCA9665A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 September 2011

74 of 92

PCA9665; PCA9665A

NXP Semiconductors

Fm+ parallel bus to I²C-bus controller

Table 50. Dynamic characteristics (2.5 volt)^[1][2][3]

V_CC= 2.5 V  0.2 V; T_amb= 40 C to +85 C; unless otherwise specified. (See Table 49 on page 74 for 3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

550

Unit

s

Initialization timing

t_init(po)

power-on initialization time

Serial interface initialization timing

t_init(sintf)

serial interface initialization time^[4]

from ENSIO bit HIGH

s

RESET timing (see Figure 39)

t_w(rst)

t_rst

reset pulse width

reset time

250

[5][6]

t_rec(rst)

reset recovery time

INT timing (see Figure 40)

t_as(int)

interrupt assert time

550

t_das(int)

interrupt de-assert time

Bus timing (see Figure 41 and Figure 43)

t_su(A)

address set-up time

address hold time

to RD, WR LOW

from RD, WR LOW

to RD, WR LOW

from RD, WR LOW

t_h(A)

t_{su(CE_N)}

t_{h(CE_N)}

t_w(RDL)

t_w(WRL)

t_d(DV)

CE set-up time