935284593112 [NXP]
AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24;
| 型号： | 935284593112 |
| 厂家： | 
NXP |
| 描述： | AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总24页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVC8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 27 December 2012
Product data sheet
1. General description
The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two 8-bit input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both An and Bn are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 2.5 V translation)
210 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
Type number
Description
Version
74AVC8T245PW 40 C to +125 C
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74AVC8T245BQ 40 C to +125 C
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
4. Functional diagram
B1
21
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
V
V
CC(B)
CC(A)
22
OE
2
DIR
3
A1
4
5
6
7
8
9
10
A8
A2
A3
A4
A5
A6
A7
001aai472
Fig 1. Logic symbol
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
2 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
DIR
A1
OE
B1
V
CC(A)
V
CC(B)
to other seven channels
001aai473
Fig 2. Logic diagram (one channel)
5. Pinning information
5.1 Pinning
74AVC8T245
terminal 1
index area
74AVC8T245
2
3
23
22
21
20
19
18
17
16
15
14
DIR
A1
V
CC(B)
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
V
V
CC(A)
DIR
CC(B)
CC(B)
OE
B1
B2
B3
B4
B5
B6
B7
B8
4
A2
3
A1
A2
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
5
A3
4
6
A4
5
A3
7
A5
6
A4
8
A6
7
A5
9
A7
8
A6
(1)
10
11
A8
GND
9
A7
GND
10
11
12
A8
GND
GND
001aai490
001aai489
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration TSSOP24
Fig 4. Pin configuration DHVQFN24
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
3 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
VCC(A)
DIR
Pin description
Pin
Description
1
supply voltage A (An, OE and DIR inputs are referenced to VCC(A))
2
direction control
data input or output
ground (0 V)
A1 to A8
GND[1]
GND[1]
GND[1]
B1 to B8
OE
3, 4, 5, 6, 7, 8, 9, 10
11
12
13
ground (0 V)
ground (0 V)
21, 20, 19, 18, 17, 16, 15, 14 data input or output
22
23
24
output enable input (active LOW)
VCC(B)
VCC(B)
supply voltage B (Bn inputs are referenced to VCC(B)
)
)
supply voltage B (Bn inputs are referenced to VCC(B)
[1] All GND pins must be connected to ground (0 V).
6. Functional description
Table 3.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[3]
Input
OE[2]
Input/output[3]
DIR[2]
An[2]
An = Bn
input
Z
Bn
L
L
input
L
H
X
X
Bn = An
H
X
Z
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The An, DIR and OE input circuit is referenced to VCC(A); The Bn input circuit is referenced to VCC(B)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
50
Suspend or 3-state mode
VO = 0 V to VCC
per VCC(A) or VCC(B) pin
V
IO
output current
supply current
mA
mA
ICC
-
100
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
4 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
IGND
Parameter
Conditions
Min
100
65
-
Max
-
Unit
mA
C
ground current
per GND pin
Tstg
storage temperature
total power dissipation
+150
500
[4]
Ptot
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage A
supply voltage B
input voltage
3.6
V
3.6
V
[1]
[2]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
40
-
+125
5
C
ns/V
t/V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. Static characteristics
Table 6.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 C[1][2]
Symbol Parameter Conditions
VOH HIGH-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
LOW-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
Min
Typ
0.69
0.07
Max
Unit
-
-
-
V
V
VOL
-
-
II
input leakage current
DIR, OE input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
0.025 0.25 A
[3]
[3]
[3]
IOZ
OFF-state output current
A or B port; VO = 0 V or VCCO
VCC(A) = VCC(B) = 3.6 V
;
-
-
-
0.5
0.5
0.5
2.5
2.5
2.5
A
A
A
suspend mode A port; VO = 0 V or VCCO
VCC(A) = 3.6 V; VCC(B) = 0 V
;
;
suspend mode B port; VO = 0 V or VCCO
VCC(A) = 0 V; VCC(B) = 3.6 V
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
5 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 6.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 C[1][2] …continued
Symbol Parameter Conditions
Min
Typ
Max
Unit
IOFF
power-off leakage current A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
0.1
1
A
B port; VI or VO = 0 V to 3.6 V;
-
-
-
0.1
1.5
1
-
A
pF
pF
V
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
CI
input capacitance
DIR, OE input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
CI/O
input/output capacitance
A and B port; VO = 3.3 V or 0 V;
VCC(A) = VCC(B) = 3.3 V
4.3
-
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 7.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Static characteristics [1][2]
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR, OE input
2
2
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
data input
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
VIL
LOW-level
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR, OE input
0.8
0.8
VCC(A) = 0.8 V
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.8
0.8
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
6 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCCO 0.1
0.85
-
-
-
-
-
-
VCCO 0.1
0.85
-
-
-
-
-
-
V
V
V
V
V
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
IO = 6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
1.05
IO = 8 mA;
1.2
1.2
V
CC(A) = VCC(B) = 1.65 V
IO = 9 mA;
CC(A) = VCC(B) = 2.3 V
1.75
1.75
V
IO = 12 mA;
2.3
2.3
VCC(A) = VCC(B) = 3.0 V
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
-
0.1
-
0.1
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
-
-
-
0.25
0.35
0.45
-
-
-
0.25
0.35
0.45
V
V
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
-
-
0.55
0.7
-
-
0.55
0.7
V
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
II
input leakage DIR, OE input; VI = 0 V or 3.6 V;
-
-
-
1
5
5
-
-
-
5
A
A
A
current
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[3]
[3]
IOZ
OFF-state
A or B port; VO = 0 V or VCCO
;
30
30
output current VCC(A) = VCC(B) = 3.6 V
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 3.6 V;
CC(B) = 0 V
V
[3]
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 3.6 V
-
5
-
30
A
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
-
-
5
5
-
-
30
30
A
A
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
7 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
10
8
-
-
55
50
A
A
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
B port; VI = 0 V or VCCI; IO = 0 A
-
8
-
-
50
-
A
A
2
12
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
10
8
-
-
55
50
A
A
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
2
-
-
8
12
-
A
A
A
-
-
50
70
-
20
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
;
A plus B port (ICC(A) + ICC(B));
-
16
-
65
A
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
;
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
VCC(A)
Typical total supply current (ICC(A) + ICC(B)
VCC(B)
)
Unit
0 V
0
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
1.8 V
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
0 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
A
A
A
A
A
A
A
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
8 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
14.4
14.4
16.2
17.6
21.9
22.2
1.2 V
7.0
1.8 V
6.0
2.5 V
5.9
3.3 V
6.0
tpd
tdis
ten
propagation delay An to Bn
6.2
12.1
16.2
9.0
ns
ns
ns
ns
ns
ns
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
12.4
16.2
10.0
21.9
11.1
11.9
16.2
9.1
11.8
16.2
8.7
11.8
16.2
9.3
disable time
enable time
21.9
9.8
21.9
9.4
21.9
9.4
21.9
9.6
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
Conditions
VCC(A)
1.5 V
Unit
0.8 V
14.4
14.4
16.2
17.6
21.9
22.2
1.2 V
12.4
7.0
1.8 V
11.9
6.0
2.5 V
11.8
5.9
3.3 V
11.8
6.0
tpd
tdis
ten
propagation delay An to Bn
12.1
6.2
ns
ns
ns
ns
ns
ns
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
disable time
enable time
5.9
4.4
4.2
3.1
3.5
14.2
6.4
13.7
4.4
13.6
3.5
13.3
2.6
13.1
2.3
17.7
17.2
17.0
16.8
16.7
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
9 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction An to
0.2
0.2
0.2
0.3
0.4
0.5
pF
pF
pF
pF
pF
pF
pF
pF
capacitance
Bn); output enabled
A port: (direction An to
Bn); output disabled
0.2
9
0.2
9
0.2
10
0.3
10
0.4
11
0.5
13
A port: (direction Bn to
An); output enabled
A port: (direction Bn to
An); output disabled
0.6
9
0.6
9
0.6
10
0.7
10
0.7
11
0.8
13
B port: (direction An to
Bn); output enabled
B port: (direction An to
Bn); output disabled
0.6
0.2
0.2
0.6
0.2
0.2
0.6
0.2
0.2
0.7
0.3
0.3
0.7
0.4
0.4
0.8
0.5
0.5
B port: (direction Bn to
An); output enabled
B port: (direction Bn to
An); output disabled
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
10 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation An to Bn
0.5
0.5
0.5
0.5
1.1
1.1
9.0
9.0
0.5
0.5
0.5
0.5
1.1
1.1
6.7
8.5
0.5
0.5
0.5
0.5
1.1
1.1
5.8
8.3
0.5
0.5
0.5
0.5
1.1
1.0
4.9
8.0
0.5
0.5
0.5
0.5
1.1
1.0
4.8 ns
7.8 ns
11.8 ns
8.9 ns
14.4 ns
7.3 ns
delay
Bn to An
disable time OE to An
OE to Bn
11.8
12.3
14.4
14.2
11.8
9.5
11.8
9.4
11.8
8.0
enable time OE to An
OE to Bn
14.4
10.4
14.4
9.0
14.4
7.7
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
1.1
1.1
8.5
6.7
0.5
0.5
0.5
0.5
1.1
1.1
5.6
5.6
8.6
8.4
8.7
8.1
0.5
0.5
0.5
0.5
1.1
1.1
4.7
5.3
8.6
7.6
8.7
7.1
0.5
0.5
0.5
0.5
1.1
1.0
4.4
5.2
8.6
7.2
8.7
5.6
0.5
0.5
0.5
0.5
1.1
1.0
4.1 ns
5.0 ns
8.6 ns
7.8 ns
8.7 ns
5.2 ns
Bn to An
disable time OE to An
OE to Bn
8.6
11.2
8.7
enable time OE to An
OE to Bn
12.8
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
1.0
1.1
8.3
5.8
0.5
0.5
0.5
0.5
1.0
1.1
5.3
4.7
7.1
7.8
6.8
8.2
0.5
0.5
0.5
0.5
1.0
1.0
4.5
4.5
7.1
6.9
6.8
6.7
0.5
0.5
0.5
0.5
1.0
0.5
3.8
4.3
7.1
6.0
6.8
5.1
0.5
0.5
0.5
0.5
1.0
0.5
3.5 ns
4.1 ns
7.1 ns
5.8 ns
6.8 ns
4.5 ns
Bn to An
disable time OE to An
OE to Bn
7.1
10.9
6.8
enable time OE to An
OE to Bn
12.4
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
0.5
1.1
8.0
4.9
0.5
0.5
0.5
0.5
0.5
1.1
5.2
4.4
5.1
7.1
4.8
7.9
0.5
0.5
0.5
0.5
0.5
0.5
4.3
3.8
5.1
6.3
4.8
6.4
0.5
0.5
0.5
0.5
0.5
0.5
3.3
3.3
5.1
5.1
4.8
4.6
0.5
0.5
0.5
0.5
0.5
0.5
2.9 ns
3.1 ns
5.1 ns
5.2 ns
4.8 ns
4.0 ns
Bn to An
disable time OE to An
OE to Bn
5.1
10.4
4.8
enable time OE to An
OE to Bn
11.9
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
0.5
1.1
7.8
4.8
0.5
0.5
0.5
0.5
0.5
1.1
5.0
4.1
4.9
6.9
4.0
7.8
0.5
0.5
0.5
0.5
0.5
0.5
4.1
3.5
4.9
6.0
4.0
6.2
0.5
0.5
0.5
0.5
0.5
0.5
3.1
2.9
4.9
4.8
4.0
4.5
0.5
0.5
0.5
0.5
0.5
0.5
2.7 ns
2.7 ns
4.9 ns
5.0 ns
4.0 ns
3.9 ns
Bn to An
disable time OE to An
OE to Bn
4.9
10.1
4.0
enable time OE to An
OE to Bn
11.7
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
11 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation An to Bn
0.5
0.5
0.5
0.5
1.1
1.1
9.9
9.9
0.5
0.5
0.5
0.5
1.1
1.1
7.4
9.4
0.5
0.5
0.5
0.5
1.1
1.1
6.4
9.2
0.5
0.5
0.5
0.5
1.1
1.0
5.4
8.8
0.5
0.5
0.5
0.5
1.1
1.0
5.3 ns
8.6 ns
13.0 ns
9.8 ns
15.9 ns
8.1 ns
delay
Bn to An
disable time OE to An
OE to Bn
13.0
13.6
15.9
15.7
13.0
10.5
15.9
11.5
13.0
10.4
15.9
9.9
13.0
8.8
enable time OE to An
OE to Bn
15.9
8.5
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
1.1
1.1
9.4
7.4
0.5
0.5
0.5
0.5
1.1
1.1
6.2
6.2
9.5
9.3
9.6
9.0
0.5
0.5
0.5
0.5
1.1
1.1
5.2
5.9
9.5
8.4
9.6
7.9
0.5
0.5
0.5
0.5
1.1
1.0
4.9
5.8
9.5
8.0
9.6
6.2
0.5
0.5
0.5
0.5
1.1
1.0
4.6 ns
5.5 ns
9.5 ns
8.6 ns
9.6 ns
5.8 ns
Bn to An
disable time OE to An
OE to Bn
9.5
12.4
9.6
enable time OE to An
OE to Bn
14.1
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
1.0
1.1
9.2
6.4
0.5
0.5
0.5
0.5
1.0
1.1
5.9
5.2
7.9
8.6
7.5
9.1
0.5
0.5
0.5
0.5
1.0
1.0
5.0
5.0
7.9
7.6
7.5
7.4
0.5
0.5
0.5
0.5
1.0
0.5
4.2
4.8
7.9
6.6
7.5
5.7
0.5
0.5
0.5
0.5
1.0
0.5
3.9 ns
4.6 ns
7.9 ns
6.4 ns
7.5 ns
5.0 ns
Bn to An
disable time OE to An
OE to Bn
7.9
12.0
7.5
enable time OE to An
OE to Bn
13.7
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
0.5
1.1
8.8
5.4
0.5
0.5
0.5
0.5
0.5
1.1
5.8
4.9
5.7
7.9
5.3
8.7
0.5
0.5
0.5
0.5
0.5
0.5
4.8
4.2
5.7
7.0
5.3
7.1
0.5
0.5
0.5
0.5
0.5
0.5
3.7
3.7
5.7
5.7
5.3
5.1
0.5
0.5
0.5
0.5
0.5
0.5
3.2 ns
3.5 ns
5.7 ns
5.8 ns
5.3 ns
4.4 ns
Bn to An
disable time OE to An
OE to Bn
5.7
11.5
5.3
enable time OE to An
OE to Bn
13.1
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation An to Bn
delay
0.5
0.5
0.5
0.5
0.5
1.1
8.6
5.3
0.5
0.5
0.5
0.5
0.5
1.1
5.5
4.6
5.4
7.6
4.4
8.6
0.5
0.5
0.5
0.5
0.5
0.5
4.6
3.9
5.4
6.6
4.4
6.9
0.5
0.5
0.5
0.5
0.5
0.5
3.5
3.2
5.4
5.3
4.4
5.0
0.5
0.5
0.5
0.5
0.5
0.5
3.0 ns
3.0 ns
5.4 ns
5.5 ns
4.4 ns
4.3 ns
Bn to An
disable time OE to An
OE to Bn
5.4
11.2
4.4
enable time OE to An
OE to Bn
12.9
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
12 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
11. Waveforms
V
I
V
An, Bn input
GND
M
t
t
PLH
PHL
V
OH
V
Bn, An output
M
V
OL
001aai475
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aai474
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VOL + 0.1 V
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
13 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuit for switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[3]
t/V[2]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCCO
VCCI
VCCI
VCCI
1.0 ns/V
1.0 ns/V
1.0 ns/V
15 pF
15 pF
15 pF
2 k
2 k
2 k
open
GND
2VCCO
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns
[3]
VCCO is the supply voltage associated with the output port.
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
14 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai476
001aai477
24
21
(1)
(2)
(3)
(4)
(5)
(6)
t
pd
(ns)
t
pd
(1)
(ns)
20
17
16
12
8
13
(2)
(3)
(4)
(5)
(6)
4
9
0
20
40
60
0
20
40
60
C
L
(pF)
C (pF)
L
a. Propagation delay (An to Bn); VCC(A) = 0.8 V
(1) VCC(B) = 0.8 V.
b. Propagation delay (An to Bn); VCC(B) = 0.8 V
(1)
(2)
V
V
CC(A) = 0.8 V.
CC(A) = 1.2 V.
(2)
VCC(B) = 1.2 V.
(3) VCC(B) = 1.5 V.
(4) VCC(B) = 1.8 V.
(3) VCC(A) = 1.5 V.
(4) VCC(A) = 1.8 V.
(5)
V
CC(B) = 2.5 V.
(5)
VCC(A) = 2.5 V.
(6) VCC(B) = 3.3 V.
(6) VCC(A) = 3.3 V.
Fig 8. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
15 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai478
001aai491
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
(2)
(3)
5
3
1
5
3
1
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (An to Bn);
VCC(A) = 1.2 V
b. HIGH to LOW propagation delay (An to Bn);
VCC(A) = 1.2 V
001aai479
001aai480
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (An to Bn);
VCC(A) = 1.5 V
d. HIGH to LOW propagation delay (An to Bn);
CC(A) = 1.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
16 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai481
001aai482
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (An to Bn);
VCC(A) = 1.8 V
b. HIGH to LOW propagation delay (An to Bn);
VCC(A) = 1.8 V
001aai483
001aai486
7
7
t
t
PHL
(ns)
PLH
(1)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (An to Bn);
VCC(A) = 2.5 V
d. HIGH to LOW propagation delay (An to Bn);
CC(A) = 2.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
17 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai485
001aai484
7
7
t
t
PHL
(ns)
PLH
(1)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (An to Bn);
VCC(A) = 3.3 V
b. HIGH to LOW propagation delay (An to Bn);
VCC(A) = 3.3 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
18 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
13. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 12. Package outline SOT355-1 (TSSOP24)
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
19 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w
M
2
11
L
12
13
1
e
E
h
2
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Fig 13. Package outline SOT815-1 (DHVQFN24)
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
20 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
14. Abbreviations
Table 16. Abbreviations
Acronym
CDM
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
CMOS
DUT
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
15. Revision history
Table 17. Revision history
Document ID
Release date
20121227
Data sheet status
Change notice
Supersedes
74AVC8T245 v.5
Modifications:
Product data sheet
-
74AVC8T245 v.4
• Table 4: conditions ICC and IGND changed (errata).
74AVC8T245 v.4
Modifications:
20111208
Product data sheet
-
74AVC8T245 v.3
• Legal pages updated.
74AVC8T245 v.3
74AVC8T245 v.2
74AVC8T245 v.1
20110928
20090428
20080711
Product data sheet
-
-
-
74AVC8T245 v.2
Product data sheet
Product data sheet
74AVC8T245 v.1
-
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
21 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
22 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AVC8T245
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
23 of 24
74AVC8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical propagation delay characteristics . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 December 2012
Document identifier: 74AVC8T245
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