935292877132 [NXP]
AUP/ULP/V SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6;
| 型号： | 935292877132 |
| 厂家： | 
NXP |
| 描述： | AUP/ULP/V SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总36页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1T45
Low-power dual supply translating transceiver; 3-state
Rev. 4 — 28 November 2011
Product data sheet
1. General description
The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a
direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable
bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage
between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low
voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to
V
CC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B
and a LOW on DIR allows transmission from B to A.
Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall
times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and
dynamic power consumption and is fully specified for partial power-down applications
using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow
current through the device when it is powered down. In suspend mode when either VCC(A)
or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.1 V to 3.6 V
VCC(B): 1.1 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1T45GW
74AUP1T45GM
40 C to +125 C
40 C to +125 C
SC-88
plastic surface-mounted package; 6 leads
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
74AUP1T45GF
74AUP1T45GN
74AUP1T45GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON6
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
SOT1202
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1T45GW
74AUP1T45GM
74AUP1T45GF
74AUP1T45GN
74AUP1T45GS
p5
p5
p5
p5
p5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
5
DIR
DIR
3
A
A
4
B
B
V
CC(A)
V
CC(B)
V
V
CC(A)
CC(B)
001aae962
001aae963
Fig 1. Logic symbol
Fig 2. Logic diagram
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
2 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
6. Pinning information
6.1 Pinning
74AUP1T45
74AUP1T45
V
1
2
3
6
5
4
V
CC(B)
CC(A)
GND
74AUP1T45
1
2
3
6
5
4
V
V
CC(B)
V
1
2
3
6
5
4
V
CC(B)
CC(A)
GND
CC(A)
GND
DIR
B
DIR
B
DIR
B
A
A
A
001aae965
001aae966
Transparent top view
Transparent top view
001aae964
Fig 3. Pin configuration SOT363
Fig 4. Pin configuration SOT886
Fig 5. Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
VCC(A)
GND
A
Pin description
Pin
1
Description
supply voltage A
ground (0 V)
2
3
data input or output A
data input or output B
direction control DIR
supply voltage B
B
4
DIR
5
VCC(B)
6
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A), VCC(B)
1.1 V to 3.6 V
1.1 V to 3.6 V
GND
Input[2]
Input/output[3]
DIR
L
A
B
A = B
input
H
input
B = A
X
suspend mode
suspend mode
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[2] The DIR input circuit is referenced to VCC(A)
[3] The input circuit of the data I/Os are always active.
.
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
3 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
Max
+4.6
+4.6
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
VO
Active mode
A port
[1][2]
[1][2]
[1][2]
0.5
0.5
0.5
-
VCC(A) + 0.5 V
VCC(B) + 0.5 V
B port
suspend or 3-state mode
VO = 0 V to VCC
+4.6
20
50
V
IO
output current
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
50
65
-
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The values of VCC(A) and VCC(B) are provided in the recommended operating conditions; see Table 6.
[3] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
1.1
1.1
0
Max
3.6
Unit
V
supply voltage A
supply voltage B
input voltage
3.6
V
3.6
V
[1]
VO
output voltage
0
VCCO
+125
200
V
Tamb
ambient temperature
input transition rise and fall rate
40
0
C
ns/V
t/V
VCCI =1.1 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
4 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
Tamb = 25 C
[1][3]
[1][4]
[1][3]
[1][4]
VIH
HIGH-level input data input
voltage
VCCI = 1.1 V to 1.95 V
0.65 VCCI
-
-
-
-
-
-
V
V
V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
1.6
2.0
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.65 VCC(A)
-
-
-
-
-
-
V
V
V
1.6
2.0
VIL
LOW-level input data input
voltage
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
-
-
-
-
-
-
0.35 VCCI
V
V
V
0.7
0.9
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
-
-
-
-
-
-
0.35 VCC(A)
V
V
V
0.7
0.9
V
CCI = 3.0 V to 3.6 V
VI = VIH
IO = 20 A;
VOH
HIGH-level
output voltage
[2]
[2]
VCCO 0.1
-
-
V
VCC(A) = VCC(B) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
0.75 VCCO
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level
VI = VIL
output voltage
IO = 20 A; VCC(A) = VCC(B) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
A
[2]
0.3 VCCO
0.31
0.31
0.31
0.44
0.31
0.44
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
0.1
VCC(A) = VCC(B) = 1.1 V to 3.6 V
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
5 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
[2]
IOZ
OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO
;
-
-
-
-
-
-
-
-
0.1
0.2
0.2
0.2
0.2
0.2
0.2
A
current
VCC(A) = VCC(B) = 1.1 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
IOFF
power-off
-
-
-
-
-
-
A
A
A
A
A
A
leakage current
VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
IOFF
additional
A port; VI or VO = 0 V to 3.6 V;
power-off
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
leakage current
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
[1]
[1]
[1]
ICC
supply current
A port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
0.5
0.5
-
A
A
A
-
VCC(A) = 0 V; VCC(B) = 3.6 V
0
B port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
-
0.5
-
A
A
A
A
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V
0.5
0.5
A plus B port (ICC(A) ICC(B)); IO = 0 A;
-
VI = GND or VCCI
;
VCC(A) = VCC(B) = 1.1 V to 3.6 V
ICC
additional supply A port; VCC(A) = VCC(B) = 3.3 V;
-
-
-
-
-
-
40
40
40
A
A
A
current
A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open
B port; VCC(A) = VCC(B) = 3.3 V;
B port at VCC(B) 0.6 V;
DIR at GND; A port = open
DIR input; VCC(A) = VCC(B) = 3.3 V;
A port at VCC(A) or GND; B port = open;
DIR at VCC(A) 0.6 V
CI
input
capacitance
DIR input; VI = GND or VCC(A)
;
-
-
0.9
2.0
-
-
pF
pF
VCC(A) = VCC(B) = 1.1 V to 3.6 V
[1][2]
CI/O
input/output
capacitance
A and B port; suspend mode; VCCI = 0 V;
VCCO = 1.1 V to 3.6 V; VO = VCCO or GND
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
6 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
Tamb = 40 C to +85 C
[1][3]
[1][4]
[1][3]
[1][4]
VIH
HIGH-level input data input
voltage
VCCI = 1.1 V to 1.95 V
0.65 VCCI
-
-
-
-
-
-
V
V
V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
1.6
2.0
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.65 VCC(A)
-
-
-
-
-
-
V
V
V
1.6
2.0
VIL
LOW-level input data input
voltage
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
-
-
-
-
-
-
0.35 VCCI
V
V
V
0.7
0.9
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH
-
-
-
-
-
-
0.35 VCC(A)
V
V
V
0.7
0.9
VOH
HIGH-level
output voltage
[2]
[2]
IO = 20 A;
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCCO 0.1
-
-
V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
VI = VIL
0.7 VCCO
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level
output voltage
IO = 20 A; VCC(A) = VCC(B) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
A
[2]
0.3 VCCO
0.37
0.35
0.33
0.45
0.33
0.45
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
0.5
VCC(A) = VCC(B) = 1.1 V to 3.6 V
[2]
IOZ
OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO
;
-
-
0.5
A
current VCC(A) = VCC(B) = 1.1 V to 3.6 V
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
7 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
IOFF
IOFF
ICC
power-off
A port; VI or VO = 0 V to 3.6 V;
-
-
-
-
-
-
-
0.5
0.5
0.5
0.6
0.6
0.6
A
leakage current VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
-
-
-
-
-
A
A
A
A
A
V
CC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
additional
power-off
leakage current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
V
CC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
[1]
[1]
[1]
supply current
A port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
0.9
0.9
-
A
A
A
-
VCC(A) = 0 V; VCC(B) = 3.6 V
0
B port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
-
0.9
-
A
A
A
A
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V
0.9
0.9
A plus B port (ICC(A) ICC(B)); IO = 0 A;
-
VI = GND or VCCI
;
VCC(A) = VCC(B) = 1.1 V to 3.6 V
ICC
additional supply A port; VCC(A) = VCC(B) = 3.3 V;
-
-
-
-
-
-
50
50
50
A
A
A
current
A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open
B port; VCC(A) = VCC(B) = 3.3 V;
B port at VCC(B) 0.6 V;
DIR at GND; A port = open
DIR input; VCC(A) = VCC(B) = 3.3 V;
A port at VCC(A) or GND; B port = open;
DIR at VCC(A) 0.6 V
T
amb = 40 C to +125 C
[1][3]
[1][4]
VIH
HIGH-level input data input
voltage
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.7 VCCI
1.6
-
-
-
-
-
-
V
V
V
2.0
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.7 VCC(A)
-
-
-
-
-
-
V
V
V
1.6
2.0
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
8 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
[1][3]
[1][4]
VIL
LOW-level input data input
voltage
VCCI = 1.1 V to 1.95 V
-
-
-
-
-
-
0.3 VCCI
V
V
V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.7
0.9
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH
-
-
-
-
-
-
0.3 VCC(A)
V
V
V
0.7
0.9
VOH
HIGH-level
output voltage
[2]
[2]
IO = 20 A;
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCCO 0.11
-
-
V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
VI = VIL
0.6 VCCO
0.93
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level
output voltage
IO = 20 A; VCC(A) = VCC(B) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
V
V
V
V
V
V
V
A
[2]
0.33 VCCO
0.41
0.39
0.36
0.50
0.36
0.50
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
0.75
VCC(A) = VCC(B) = 1.1 V to 3.6 V
[2]
IOZ
IOFF
OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO
;
-
-
-
-
-
-
-
-
0.75
0.75
0.75
0.75
A
A
A
A
current
VCC(A) = VCC(B) = 1.1 V to 3.6 V
power-off
A port; VI or VO = 0 V to 3.6 V;
leakage current
VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
9 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
IOFF
additional
power-off
leakage current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
-
-
-
-
0.75
0.75
0.75
A
B port; VI or VO = 0 V to 3.6 V;
-
-
A
A
V
CC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V
DIR input; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V
[1]
[1]
[1]
ICC
supply current
A port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
1.4
1.4
-
A
A
A
-
VCC(A) = 0 V; VCC(B) = 3.6 V
0
B port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
-
-
-
1.4
-
A
A
A
A
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V
1.4
1.4
A plus B port (ICC(A) ICC(B)); IO = 0 A;
-
VI = GND or VCCI
;
VCC(A) = VCC(B) = 1.1 V to 3.6 V
ICC
additional supply A port; VCC(A) = VCC(B) = 3.3 V;
-
-
-
-
-
-
75
75
75
A
A
A
current
A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open
B port; VCC(A) = VCC(B) = 3.3 V;
B port at VCC(B) 0.6 V;
DIR at GND; A port = open
DIR input; VCC(A) = VCC(B) = 3.3 V;
A port at VCC(A) or GND; B port = open;
DIR at VCC(A) 0.6 V
[1] VCCI is the supply voltage associated with the data input port.
[2] CCO is the supply voltage associated with the output port.
[3] For VCCI values not specified in the data sheet: minimum VIH = 0.7 VCCI and maximum VIL = 0.3 VCCI
V
.
[4] For VCCI values not specified in the data sheet: minimum VIH = 0.7 VCC(A) and maximum VIL = 0.3 VCC(A)
.
[5] All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation.
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
10 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
CL = 5 pF; VCC(A) = 1.1 V to 1.3 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.8
2.8
2.4
2.5
2.3
15.4 28.0 2.4
10.2 16.2 2.6
28.3
17.5
14.4
10.7
9.7
31.2
19.3
15.9
11.8
10.7
ns
ns
ns
ns
ns
8.1
6.3
5.6
13.0 2.2
10.0 2.1
9.0
1.9
tdis
disable time
2.7
2.9
2.7
2.7
2.9
5.3
5.3
5.3
5.3
5.3
8.5
8.4
8.5
8.7
8.7
2.5
2.7
2.5
2.5
2.5
8.7
8.7
9.0
8.9
9.1
9.6
9.7
ns
ns
ns
ns
ns
10.0
9.9
10.1
6.1
5.0
4.2
3.3
3.6
13.2 22.1 5.4
23.4
15.2
13.5
10.2
9.7
25.8
16.7
14.9
11.2
10.7
ns
ns
ns
ns
ns
9.3
8.1
6.3
6.3
13.9 4.4
12.3 3.6
9.3
9.2
2.9
3.2
CL = 5 pF; VCC(A) = 1.4 V to 1.6 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.5
2.5
2.1
2.2
2.0
14.5 26.6 2.2
27.1
15.9
12.7
8.9
29.9
17.5
14.0
9.8
ns
ns
ns
ns
ns
9.4
7.4
5.5
4.7
14.5 2.3
11.2 1.9
8.0
6.8
1.8
1.6
7.6
8.4
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
11 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.0
2.2
2.1
2.1
2.2
3.8
3.8
3.8
3.8
3.8
5.3
5.3
5.5
5.5
5.5
1.9
2.0
1.8
1.9
1.9
5.7
5.7
5.9
5.9
6.0
6.3
6.4
6.6
6.6
6.6
ns
ns
ns
ns
ns
[3]
5.7
4.7
3.9
3.0
3.3
12.7 21.0 5.2
22.3
14.1
12.3
8.8
24.6
15.5
13.5
9.7
ns
ns
ns
ns
ns
8.7
7.4
5.6
5.5
12.7 4.1
10.9 3.3
7.8
7.4
2.6
2.9
8.1
8.9
CL = 5 pF; VCC(A) = 1.65 V to 1.95 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.4
2.4
2.0
2.0
1.9
14.2 26.1 2.0
26.5
15.4
12.1
8.2
29.2
17.0
13.4
9.1
ns
ns
ns
ns
ns
9.1
7.0
5.1
4.3
13.9 2.1
10.7 1.7
7.4
6.1
1.6
1.5
6.9
7.7
tdis
disable time
2.0
2.1
2.0
2.0
2.1
3.5
3.5
3.5
3.5
3.5
4.8
4.8
5.0
4.9
4.9
1.8
1.9
1.8
1.8
1.8
5.2
5.2
5.4
5.4
5.4
5.8
5.7
6.0
6.0
6.0
ns
ns
ns
ns
ns
5.8
4.6
3.8
2.9
3.1
12.4 20.6 5.1
21.9
13.5
11.8
8.3
24.2
14.9
13.0
9.1
ns
ns
ns
ns
ns
8.4
7.1
5.2
5.1
12.2 3.9
10.4 3.2
7.3
6.9
2.5
2.7
7.5
8.3
CL = 5 pF; VCC(A) = 2.3 V to 2.7 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.4
2.3
1.9
1.9
1.8
13.6 25.5 2.0
25.9
14.7
11.4
7.5
28.6
16.2
12.5
8.3
ns
ns
ns
ns
ns
8.5
6.5
4.6
3.8
13.3 2.1
10.0 1.7
6.7
5.3
1.6
1.4
6.2
6.8
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
12 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
1.4
1.6
1.5
1.4
1.6
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.4
3.4
3.4
1.3
1.4
1.3
1.3
1.3
3.6
3.6
3.8
3.8
3.7
4.0
4.0
4.2
4.2
4.1
ns
ns
ns
ns
ns
[3]
5.8
4.5
3.7
2.8
3.1
12.3 20.4 5.1
21.8
13.2
11.3
7.8
24.0
14.5
12.5
8.6
ns
ns
ns
ns
ns
8.3
7.0
5.0
4.9
11.9 4.0
10.0 3.2
6.8
6.4
2.5
2.7
7.0
7.8
CL = 5 pF; VCC(A) = 3.0 V to 3.6 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.3
2.3
1.9
1.9
1.7
13.1 24.9 2.0
25.2
14.1
10.8
7.0
27.8
15.5
12.0
7.7
ns
ns
ns
ns
ns
8.1
6.1
4.3
3.5
12.8 2.0
9.5
6.2
5.0
1.7
1.6
1.4
5.7
6.3
tdis
disable time
1.7
1.8
1.7
1.7
1.8
2.8
2.8
2.8
2.8
2.8
3.5
3.5
3.6
3.6
3.6
1.5
1.7
1.5
1.5
1.5
3.8
3.8
4.0
3.9
3.9
4.2
4.2
4.4
4.4
4.3
ns
ns
ns
ns
ns
5.8
4.6
3.8
2.8
3.1
12.3 20.6 5.1
22.0
13.1
11.3
7.6
24.2
14.5
12.5
8.4
ns
ns
ns
ns
ns
8.3
6.9
5.0
4.9
11.8 4.0
10.0 3.2
6.7
6.3
2.5
2.7
6.9
7.6
CL = 10 pF; VCC(A) = 1.1 V to 1.3 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.0
3.0
3.1
2.7
2.7
16.2 29.8 2.7
10.8 17.5 2.7
30.2
18.6
14.6
11.2
10.1
33.3
20.5
16.1
12.4
11.1
ns
ns
ns
ns
ns
8.7
6.8
6.1
13.5 2.8
10.5 2.4
9.6
2.4
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
13 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.2
3.5
3.7
3.2
3.6
6.5
6.5
6.5
6.5
6.5
9.9
10.0 3.2
9.8 3.5
3.1
10.2
10.2
10.1
10.2
10.3
11.3
11.3
11.1
11.3
11.4
ns
ns
ns
ns
ns
10.1 3.1
10.1 3.2
[3]
6.4
5.3
5.2
3.6
4.4
14.3 23.5 5.8
10.2 15.4 4.6
24.8
16.6
14.7
11.0
11.4
27.4
18.4
16.2
12.1
12.5
ns
ns
ns
ns
ns
9.2
7.1
7.6
13.6 4.7
10.1 3.2
10.8 3.8
CL = 10 pF; VCC(A) = 1.4 V to 1.6 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.7
2.7
2.8
2.4
2.4
15.3 28.3 2.4
10.0 15.8 2.5
29.0
17.0
13.0
9.4
31.9
18.7
14.4
10.4
8.9
ns
ns
ns
ns
ns
7.9
6.0
5.2
11.8 2.5
8.6
7.4
2.2
2.1
8.0
tdis
disable time
2.5
2.7
2.9
2.5
2.8
4.7
4.7
4.7
4.7
4.7
6.4
6.5
6.5
6.5
6.6
2.3
2.4
2.6
2.3
2.4
6.8
6.9
6.9
6.9
6.9
7.6
7.6
7.6
7.6
7.7
ns
ns
ns
ns
ns
6.1
5.0
4.9
3.3
4.1
13.7 22.4 5.6
23.8
15.5
13.4
9.6
26.3
17.1
14.8
10.6
10.8
ns
ns
ns
ns
ns
9.6
8.5
6.4
6.7
14.2 4.3
12.3 4.4
8.7
9.1
3.0
3.5
9.7
CL = 10 pF; VCC(A) = 1.65 V to 1.95 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.6
2.6
2.7
2.3
2.3
15.0 27.8 2.3
28.3
16.5
12.4
8.8
31.2
18.2
13.7
9.7
ns
ns
ns
ns
ns
9.7
7.5
5.6
4.8
15.2 2.3
11.2 2.3
7.9
6.7
2.0
1.9
7.4
8.2
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
14 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.5
2.7
2.9
2.5
2.8
4.6
4.6
4.6
4.6
4.6
6.2
6.3
6.3
6.2
6.3
2.4
2.5
2.7
2.4
2.5
6.6
6.7
6.7
6.7
6.7
7.3
7.4
7.4
7.4
7.4
ns
ns
ns
ns
ns
[3]
6.1
5.0
4.8
3.2
3.9
13.5 22.1 5.4
23.4
14.9
13.0
9.1
25.8
16.5
14.3
10.0
10.2
ns
ns
ns
ns
ns
9.3
8.3
6.0
6.4
13.6 4.2
11.8 4.2
8.1
8.5
2.8
3.3
9.2
CL = 10 pF; VCC(A) = 2.3 V to 2.7 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.5
2.5
2.6
2.2
2.2
14.4 27.2 2.3
27.8
15.8
11.7
8.0
30.6
17.4
12.9
8.9
ns
ns
ns
ns
ns
9.1
7.0
5.1
4.3
14.6 2.3
10.5 2.2
7.2
5.9
1.9
1.9
6.6
7.3
tdis
disable time
1.8
2.0
2.1
1.8
2.1
3.3
3.3
3.3
3.3
3.3
4.2
4.4
4.4
4.3
4.4
1.7
1.8
2.0
1.7
1.8
4.6
4.7
4.7
4.7
4.7
5.1
5.2
5.2
5.2
5.2
ns
ns
ns
ns
ns
6.1
4.9
4.8
3.1
3.9
13.4 21.8 5.4
23.2
14.6
12.5
8.6
25.6
16.1
13.8
9.5
ns
ns
ns
ns
ns
9.2
8.1
5.8
6.2
13.3 4.2
11.4 4.2
7.7
8.0
2.8
3.3
8.7
9.6
CL = 10 pF; VCC(A) = 3.0 V to 3.6 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.5
2.5
2.5
2.2
2.1
14.0 26.6 2.2
27.0
15.1
11.2
7.5
29.8
16.7
12.4
8.3
ns
ns
ns
ns
ns
8.7
6.6
4.8
4.0
14.0 2.3
10.1 2.2
6.8
5.5
1.9
1.9
6.1
6.8
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
15 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.3
2.5
2.6
2.3
2.6
4.0
4.0
4.0
4.0
4.0
5.0
5.2
5.2
5.1
5.2
2.2
2.3
2.5
2.2
2.3
5.3
5.4
5.4
5.4
5.4
5.9
6.0
6.0
6.0
6.0
ns
ns
ns
ns
ns
[3]
6.2
4.9
4.8
3.1
3.9
13.5 22.0 5.5
23.4
14.6
12.4
8.5
25.8
16.1
13.7
9.4
ns
ns
ns
ns
ns
9.2
8.1
5.8
6.2
13.2 4.2
11.3 4.3
7.6
7.9
2.8
3.3
8.5
9.5
CL = 15 pF; VCC(A) = 1.1 V to 1.3 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.4
3.7
3.2
3.2
3.1
16.9 31.6 3.0
11.3 18.2 3.1
32.0
19.5
15.6
12.0
10.7
35.2
21.5
17.2
13.2
11.8
ns
ns
ns
ns
ns
9.1
7.3
6.5
14.3 3.0
11.2 2.8
10.2 2.6
tdis
disable time
3.9
4.5
4.2
3.9
4.5
7.6
7.6
7.6
7.6
7.6
11.4 3.8
11.3 4.1
11.3 4.1
11.7 3.8
11.7 4.1
11.7
11.7
11.7
11.9
11.9
12.9
12.9
12.9
13.1
13.1
ns
ns
ns
ns
ns
7.2
6.3
5.7
4.1
5.3
15.4 24.9 6.5
11.1 16.3 5.4
10.4 15.0 5.2
26.3
17.7
16.2
12.1
12.7
29.0
19.5
17.9
13.4
14.1
ns
ns
ns
ns
ns
7.9
8.8
11.4 3.8
12.2 4.9
CL = 15 pF; VCC(A) = 1.4 V to 1.6 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.1
3.4
3.0
2.9
2.8
16.1 30.1 2.8
10.5 16.5 2.8
30.7
17.9
13.9
10.1
8.7
33.8
19.7
15.4
11.2
9.6
ns
ns
ns
ns
ns
8.4
6.4
5.6
12.6 2.7
9.3
8.0
2.5
2.3
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
16 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.1
3.5
3.3
3.1
3.5
5.6
5.6
5.6
5.6
5.6
7.6
7.5
7.6
7.7
7.8
2.9
3.1
3.1
2.9
3.1
8.0
8.0
8.0
8.1
8.1
8.9
8.8
8.9
9.0
9.0
ns
ns
ns
ns
ns
[3]
6.9
6.0
5.4
3.8
5.0
14.9 23.8 6.4
10.5 15.1 5.2
25.3
16.6
15.0
10.7
11.1
27.9
18.3
16.5
11.9
12.3
ns
ns
ns
ns
ns
9.7
7.2
8.0
13.7 5.0
9.9 3.5
10.5 4.6
CL = 15 pF; VCC(A) = 1.65 V to 1.95 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.0
3.2
2.8
2.8
2.6
15.8 29.6 2.6
10.2 15.9 2.6
30.1
17.4
13.4
9.5
33.2
19.2
14.8
10.5
8.9
ns
ns
ns
ns
ns
8.0
6.0
5.2
12.0 2.5
8.6
7.3
2.3
2.2
8.0
tdis
disable time
3.2
3.7
3.5
3.2
3.7
5.8
5.8
5.8
5.8
5.8
7.6
7.6
7.7
7.8
7.8
3.1
3.3
3.3
3.1
3.4
8.0
8.1
8.1
8.2
8.1
8.9
8.9
9.0
9.0
9.0
ns
ns
ns
ns
ns
6.9
5.9
5.3
3.7
4.9
14.7 23.4 6.2
10.2 14.6 5.0
24.9
16.0
14.5
10.2
10.6
27.4
17.7
16.0
11.3
11.7
ns
ns
ns
ns
ns
9.4
6.8
7.6
13.2 4.8
9.4
9.9
3.4
4.4
CL = 15 pF; VCC(A) = 2.3 V to 2.7 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.0
3.1
2.7
2.7
2.5
15.2 29.0 2.6
29.5
16.7
12.6
8.7
32.5
18.4
13.9
9.6
ns
ns
ns
ns
ns
9.6
7.5
5.5
4.7
15.3 2.6
11.3 2.5
7.9
6.5
2.3
2.1
7.2
8.0
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
17 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.4
2.7
2.5
2.4
2.7
4.1
4.1
4.1
4.1
4.1
5.2
5.3
5.4
5.4
5.3
2.2
2.4
2.4
2.2
2.4
5.6
5.7
5.7
5.7
5.6
6.2
6.3
6.3
6.3
6.2
ns
ns
ns
ns
ns
[3]
6.9
5.9
5.3
3.7
4.8
14.6 23.2 6.2
10.1 14.2 5.0
24.7
15.6
14.0
9.8
27.2
17.3
15.5
10.8
11.2
ns
ns
ns
ns
ns
9.2
6.7
7.4
12.8 4.8
8.9
9.4
3.4
4.4
10.1
CL = 15 pF; VCC(A) = 3.0 V to 3.6 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
2.9
3.1
2.7
2.7
2.5
14.7 28.3 2.6
28.8
16.0
12.1
8.2
31.7
17.7
13.4
9.1
ns
ns
ns
ns
ns
9.2
7.1
5.2
4.5
14.7 2.6
10.9 2.4
7.4
6.1
2.2
2.1
6.8
7.5
tdis
disable time
3.1
3.5
3.3
3.1
3.5
5.3
5.3
5.3
5.3
5.3
6.5
6.6
6.7
6.8
6.6
3.0
3.2
3.2
3.0
3.2
6.9
7.0
7.0
7.1
6.9
7.6
7.7
7.8
7.8
7.6
ns
ns
ns
ns
ns
6.9
5.9
5.3
3.7
4.8
14.6 23.4 6.3
10.1 14.2 5.0
24.9
15.6
13.9
9.6
27.4
17.2
15.4
10.6
11.0
ns
ns
ns
ns
ns
9.2
6.6
7.4
12.7 4.8
8.8
9.3
3.4
4.4
10.0
CL = 30 pF; VCC(A) = 1.1 V to 1.3 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
4.2
4.5
4.2
4.0
4.0
19.1 36.0 3.8
12.8 20.6 4.0
10.4 16.2 3.8
36.8
22.0
17.4
13.2
12.5
40.5
24.2
19.2
14.5
13.8
ns
ns
ns
ns
ns
8.3
7.5
12.4 3.5
11.5 3.7
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
18 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
5.6
6.1
6.6
5.6
7.0
11.0 15.7 5.5
11.0 15.6 6.0
11.0 15.5 6.5
11.0 15.6 5.5
11.0 15.9 6.6
16.2
15.9
15.8
15.8
16.7
17.9
17.5
17.4
17.5
18.4
ns
ns
ns
ns
ns
[3]
8.7
7.3
8.1
5.2
8.1
18.9 29.0 8.1
13.8 19.3 6.8
13.7 19.2 7.7
10.3 14.0 4.9
12.5 16.5 7.5
30.5
20.7
20.3
14.7
18.0
33.6
22.8
22.4
16.2
19.9
ns
ns
ns
ns
ns
CL = 30 pF; VCC(A) = 1.4 V to 1.6 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
4.0
4.2
3.9
3.8
3.7
18.2 34.5 3.5
12.0 18.9 3.7
35.5
20.3
15.8
11.4
10.4
39.1
22.4
17.4
12.6
11.4
ns
ns
ns
ns
ns
9.6
7.5
6.7
14.4 3.5
10.4 3.2
9.3
3.4
tdis
disable time
4.4
4.8
5.2
4.4
5.5
8.3
8.3
8.3
8.3
8.3
10.8 4.3
10.7 4.6
10.8 5.0
10.8 4.3
11.0 5.1
11.4
11.2
11.2
11.1
11.8
12.6
12.3
12.4
12.3
13.0
ns
ns
ns
ns
ns
8.4
7.1
7.8
4.9
7.7
18.3 27.9 7.9
13.2 18.2 6.6
13.1 17.9 7.4
29.5
19.6
19.1
13.4
16.3
32.5
21.6
21.0
14.8
18.0
ns
ns
ns
ns
ns
9.6
12.6 4.6
11.7 14.8 7.2
CL = 30 pF; VCC(A) = 1.65 V to 1.95 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.9
4.1
3.8
3.6
3.5
18.0 34.0 3.4
11.7 18.3 3.5
34.9
19.8
15.2
10.8
9.7
38.4
21.9
16.8
11.9
10.7
ns
ns
ns
ns
ns
9.2
7.1
6.3
13.9 3.4
9.8
8.6
3.1
3.2
74AUP1T45
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Product data sheet
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19 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
5.0
5.4
5.8
5.0
6.2
9.2
9.2
9.1
9.1
9.2
11.7 4.8
11.7 5.3
11.9 5.7
11.7 4.8
11.9 5.8
12.3
12.1
12.3
12.1
12.7
13.6
13.4
13.6
13.4
14.1
ns
ns
ns
ns
ns
[3]
8.4
7.0
7.7
4.8
7.6
18.1 27.6 7.8
12.9 17.7 6.4
12.8 17.4 7.2
29.1
19.1
18.6
12.9
15.8
32.0
21.0
20.6
14.2
17.4
ns
ns
ns
ns
ns
9.3
12.0 4.5
11.3 14.2 7.0
CL = 30 pF; VCC(A) = 2.3 V to 2.7 V
[2]
[3]
[3]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.8
4.0
3.7
3.4
3.5
17.4 33.4 3.4
11.1 17.7 3.5
34.3
19.1
14.4
10.0
8.9
37.8
21.1
15.9
11.1
9.8
ns
ns
ns
ns
ns
8.7
6.5
5.7
13.2 3.3
9.1
7.8
3.0
3.1
tdis
disable time
3.6
3.9
4.2
3.6
4.5
6.5
6.5
6.5
6.5
6.5
8.1
8.1
8.3
8.2
8.2
3.5
3.8
4.1
3.5
4.2
8.5
8.5
8.6
8.5
8.9
9.4
9.4
9.5
9.4
9.8
ns
ns
ns
ns
ns
8.4
7.0
7.7
4.8
7.6
18.0 27.4 7.8
12.8 17.3 6.4
12.6 17.0 7.2
28.8
18.7
18.2
12.4
15.3
31.8
20.6
20.0
13.7
16.9
ns
ns
ns
ns
ns
9.1
11.6 4.5
11.1 13.7 7.0
CL = 30 pF; VCC(A) = 3.0 V to 3.6 V
[2]
tpd
propagation delay A to B or B to A; see Figure 6
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
3.8
3.9
3.7
3.2
3.4
16.9 32.8 3.3
10.7 17.1 3.5
33.5
18.5
13.9
9.5
36.9
20.4
15.4
10.5
9.3
ns
ns
ns
ns
ns
8.3
6.3
5.5
12.7 3.3
8.6
7.4
2.9
3.1
8.4
74AUP1T45
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
[3]
tdis
disable time
DIR to A; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 7
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
5.0
5.4
5.9
5.0
6.2
9.0
9.0
9.0
9.0
9.0
11.0 4.9
11.1 5.3
11.3 5.7
11.2 4.9
11.2 5.9
11.5
11.4
11.6
11.4
11.9
12.7
12.6
12.8
12.6
13.2
ns
ns
ns
ns
ns
[3]
8.4
7.0
7.7
4.8
7.6
18.1 27.6 7.8
12.8 17.3 6.4
12.6 17.0 7.2
29.1
18.6
18.1
12.3
15.1
32.0
20.6
19.9
13.6
16.7
ns
ns
ns
ns
ns
9.0
11.5 4.5
11.1 13.6 7.0
74AUP1T45
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Product data sheet
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21 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max Min
Max
Max
(85 C) (125 C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation A port; (direction A to B)
capacitance
[4][5]
[4][5]
[4][5]
[4][5]
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
A port; (direction B to A)
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
B port; (direction A to B)
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
B port; (direction B to A)
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
-
-
-
-
-
0.6
0.7
0.7
0.9
1.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
-
-
-
-
-
3.7
3.8
4.0
4.6
5.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
-
-
-
-
-
3.7
3.8
4.0
4.6
5.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
-
-
-
-
-
0.6
0.7
0.7
0.9
1.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
[1] All typical values are measured at nominal VCC(A) and VCC(B)
[2] tpd is the same as tPLH and tPHL
[3] dis is the same as tPLZ and tPHZ
.
.
t
.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[5] fi = 1 MHz; VI = GND to VCC
74AUP1T45
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
12. Waveforms
V
I
V
A, B input
M
GND
t
t
PLH
PHL
V
OH
B, A output
V
M
001aae967
V
OL
Measurement points are given in Table 9.
OL and VOH are typical output voltage drops that occur with the output load.
V
Fig 6. The data input (A, B) to output (B, A) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. Enable and disable times
Table 9. Measurement points
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
VM
Output[2]
VM
VX
VOL + 0.1 V
VY
0.5 VCCI
0.5 VCCI
0.5 VCCI
0.5 VCCO
0.5 VCCO
0.5 VCCO
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
V
EXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC(A), VCC(B)
1.1 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[2]
[3]
tr = tf
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
VCCI
3.0 ns
5 pF, 10 pF, 15 pF 5 k or 1 M open
GND
2 VCCO
and 30 pF
[1] VCCI is the supply voltage associated with the data input port.
[2] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
[3] VCCO is the supply voltage associated with the output port.
74AUP1T45
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Product data sheet
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 9 is an example of the 74AUP1T45 being used in an
unidirectional logic level-shifting application.
74AUP1T45
V
V
V
V
CC1
CC1
CC2
CC2
V
V
CC(B)
CC(A)
GND
A
1
2
3
6
5
4
DIR
B
System-1
System-2
001aae969
Fig 9. Unidirectional logic level-shifting application
Table 11. Description unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
GND
A
Function
VCC1
GND
OUT
IN
Description
supply voltage of system-1 (1.1 V to 3.6 V)
device ground (0 V)
2
3
output level depends on VCC1 voltage
4
B
input threshold value depends on VCC2 voltage
the GND (LOW level) determines B port to A port direction
supply voltage of system-2 (1.1 V to 3.6 V)
5
DIR
DIR
6
VCC(B)
VCC2
74AUP1T45
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Product data sheet
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 10 shows the 74AUP1T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable (OE) pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
74AUP1T45
V
V
V
V
CC2
CC1
CC1
CC2
V
V
CC(B)
CC(A)
GND
A
1
2
3
6
5
4
PULL-UP/DOWN
OR
BUSHOLD
PULL-UP/DOWN
OR
BUSHOLD
DIR
B
I/O-1
I/O-2
DIR CTRL
System-1
System-2
001aae970
System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.
Fig 10. Bidirectional logic level-shifting application
Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 12. Description bidirectional logic level-shifting application[1][2]
State DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on the pull-up or pull-down.
3
4
L
L
Z
Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The
bus-line state depends on the pull-up or pull-down.
input
output
system-2 data to system-1
[1] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.
[2] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74AUP1T45
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Product data sheet
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74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
13.3 Power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply
current, bus contention, oscillations, or other anomalies. Take the following precautions to
guard against such power-up problems:
• Connect ground before any supply voltage is applied.
• Power-up VCC(A)
.
• VCC(B) can be ramped up along with or after VCC(A)
.
13.4 Enable times
Calculate the enable times for the 74AUP1T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74AUP1T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
27 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
14. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 11. Package outline SOT363 (SC-88)
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
28 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 12. Package outline SOT886 (XSON6)
74AUP1T45
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
29 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(1)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 13. Package outline SOT891 (XSON6)
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
30 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig 14. Package outline SOT1115 (XSON6)
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
31 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig 15. Package outline SOT1202 (XSON6)
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
32 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
15. Abbreviations
Table 13. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
16. Revision history
Table 14. Revision history
Document ID
74AUP1T45 v.4
Modifications:
74AUP1T45 v.3
74AUP1T45 v.2
74AUP1T45 v.1
Release date
20111128
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP1T45 v.3
• Legal pages updated.
20101104
20090803
20061018
Product data sheet
-
-
-
74AUP1T45 v.2
Product data sheet
Product data sheet
74AUP1T45 v.1
-
74AUP1T45
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
33 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74AUP1T45
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 28 November 2011
34 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1T45
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Product data sheet
Rev. 4 — 28 November 2011
35 of 36
74AUP1T45
NXP Semiconductors
Low-power dual supply translating transceiver; 3-state
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
9
10
11
12
13
Application information. . . . . . . . . . . . . . . . . . 25
Unidirectional logic level-shifting application . 25
Bidirectional logic level-shifting application. . . 26
Power-up considerations . . . . . . . . . . . . . . . . 27
Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 27
13.1
13.2
13.3
13.4
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 33
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 34
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 35
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 November 2011
Document identifier: 74AUP1T45
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