935294091118 [NXP]
CBTLV/3B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PQCC24, 5.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, SOT815-1, DHVQFN-24;
| 型号： | 935294091118 |
| 厂家： | 
NXP |
| 描述： | CBTLV/3B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PQCC24, 5.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, SOT815-1, DHVQFN-24 驱动 输出元件 逻辑集成电路 |
| 文件： | 总18页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74CBTLV3861
10-bit bus switch with output enable
Rev. 3 — 16 December 2011
Product data sheet
1. General description
The 74CBTLV3861 is a 10-bit bus switch with one output enable (OE) input. When OE is
LOW, the switch is closed and port A is connected to the B port. When OE is HIGH, the
switch is disabled.
To ensure the high-impedance OFF-state during power-up or power-down, OE should be
tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5 switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74CBTLV3861DK 40 C to +125 C SSOP24[1]
74CBTLV3861PW 40 C to +125 C TSSOP24
plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
SOT556-1
SOT355-1
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
74CBTLV3861BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
[1] Also known as QSOP24 package
4. Functional diagram
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
A10
11
2
3
4
5
6
7
8
9
23
OE
22
B1
21
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
B9
13
B10
001aan142
Fig 1. Logic symbol
nB
nA
OE
001aan143
Fig 2. Logic diagram (one switch)
74CBTLV3861
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
2 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
5. Pinning information
5.1 Pinning
74CBTLV3861
74CBTLV3861
1
2
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
n.c.
A1
V
n.c.
A1
1
2
V
CC
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
3
A2
A2
3
4
A3
A3
4
5
A4
A4
5
6
A5
A5
6
7
A6
A6
7
8
A7
A7
8
9
A8
A8
9
10
11
12
10
11
12
A9
A9
A10
GND
A10
GND
001aan144
001aan145
Fig 3. Pin configuration for TSSOP24 (SOT355-1)
Fig 4. Pin configuration for SSOP24 (SOT556-1)
74CBTLV3861
terminal 1
index area
2
3
23
22
21
20
19
18
17
16
15
14
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
OE
B1
B2
B2
B4
B5
B6
B7
B8
B9
4
5
6
7
8
9
10
11
001aan146
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5. Pin configuration for DHVQFN24 (SOT815-1)
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
3 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
5.2 Pin description
Table 2.
Symbol
n.c.
Pin description
Pin
Description
1
not connected
A1 to A10
GND
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12
data input/output (A port)
ground (0 V)
B1 to B10
OE
22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port)
23
24
output enable input (active LOW)
positive supply voltage
VCC
6. Functional description
Table 3.
Function selection[1]
Input
OE
L
Input/output
An, Bn
An = Bn
Z
H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
50
50
-
Max
+4.6
+4.6
VCC + 0.5
-
Unit
V
supply voltage
[1]
[1]
input voltage
V
VSW
IIK
switch voltage
enable and disable mode
VI < 0.5 V
V
input clamping current
switch clamping current
switch current
mA
mA
mA
mA
mA
C
ISK
VI < 0.5 V
-
ISW
VSW = 0 V to VCC
128
+100
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
4 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
2.3
0
Max
3.6
Unit
V
supply voltage
input voltage
VI
3.6
V
VSW
switch voltage
ambient temperature
enable and disable mode
0
VCC
+125
200
V
Tamb
40
-
C
ns/V
[1]
t/V
input transition rise and fall rate VCC = 2.3 V to 3.6 V
[1] Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
1.7
2.0
-
Typ[1]
Max
-
Min
1.7
2.0
-
Max
-
VIH
VIL
HIGH-level
input voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
-
-
-
V
-
-
V
LOW-levelinput VCC = 2.3 V to 2.7 V
voltage
0.7
0.9
1
0.7
0.9
20
V
VCC = 3.0 V to 3.6 V
-
-
V
II
input leakage
current
pin OE; VI = GND to VCC
VCC = 3.6 V
;
-
-
A
IS(OFF)
IS(ON)
IOFF
ICC
OFF-state
leakage current
VCC = 3.6 V; see Figure 6
VCC = 3.6 V; see Figure 7
VI or VO = 0 V to 3.6 V;
-
-
-
-
-
-
-
-
1
1
-
-
-
-
20
20
50
50
A
A
A
A
ON-state
leakage current
power-off
leakage current VCC = 0 V
10
10
supply current VI = GND or VCC; IO = 0 A;
VSW = GND or VCC
VCC = 3.6 V
;
[2]
ICC
additional
supply current
pin OE; VI = VCC 0.6 V;
SW = GND or VCC
VCC = 3.6 V
-
-
300
-
2000
A
V
;
CI
input
capacitance
pin OE; VCC = 3.3 V;
VI = 0 V to 3.3 V
-
-
-
0.9
5.2
-
-
-
-
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
VCC = 3.3 V; VI = 0 V to 3.3 V
CS(ON)
ON-state
VCC = 3.3 V; VI = 0 V to 3.3 V
14.3
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] One input at 3 V, other inputs at VCC or GND.
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
5 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
9.1 Test circuits
V
CC
V
CC
OE
Bn
OE
An
V
V
IL
IH
I
I
I
s
s
s
An
Bn
A
A
A
GND
GND
V
V
V
V
O
I
O
I
001aan147
001aan148
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage
current (one switch)
Fig 7. Test circuit for measuring ON-state leakage
current (one switch)
9.2 ON resistance
Table 7.
Resistance RON
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
RON
ON resistance VCC = 2.3 V to 2.7 V;
see Figure 9 to Figure 11
ISW = 64 mA; VI = 0 V
ISW = 24 mA; VI = 0 V
ISW = 15 mA; VI = 1.7 V
-
-
-
4.2
4.2
8.4
8.0
8.0
40
-
-
-
15.0
15.0
60.0
VCC = 3.0 V to 3.6 V;
see Figure 12 to Figure 14
ISW = 64 mA; VI = 0 V
ISW = 24 mA; VI = 0 V
ISW = 15 mA; VI = 2.4 V
-
-
-
4.0
4.0
6.2
7.0
7.0
15
-
-
-
11.0
11.0
25.5
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
6 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
9.3 ON resistance test circuit and graphs
001aai109
11
R
ON
(Ω)
9
7
5
3
V
SW
V
V
CC
OE
An
(1)
(2)
V
IL
Bn
(3)
(4)
GND
V
I
SW
I
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
001aan149
RON = VSW / ISW
.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 8. Test circuit for measuring ON resistance
(one switch)
Fig 9. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 15 mA
001aai110
001aai111
11
11
R
ON
R
ON
(Ω)
(Ω)
9
7
5
3
9
7
5
3
(1)
(2)
(1)
(2)
(3)
(4)
(3)
(4)
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 24 mA
Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 64 mA
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
7 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
001aai105
001aai106
8
8
6
4
2
R
ON
R
ON
(Ω)
(Ω)
6
4
2
(1)
(2)
(1)
(2)
(3)
(4)
(3)
(4)
0
1
2
3
4
0
1
2
3
4
V (V)
V (V)
I
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 12. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 15 mA
Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 24 mA
001aai107
7.5
R
ON
(Ω)
6.5
5.5
4.5
3.5
2.5
(1)
(2)
(3)
(4)
0
1
2
3
4
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
8 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
10. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 17
Symbol Parameter Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
ten
tdis
propagation delay An to Bn or Bn to An;
see Figure 15
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
-
-
0.13
0.20
-
-
0.20
0.31
ns
ns
[4]
enable time
disable time
OE to An or Bn;
see Figure 16
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.0
1.0
2.9
2.4
5.5
4.9
1.0
1.0
8.0
7.0
ns
ns
[5]
OE to An or Bn;
see Figure 16
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.0
1.0
2.6
3.1
5.5
5.8
1.0
1.0
8.0
8.5
ns
ns
[1] All typical values are measured at Tamb = 25 C and at nominal VCC
.
[2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven
by an ideal voltage source (zero output impedance).
[3]
t
pd is the same as tPLH and tPHL
.
[4] ten is the same as tPZH and tPZL
.
[5] tdis is the same as tPHZ and tPLZ
.
11. Waveforms
V
I
V
V
M
input
0 V
M
t
t
PLH
PHL
V
OH
V
V
M
output
M
V
OL
001aai367
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. The data input (An, Bn) to output (Bn, An) propagation delay times
Table 9.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VI
tr = tf
VX
VY
2.3 V to 2.7 V
3.0 V to 3.6 V
0.5VCC
0.5VCC
VCC
VCC
2.0 ns
2.0 ns
0.5VCC
0.5VCC
VOL + 0.15 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.3 V
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
9 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
V
I
OE input
V
V
M
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
enabled
switch
disabled
001aan150
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
74CBTLV3861
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
10 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 17. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
2.3 V to 2.7 V
3.0 V to 3.6 V
30 pF
50 pF
500
500
open
GND
2VCC
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
11 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
12. Package outline
SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm
SOT556-1
D
E
A
X
c
y
H
v
M
A
E
Z
13
24
A
2
A
(A )
3
A
1
θ
L
p
L
12
1
detail X
w M
e
b
p
0
2.5
5 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
1
L
p
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.25
0.10
1.55
1.40
0.31
0.20
0.25
0.18
8.8
8.6
4.0
3.8
6.2
5.8
0.89
0.41
1.05
0.66
mm
1.73
0.25
0.01
0.635
0.025
0.25
0.18
0.1
0.0098 0.061
0.0040 0.055
0.012 0.0098 0.344 0.157
0.008 0.0075 0.337 0.150
0.244
0.228
0.035
0.016
0.040
0.026
8o
0o
inches
0.068
0.041
0.01 0.007 0.004
Note
1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT556-1
MO-137
Fig 18. Package outline SOT556-1 (SSOP24)
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
12 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 19. Package outline SOT355-1 (TSSOP24)
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
13 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w M
2
11
L
12
13
1
e
2
E
h
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Fig 20. Package outline SOT815-1 (DHVQFN24)
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
14 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
13. Abbreviations
Table 11. Abbreviations
Acronym
CDM
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
CMOS
DUT
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
14. Revision history
Table 12. Revision history
Document ID
Release date
20111216
Data sheet status
Change notice
Supersedes
74CBTLV3861 v.3
Modifications:
Product data sheet
-
74CBTLV3861 v.2
• Legal pages updated.
74CBTLV3861 v.2
74CBTLV3861 v.1
20110120
Product data sheet
-
-
74CBTLV3861 v.1
-
20101206
Product data sheet
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
15 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
16 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74CBTLV3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
17 of 18
74CBTLV3861
NXP Semiconductors
10-bit bus switch with output enable
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
9.1
9.2
9.3
10
11
12
13
14
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 December 2011
Document identifier: 74CBTLV3861
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