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935296291518 [NXP]

32-BIT, FLASH, 204MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100;
935296291518
型号： 935296291518
厂家： NXP    NXP
描述：

32-BIT, FLASH, 204MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
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LPC4350/30/20/10  
32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet;  
two High-speed USBs; advanced configurable peripherals  
Rev. 4.1 — 11 December 2013  
Product data sheet  
1. General description  
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded  
applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM,  
advanced configurable peripherals such as the State Configurable Timer (SCT) and the  
Serial General-Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,  
LCD, an external memory controller, and multiple digital and analog peripherals. The  
LPC4350/30/20/10 operate at CPU frequencies of up to 204 MHz.  
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements  
such as low power consumption, enhanced debug features, and a high level of support  
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a  
Harvard architecture with separate local instruction and data buses as well as a third bus  
for peripherals, and includes an internal prefetch unit that supports speculative branching.  
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD  
instructions. A hardware floating-point processor is integrated in the core.  
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which  
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers  
up to 204 MHz performance with a simple instruction set and reduced code size.  
2. Features and benefits  
Cortex-M4 Processor core  
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.  
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.  
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).  
Hardware floating-point unit.  
Non-maskable Interrupt (NMI) input.  
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch  
points.  
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.  
System tick timer.  
Cortex-M0 Processor core  
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4  
application processor.  
Running at frequencies of up to 204 MHz.  
JTAG and built-in NVIC.  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
On-chip memory  
Up to 264 kB SRAM for code and data use.  
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be  
powered down individually.  
64 kB ROM containing boot code and on-chip software drivers.  
64 bit + 256 bit general-purpose One-Time Programmable (OTP) memory.  
Clock generation unit  
Crystal oscillator with an operating range of 1 MHz to 25 MHz.  
12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and  
voltage.  
Ultra-low power Real-Time Clock (RTC) crystal oscillator.  
Three PLLs allow CPU operation up to the maximum CPU rate without the need for  
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the  
third PLL can be used as audio PLL.  
Clock output.  
Configurable digital peripherals  
Serial GPIO (SGPIO) interface.  
State Configurable Timer (SCT) subsystem on AHB.  
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and  
outputs to event driven peripherals like the timers, SCT, and ADC0/1.  
Serial interfaces  
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to  
52 MB per second.  
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high  
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time  
stamping (IEEE 1588-2008 v2).  
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and  
on-chip high-speed PHY (USB0).  
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip  
full-speed PHY and ULPI interface to external high-speed PHY (USB1).  
USB interface electrical test software included in ROM USB stack.  
Four 550 UARTs with DMA support: one UART with full modem interface; one  
UART with IrDA interface; three USARTs support UART synchronous mode and a  
smart card interface conforming to ISO7816 specification.  
Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller  
excludes operation of all other peripherals connected to the same bus bridge See  
Figure 1 and Ref. 1.  
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA  
support.  
One SPI controller.  
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O  
pins conforming to the full I2C-bus specification. Supports data rates of up to  
1 Mbit/s.  
One standard I2C-bus interface with monitor mode and with standard I/O pins.  
Two I2S interfaces, each with DMA support and with one input and one output.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
2 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Digital peripherals  
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,  
and SDRAM devices.  
LCD controller with DMA support and a programmable display resolution of up to  
1024 H 768 V. Supports monochrome and color STN panels and TFT color  
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel  
mapping.  
Secure Digital Input Output (SD/MMC) card interface.  
Eight-channel General-Purpose DMA controller can access all memories on the  
AHB and all DMA-capable AHB slaves.  
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable  
pull-up/pull-down resistors.  
GPIO registers are located on the AHB for fast access. GPIO ports have DMA  
support.  
Up to eight GPIO pins can be selected from all GPIO pins as edge and level  
sensitive interrupt sources.  
Two GPIO group interrupt modules enable an interrupt based on a programmable  
pattern of input states of a group of GPIO pins.  
Four general-purpose timer/counters with capture and match capabilities.  
One motor control Pulse Width Modulator (PWM) for three-phase motor control.  
One Quadrature Encoder Interface (QEI).  
Repetitive Interrupt timer (RI timer).  
Windowed watchdog timer (WWDT).  
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes  
of battery powered backup registers.  
Alarm timer; can be battery powered.  
Analog peripherals  
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.  
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.  
Up to eight input channels per ADC.  
Unique ID for each device.  
Power  
Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for  
the core supply and the RTC power domain.  
RTC power domain can be powered separately by a 3 V battery supply.  
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep  
power-down.  
Processor wake-up from Sleep mode via wake-up interrupts from various  
peripherals.  
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via  
external interrupts and interrupts generated by battery powered blocks in the RTC  
power domain.  
Brownout detect with four separate thresholds for interrupt and forced reset.  
Power-On Reset (POR).  
Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP144  
package.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
3 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
3. Applications  
Motor control  
Embedded audio applications  
Industrial automation  
e-metering  
Power management  
White goods  
RFID readers  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
4 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm  
LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls  
Version  
LPC4350FET256 LBGA256  
SOT740-2  
SOT570-3  
SOT740-2  
SOT570-3  
LPC4330FET256 LBGA256  
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm  
LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls  
LPC4330FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1  
LPC4330FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1  
LPC4320FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1  
LPC4320FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1  
LPC4310FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1  
LPC4310FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1  
4.1 Ordering options  
Table 2.  
Ordering options  
Type number  
Total  
SRAM  
LCD Ethernet USB0  
(Host,  
USB1  
(Host,  
ADC  
channels  
PWM  
QEI  
GPIO Package  
Device, Device)/  
OTG)  
ULPI  
interface  
LPC4350FET256 264 kB yes yes  
LPC4350FET180 264 kB yes yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
no  
yes/yes  
yes/yes  
yes/yes  
yes/yes  
yes/no  
yes/no  
no  
8
8
8
8
4
8
4
8
4
8
yes  
yes  
yes  
yes  
no  
yes  
yes  
yes  
yes  
no  
164  
118  
164  
118  
49  
LBGA256  
TFBGA180  
LBGA256  
TFBGA180  
TFBGA100  
LQFP144  
TFBGA100  
LQFP144  
TFBGA100  
LQFP144  
LPC4330FET256 264 kB no  
LPC4330FET180 264 kB no  
LPC4330FET100 264 kB no  
LPC4330FBD144 264 kB no  
LPC4320FET100 200 kB no  
LPC4320FBD144 200 kB no  
LPC4310FET100 168 kB no  
LPC4310FBD144 168 kB no  
yes  
yes  
yes  
yes  
no  
yes  
no  
no  
83  
no  
49  
no  
no  
yes  
no  
no  
83  
no  
no  
no  
49  
no  
no  
no  
yes  
no  
83  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
5 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
5. Block diagram  
LPC4350/30/20/20/10  
TEST/DEBUG  
INTERFACE  
TEST/DEBUG  
INTERFACE  
ARM  
HIGH-SPEED PHY  
HIGH-SPEED  
CORTEX-M0  
ARM  
CORTEX-M4  
(1)  
ETHERNET  
10/100  
HIGH-SPEED  
(1)  
SD/  
MMC  
USB0  
(1)  
(1)  
LCD  
USB1  
DMA  
MAC  
HOST/  
DEVICE/OTG  
HOST/DEVICE  
IEEE 1588  
masters  
slaves  
BRIDGE  
AHB MULTILAYER MATRIX  
SPI  
SGPIO  
slaves  
128 kB LOCAL SRAM  
BRIDGE  
BRIDGE 0  
BRIDGE 1  
BRIDGE 2  
BRIDGE 3  
BRIDGE  
72 kB LOCAL SRAM  
64 kB ROM  
ALARM TIMER  
2
RI TIMER  
USART2  
USART3  
TIMER2  
TIMER3  
SSP1  
I C1  
CGU  
CCU1  
CCU2  
RGU  
WWDT  
MOTOR  
32 kB AHB SRAM  
CONTROL  
(1)  
BACKUP REGISTERS  
USART0  
10-bit DAC  
C_CAN0  
PWM  
16 +16 kB AHB SRAM  
2
I C0  
POWER MODE CONTROL  
SCT  
UART1  
SSP0  
2
I S0  
10-bit ADC0  
10-bit ADC1  
CONFIGURATION  
EMC  
HS GPIO  
SPIFI  
REGISTERS  
2
I S1  
TIMER0  
EVENT ROUTER  
C_CAN1  
TIMER1  
SCU  
OTP MEMORY  
(1)  
QEI  
RTC  
RTC OSC  
AES ENCRYPTION/  
DECRYPTION  
(2)  
GIMA  
GPIO  
INTERRUPTS  
12 MHz IRC  
GPIO GROUP0  
INTERRUPT  
RTC POWER DOMAIN  
GPIO GROUP1  
INTERRUPT  
= connected to GPDMA  
002aaf772  
(1) Not available on all parts (see Table 2).  
Fig 1. LPC4350/30/20/10 Block diagram  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
6 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
6. Pinning information  
6.1 Pinning  
LPC4350/30FET256  
LPC4350/30FET180  
ball A1  
index area  
ball A1  
index area  
2
4
6
8
10 12 14 16  
11 13 15  
2
4
6
8
10  
12  
14  
1
3
5
7
9
1
3
5
7
9
11  
13  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
002aaf813  
002aag374  
Transparent top view  
Transparent top view  
Fig 2. Pin configuration LBGA256 package  
Fig 3. Pin configuration TFBGA180 package  
ball A1  
index area  
LPC4330/20/10FET100  
1
2
3
4
5
6
7
8
9 10  
A
B
C
D
E
F
109  
144  
72  
G
H
J
LPC4330/20/10FBD144  
K
37  
002aag375  
Transparent top view  
002aag377  
Fig 4. Pin configuration TFBGA100 package  
Fig 5. Pin configuration LQFP144 package  
6.2 Pin description  
On the LPC4350/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA  
to PF, with up to 20 pins used per port. Each digital pin can support up to eight different  
digital functions, including General-Purpose I/O (GPIO), selectable through the System  
Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port  
assigned to it.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
7 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Not all functions listed in Table 3 are available on all packages. See Table 2 for availability  
of USB0, USB1, Ethernet, and LCD functions.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
8 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
Multiplexed digital pins  
[2]  
P0_0  
L3  
K3  
G2 32  
N;  
PU  
I/O GPIO0[0] — General purpose digital input/output pin.  
I/O SSP1_MISO — Master In Slave Out for SSP1.  
I
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).  
I/O SGPIO0 — General purpose digital input/output pin.  
-
-
R — Function reserved.  
R — Function reserved.  
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
[2]  
P0_1  
M2  
K2  
G1 34  
N;  
PU  
I/O GPIO0[1] — General purpose digital input/output pin.  
I/O SSP1_MOSI — Master Out Slave in for SSP1.  
I
ENET_COL — Ethernet Collision detect (MII interface).  
I/O SGPIO1 — General purpose digital input/output pin.  
-
-
R — Function reserved.  
R — Function reserved.  
ENET_TX_EN — Ethernet transmit enable (RMII/MII  
interface).  
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
[2]  
P1_0  
P2  
L1  
H1 38  
N;  
I/O GPIO0[4] — General purpose digital input/output pin.  
PU  
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.  
I/O EMC_A5 — External memory address line 5.  
-
-
R — Function reserved.  
R — Function reserved.  
I/O SSP0_SSEL — Slave Select for SSP0.  
I/O SGPIO7 — General purpose digital input/output pin.  
-
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
9 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
P1_1  
R2  
R3  
P5  
T3  
N1  
N2  
M2  
P2  
K2  
K1  
J1  
J2  
42  
43  
44  
47  
N;  
PU  
I/O GPIO0[8] — General purpose digital input/output pin. Boot pin  
(see Table 5).  
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.  
I/O EMC_A6 — External memory address line 6.  
I/O SGPIO8 — General purpose digital input/output pin.  
-
R — Function reserved.  
I/O SSP0_MISO — Master In Slave Out for SSP0.  
-
-
R — Function reserved.  
R — Function reserved.  
P1_2  
P1_3  
P1_4  
N;  
PU  
I/O GPIO0[9] — General purpose digital input/output pin. Boot pin  
(see Table 5).  
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.  
I/O EMC_A7 — External memory address line 7.  
I/O SGPIO9 — General purpose digital input/output pin.  
-
R — Function reserved.  
I/O SSP0_MOSI — Master Out Slave in for SSP0.  
-
-
R — Function reserved.  
R — Function reserved.  
N;  
PU  
I/O GPIO0[10] — General purpose digital input/output pin.  
CTOUT_8 — SCT output 8. Match output 0 of timer 2.  
I/O SGPIO10 — General purpose digital input/output pin.  
O
O
O
EMC_OE — LOW active Output Enable signal.  
USB0_IND1 — USB0 port indicator LED control  
output 1.  
I/O SSP1_MISO — Master In Slave Out for SSP1.  
-
R — Function reserved.  
O
SD_RST — SD/MMC reset signal for MMC4.4 card.  
N;  
PU  
I/O GPIO0[11] — General purpose digital input/output pin.  
CTOUT_9 — SCT output 9. Match output 3 of timer 3.  
I/O SGPIO11 — General purpose digital input/output pin.  
O
O
O
EMC_BLS0 — LOW active Byte Lane select signal 0.  
USB0_IND0 — USB0 port indicator LED control output 0.  
I/O SSP1_MOSI — Master Out Slave in for SSP1.  
-
R — Function reserved.  
O
SD_VOLT1 — SD/MMC bus voltage select output 1.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
10 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P1_5  
R5  
N3  
J4  
48  
N;  
I/O GPIO1[8] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.  
R — Function reserved.  
O
I
EMC_CS0 — LOW active Chip Select 0 signal.  
USB0_PWR_FAULT — Port power fault signal indicating  
overcurrent condition; this signal monitors over-current on the  
USB bus (external circuitry required to detect over-current  
condition).  
I/O SSP1_SSEL — Slave Select for SSP1.  
I/O SGPIO15 — General purpose digital input/output pin.  
O
SD_POW — SD/MMC power monitor output.  
[2]  
P1_6  
T4  
P3  
K4  
49  
N;  
I/O GPIO1[9] — General purpose digital input/output pin.  
PU  
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.  
R — Function reserved.  
-
O
-
EMC_WE — LOW active Write Enable signal.  
R — Function reserved.  
-
R — Function reserved.  
I/O SGPIO14 — General purpose digital input/output pin.  
I/O SD_CMD — SD/MMC command signal.  
[2]  
P1_7  
T5  
N4  
G4 50  
N;  
I/O GPIO1[0] — General purpose digital input/output pin.  
PU  
I
U1_DSR — Data Set Ready input for UART1.  
O
CTOUT_13 — SCT output 13. Match output 3 of timer 3.  
I/O EMC_D0 — External memory data line 0.  
O
USB0_PPWR — VBUS drive signal (towards external charge  
pump or power management unit); indicates that VBUS must  
be driven (active HIGH).  
Add a pull-down resistor to disable the power switch at reset.  
This signal has opposite polarity compared to the USB_PPWR  
used on other NXP LPC parts.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
11 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P1_8  
R7  
M5  
H5 51  
N;  
I/O GPIO1[1] — General purpose digital input/output pin.  
PU  
O
O
U1_DTR — Data Terminal Ready output for UART1.  
CTOUT_12 — SCT output 12. Match output 3 of  
timer 3.  
I/O EMC_D1 — External memory data line 1.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
SD_VOLT0 — SD/MMC bus voltage select output 0.  
[2]  
[2]  
[2]  
P1_9  
T7  
R8  
T9  
N5  
N6  
P8  
J5  
52  
N;  
PU  
I/O GPIO1[2] — General purpose digital input/output pin.  
O
O
U1_RTS — Request to Send output for UART1.  
CTOUT_11 — SCT output 11. Match output 3 of timer 2.  
I/O EMC_D2 — External memory data line 2.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O SD_DAT0 — SD/MMC data bus line 0.  
P1_10  
H6 53  
N;  
PU  
I/O GPIO1[3] — General purpose digital input/output pin.  
I
U1_RI — Ring Indicator input for UART1.  
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.  
I/O EMC_D3 — External memory data line 3.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O SD_DAT1 — SD/MMC data bus line 1.  
P1_11  
J7  
55  
N;  
I/O GPIO1[4] — General purpose digital input/output pin.  
PU  
I
U1_CTS — Clear to Send input for UART1.  
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.  
I/O EMC_D4 — External memory data line 4.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O SD_DAT2 — SD/MMC data bus line 2.  
LPC4350_30_20_10  
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Product data sheet  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
P1_12  
R9  
P7  
K7  
56  
N;  
PU  
I/O GPIO1[5] — General purpose digital input/output pin.  
I
U1_DCD — Data Carrier Detect input for UART1.  
R — Function reserved.  
-
I/O EMC_D5 — External memory data line 5.  
I
T0_CAP1 — Capture input 1 of timer 0.  
R — Function reserved.  
-
I/O SGPIO8 — General purpose digital input/output pin.  
I/O SD_DAT3 — SD/MMC data bus line 3.  
P1_13  
P1_14  
P1_15  
R10 L8  
H8 60  
N;  
PU  
I/O GPIO1[6] — General purpose digital input/output pin.  
O
-
U1_TXD — Transmitter output for UART1.  
R — Function reserved.  
I/O EMC_D6 — External memory data line 6.  
I
T0_CAP0 — Capture input 0 of timer 0.  
R — Function reserved.  
-
I/O SGPIO9 — General purpose digital input/output pin.  
SD_CD — SD/MMC card detect input.  
I/O GPIO1[7] — General purpose digital input/output pin.  
I
R11 K7  
J8  
61  
N;  
PU  
I
U1_RXD — Receiver input for UART1.  
R — Function reserved.  
-
I/O EMC_D7 — External memory data line 7.  
O
-
T0_MAT2 — Match output 2 of timer 0.  
R — Function reserved.  
I/O SGPIO10 — General purpose digital input/output pin.  
R — Function reserved.  
I/O GPIO0[2] — General purpose digital input/output pin.  
U2_TXD — Transmitter output for USART2.  
I/O SGPIO2 — General purpose digital input/output pin.  
-
T12 P11 K8  
62  
N;  
PU  
O
I
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).  
T0_MAT1 — Match output 1 of timer 0.  
R — Function reserved.  
O
-
-
R — Function reserved.  
-
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
13 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[3]  
[2]  
[2]  
P1_16  
M7  
L5  
H9 64  
N;  
PU  
I/O GPIO0[3] — General purpose digital input/output pin.  
I
U2_RXD — Receiver input for USART2.  
I/O SGPIO3 — General purpose digital input/output pin.  
I
ENET_CRS — Ethernet Carrier Sense (MII interface).  
T0_MAT0 — Match output 0 of timer 0.  
R — Function reserved.  
O
-
-
R — Function reserved.  
I
ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII  
interface).  
P1_17  
P1_18  
P1_19  
M8  
L6  
H10 66  
N;  
PU  
I/O GPIO0[12] — General purpose digital input/output pin.  
I/O U2_UCLK — Serial clock input/output for USART2 in  
synchronous mode.  
-
R — Function reserved.  
I/O ENET_MDIO — Ethernet MIIM data input and output.  
I
T0_CAP3 — Capture input 3 of timer 0.  
CAN1_TD — CAN1 transmitter output.  
O
I/O SGPIO11 — General purpose digital input/output pin.  
R — Function reserved.  
-
N12 N10 J10 67  
N;  
PU  
I/O GPIO0[13] — General purpose digital input/output pin.  
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for  
USART2.  
-
R — Function reserved.  
O
O
I
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).  
T0_MAT3 — Match output 3 of timer 0.  
CAN1_RD — CAN1 receiver input.  
I/O SGPIO12 — General purpose digital input/output pin.  
-
I
R — Function reserved.  
M11 N9  
K9  
68  
N;  
PU  
ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit  
Clock (MII interface) or Ethernet Reference Clock (RMII  
interface).  
I/O SSP1_SCK — Serial clock for SSP1.  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
CLKOUT — Clock output pin.  
R — Function reserved.  
O
I2S0_RX_MCLK — I2S receive master clock.  
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
14 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P1_20  
M10 J10 K10 70  
N;  
PU  
I/O GPIO0[15] — General purpose digital input/output pin.  
I/O SSP1_SSEL — Slave Select for SSP1.  
-
R — Function reserved.  
O
I
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).  
T0_CAP2 — Capture input 2 of timer 0.  
R — Function reserved.  
-
I/O SGPIO13 — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO4 — General purpose digital input/output pin.  
U0_TXD — Transmitter output for USART0.  
I/O EMC_A13 — External memory address line 13.  
-
[2]  
P2_0  
T16 N14 G10 75  
N;  
PU  
O
O
USB0_PPWR — VBUS drive signal (towards external charge  
pump or power management unit); indicates that VBUS must  
be driven (active HIGH).  
Add a pull-down resistor to disable the power switch at reset.  
This signal has opposite polarity compared to the USB_PPWR  
used on other NXP LPC parts.  
I/O GPIO5[0] — General purpose digital input/output pin.  
-
R — Function reserved.  
I
T3_CAP0 — Capture input 0 of timer 3.  
ENET_MDC — Ethernet MIIM clock.  
O
[2]  
P2_1  
N15 M13 G7 81  
N;  
PU  
I/O SGPIO5 — General purpose digital input/output pin.  
U0_RXD — Receiver input for USART0.  
I/O EMC_A12 — External memory address line 12.  
I
I
USB0_PWR_FAULT — Port power fault signal indicating  
overcurrent condition; this signal monitors over-current on the  
USB bus (external circuitry required to detect over-current  
condition).  
I/O GPIO5[1] — General purpose digital input/output pin.  
-
I
R — Function reserved.  
T3_CAP1 — Capture input 1 of timer 3.  
R — Function reserved.  
-
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
15 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P2_2  
M15 L13 F5  
84  
N;  
I/O SGPIO6 — General purpose digital input/output pin.  
PU  
I/O U0_UCLK — Serial clock input/output for USART0 in  
synchronous mode.  
I/O EMC_A11 — External memory address line 11.  
O
USB0_IND1 — USB0 port indicator LED control output 1.  
I/O GPIO5[2] — General purpose digital input/output pin.  
I
I
-
CTIN_6 — SCT input 6. Capture input 1 of timer 3.  
T3_CAP2 — Capture input 2 of timer 3.  
R — Function reserved.  
[3]  
P2_3  
J12 G11 D8 87  
N;  
I/O SGPIO12 — General purpose digital input/output pin.  
PU  
I/O I2C1_SDA — I2C1 data input/output (this pin does not use a  
specialized I2C pad).  
O
I
U3_TXD — Transmitter output for USART3.  
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture  
input 1 of timer 2.  
I/O GPIO5[3] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
O
T3_MAT0 — Match output 0 of timer 3.  
USB0_PPWR — VBUS drive signal (towards external charge  
pump or power management unit); indicates that VBUS must  
be driven (active HIGH).  
Add a pull-down resistor to disable the power switch at reset.  
This signal has opposite polarity compared to the USB_PPWR  
used on other NXP LPC parts.  
[3]  
P2_4  
K11 L9  
D9 88  
N;  
I/O SGPIO13 — General purpose digital input/output pin.  
PU  
I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a  
specialized I2C pad).  
I
I
U3_RXD — Receiver input for USART3.  
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.  
I/O GPIO5[4] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
I
T3_MAT1 — Match output 1 of timer 3.  
USB0_PWR_FAULT — Port power fault signal indicating  
overcurrent condition; this signal monitors over-current on the  
USB bus (external circuitry required to detect over-current  
condition).  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
16 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[3]  
P2_5  
K14 J12 D10 91  
N;  
I/O SGPIO14 — General purpose digital input/output pin.  
PU  
I
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.  
USB1_VBUS — Monitors the presence of USB1 bus power.  
Note: This signal must be HIGH for USB reset to occur.  
ADCTRIG1 — ADC trigger input 1.  
I
I/O GPIO5[5] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
O
T3_MAT2 — Match output 2 of timer 3.  
USB0_IND0 — USB0 port indicator LED control output 0.  
[2]  
P2_6  
K16 J14 G9 95  
N;  
I/O SGPIO7 — General purpose digital input/output pin.  
PU  
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for  
USART0.  
I/O EMC_A10 — External memory address line 10.  
O
USB0_IND0 — USB0 port indicator LED control  
output 0.  
I/O GPIO5[6] — General purpose digital input/output pin.  
I
I
-
CTIN_7 — SCT input 7.  
T3_CAP3 — Capture input 3 of timer 3.  
R — Function reserved.  
[2]  
P2_7  
H14 G12 C10 96  
N;  
PU  
I/O GPIO0[7] — General purpose digital input/output pin. If this pin  
is pulled LOW at reset, the part enters ISP mode using  
USART0.  
O
CTOUT_1 — SCT output 1. Match output 3 of timer 3.  
I/O U3_UCLK — Serial clock input/output for USART3 in  
synchronous mode.  
I/O EMC_A9 — External memory address line 9.  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
T3_MAT3 — Match output 3 of timer 3.  
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
17 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P2_8  
J16 H14 C6 98  
N;  
I/O SGPIO15 — General purpose digital input/output pin. Boot pin  
PU  
(see Table 5).  
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.  
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for  
USART3.  
I/O EMC_A8 — External memory address line 8.  
I/O GPIO5[7] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P2_9  
H16 G14 B10 102  
N;  
I/O GPIO1[10] — General purpose digital input/output pin. Boot  
PU  
pin (see Table 5.  
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.  
I/O U3_BAUD — Baud pin for USART3.  
I/O EMC_A0 — External memory address line 0.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P2_10  
G16 F14 E8  
104  
N;  
I/O GPIO0[14] — General purpose digital input/output pin.  
PU  
O
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.  
U2_TXD — Transmitter output for USART2.  
I/O EMC_A1 — External memory address line 1.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P2_11  
F16 E13 A9  
105  
N;  
I/O GPIO1[11] — General purpose digital input/output pin.  
PU  
O
I
CTOUT_5 — SCT output 5. Match output 3 of timer 3.  
U2_RXD — Receiver input for USART2.  
I/O EMC_A2 — External memory address line 2.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
18 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
P2_12  
E15 D13 B9  
106  
N;  
PU  
I/O GPIO1[12] — General purpose digital input/output pin.  
O
-
CTOUT_4 — SCT output 4. Match output 3 of timer 3.  
R — Function reserved.  
I/O EMC_A3 — External memory address line 3.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O U2_UCLK — Serial clock input/output for USART2 in  
synchronous mode.  
P2_13  
C16 E14 A10 108  
N;  
PU  
I/O GPIO1[13] — General purpose digital input/output pin.  
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.  
R — Function reserved.  
-
I/O EMC_A4 — External memory address line 4.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for  
USART2.  
P3_0  
F13 D12 A8  
112  
N;  
PU  
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
O
I2S0_RX_MCLK — I2S receive master clock.  
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
O
I2S0_TX_MCLK — I2S transmit master clock.  
I/O SSP0_SCK — Serial clock for SSP0.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
19 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[4]  
P3_1  
G11 D10 F7  
114  
N;  
PU  
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I/O I2S0_RX_WS — Receive Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I
CAN0_RD — CAN receiver input.  
O
USB1_IND1 — USB1 Port indicator LED control output 1.  
I/O GPIO5[8] — General purpose digital input/output pin.  
-
R — Function reserved.  
LCD_VD15 — LCD data.  
R — Function reserved.  
O
-
P3_2  
F11 D9  
G6 116  
OL; I/O I2S0_TX_SDA — I2S transmit data. It is driven by the  
PU  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
O
O
CAN0_TD — CAN transmitter output.  
USB1_IND0 — USB1 Port indicator LED control output 0.  
I/O GPIO5[9] — General purpose digital input/output pin.  
-
R — Function reserved.  
LCD_VD14 — LCD data.  
R — Function reserved.  
R — Function reserved.  
O
-
P3_3  
B14 B13 A7  
118  
N;  
-
PU  
I/O SPI_SCK — Serial clock for SPI.  
I/O SSP0_SCK — Serial clock for SSP0.  
O
O
-
SPIFI_SCK — Serial clock for SPIFI.  
CGU_OUT1 — CGU spare clock output 1.  
R — Function reserved.  
O
I2S0_TX_MCLK — I2S transmit master clock.  
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
20 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P3_4  
A15 C14 B8  
119  
N;  
I/O GPIO1[14] — General purpose digital input/output pin.  
PU  
-
-
R — Function reserved.  
R — Function reserved.  
I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.  
U1_TXD — Transmitter output for UART 1.  
O
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
O
LCD_VD13 — LCD data.  
[2]  
P3_5  
C12 C11 B7  
121  
N;  
I/O GPIO1[15] — General purpose digital input/output pin.  
PU  
-
-
R — Function reserved.  
R — Function reserved.  
I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.  
U1_RXD — Receiver input for UART 1.  
I
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
I/O I2S1_RX_WS — Receive Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
O
LCD_VD12 — LCD data.  
[2]  
P3_6  
B13 B12 C7 122  
N;  
PU  
I/O GPIO0[6] — General purpose digital input/output pin.  
I/O SPI_MISO — Master In Slave Out for SPI.  
I/O SSP0_SSEL — Slave Select for SSP0.  
I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.  
-
R — Function reserved.  
I/O SSP0_MISO — Master In Slave Out for SSP0.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P3_7  
C11 C10 D7 123  
N;  
PU  
I/O SPI_MOSI — Master Out Slave In for SPI.  
I/O SSP0_MISO — Master In Slave Out for SSP0.  
I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.  
I/O GPIO5[10] — General purpose digital input/output pin.  
I/O SSP0_MOSI — Master Out Slave in for SSP0.  
-
-
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P3_8  
C10 C9  
E7  
124  
N;  
PU  
-
I
R — Function reserved.  
SPI_SSEL — Slave Select for SPI. Note that this pin in an  
input pin only. The SPI in master mode cannot drive the CS  
input on the slave. Any GPIO pin can be used for SPI chip  
select in master mode.  
I/O SSP0_MOSI — Master Out Slave in for SSP0.  
I/O SPIFI_CS — SPIFI serial flash chip select.  
I/O GPIO5[11] — General purpose digital input/output pin.  
I/O SSP0_SSEL — Slave Select for SSP0.  
-
-
R — Function reserved.  
R — Function reserved.  
[2]  
P4_0  
D5  
D4  
-
1
N;  
I/O GPIO2[0] — General purpose digital input/output pin.  
PU  
O
I
MCOA0 — Motor control PWM channel 0, output A.  
NMI — External interrupt input to NMI.  
R — Function reserved.  
-
-
R — Function reserved.  
O
LCD_VD13 — LCD data.  
I/O U3_UCLK — Serial clock input/output for USART3 in  
synchronous mode.  
-
R — Function reserved.  
[5]  
P4_1  
A1  
D3  
-
3
N;  
I/O GPIO2[1] — General purpose digital input/output pin.  
PU  
O
O
-
CTOUT_1 — SCT output 1. Match output 3 of timer 3.  
LCD_VD0 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
O
O
I
LCD_VD19 — LCD data.  
U3_TXD — Transmitter output for USART3.  
ENET_COL — Ethernet Collision detect (MII interface).  
AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[2]  
P4_2  
D3  
A2  
-
8
N;  
I/O GPIO2[2] — General purpose digital input/output pin.  
PU  
O
O
-
CTOUT_0 — SCT output 0. Match output 0 of timer 0.  
LCD_VD3 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
O
I
LCD_VD12 — LCD data.  
U3_RXD — Receiver input for USART3.  
I/O SGPIO8 — General purpose digital input/output pin.  
LPC4350_30_20_10  
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LPC4350/30/20/10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
P4_3  
C2  
B2  
-
7
N;  
I/O GPIO2[3] — General purpose digital input/output pin.  
PU  
O
O
-
CTOUT_3 — SCT output 3. Match output 3 of timer 0.  
LCD_VD2 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
O
LCD_VD21 — LCD data.  
I/O U3_BAUD — Baud pin for USART3.  
I/O SGPIO9 — General purpose digital input/output pin.  
AI ADC0_0 — DAC output; ADC0 and ADC1, input channel 0.  
Configure the pin as GPIO input and use the ADC function  
select register in the SCU to select the ADC.  
[5]  
P4_4  
B1  
A1  
-
9
N;  
I/O GPIO2[4] — General purpose digital input/output pin.  
PU  
O
O
-
CTOUT_2 — SCT output 2. Match output 2 of timer 0.  
LCD_VD1 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
O
LCD_VD20 — LCD data.  
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for  
USART3.  
I/O SGPIO10 — General purpose digital input/output pin.  
O
DAC — DAC output. Shared between 10-bit ADC0/1 and  
DAC.. Configure the pin as GPIO input and use the analog  
function select register in the SCU to select the DAC.  
[2]  
P4_5  
D2  
C2  
-
10  
N;  
I/O GPIO2[5] — General purpose digital input/output pin.  
PU  
O
O
CTOUT_5 — SCT output 5. Match output 3 of timer 3.  
LCD_FP — Frame pulse (STN). Vertical synchronization pulse  
(TFT).  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O SGPIO11 — General purpose digital input/output pin.  
LPC4350_30_20_10  
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Product data sheet  
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23 of 150  
LPC4350/30/20/10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P4_6  
C1  
B1  
-
11  
N;  
I/O GPIO2[6] — General purpose digital input/output pin.  
PU  
O
O
CTOUT_4 — SCT output 4. Match output 3 of timer 3.  
LCD_ENAB/LCDM — STN AC bias drive or TFT data enable  
input.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
I/O SGPIO12 — General purpose digital input/output pin.  
[2]  
P4_7  
H4  
F4  
-
14  
O;  
PU  
O
I
LCD_DCLK — LCD panel clock.  
GP_CLKIN — General-purpose clock input to the CGU.  
R — Function reserved.  
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
[2]  
P4_8  
E2  
D2  
-
15  
N;  
-
R — Function reserved.  
PU  
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.  
LCD_VD9 — LCD data.  
O
-
R — Function reserved.  
I/O GPIO5[12] — General purpose digital input/output pin.  
O
O
LCD_VD22 — LCD data.  
CAN1_TD — CAN1 transmitter output.  
I/O SGPIO13 — General purpose digital input/output pin.  
[2]  
P4_9  
L2  
J2  
-
33  
N;  
-
R — Function reserved.  
PU  
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.  
LCD_VD11 — LCD data.  
O
-
R — Function reserved.  
I/O GPIO5[13] — General purpose digital input/output pin.  
O
I
LCD_VD15 — LCD data.  
CAN1_RD — CAN1 receiver input.  
I/O SGPIO14 — General purpose digital input/output pin.  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
24 of 150  
LPC4350/30/20/10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
P4_10  
M3  
N3  
P3  
L3  
L2  
M1  
-
-
-
35  
37  
39  
N;  
PU  
-
R — Function reserved.  
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.  
LCD_VD10 — LCD data.  
O
-
R — Function reserved.  
I/O GPIO5[14] — General purpose digital input/output pin.  
O
-
LCD_VD14 — LCD data.  
R — Function reserved.  
I/O SGPIO15 — General purpose digital input/output pin.  
I/O GPIO2[9] — General purpose digital input/output pin.  
P5_0  
N;  
PU  
O
MCOB2 — Motor control PWM channel 2, output B.  
I/O EMC_D12 — External memory data line 12.  
-
I
R — Function reserved.  
U1_DSR — Data Set Ready input for UART 1.  
T1_CAP0 — Capture input 0 of timer 1.  
R — Function reserved.  
I
-
-
R — Function reserved.  
P5_1  
N;  
PU  
I/O GPIO2[10] — General purpose digital input/output pin.  
MCI2 — Motor control PWM channel 2, input.  
I/O EMC_D13 — External memory data line 13.  
I
-
R — Function reserved.  
O
U1_DTR — Data Terminal Ready output for UART 1. Can also  
be configured to be an RS-485/EIA-485 output enable signal  
for UART 1.  
I
T1_CAP1 — Capture input 1 of timer 1.  
R — Function reserved.  
-
-
R — Function reserved.  
[2]  
P5_2  
R4  
M3  
-
46  
N;  
PU  
I/O GPIO2[11] — General purpose digital input/output pin.  
MCI1 — Motor control PWM channel 1, input.  
I/O EMC_D14 — External memory data line 14.  
I
-
R — Function reserved.  
O
U1_RTS — Request to Send output for UART 1. Can also be  
configured to be an RS-485/EIA-485 output enable signal for  
UART 1.  
I
T1_CAP2 — Capture input 2 of timer 1.  
R — Function reserved.  
-
-
R — Function reserved.  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
25 of 150  
LPC4350/30/20/10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
P5_3  
T8  
P6  
-
-
-
-
54  
57  
58  
63  
N;  
PU  
I/O GPIO2[12] — General purpose digital input/output pin.  
I
MCI0 — Motor control PWM channel 0, input.  
I/O EMC_D15 — External memory data line 15.  
-
I
R — Function reserved.  
U1_RI — Ring Indicator input for UART 1.  
T1_CAP3 — Capture input 3 of timer 1.  
R — Function reserved.  
I
-
-
R — Function reserved.  
P5_4  
P5_5  
P5_6  
P9  
N7  
N;  
PU  
I/O GPIO2[13] — General purpose digital input/output pin.  
MCOB0 — Motor control PWM channel 0, output B.  
I/O EMC_D8 — External memory data line 8.  
O
-
R — Function reserved.  
I
U1_CTS — Clear to Send input for UART 1.  
T1_MAT0 — Match output 0 of timer 1.  
R — Function reserved.  
O
-
-
R — Function reserved.  
P10 N8  
N;  
PU  
I/O GPIO2[14] — General purpose digital input/output pin.  
MCOA1 — Motor control PWM channel 1, output A.  
I/O EMC_D9 — External memory data line 9.  
O
-
R — Function reserved.  
I
U1_DCD — Data Carrier Detect input for UART 1.  
T1_MAT1 — Match output 1 of timer 1.  
R — Function reserved.  
O
-
-
R — Function reserved.  
T13 M11  
N;  
PU  
I/O GPIO2[15] — General purpose digital input/output pin.  
MCOB1 — Motor control PWM channel 1, output B.  
I/O EMC_D10 — External memory data line 10.  
O
-
R — Function reserved.  
O
O
-
U1_TXD — Transmitter output for UART 1.  
T1_MAT2 — Match output 2 of timer 1.  
R — Function reserved.  
-
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
26 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P5_7  
R12 N11  
-
65  
N;  
I/O GPIO2[7] — General purpose digital input/output pin.  
PU  
O
MCOA2 — Motor control PWM channel 2, output A.  
I/O EMC_D11 — External memory data line 11.  
-
R — Function reserved.  
I
U1_RXD — Receiver input for UART 1.  
T1_MAT3 — Match output 3 of timer 1.  
R — Function reserved.  
O
-
-
R — Function reserved.  
[2]  
P6_0  
M12 M10 H7 73  
N;  
-
R — Function reserved.  
PU  
O
-
I2S0_RX_MCLK — I2S receive master clock.  
R — Function reserved.  
-
R — Function reserved.  
I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and  
received by the slave. Corresponds to the signal SCK in the  
I2S-bus specification.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P6_1  
R15 P14 G5 74  
N;  
PU  
I/O GPIO3[0] — General purpose digital input/output pin.  
EMC_DYCS1 — SDRAM chip select 1.  
O
I/O U0_UCLK — Serial clock input/output for USART0 in  
synchronous mode.  
I/O I2S0_RX_WS — Receive Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
-
I
R — Function reserved.  
T2_CAP0 — Capture input 2 of timer 2.  
R — Function reserved.  
-
-
R — Function reserved.  
[2]  
P6_2  
L13 K11 J9  
78  
N;  
PU  
I/O GPIO3[1] — General purpose digital input/output pin.  
EMC_CKEOUT1 — SDRAM clock enable 1.  
O
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for  
USART0.  
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
-
I
R — Function reserved.  
T2_CAP1 — Capture input 1 of timer 2.  
R — Function reserved.  
-
-
R — Function reserved.  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
27 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P6_3  
P15 N13  
-
79  
N;  
I/O GPIO3[2] — General purpose digital input/output pin.  
PU  
O
USB0_PPWR — VBUS drive signal (towards external charge  
pump or power management unit); indicates that the VBUS  
signal must be driven (active HIGH).  
Add a pull-down resistor to disable the power switch at reset.  
This signal has opposite polarity compared to the USB_PPWR  
used on other NXP LPC parts.  
I/O SGPIO4 — General purpose digital input/output pin.  
O
-
EMC_CS1 — LOW active Chip Select 1 signal.  
R — Function reserved.  
I
T2_CAP2 — Capture input 2 of timer 2.  
R — Function reserved.  
-
-
R — Function reserved.  
[2]  
P6_4  
R16 M14 F6  
80  
N;  
I/O GPIO3[3] — General purpose digital input/output pin.  
PU  
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.  
U0_TXD — Transmitter output for USART0.  
EMC_CAS — LOW active SDRAM Column Address Strobe.  
R — Function reserved.  
O
O
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
[2]  
P6_5  
P16 L14 F9  
82  
N;  
I/O GPIO3[4] — General purpose digital input/output pin.  
PU  
O
I
CTOUT_6 — SCT output 6. Match output 2 of timer 1.  
U0_RXD — Receiver input for USART0.  
EMC_RAS — LOW active SDRAM Row Address Strobe.  
R — Function reserved.  
O
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
28 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P6_6  
L14 K12  
-
83  
N;  
I/O GPIO0[5] — General purpose digital input/output pin.  
PU  
O
EMC_BLS1 — LOW active Byte Lane select signal 1.  
I/O SGPIO5 — General purpose digital input/output pin.  
I
USB0_PWR_FAULT — Port power fault signal indicating  
overcurrent condition; this signal monitors over-current on the  
USB bus (external circuitry required to detect over-current  
condition).  
-
I
R — Function reserved.  
T2_CAP3 — Capture input 3 of timer 2.  
R — Function reserved.  
-
-
-
R — Function reserved.  
[2]  
[2]  
[2]  
P6_7  
P6_8  
P6_9  
J13 H11  
-
85  
86  
97  
N;  
PU  
R — Function reserved.  
I/O EMC_A15 — External memory address line 15.  
I/O SGPIO6 — General purpose digital input/output pin.  
O
USB0_IND1 — USB0 port indicator LED control output 1.  
I/O GPIO5[15] — General purpose digital input/output pin.  
O
-
T2_MAT0 — Match output 0 of timer 2.  
R — Function reserved.  
-
R — Function reserved.  
H13 F12  
-
N;  
PU  
-
R — Function reserved.  
I/O EMC_A14 — External memory address line 14.  
I/O SGPIO7 — General purpose digital input/output pin.  
O
USB0_IND0 — USB0 port indicator LED control output 0.  
I/O GPIO5[16] — General purpose digital input/output pin.  
O
-
T2_MAT1 — Match output 1 of timer 2.  
R — Function reserved.  
-
R — Function reserved.  
J15 H13 F8  
N;  
I/O GPIO3[5] — General purpose digital input/output pin.  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
EMC_DYCS0 — SDRAM chip select 0.  
R — Function reserved.  
O
-
T2_MAT2 — Match output 2 of timer 2.  
R — Function reserved.  
-
R — Function reserved.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
29 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P6_10  
H15 G13  
-
100  
N;  
I/O GPIO3[6] — General purpose digital input/output pin.  
PU  
O
-
MCABORT — Motor control PWM, LOW-active fast abort.  
R — Function reserved.  
O
EMC_DQMOUT1 — Data mask 1 used with SDRAM and static  
devices.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P6_11  
H12 F11 C9 101  
N;  
I/O GPIO3[7] — General purpose digital input/output pin.  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
EMC_CKEOUT0 — SDRAM clock enable 0.  
R — Function reserved.  
O
-
T2_MAT3 — Match output 3 of timer 2.  
R — Function reserved.  
-
R — Function reserved.  
[2]  
P6_12  
G15 F13  
-
103  
N;  
I/O GPIO2[8] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_7 — SCT output 7. Match output 3 of timer 1.  
R — Function reserved.  
O
EMC_DQMOUT0 — Data mask 0 used with SDRAM and static  
devices.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
P7_0  
B16 B14  
-
110  
N;  
I/O GPIO3[8] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_14 — SCT output 14. Match output 2 of timer 3.  
R — Function reserved.  
O
-
LCD_LE — Line end signal.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
I/O SGPIO4 — General purpose digital input/output pin.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
30 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P7_1  
C14 C13  
A16 A14  
C13 C12  
-
113  
N;  
PU  
I/O GPIO3[9] — General purpose digital input/output pin.  
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.  
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
O
O
-
LCD_VD19 — LCD data.  
LCD_VD7 — LCD data.  
R — Function reserved.  
O
U2_TXD — Transmitter output for USART2.  
I/O SGPIO5 — General purpose digital input/output pin.  
I/O GPIO3[10] — General purpose digital input/output pin.  
[2]  
P7_2  
-
115  
N;  
PU  
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.  
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
O
O
-
LCD_VD18 — LCD data.  
LCD_VD6 — LCD data.  
R — Function reserved.  
I
U2_RXD — Receiver input for USART2.  
I/O SGPIO6 — General purpose digital input/output pin.  
I/O GPIO3[11] — General purpose digital input/output pin.  
[2]  
P7_3  
-
117  
N;  
PU  
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.  
R — Function reserved.  
-
O
O
-
LCD_VD17 — LCD data.  
LCD_VD5 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
[5]  
P7_4  
C8  
C6  
-
132  
N;  
I/O GPIO3[12] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_13 — SCT output 13. Match output 3 of timer 3.  
R — Function reserved.  
O
O
O
-
LCD_VD16 — LCD data.  
LCD_VD4 — LCD data.  
TRACEDATA[0] — Trace data, bit 0.  
R — Function reserved.  
-
R — Function reserved.  
AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
31 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
P7_5  
A7  
A7  
-
133  
N;  
I/O GPIO3[13] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_12 — SCT output 12. Match output 3 of timer 3.  
R — Function reserved.  
O
O
O
-
LCD_VD8 — LCD data.  
LCD_VD23 — LCD data.  
TRACEDATA[1] — Trace data, bit 1.  
R — Function reserved.  
-
R — Function reserved.  
AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[2]  
P7_6  
C7  
F5  
-
134  
N;  
I/O GPIO3[14] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_11 — SCT output 1. Match output 3 of timer 2.  
R — Function reserved.  
O
LCD_LP — Line synchronization pulse (STN). Horizontal  
synchronization pulse (TFT).  
-
R — Function reserved.  
O
-
TRACEDATA[2] — Trace data, bit 2.  
R — Function reserved.  
-
R — Function reserved.  
[5]  
P7_7  
B6  
D5  
-
140  
N;  
I/O GPIO3[15] — General purpose digital input/output pin.  
PU  
O
-
CTOUT_8 — SCT output 8. Match output 0 of timer 2.  
R — Function reserved.  
O
-
LCD_PWR — LCD panel power enable.  
R — Function reserved.  
O
O
TRACEDATA[3] — Trace data, bit 3.  
ENET_MDC — Ethernet MIIM clock.  
I/O SGPIO7 — General purpose digital input/output pin.  
AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
32 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[3]  
P8_0  
E5  
E4  
-
-
N;  
I/O GPIO4[0] — General purpose digital input/output pin.  
PU  
I
USB0_PWR_FAULT — Port power fault signal indicating  
overcurrent condition; this signal monitors over-current on the  
USB bus (external circuitry required to detect over-current  
condition).  
-
I
R — Function reserved.  
MCI2 — Motor control PWM channel 2, input.  
I/O SGPIO8 — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
O
T0_MAT0 — Match output 0 of timer 0.  
[3]  
[3]  
[2]  
P8_1  
P8_2  
P8_3  
H5  
K4  
J3  
G4  
-
-
-
-
-
-
N;  
PU  
I/O GPIO4[1] — General purpose digital input/output pin.  
O
-
USB0_IND1 — USB0 port indicator LED control output 1.  
R — Function reserved.  
I
MCI1 — Motor control PWM channel 1, input.  
I/O SGPIO9 — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
O
T0_MAT1 — Match output 1 of timer 0.  
J4  
N;  
PU  
I/O GPIO4[2] — General purpose digital input/output pin.  
O
-
USB0_IND0 — USB0 port indicator LED control output 0.  
R — Function reserved.  
I
MCI0 — Motor control PWM channel 0, input.  
I/O SGPIO10 — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
O
T0_MAT2 — Match output 2 of timer 0.  
H3  
N;  
PU  
I/O GPIO4[3] — General purpose digital input/output pin.  
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.  
-
R — Function reserved.  
O
O
-
LCD_VD12 — LCD data.  
LCD_VD19 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
O
T0_MAT3 — Match output 3 of timer 0.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
33 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
P8_4  
J2  
J1  
K3  
H2  
H1  
J3  
-
-
-
-
-
-
N;  
PU  
I/O GPIO4[4] — General purpose digital input/output pin.  
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.  
-
R — Function reserved.  
O
O
-
LCD_VD7 — LCD data.  
LCD_VD16 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
I
T0_CAP0 — Capture input 0 of timer 0.  
P8_5  
N;  
PU  
I/O GPIO4[5] — General purpose digital input/output pin.  
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.  
-
R — Function reserved.  
O
O
-
LCD_VD6 — LCD data.  
LCD_VD8 — LCD data.  
R — Function reserved.  
-
R — Function reserved.  
I
T0_CAP1 — Capture input 1 of timer 0.  
P8_6  
N;  
I/O GPIO4[6] — General purpose digital input/output pin.  
PU  
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control  
signal from the PHY.  
-
R — Function reserved.  
LCD_VD5 — LCD data.  
O
O
LCD_LP — Line synchronization pulse (STN). Horizontal  
synchronization pulse (TFT).  
-
-
I
R — Function reserved.  
R — Function reserved.  
T0_CAP2 — Capture input 2 of timer 0.  
[2]  
P8_7  
K1  
J1  
-
-
N;  
I/O GPIO4[7] — General purpose digital input/output pin.  
PU  
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end or  
interrupt transfers to the PHY.  
-
R — Function reserved.  
O
O
-
LCD_VD4 — LCD data.  
LCD_PWR — LCD panel power enable.  
R — Function reserved.  
-
R — Function reserved.  
I
T0_CAP3 — Capture input 3 of timer 0.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
34 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P8_8  
L1  
K1  
-
-
N;  
PU  
-
I
R — Function reserved.  
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock  
generated by the PHY.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
O
CGU_OUT0 — CGU spare clock output 0.  
I2S1_TX_MCLK — I2S1 transmit master clock.  
[2]  
P9_0  
T1  
P1  
-
-
N;  
I/O GPIO4[12] — General purpose digital input/output pin.  
PU  
O
-
MCABORT — Motor control PWM, LOW-active fast abort.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
I
ENET_CRS — Ethernet Carrier Sense (MII interface).  
I/O SGPIO0 — General purpose digital input/output pin.  
I/O SSP0_SSEL — Slave Select for SSP0.  
[2]  
P9_1  
N6  
P4  
-
-
N;  
I/O GPIO4[13] — General purpose digital input/output pin.  
PU  
O
-
MCOA2 — Motor control PWM channel 2, output A.  
R — Function reserved.  
-
R — Function reserved.  
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I
ENET_RX_ER — Ethernet receive error (MII interface).  
I/O SGPIO1 — General purpose digital input/output pin.  
I/O SSP0_MISO — Master In Slave Out for SSP0.  
I/O GPIO4[14] — General purpose digital input/output pin.  
[2]  
P9_2  
N8  
M6  
-
-
N;  
PU  
O
-
MCOB2 — Motor control PWM channel 2, output B.  
R — Function reserved.  
-
R — Function reserved.  
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
I
ENET_RXD3 — Ethernet receive data 3 (MII interface).  
I/O SGPIO2 — General purpose digital input/output pin.  
I/O SSP0_MOSI — Master Out Slave in for SSP0.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
35 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
P9_3  
M6  
P5  
-
-
-
-
N;  
PU  
I/O GPIO4[15] — General purpose digital input/output pin.  
O
O
-
MCOA0 — Motor control PWM channel 0, output A.  
USB1_IND1 — USB1 Port indicator LED control output 1.  
R — Function reserved.  
-
R — Function reserved.  
I
ENET_RXD2 — Ethernet receive data 2 (MII interface).  
I/O SGPIO9 — General purpose digital input/output pin.  
O
-
U3_TXD — Transmitter output for USART3.  
R — Function reserved.  
P9_4  
N10 M8  
-
N;  
PU  
O
O
-
MCOB0 — Motor control PWM channel 0, output B.  
USB1_IND0 — USB1 Port indicator LED control output 0.  
R — Function reserved.  
I/O GPIO5[17] — General purpose digital input/output pin.  
ENET_TXD2 — Ethernet transmit data 2 (MII interface).  
I/O SGPIO4 — General purpose digital input/output pin.  
O
I
U3_RXD — Receiver input for USART3.  
R — Function reserved.  
P9_5  
M9  
L7  
69  
N;  
-
PU  
O
O
MCOA1 — Motor control PWM channel 1, output A.  
USB1_PPWR — VBUS drive signal (towards external charge  
pump or power management unit); indicates that VBUS must  
be driven (active high).  
Add a pull-down resistor to disable the power switch at reset.  
This signal has opposite polarity compared to the USB_PPWR  
used on other NXP LPC parts.  
-
R — Function reserved.  
I/O GPIO5[18] — General purpose digital input/output pin.  
ENET_TXD3 — Ethernet transmit data 3 (MII interface).  
I/O SGPIO3 — General purpose digital input/output pin.  
U0_TXD — Transmitter output for USART0.  
O
O
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
36 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
P9_6  
L11 M9  
-
72  
N;  
I/O GPIO4[11] — General purpose digital input/output pin.  
PU  
O
I
MCOB1 — Motor control PWM channel 1, output B.  
USB1_PWR_FAULT — USB1 Port power fault signal  
indicating over-current condition; this signal monitors  
over-current on the USB1 bus (external circuitry required to  
detect over-current condition).  
-
-
I
R — Function reserved.  
R — Function reserved.  
ENET_COL — Ethernet Collision detect (MII interface).  
I/O SGPIO8 — General purpose digital input/output pin.  
I
U0_RXD — Receiver input for USART0.  
R — Function reserved.  
[2]  
[3]  
[3]  
PA_0  
PA_1  
PA_2  
L12 L10  
J14 H12  
K15 J13  
-
-
-
-
-
-
N;  
PU  
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
O
-
I2S1_RX_MCLK — I2S1 receive master clock.  
CGU_OUT1 — CGU spare clock output 1.  
R — Function reserved.  
N;  
PU  
I/O GPIO4[8] — General purpose digital input/output pin.  
I
QEI_IDX — Quadrature Encoder Interface INDEX input.  
R — Function reserved.  
-
O
-
U2_TXD — Transmitter output for USART2.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
N;  
I/O GPIO4[9] — General purpose digital input/output pin.  
PU  
I
QEI_PHB — Quadrature Encoder Interface PHB input.  
R — Function reserved.  
-
I
U2_RXD — Receiver input for USART2.  
R — Function reserved.  
-
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
37 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[3]  
[2]  
[2]  
[2]  
PA_3  
H11 E10  
G13 E12  
B15 D14  
A14 A13  
-
-
-
-
-
-
-
-
N;  
PU  
I/O GPIO4[10] — General purpose digital input/output pin.  
I
QEI_PHA — Quadrature Encoder Interface PHA input.  
R — Function reserved.  
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
PA_4  
PB_0  
PB_1  
N;  
PU  
-
R — Function reserved.  
O
-
CTOUT_9 — SCT output 9. Match output 3 of timer 3.  
R — Function reserved.  
I/O EMC_A23 — External memory address line 23.  
I/O GPIO5[19] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
N;  
PU  
-
R — Function reserved.  
O
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.  
LCD_VD23 — LCD data.  
R — Function reserved.  
I/O GPIO5[20] — General purpose digital input/output pin.  
-
-
-
-
I
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
N;  
PU  
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP  
data line direction.  
O
-
LCD_VD22 — LCD data.  
R — Function reserved.  
I/O GPIO5[21] — General purpose digital input/output pin.  
O
-
CTOUT_6 — SCT output 6. Match output 2 of timer 1.  
R — Function reserved.  
-
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
38 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
PB_2  
B12 B11  
A13 A12  
B11 B10  
A12 A11  
-
-
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.  
O
-
LCD_VD21 — LCD data.  
R — Function reserved.  
I/O GPIO5[22] — General purpose digital input/output pin.  
O
-
CTOUT_7 — SCT output 7. Match output 3 of timer 1.  
R — Function reserved.  
-
R — Function reserved.  
PB_3  
PB_4  
PB_5  
N;  
PU  
-
R — Function reserved.  
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.  
O
-
LCD_VD20 — LCD data.  
R — Function reserved.  
I/O GPIO5[23] — General purpose digital input/output pin.  
O
-
CTOUT_8 — SCT output 8. Match output 0 of timer 2.  
R — Function reserved.  
-
R — Function reserved.  
N;  
PU  
-
R — Function reserved.  
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.  
O
-
LCD_VD15 — LCD data.  
R — Function reserved.  
I/O GPIO5[24] — General purpose digital input/output pin.  
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.  
R — Function reserved.  
-
-
-
R — Function reserved.  
N;  
R — Function reserved.  
PU  
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.  
O
-
LCD_VD14 — LCD data.  
R — Function reserved.  
I/O GPIO5[25] — General purpose digital input/output pin.  
I
CTIN_7 — SCT input 7.  
O
-
LCD_PWR — LCD panel power enable.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
39 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
PB_6  
A6  
C5  
-
-
N;  
-
R — Function reserved.  
PU  
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.  
O
-
LCD_VD13 — LCD data.  
R — Function reserved.  
I/O GPIO5[26] — General purpose digital input/output pin.  
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.  
LCD_VD19 — LCD data.  
O
-
R — Function reserved.  
AI ADC0_6 — ADC0 and ADC1, input channel 6. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[5]  
PC_0  
D4  
-
-
-
N;  
PU  
-
I
R — Function reserved.  
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock  
generated by the PHY.  
-
R — Function reserved.  
I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).  
O
-
LCD_DCLK — LCD panel clock.  
R — Function reserved.  
-
R — Function reserved.  
I/O SD_CLK — SD/MMC card clock.  
AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the  
pin as input (USB_ULPI_CLK) and use the ADC function select  
register in the SCU to select the ADC.  
[2]  
PC_1  
E4  
-
-
-
N;  
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.  
PU  
-
R — Function reserved.  
I
U1_RI — Ring Indicator input for UART 1.  
ENET_MDC — Ethernet MIIM clock.  
O
I/O GPIO6[0] — General purpose digital input/output pin.  
-
R — Function reserved.  
I
T3_CAP0 — Capture input 0 of timer 3.  
SD_VOLT0 — SD/MMC bus voltage select output 0.  
O
[2]  
PC_2  
F6  
-
-
-
N;  
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.  
PU  
-
R — Function reserved.  
I
U1_CTS — Clear to Send input for UART 1.  
ENET_TXD2 — Ethernet transmit data 2 (MII interface).  
O
I/O GPIO6[1] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
O
SD_RST — SD/MMC reset signal for MMC4.4 card.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
40 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
PC_3  
F5  
-
-
-
N;  
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.  
PU  
-
R — Function reserved.  
O
U1_RTS — Request to Send output for UART 1. Can also be  
configured to be an RS-485/EIA-485 output enable signal for  
UART 1.  
O
ENET_TXD3 — Ethernet transmit data 3 (MII interface).  
I/O GPIO6[2] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
O
SD_VOLT1 — SD/MMC bus voltage select output 1.  
AI ADC1_0 — DAC output; ADC1 and ADC0, input channel 0.  
Configure the pin as GPIO input and use the ADC function  
select register in the SCU to select the ADC.  
[2]  
PC_4  
F4  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.  
-
R — Function reserved.  
ENET_TX_EN — Ethernet transmit enable (RMII/MII  
interface).  
I/O GPIO6[3] — General purpose digital input/output pin.  
-
I
R — Function reserved.  
T3_CAP1 — Capture input 1 of timer 3.  
I/O SD_DAT0 — SD/MMC data bus line 0.  
R — Function reserved.  
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.  
[2]  
PC_5  
G4  
-
-
-
N;  
PU  
-
-
R — Function reserved.  
O
ENET_TX_ER — Ethernet Transmit Error (MII interface).  
I/O GPIO6[4] — General purpose digital input/output pin.  
-
I
R — Function reserved.  
T3_CAP2 — Capture input 2 of timer 3.  
I/O SD_DAT1 — SD/MMC data bus line 1.  
R — Function reserved.  
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.  
[2]  
PC_6  
H6  
-
-
-
N;  
PU  
-
-
I
R — Function reserved.  
ENET_RXD2 — Ethernet receive data 2 (MII interface).  
I/O GPIO6[5] — General purpose digital input/output pin.  
-
I
R — Function reserved.  
T3_CAP3 — Capture input 3 of timer 3.  
I/O SD_DAT2 — SD/MMC data bus line 2.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
41 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PC_7  
G5  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.  
-
I
R — Function reserved.  
ENET_RXD3 — Ethernet receive data 3 (MII interface).  
I/O GPIO6[6] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
T3_MAT0 — Match output 0 of timer 3.  
I/O SD_DAT3 — SD/MMC data bus line 3.  
R — Function reserved.  
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.  
[2]  
PC_8  
PC_9  
PC_10  
N4  
-
-
-
N;  
PU  
-
-
I
R — Function reserved.  
ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII  
interface).  
I/O GPIO6[7] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
I
T3_MAT1 — Match output 1 of timer 3.  
SD_CD — SD/MMC card detect input.  
R — Function reserved.  
[2]  
K2  
-
-
-
N;  
PU  
-
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control  
signal from the PHY.  
-
I
R — Function reserved.  
ENET_RX_ER — Ethernet receive error (MII interface).  
I/O GPIO6[8] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
O
-
T3_MAT2 — Match output 2 of timer 3.  
SD_POW — SD/MMC power monitor output.  
R — Function reserved.  
[2]  
M5  
-
-
-
N;  
PU  
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end or  
interrupt transfers to the PHY.  
I
U1_DSR — Data Set Ready input for UART 1.  
R — Function reserved.  
-
I/O GPIO6[9] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
T3_MAT3 — Match output 3 of timer 3.  
I/O SD_CMD — SD/MMC command signal.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
42 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PC_11  
L5  
-
-
-
N;  
PU  
-
I
R — Function reserved.  
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI  
data line direction.  
I
U1_DCD — Data Carrier Detect input for UART 1.  
R — Function reserved.  
-
I/O GPIO6[10] — General purpose digital input/output pin.  
-
-
R — Function reserved.  
R — Function reserved.  
I/O SD_DAT4 — SD/MMC data bus line 4.  
[2]  
PC_12  
L6  
-
-
-
N;  
PU  
-
R — Function reserved.  
R — Function reserved.  
-
O
U1_DTR — Data Terminal Ready output for UART 1. Can also  
be configured to be an RS-485/EIA-485 output enable signal  
for UART 1.  
-
R — Function reserved.  
I/O GPIO6[11] — General purpose digital input/output pin.  
I/O SGPIO11 — General purpose digital input/output pin.  
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
I/O SD_DAT5 — SD/MMC data bus line 5.  
[2]  
PC_13  
M1  
-
-
-
N;  
-
R — Function reserved.  
PU  
-
R — Function reserved.  
O
-
U1_TXD — Transmitter output for UART 1.  
R — Function reserved.  
I/O GPIO6[12] — General purpose digital input/output pin.  
I/O SGPIO12 — General purpose digital input/output pin.  
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
I/O SD_DAT6 — SD/MMC data bus line 6.  
[2]  
PC_14  
N1  
-
-
-
N;  
PU  
-
-
I
R — Function reserved.  
R — Function reserved.  
U1_RXD — Receiver input for UART 1.  
R — Function reserved.  
-
I/O GPIO6[13] — General purpose digital input/output pin.  
I/O SGPIO13 — General purpose digital input/output pin.  
O
ENET_TX_ER — Ethernet Transmit Error (MII interface).  
I/O SD_DAT7 — SD/MMC data bus line 7.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
43 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PD_0  
N2  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.  
EMC_DQMOUT2 — Data mask 2 used with SDRAM and static  
devices.  
-
R — Function reserved.  
I/O GPIO6[14] — General purpose digital input/output pin.  
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO4 — General purpose digital input/output pin.  
[2]  
[2]  
[2]  
PD_1  
PD_2  
PD_3  
P1  
R1  
P4  
-
-
-
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
EMC_CKEOUT2 — SDRAM clock enable 2.  
R — Function reserved.  
I/O GPIO6[15] — General purpose digital input/output pin.  
O
-
SD_POW — SD/MMC power monitor output.  
R — Function reserved.  
I/O SGPIO5 — General purpose digital input/output pin.  
N;  
PU  
-
R — Function reserved.  
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.  
I/O EMC_D16 — External memory data line 16.  
R — Function reserved.  
I/O GPIO6[16] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO6 — General purpose digital input/output pin.  
N;  
-
R — Function reserved.  
PU  
O
CTOUT_6 — SCT output 7. Match output 2 of timer 1.  
I/O EMC_D17 — External memory data line 17.  
R — Function reserved.  
I/O GPIO6[17] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO7 — General purpose digital input/output pin.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
44 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
PD_4  
T2  
P6  
R6  
T6  
-
-
-
-
-
-
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.  
I/O EMC_D18 — External memory data line 18.  
R — Function reserved.  
I/O GPIO6[18] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO8 — General purpose digital input/output pin.  
PD_5  
PD_6  
PD_7  
N;  
PU  
-
R — Function reserved.  
O
CTOUT_9 — SCT output 9. Match output 3 of timer 3.  
I/O EMC_D19 — External memory data line 19.  
R — Function reserved.  
I/O GPIO6[19] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO9 — General purpose digital input/output pin.  
N;  
PU  
-
R — Function reserved.  
O
CTOUT_10 — SCT output 10. Match output 3 of timer 3.  
I/O EMC_D20 — External memory data line 20.  
R — Function reserved.  
I/O GPIO6[20] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO10 — General purpose digital input/output pin.  
N;  
PU  
-
I
R — Function reserved.  
CTIN_5 — SCT input 5. Capture input 2 of timer 2.  
I/O EMC_D21 — External memory data line 21.  
R — Function reserved.  
I/O GPIO6[21] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO11 — General purpose digital input/output pin.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
45 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
PD_8  
P8  
-
-
-
-
-
-
-
-
-
N;  
PU  
-
I
R — Function reserved.  
CTIN_6 — SCT input 6. Capture input 1 of timer 3.  
I/O EMC_D22 — External memory data line 22.  
R — Function reserved.  
I/O GPIO6[22] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO12 — General purpose digital input/output pin.  
PD_9  
T11  
N;  
PU  
-
R — Function reserved.  
O
CTOUT_13 — SCT output 13. Match output 3 of timer 3.  
I/O EMC_D23 — External memory data line 23.  
R — Function reserved.  
I/O GPIO6[23] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
I/O SGPIO13 — General purpose digital input/output pin.  
PD_10  
P11  
N;  
PU  
-
I
R — Function reserved.  
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture  
input 1 of timer 2.  
O
-
EMC_BLS3 — LOW active Byte Lane select signal 3.  
R — Function reserved.  
I/O GPIO6[24] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
[2]  
PD_11  
N9  
M7  
-
-
N;  
-
R — Function reserved.  
PU  
-
R — Function reserved.  
O
-
EMC_CS3 — LOW active Chip Select 3 signal.  
R — Function reserved.  
I/O GPIO6[25] — General purpose digital input/output pin.  
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.  
O
-
CTOUT_14 — SCT output 14. Match output 2 of timer 3.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
46 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
PD_12  
N11 P9  
-
-
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
EMC_CS2 — LOW active Chip Select 2 signal.  
R — Function reserved.  
I/O GPIO6[26] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.  
R — Function reserved.  
PD_13  
PD_14  
PD_15  
T14  
-
N;  
PU  
-
R — Function reserved.  
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.  
EMC_BLS2 — LOW active Byte Lane select signal 2.  
R — Function reserved.  
O
-
I/O GPIO6[27] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
-
CTOUT_13 — SCT output 13. Match output 3 of timer 3.  
R — Function reserved.  
R13 L11  
N;  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
EMC_DYCS2 — SDRAM chip select 2.  
R — Function reserved.  
I/O GPIO6[28] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
-
CTOUT_11 — SCT output 11. Match output 3 of timer 2.  
R — Function reserved.  
T15 P13  
N;  
-
R — Function reserved.  
PU  
-
R — Function reserved.  
I/O EMC_A17 — External memory address line 17.  
R — Function reserved.  
I/O GPIO6[29] — General purpose digital input/output pin.  
-
I
SD_WP — SD/MMC card write protect input.  
CTOUT_8 — SCT output 8. Match output 0 of timer 2.  
R — Function reserved.  
O
-
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
47 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
PD_16  
R14 P12  
P14 N12  
N14 M12  
M14 L12  
-
-
-
-
-
-
-
-
N;  
PU  
-
-
R — Function reserved.  
R — Function reserved.  
I/O EMC_A16 — External memory address line 16.  
R — Function reserved.  
I/O GPIO6[30] — General purpose digital input/output pin.  
-
O
O
-
SD_VOLT2 — SD/MMC bus voltage select output 2.  
CTOUT_12 — SCT output 12. Match output 3 of timer 3.  
R — Function reserved.  
PE_0  
PE_1  
PE_2  
N;  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
I/O EMC_A18 — External memory address line 18.  
I/O GPIO7[0] — General purpose digital input/output pin.  
O
-
CAN1_TD — CAN1 transmitter output.  
R — Function reserved.  
-
R — Function reserved.  
N;  
PU  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
I/O EMC_A19 — External memory address line 19.  
I/O GPIO7[1] — General purpose digital input/output pin.  
I
-
-
I
I
-
CAN1_RD — CAN1 receiver input.  
R — Function reserved.  
R — Function reserved.  
N;  
PU  
ADCTRIG0 — ADC trigger input 0.  
CAN0_RD — CAN receiver input.  
R — Function reserved.  
I/O EMC_A20 — External memory address line 20.  
I/O GPIO7[2] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
48 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
PE_3  
K12 K10  
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
O
I
CAN0_TD — CAN transmitter output.  
ADCTRIG1 — ADC trigger input 1.  
I/O EMC_A21 — External memory address line 21.  
I/O GPIO7[3] — General purpose digital input/output pin.  
-
-
-
-
I
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
PE_4  
K13 J11  
N;  
PU  
R — Function reserved.  
NMI — External interrupt input to NMI.  
R — Function reserved.  
-
I/O EMC_A22 — External memory address line 22.  
I/O GPIO7[4] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
PE_5  
N16  
-
N;  
-
R — Function reserved.  
PU  
O
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.  
U1_RTS — Request to Send output for UART 1. Can also be  
configured to be an RS-485/EIA-485 output enable signal for  
UART 1.  
I/O EMC_D24 — External memory data line 24.  
I/O GPIO7[5] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
[2]  
PE_6  
M16  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
I
CTOUT_2 — SCT output 2. Match output 2 of timer 0.  
U1_RI — Ring Indicator input for UART 1.  
I/O EMC_D25 — External memory data line 25.  
I/O GPIO7[6] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
49 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
[2]  
[2]  
[2]  
PE_7  
F15  
F14  
E16  
E14  
-
-
-
-
-
-
-
-
-
-
-
-
N;  
PU  
-
R — Function reserved.  
O
I
CTOUT_5 — SCT output 5. Match output 3 of timer 3.  
U1_CTS — Clear to Send input for UART1.  
I/O EMC_D26 — External memory data line 26.  
I/O GPIO7[7] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
PE_8  
PE_9  
PE_10  
N;  
PU  
-
R — Function reserved.  
O
I
CTOUT_4 — SCT output 4. Match output 3 of timer 3.  
U1_DSR — Data Set Ready input for UART 1.  
I/O EMC_D27 — External memory data line 27.  
I/O GPIO7[8] — General purpose digital input/output pin.  
-
-
-
-
I
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
N;  
PU  
R — Function reserved.  
CTIN_4 — SCT input 4. Capture input 2 of timer 1.  
U1_DCD — Data Carrier Detect input for UART 1.  
I
I/O EMC_D28 — External memory data line 28.  
I/O GPIO7[9] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
N;  
-
R — Function reserved.  
PU  
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.  
O
U1_DTR — Data Terminal Ready output for UART 1. Can also  
be configured to be an RS-485/EIA-485 output enable signal  
for UART 1.  
I/O EMC_D29 — External memory data line 29.  
I/O GPIO7[10] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
50 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PE_11  
D16  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
O
CTOUT_12 — SCT output 12. Match output 3 of timer 3.  
U1_TXD — Transmitter output for UART 1.  
I/O EMC_D30 — External memory data line 30.  
I/O GPIO7[11] — General purpose digital input/output pin.  
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
-
-
[2]  
PE_12  
D15  
-
-
-
N;  
-
PU  
O
CTOUT_11 — SCT output 11. Match output 3 of  
timer 2.  
I
U1_RXD — Receiver input for UART 1.  
I/O EMC_D31 — External memory data line 31.  
I/O GPIO7[12] — General purpose digital input/output pin.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
[2]  
PE_13  
G14  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.  
I/O I2C1_SDA — I2C1 data input/output (this pin does not use a  
specialized I2C pad).  
O
EMC_DQMOUT3 — Data mask 3 used with SDRAM and static  
devices.  
I/O GPIO7[13] — General purpose digital input/output pin.  
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
EMC_DYCS3 — SDRAM chip select 3.  
-
-
[2]  
PE_14  
C15  
-
-
-
N;  
-
PU  
-
-
O
I/O GPIO7[14] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
51 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PE_15  
E13  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.  
I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a  
specialized I2C pad).  
O
EMC_CKEOUT3 — SDRAM clock enable 3.  
I/O GPIO7[15] — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
R — Function reserved.  
R — Function reserved.  
[2]  
[2]  
[2]  
PF_0  
PF_1  
PF_2  
D12  
E11  
D11  
-
-
-
-
-
-
-
-
-
O;  
PU  
I/O SSP0_SCK — Serial clock for SSP0.  
I
GP_CLKIN — General-purpose clock input to the CGU.  
R — Function reserved.  
-
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
I2S1_TX_MCLK — I2S1 transmit master clock.  
R — Function reserved.  
N;  
PU  
-
R — Function reserved.  
I/O SSP0_SSEL — Slave Select for SSP0.  
R — Function reserved.  
I/O GPIO7[16] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO0 — General purpose digital input/output pin.  
-
-
-
R — Function reserved.  
N;  
-
R — Function reserved.  
PU  
O
U3_TXD — Transmitter output for USART3.  
I/O SSP0_MISO — Master In Slave Out for SSP0.  
R — Function reserved.  
I/O GPIO7[17] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO1 — General purpose digital input/output pin.  
R — Function reserved.  
-
-
-
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
52 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[2]  
PF_3  
E10  
-
-
-
N;  
PU  
-
I
R — Function reserved.  
U3_RXD — Receiver input for USART3.  
I/O SSP0_MOSI — Master Out Slave in for SSP0.  
R — Function reserved.  
I/O GPIO7[18] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO2 — General purpose digital input/output pin.  
R — Function reserved.  
I/O SSP1_SCK — Serial clock for SSP1.  
-
-
-
[2]  
PF_4  
D10 D6  
H4 120  
O;  
PU  
I
GP_CLKIN — General-purpose clock input to the CGU.  
TRACECLK — Trace clock.  
O
-
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
I2S0_TX_MCLK — I2S transmit master clock.  
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master  
and received by the slave. Corresponds to the signal SCK in  
the I2S-bus specification.  
[5]  
PF_5  
E9  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O U3_UCLK — Serial clock input/output for USART3 in  
synchronous mode.  
I/O SSP1_SSEL — Slave Select for SSP1.  
O
TRACEDATA[0] — Trace data, bit 0.  
I/O GPIO7[19] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO4 — General purpose digital input/output pin.  
R — Function reserved.  
-
-
AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
LPC4350_30_20_10  
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© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
53 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
PF_6  
E7  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for  
USART3.  
I/O SSP1_MISO — Master In Slave Out for SSP1.  
O
TRACEDATA[1] — Trace data, bit 1.  
I/O GPIO7[20] — General purpose digital input/output pin.  
R — Function reserved.  
-
I/O SGPIO5 — General purpose digital input/output pin.  
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the  
transmitter and read by the receiver. Corresponds to the signal  
SD in the I2S-bus specification.  
AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[5]  
PF_7  
B7  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O U3_BAUD — Baud pin for USART3.  
I/O SSP1_MOSI — Master Out Slave in for SSP1.  
O
TRACEDATA[2] — Trace data, bit 2.  
I/O GPIO7[21] — General purpose digital input/output pin.  
R — Function reserved.  
-
I/O SGPIO6 — General purpose digital input/output pin.  
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the  
master and received by the slave. Corresponds to the signal  
WS in the I2S-bus specification.  
AI/ ADC1_7 — ADC1 and ADC0, input channel 7 or band gap  
O
output. Configure the pin as GPIO input and use the ADC  
function select register in the SCU to select the ADC.  
[5]  
PF_8  
E6  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O U0_UCLK — Serial clock input/output for USART0 in  
synchronous mode.  
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.  
TRACEDATA[3] — Trace data, bit 3.  
O
I/O GPIO7[22] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO7 — General purpose digital input/output pin.  
R — Function reserved.  
-
-
AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
54 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[5]  
PF_9  
D6  
-
-
-
N;  
-
R — Function reserved.  
PU  
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for  
USART0.  
O
-
CTOUT_1 — SCT output 1. Match output 3 of timer 3.  
R — Function reserved.  
I/O GPIO7[23] — General purpose digital input/output pin.  
R — Function reserved.  
I/O SGPIO3 — General purpose digital input/output pin.  
R — Function reserved.  
-
-
AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[5]  
PF_10  
A3  
-
-
-
N;  
-
R — Function reserved.  
PU  
O
-
U0_TXD — Transmitter output for USART0.  
R — Function reserved.  
-
R — Function reserved.  
I/O GPIO7[24] — General purpose digital input/output pin.  
-
I
R — Function reserved.  
SD_WP — SD/MMC card write protect input.  
R — Function reserved.  
-
AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
[5]  
PF_11  
A2  
-
-
-
N;  
PU  
-
I
R — Function reserved.  
U0_RXD — Receiver input for USART0.  
R — Function reserved.  
-
-
R — Function reserved.  
I/O GPIO7[25] — General purpose digital input/output pin.  
-
R — Function reserved.  
O
-
SD_VOLT2 — SD/MMC bus voltage select output 2.  
R — Function reserved.  
AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the  
pin as GPIO input and use the ADC function select register in  
the SCU to select the ADC.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
55 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
Clock pins  
[4]  
CLK0  
N5  
M4  
K3  
45  
O;  
PU  
O
O
-
EMC_CLK0 — SDRAM clock 0.  
CLKOUT — Clock output pin.  
R — Function reserved.  
-
R — Function reserved.  
I/O SD_CLK — SD/MMC card clock.  
EMC_CLK01 — SDRAM clock 0 and clock 1 combined.  
I/O SSP1_SCK — Serial clock for SSP1.  
O
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit  
Clock (MII interface) or Ethernet Reference Clock (RMII  
interface).  
[4]  
CLK1  
T10  
-
-
-
O;  
PU  
O
O
-
EMC_CLK1 — SDRAM clock 1.  
CLKOUT — Clock output pin.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
CGU_OUT0 — CGU spare clock output 0.  
R — Function reserved.  
O
O
O
-
I2S1_TX_MCLK — I2S1 transmit master clock.  
EMC_CLK3 — SDRAM clock 3.  
CLKOUT — Clock output pin.  
R — Function reserved.  
[4]  
CLK2  
D14 P10 K6  
99  
O;  
PU  
-
R — Function reserved.  
I/O SD_CLK — SD/MMC card clock.  
O
O
EMC_CLK23 — SDRAM clock 2 and clock 3 combined.  
I2S0_TX_MCLK — I2S transmit master clock.  
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and  
received by the slave. Corresponds to the signal SCK in the  
I2S-bus specification.  
[4]  
CLK3  
P12  
-
-
-
O;  
PU  
O
O
-
EMC_CLK2 — SDRAM clock 2.  
CLKOUT — Clock output pin.  
R — Function reserved.  
-
R — Function reserved.  
-
R — Function reserved.  
O
-
CGU_OUT1 — CGU spare clock output 1.  
R — Function reserved.  
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and  
received by the slave. Corresponds to the signal SCK in the  
I2S-bus specification.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
56 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
Debug pins  
[2]  
[2]  
DBGEN  
L4  
K4  
G5  
A6  
28  
I
I
I
JTAG interface control signal. Also used for boundary scan.  
TCK/SWDCLK J5  
H2 27  
I; F  
Test Clock for JTAG interface (default) or Serial Wire (SW)  
clock.  
[2]  
[2]  
TRST  
M4  
K6  
L4  
K5  
B4  
29  
I; PU I  
I; PU I  
Test Reset for JTAG interface.  
TMS/SWDIO  
C4 30  
Test Mode Select for JTAG interface (default) or SW debug  
data input/output.  
[2]  
[2]  
TDO/SWO  
TDI  
K5  
J4  
J5  
H3 31  
G3 26  
O
O
Test Data Out for JTAG interface (default) or SW trace output.  
Test Data In for JTAG interface.  
H4  
I; PU I  
USB0 pins  
USB0_DP  
USB0_DM  
USB0_VBUS  
[6]  
[6]  
F2  
G2  
F1  
E2  
F2  
E1  
E1  
E2  
E3  
18  
20  
21  
-
-
-
I/O USB0 bidirectional D+ line.  
I/O USB0 bidirectional Dline.  
[6]  
[7]  
I/O VBUS pin (power on USB cable). This pin includes an internal  
pull-down resistor of 64 kΩ (typical) 16 kΩ.  
[8]  
USB0_ID  
H2  
H1  
G2  
G1  
F1  
F3  
22  
24  
-
-
I
Indicates to the transceiver whether connected as an A-device  
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this  
pin has an internal pull-up resistor.  
[8]  
USB0_RREF  
12.0 kΩ (accuracy 1 %) on-board resistor to ground for current  
reference.  
USB1 pins  
USB1_DP  
USB1_DM  
I2C-bus pins  
I2C0_SCL  
[9]  
[9]  
F12 D11 E9  
89  
-
-
I/O USB1 bidirectional D+ line.  
G12 E11 E10 90  
I/O USB1 bidirectional Dline.  
[10]  
[10]  
L15 K13 D6 92  
I; F I/O I2C clock input/output. Open-drain output (for I2C-bus  
compliance).  
I; F I/O I2C data input/output. Open-drain output (for I2C-bus  
compliance).  
I2C0_SDA  
L16 K14 E6  
93  
Reset and wake-up pins  
[11]  
RESET  
D9  
C7  
B6  
128  
I; IA  
I
External reset input: A LOW-going pulse as short as 50 ns on  
this pin resets the device, causing I/O ports and peripherals to  
take on their default states, and processor execution to begin  
at address 0.  
[11]  
[11]  
[11]  
WAKEUP0  
WAKEUP1  
WAKEUP2  
A9  
A9  
A4  
130  
I; IA  
I; IA  
I; IA  
I
I
I
External wake-up input; can raise an interrupt and can cause  
wake-up from any of the low-power modes. A pulse with a  
duration > 45 ns wakes up the part.  
A10 C8  
-
-
-
-
External wake-up input; can raise an interrupt and can cause  
wake-up from any of the low-power modes. A pulse with a  
duration > 45 ns wakes up the part.  
C9  
E5  
External wake-up input; can raise an interrupt and can cause  
wake-up from any of the low-power modes. A pulse with a  
duration > 45 ns wakes up the part.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
57 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
[11]  
WAKEUP3  
D8  
-
-
-
I; IA  
I
External wake-up input; can raise an interrupt and can cause  
wake-up from any of the low-power modes. A pulse with a  
duration > 45 ns wakes up the part.  
ADC pins  
[8]  
[8]  
[8]  
[8]  
[8]  
[8]  
[8]  
[8]  
ADC0_0/  
ADC1_0/DAC  
E3  
C3  
A4  
B5  
C6  
B3  
A5  
C5  
B6  
C4  
B3  
B4  
A5  
C3  
A4  
B5  
A2  
A1  
B3  
A3  
-
6
I; IA  
I; IA  
I; IA  
I; IA  
I; IA  
I; IA  
I; IA  
I; IA  
I
I
I
I
I
I
I
I
ADC input channel 0. Shared between 10-bit ADC0/1 and  
DAC.  
ADC0_1/  
ADC1_1  
2
ADC input channel 1. Shared between 10-bit ADC0/1.  
ADC input channel 2. Shared between 10-bit ADC0/1.  
ADC input channel 3. Shared between 10-bit ADC0/1.  
ADC input channel 4. Shared between 10-bit ADC0/1.  
ADC input channel 5. Shared between 10-bit ADC0/1.  
ADC input channel 6. Shared between 10-bit ADC0/1.  
ADC input channel 7. Shared between 10-bit ADC0/1.  
ADC0_2/  
ADC1_2  
143  
139  
138  
144  
142  
136  
ADC0_3/  
ADC1_3  
ADC0_4/  
ADC1_4  
ADC0_5/  
ADC1_5  
-
ADC0_6/  
ADC1_6  
-
ADC0_7/  
ADC1_7  
-
RTC  
[11]  
[8]  
RTC_ALARM  
RTCX1  
A11 A10 C3 129  
-
-
-
O
I
RTC controlled output.  
A8  
B8  
A8  
B7  
A5  
B5  
125  
126  
Input to the RTC 32 kHz ultra-low power oscillator circuit.  
Output from the RTC 32 kHz ultra-low power oscillator circuit.  
[8]  
RTCX2  
O
Crystal oscillator pins  
[8]  
[8]  
XTAL1  
D1  
C1  
D1  
B1  
12  
-
-
I
Input to the oscillator circuit and internal clock generator  
circuits.  
XTAL2  
E1  
C1 13  
O
Output from the oscillator amplifier.  
Power and ground pins  
USB0_VDDA  
3V3_DRIVER  
F3  
G3  
H3  
G1  
B4  
E3  
F3  
G3  
F1  
A6  
D1 16  
D2 17  
D3 19  
-
-
-
-
-
-
-
-
Separate analog 3.3 V power supply for driver.  
USB 3.3 V separate power supply voltage.  
USB0  
_VDDA3V3  
USB0_VSSA  
_TERM  
Dedicated analog ground for clean reference for termination  
resistors.  
USB0_VSSA  
_REF  
F2  
B2  
23  
Dedicated clean analog ground for generation of reference  
currents and voltages.  
VDDA  
VBAT  
137  
-
-
-
-
Analog power supply and ADC reference voltage.  
B10 B9  
C5 127  
RTC power supply: 3.3 V on this pin supplies power to the  
RTC.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
58 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 3.  
Pin description …continued  
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.  
Symbol  
Description  
VDDREG  
F10, D8,  
E4, 94,  
E5, 131,  
-
Main regulator power supply. Tie the VDDREG and VDDIO  
pins to a common power supply to ensure the same ramp-up  
time for both supply voltages.  
F9,  
L8,  
L7  
E8  
F4  
59,  
25  
[12]  
[12]  
VPP  
E8  
-
-
-
-
-
-
-
OTP programming voltage.  
VDDIO  
D7,  
H5,  
F10, 5,  
I/O power supply. Tie the VDDREG and VDDIO pins to a  
common power supply to ensure the same ramp-up time for  
both supply voltages.  
E12, H10, K5  
F7,  
36,  
41,  
K8,  
F8,  
G10  
71,  
G10,  
H10,  
J6,  
77,  
107,  
111,  
141  
J7,  
K7,  
L9,  
L10,  
N7,  
N13  
VDD  
VSS  
-
-
-
-
-
-
Power supply for main regulator, I/O, and OTP.  
Ground.  
[13]  
[14]  
G9, F10,  
H7, D7,  
J10, E6,  
J11, E7,  
-
-
-
-
K8  
E9,  
K6,  
K9  
[13]  
[14]  
VSSIO  
C4,  
D13,  
G6,  
G7,  
G8,  
H8,  
H9,  
J8,  
-
C8, 4,  
D4, 40,  
D5, 76,  
G8, 109  
J3,  
Ground.  
J6  
J9,  
K9,  
K10,  
M13,  
P7,  
P13  
VSSA  
B2  
B9  
A3  
B8  
C2 135  
-
-
-
-
Analog ground.  
n.c.  
Not connected  
-
-
-
[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in  
the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA  
= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset  
without boot code operation.  
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[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O  
functions with TTL levels and hysteresis; normal drive strength.  
[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O  
functions with TTL levels, and hysteresis; high drive strength.  
[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed  
digital I/O functions with TTL levels and hysteresis.  
[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;  
if VDDIO not present, do not exceed 3.6 V). When configured as an ADC input or DAC output, the pin is not 5 V tolerant and the digital  
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP  
register.  
[6] 5 V tolerant transparent analog pad.  
[7] For maximum load CL = 6.5 μF and maximum pull-down resistance Rpd = 80 kΩ, the VBUS signal takes about 2 s to fall from VBUS =  
5 V to VBUS = 0.2 V when it is no longer driven.  
[8] Transparent analog pad. Not 5 V tolerant.  
[9] Pad provides USB functions 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with  
the USB specification, revision 2.0 (Full-speed and Low-speed mode only).  
[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to  
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.  
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.  
[12] On the TFBGA100 package, VPP is internally connected to VDDIO.  
[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.  
[14] On the TFBGA100 package, VSS is internally connected to VSSIO.  
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7. Functional description  
7.1 Architectural overview  
The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus,  
and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and  
data accesses from different slave ports.  
The LPC4350/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M4  
buses and other bus masters to peripherals in a flexible manner that optimizes  
performance by allowing peripherals that are on different slaves ports of the matrix to be  
accessed simultaneously by different bus masters.  
An ARM Cortex-M0 co-processor is included in the LPC4350/30/20/10, capable of  
off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are  
connected to both processors. The processors communicate with each other via an  
interprocessor communication protocol.  
7.2 ARM Cortex-M4 processor  
The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture  
with separate local instruction and data buses as well as a third bus for peripherals, and  
includes an internal prefetch unit that supports speculative branching. The ARM  
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A  
hardware floating-point processor is integrated in the core. The processor includes an  
NVIC with up to 53 interrupts.  
7.3 ARM Cortex-M0 co-processor  
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high  
performance and very low-power consumption. The ARM Cortex-M0 co-processor uses a  
3-stage pipeline von-Neumann architecture and a small but powerful instruction set  
providing high-end processing hardware. The co-processor incorporates an NVIC with 32  
interrupts.  
7.4 Interprocessor communication  
The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on  
using shared SRAM as mailbox and one processor raising an interrupt on the other  
processor's NVIC, for example after it has delivered a new message in the mailbox. The  
receiving processor can reply by raising an interrupt on the sending processor's NVIC to  
acknowledge the message.  
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7.5 AHB multilayer matrix  
HIGH-SPEED PHY  
TEST/DEBUG  
INTERFACE  
TEST/DEBUG  
INTERFACE  
ARM  
ARM  
SD/  
MMC  
DMA  
1
ETHERNET  
USB0  
USB1  
LCD  
masters  
CORTEX-M4 CORTEX-M0  
System  
I-  
D-  
0
bus code code  
bus bus  
slaves  
64 kB ROM  
128 kB LOCAL SRAM  
72 kB LOCAL SRAM  
SPIFI  
SGPIO  
32 kB AHB SRAM  
16 kB + 16 kB  
AHB SRAM  
EXTERNAL  
MEMORY  
CONTROLLER  
AHB PERIPHERALS  
REGISTER  
INTERFACES  
APB, RTC  
DOMAIN  
PERIPHERALS  
AHB MULTILAYER MATRIX  
= master-slave connection  
002aaf873  
Fig 6. AHB multilayer matrix master and slave connections  
7.6 Nested Vectored Interrupt Controller (NVIC)  
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low  
interrupt latency and efficient processing of late arriving interrupts.  
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most  
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.  
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32-bit ARM Cortex-M4/M0 microcontroller  
7.6.1 Features  
• Controls system exceptions and peripheral interrupts.  
• The Cortex-M4 NVIC supports up to 53 vectored interrupts.  
• Eight programmable interrupt priority levels with hardware priority level masking.  
• Relocatable vector table.  
• Non-Maskable Interrupt (NMI).  
• Software interrupt generation.  
7.6.2 Interrupt sources  
Each peripheral device has one interrupt line connected to the NVIC but may have several  
interrupt flags. Individual interrupt flags can represent more than one interrupt source.  
7.7 System Tick timer (SysTick)  
The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate  
a dedicated SYSTICK exception at a 10 ms interval.  
7.8 Event router  
The event router combines various internal signals, interrupts, and the external interrupt  
pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event  
router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,  
Deep-sleep, Power-down, and Deep power-down modes. Individual events can be  
configured as edge or level sensitive and can be enabled or disabled in the event router.  
The event router can be battery powered.  
The following events if enabled in the event router can create a wake-up signal from  
sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:  
• External pins WAKEUP0/1/2/3 and RESET  
• Alarm timer, RTC (32 kHz oscillator running)  
The following events if enabled in the event router can create a wake-up signal from sleep  
mode only and/or create an interrupt:  
• WWDT, BOD interrupts  
• C_CAN0/1 and QEI interrupts  
• Ethernet, USB0, USB1 signals  
• Selected outputs of combined timers (SCT and timer0/1/3)  
Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in  
the NVIC.  
7.9 Global Input Multiplexer Array (GIMA)  
The GIMA routes signals to event-driven peripheral targets like the SCT, timers, event  
router, or the ADCs.  
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7.9.1 Features  
• Single selection of a source.  
• Signal inversion.  
• Can capture a pulse if the input event source is faster than the target clock.  
• Synchronization of input event and target clock.  
• Single-cycle pulse generation for target.  
7.10 On-chip static RAM  
The LPC4350/30/20/10 support up to 200 kB local SRAM and an additional 64 kB AHB  
SRAM with separate bus master access for higher throughput and individual power  
control for low-power operation.  
7.11 In-System Programming (ISP)  
In-System Programming (ISP) means programming or reprogramming the on-chip SRAM  
memory, using the boot loader software and the USART0 serial port. ISP can be  
performed when the part resides in the end-user board. ISP loads data into on-chip SRAM  
and execute code from on-chip SRAM.  
7.12 Boot ROM  
The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After  
a reset, the ARM processor will start its code execution from this memory.  
The boot ROM memory includes the following features:  
• The ROM memory size is 64 kB.  
• Supports booting from UART interfaces and external static memory such as NOR  
flash, quad SPI flash, and USB0 and USB1.  
• Includes API for OTP programming.  
• Includes a flexible USB device stack that supports Human Interface Device (HID),  
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.  
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If  
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is  
determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.  
Table 4.  
Boot mode when OTP BOOT_SRC bits are programmed  
Boot mode BOOT_SRC BOOT_SRC BOOT_SRC BOOT_SRC Description  
bit 3  
bit 2  
bit 1  
bit 0  
Pin state  
USART0  
SPIFI  
0
0
0
0
Boot source is defined by the reset state of P1_1,  
P1_2, P2_8, and P2_9 pins. See Table 5.  
0
0
0
0
0
0
0
1
1
1
0
1
Boot from device connected to USART0 using pins  
P2_0 and P2_1.  
Boot from Quad SPI flash connected to the SPIFI  
interface using pins P3_3 to P3_8.  
EMC 8-bit  
Boot from external static memory (such as NOR  
flash) using CS0 and an 8-bit data bus.  
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Table 4.  
Boot mode when OTP BOOT_SRC bits are programmed …continued  
Boot mode BOOT_SRC BOOT_SRC BOOT_SRC BOOT_SRC Description  
bit 3  
bit 2  
bit 1  
bit 0  
EMC 16-bit  
EMC 32-bit  
0
1
0
0
Boot from external static memory (such as NOR  
flash) using CS0 and a 16-bit data bus.  
0
1
0
1
Boot from external static memory (such as NOR  
flash) using CS0 and a 32-bit data bus.  
USB0  
0
0
1
1
1
0
1
1
0
0
1
0
Boot from USB0.  
Boot from USB1.  
USB1  
SPI (SSP)  
Boot from SPI flash connected to the SSP0  
interface on P3_3 (function SSP0_SCK), P3_6  
(function SSP0_SSEL), P3_7 (function  
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].  
USART3  
1
0
0
1
Boot from device connected to USART3 using pins  
P2_3 and P2_4.  
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.  
Remark: Pin functions for SPIFI and SSP0 boot are different.  
Table 5.  
Boot mode when OPT BOOT_SRC bits are zero  
Pins  
Boot mode  
Description  
P2_9  
P2_8  
P1_2  
P1_1  
USART0  
SPIFI  
LOW  
LOW  
LOW  
LOW  
Boot from device connected to USART0 using pins  
P2_0 and P2_1.  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
LOW  
HIGH  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
LOW  
Boot from Quad SPI flash connected to the SPIFI  
interface on P3_3 to P3_8[1]  
.
EMC 8-bit  
EMC 16-bit  
EMC 32-bit  
Boot from external static memory (such as NOR  
flash) using CS0 and an 8-bit data bus.  
Boot from external static memory (such as NOR  
flash) using CS0 and a 16-bit data bus.  
Boot from external static memory (such as NOR  
flash) using CS0 and a 32-bit data bus.  
USB0  
LOW  
LOW  
LOW  
HIGH  
HIGH  
HIGH  
LOW  
HIGH  
HIGH  
HIGH  
LOW  
HIGH  
Boot from USB0  
Boot from USB1.  
USB1  
SPI (SSP)  
Boot from SPI flash connected to the SSP0  
interface on P3_3 (function SSP0_SCK), P3_6  
(function SSP0_SSEL), P3_7 (function  
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]  
.
USART3  
HIGH  
LOW  
LOW  
LOW  
Boot from device connected to USART3 using pins  
P2_3 and P2_4.  
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.  
Remark: Pin functions for SPIFI and SSP0 boot are different.  
7.13 Memory mapping  
The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the  
Cortex-M0 processors and all SRAM is shared between both processors. Each processor  
uses its own ARM private bus memory map for the NVIC and other system functions.  
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LPC4350/30/20/10  
4 GB  
0xFFFF FFFF  
reserved  
0xE010 0000  
ARM private bus  
0xE000 0000  
reserved  
0x8800 0000  
SPIFI data  
0x8000 0000  
256 MB dynamic external memory DYCS3  
0x7000 0000  
256 MB dynamic external memory DYCS2  
0x6000 0000  
reserved  
0x4400 0000  
peripheral bit band alias region  
0x4200 0000  
reserved  
0x4010 2000  
SGPIO  
0x4010 1000  
0x4010 0000  
SPI  
reserved  
0x400F 8000  
high-speed GPIO  
0x400F 4000  
reserved  
0x400F 2000  
reserved  
0x400F 1000  
reserved  
0x400F 0000  
APB peripherals #3  
0x400E 0000  
reserved  
0x400D 0000  
APB peripherals #2  
0x400C 0000  
reserved  
0x400B 0000  
0x2000 0000  
APB peripherals #1  
16 MB static external memory CS3  
0x400A 0000  
0x1F00 0000  
0x1E00 0000  
0x1D00 0000  
0x1C00 0000  
reserved  
16 MB static external memory CS2  
16 MB static external memory CS1  
0x4009 0000  
APB peripherals #0  
0x4008 0000  
16 MB static external memory CS0  
reserved  
0x4006 0000  
clocking/reset peripherals  
0x4005 0000  
reserved  
RTC domain peripherals  
0x4004 0000  
0x1800 0000  
0x1400 0000  
reserved  
SPIFI data  
0x4001 2000  
AHB peripherals  
1 GB  
0x4000 0000  
reserved  
256 MB dynamic external memory DYCS1  
0x1041 0000  
0x1040 0000  
0x1009 2000  
0x3000 0000  
64 kB ROM  
reserved  
128 MB dynamic external memory DYCS0  
0x2800 0000  
reserved  
64 kB + 8 kB local SRAM  
(LPC4350/30)  
0x2400 0000  
0x1008 A000  
32 MB AHB SRAM bit banding  
0x2200 0000  
32 kB + 8 kB local SRAM  
(LPC4320/10)  
reserved  
0x2001 0000  
0x1008 0000  
0x1002 0000  
0x1001 8000  
16 kB AHB SRAM (LPC4350/30/20/10)  
reserved  
0x2000 C000  
16 kB AHB SRAM (LPC4350/30)  
0x2000 8000  
16 kB AHB SRAM (LPC4350/30)  
32 kB local SRAM (LPC4350/30/20)  
0x2000 4000  
96 kB local SRAM  
(LPC4350/30/20/10)  
16 kB AHB SRAM (LPC4350/30/20/10)  
0x2000 0000  
0x1000 0000  
local SRAM/  
external static memory banks  
0x1000 0000  
256 MB shadow area  
0x0000 0000  
0 GB  
002aaf774  
Fig 7. LPC4350/30/20/10 Memory mapping (overview)  
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
LPC4350/30/20/10  
0x400F 0000  
reserved  
ADC1  
0x400E 5000  
0x400E 4000  
0x400E 3000  
0x400E 2000  
0x400E 1000  
0xFFFF FFFF  
APB3  
external memories and  
ARM private bus  
peripherals  
ADC0  
0x6000 0000  
0x4400 0000  
0x4006 0000  
0x4005 4000  
C_CAN0  
DAC  
reserved  
RGU  
reserved  
peripheral bit band alias region  
reserved  
0x4005 3000  
0x4005 2000  
0x4005 1000  
0x4005 0000  
clocking  
reset control  
peripherals  
I2C1  
0x4200 0000  
0x4010 2000  
0x4010 1000  
0x4010 0000  
0x400E 0000  
0x400C 8000  
CCU2  
CCU1  
CGU  
SGPIO  
SPI  
GIMA  
0x400C 7000  
0x400C 6000  
QEI  
SSP1  
APB2  
peripherals  
reserved  
0x400C 5000  
0x400C 4000  
0x400C 3000  
0x400C 2000  
0x400C 1000  
0x400F 8000  
0x400F 4000  
0x400F 2000  
reserved  
RTC  
timer3  
high-speed GPIO  
reserved  
0x4004 7000  
0x4004 6000  
timer2  
OTP controller  
event router  
CREG  
USART3  
USART2  
0x4004 5000  
0x4004 4000  
0x4004 3000  
0x4004 2000  
reserved  
reserved  
0x400F 1000  
0x400F 0000  
0x400E 0000  
0x400D 0000  
0x400C 0000  
RTC domain  
peripherals  
RI timer  
0x400C 0000  
0x400B 0000  
APB3 peripherals  
reserved  
power mode control  
backup registers  
alarm timer  
reserved  
C_CAN1  
I2S1  
I2S0  
0x400A 5000  
0x400A 4000  
0x400A 3000  
0x400A 2000  
0x400A 1000  
0x4004 1000  
0x4004 0000  
APB2 peripherals  
reserved  
APB1  
peripherals  
0x400B 0000  
0x400A 0000  
0x4009 0000  
0x4008 0000  
APB1 peripherals  
0x4001 2000  
0x4001 0000  
ethernet  
reserved  
LCD  
I2C0  
reserved  
motor control PWM  
0x4000 9000  
0x4000 8000  
0x4000 7000  
0x4000 6000  
0x400A 0000  
APB0 peripherals  
0x4008 A000  
0x4008 9000  
0x4008 8000  
0x4008 7000  
GPIO GROUP1 interrupt  
reserved  
USB1  
0x4006 0000  
0x4005 0000  
0x4004 0000  
GPIO GROUP0 interrupt  
GPIO interrupts  
SCU  
USB0  
clocking/reset peripherals  
RTC domain peripherals  
reserved  
EMC  
SD/MMC  
SPIFI  
0x4000 5000  
0x4000 4000  
0x4000 3000  
0x4000 2000  
0x4000 1000  
0x4000 0000  
AHB  
peripherals  
0x4008 6000  
0x4008 5000  
0x4008 4000  
0x4008 3000  
0x4008 2000  
APB0  
peripherals  
timer1  
timer0  
0x4001 2000  
0x4000 0000  
AHB peripherals  
DMA  
SSP0  
reserved  
SCT  
SRAM memories  
external memory banks  
UART1 w/ modem  
USART0  
0x4008 1000  
0x4008 0000  
0x0000 0000  
WWDT  
002aaf775  
Fig 8. LPC4350/30/20/10 Memory mapping (peripherals)  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
7.14 One-Time Programmable (OTP) memory  
The OTP provides 64 bit + 256 bit One-Time Programmable (OTP) memory for  
general-purpose use.  
7.15 General-Purpose I/O (GPIO)  
The LPC4350/30/20/10 provide eight GPIO ports with up to 31 GPIO pins each.  
Device pins that are not connected to a specific peripheral function are controlled by the  
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate  
registers allow setting or clearing any number of outputs simultaneously. The value of the  
output register may be read back as well as the current state of the port pins.  
All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on  
reset. The input buffer must be turned on in the system control block SFS register before  
the GPIO input can be read.  
7.15.1 Features  
• Accelerated GPIO functions:  
– GPIO registers are located on the AHB so that the fastest possible I/O timing can  
be achieved.  
– Mask registers allow treating sets of port bits as a group, leaving other bits  
unchanged.  
– All GPIO registers are byte and half-word addressable.  
– Entire port value can be written in one instruction.  
• Bit-level set and clear registers allow a single instruction set or clear of any number of  
bits in one port.  
• Direction control of individual bits.  
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or  
level-sensitive GPIO interrupt request (GPIO interrupts).  
• Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO  
group0 and group1 interrupts).  
7.16 Configurable digital peripherals  
7.16.1 State Configurable Timer (SCT) subsystem  
The SCT allows a wide variety of timing, counting, output modulation, and input capture  
operations. The inputs and outputs of the SCT are shared with the capture and match  
inputs/outputs of the 32-bit general-purpose counter/timers.  
The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the  
two-counter case, in addition to the counter value the following operational elements are  
independent for each half:  
• State variable  
• Limit, halt, stop, and start conditions  
• Values of Match/Capture registers, plus reload or capture control values  
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In the two-counter case, the following operational elements are global to the SCT, but the  
last three can use match conditions from either counter:  
• Clock selection  
• Inputs  
• Events  
• Outputs  
• Interrupts  
7.16.1.1 Features  
• Two 16-bit counters or one 32-bit counter.  
• Counters clocked by bus clock or selected input.  
• Counters can be configured as up-counters or up-down counters.  
• State variable allows sequencing across multiple counter cycles.  
• Event combines input or output condition and/or counter match in a specified state.  
• Events control outputs and interrupts.  
• Selected events can limit, halt, start, or stop a counter.  
• Supports:  
– up to 8 inputs  
– 16 outputs  
– 16 match/capture registers  
– 16 events  
– 32 states  
7.16.2 Serial GPIO (SGPIO)  
The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate  
serial stream processing.  
7.16.2.1 Features  
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to  
serial data conversion.  
• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value  
from a pin or an output value to a pin with every cycle of a shift clock.  
• Each slice is double-buffered.  
• Interrupt is generated on a full FIFO, shift clock, or pattern match.  
• Slices can be concatenated to increase buffer size.  
• Each slice has a 32-bit pattern match filter.  
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7.17 AHB peripherals  
7.17.1 General-Purpose DMA (GPDMA)  
The DMA controller allows peripheral-to memory, memory-to-peripheral,  
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream  
provides unidirectional serial DMA transfers for a single source and destination. For  
example, a bidirectional port requires one stream for transmit and one for receives. The  
source and destination areas can each be either a memory region or a peripheral for  
master 1, but only memory for master 0.  
7.17.1.1 Features  
• Eight DMA channels. Each channel can support a unidirectional transfer.  
• 16 DMA request lines.  
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA  
Controller can assert either a burst DMA request or a single DMA request. The DMA  
burst size is set by programming the DMA Controller.  
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and  
peripheral-to-peripheral transfers are supported.  
• Scatter or gather DMA is supported through the use of linked lists. This means that  
the source and destination areas do not have to occupy contiguous areas of memory.  
• Hardware DMA channel priority.  
• AHB slave DMA programming interface. The DMA Controller is programmed by  
writing to the DMA control registers over the AHB slave interface.  
• Two AHB bus masters for transferring data. These interfaces transfer data when a  
DMA request goes active. Master 1 can access memories and peripherals, master 0  
can access memories only.  
• 32-bit AHB master bus width.  
• Incrementing or non-incrementing addressing for source and destination.  
• Programmable DMA burst size. The DMA burst size can be programmed to more  
efficiently transfer data.  
• Internal four-word FIFO per channel.  
• Supports 8, 16, and 32-bit wide transactions.  
• Big-endian and little-endian support. The DMA Controller defaults to little-endian  
mode on reset.  
• An interrupt to the processor can be generated on a DMA completion or when a DMA  
error has occurred.  
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read  
prior to masking.  
7.17.2 SPI Flash Interface (SPIFI)  
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM  
Cortex-M4 processor with little performance penalty compared to parallel flash devices  
with higher pin count.  
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After a few commands configure the interface at startup, the entire flash content is  
accessible as normal memory using byte, halfword, and word accesses by the processor  
and/or DMA channels. Simple sequences of commands handle erasing and  
programming.  
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup  
and initialization and then move to a half-duplex, command-driven 4-bit protocol for  
normal operation. Different serial flash vendors and devices accept or require different  
commands and command formats. SPIFI provides sufficient flexibility to be compatible  
with common flash devices and includes extensions to help insure compatibility with future  
devices.  
7.17.2.1 Features  
• Interfaces to serial flash memory in the main memory map.  
• Supports classic and 4-bit bidirectional serial protocols.  
• Half-duplex protocol compatible with various vendors and devices.  
• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to  
52 MB per second.  
• Supports DMA access.  
7.17.3 SD/MMC card interface  
The SD/MMC card interface supports the following modes to control:  
• Secure Digital memory (SD version 3.0)  
• Secure Digital I/O (SDIO version 2.0)  
• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)  
• MultiMedia Cards (MMC version 4.4)  
7.17.4 External Memory Controller (EMC)  
The LPC4350/30/20/10 EMC is a Memory Controller peripheral offering support for  
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it  
can be used as an interface with off-chip memory-mapped devices and peripherals.  
7.17.4.1 Features  
• Dynamic memory interface support including single data rate SDRAM.  
• Asynchronous static memory device support including RAM, ROM, and NOR flash,  
with or without asynchronous page mode.  
• Low transaction latency.  
• Read and write buffers to reduce latency and to improve performance.  
• 8/16/32 data and 24 address lines-wide static memory support.  
• 16 bit and 32 bit wide chip select SDRAM memory support.  
• Static memory features include:  
– Asynchronous page mode read  
– Programmable Wait States  
– Bus turnaround delay  
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– Output enable and write enable delays  
– Extended wait  
• Four chip selects for synchronous memory and four chip selects for static memory  
devices.  
• Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to  
SDRAMs.  
• Dynamic memory self-refresh mode controlled by software.  
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row  
address synchronous memory parts. Those are typically 512 MB, 256 MB, and  
128 MB parts, with 4, 8, 16, or 32 data bits per device.  
• Separate reset domains allow auto-refresh through a chip reset if desired.  
• SDRAM clock can run at full or half the Cortex-M4 core frequency.  
Note: Synchronous static memory devices (synchronous burst mode) are not supported.  
7.17.5 High-speed USB Host/Device/OTG interface (USB0)  
Remark: The USB0 controller is available on parts LPC4350/30/20. See Table 2.  
The USB OTG module allows the LPC4350/30/20/10 to connect directly to a USB Host  
such as a PC (in device mode) or to a USB Device in host mode.  
7.17.5.1 Features  
• On-chip UTMI+ compliant high-speed transceiver (PHY).  
• Complies with Universal Serial Bus specification 2.0.  
• Complies with USB On-The-Go supplement.  
• Complies with Enhanced Host Controller Interface Specification.  
• Supports auto USB 2.0 mode discovery.  
• Supports all high-speed USB-compliant peripherals.  
• Supports all full-speed USB-compliant peripherals.  
• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol  
(SRP) for OTG peripherals.  
• Supports interrupts.  
• This module has its own, integrated DMA engine.  
• USB interface electrical test software included in ROM USB stack.  
7.17.6 High-speed USB Host/Device interface with ULPI (USB1)  
Remark: The USB1 controller is available on parts LPC4350/30. See Table 2.  
The USB1 interface can operate as a full-speed USB Host/Device interface or can  
connect to an external ULPI PHY for High-speed operation.  
7.17.6.1 Features  
• Complies with Universal Serial Bus specification 2.0.  
• Complies with Enhanced Host Controller Interface Specification.  
• Supports auto USB 2.0 mode discovery.  
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• Supports all high-speed USB-compliant peripherals if connected to external ULPI  
PHY.  
• Supports all full-speed USB-compliant peripherals.  
• Supports interrupts.  
• This module has its own, integrated DMA engine.  
• USB interface electrical test software included in ROM USB stack.  
7.17.7 LCD controller  
Remark: The LCD controller is available on LPC4350 only. See Table 2.  
The LCD controller provides all of the necessary control signals to interface directly to  
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT  
panels can be operated. The display resolution is selectable and can be up to 1024 768  
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.  
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of  
the displayed data) while still supporting many colors.  
The LCD interface includes its own DMA controller to allow it to operate independently of  
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,  
providing flexibility for system timing. Hardware cursor support can further reduce the  
amount of CPU time required to operate the display.  
7.17.7.1 Features  
• AHB master interface to access frame buffer.  
• Setup and control via a separate AHB slave interface.  
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.  
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays  
with 4-bit or 8-bit interfaces.  
• Supports single and dual-panel color STN displays.  
• Supports Thin Film Transistor (TFT) color displays.  
• Programmable display resolution including, but not limited to: 320 200, 320 240,  
640 200, 640 240, 640 480, 800 600, and 1024 768.  
• Hardware cursor support for single-panel displays.  
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.  
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.  
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.  
• 16 bpp true-color non-palettized for color STN and TFT.  
• 24 bpp true-color non-palettized for color TFT.  
• Programmable timing for different display panels.  
• 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM.  
• Frame, line, and pixel clock signals.  
• AC bias signal for STN, data enable signal for TFT panels.  
• Supports little and big-endian, and Windows CE data formats.  
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• LCD panel clock may be generated from the peripheral clock, or from a clock input  
pin.  
7.17.8 Ethernet  
Remark: The Ethernet peripheral is available on parts LPC4350/30. See Table 2.  
7.17.8.1 Features  
• 10/100 Mbit/s  
• DMA support  
• Power management remote wake-up frame and magic packet detection  
• Supports both full-duplex and half-duplex operation  
– Supports CSMA/CD Protocol for half-duplex operation.  
– Supports IEEE 802.3x flow control for full-duplex operation.  
– Optional forwarding of received pause control frames to the user application in  
full-duplex operation.  
– Back-pressure support for half-duplex operation.  
– Automatic transmission of zero-quanta pause frame on deassertion of flow control  
input in full-duplex operation.  
• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE  
1588-2008 v2).  
7.18 Digital serial peripherals  
7.18.1 UART1  
The LPC4350/30/20/10 contain one UART with standard transmit and receive data lines.  
UART1 also provides a full modem control handshake interface and support for  
RS-485/9-bit mode allowing both software address detection and automatic address  
detection using 9-bit mode.  
UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd  
can be achieved with any crystal frequency above 2 MHz.  
7.18.1.1 Features  
• Maximum UART data bit rate of 8 MBit/s.  
• 16 B Receive and Transmit FIFOs.  
• Register locations conform to 16C550 industry standard.  
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.  
• Built-in fractional baud rate generator covering wide range of baud rates without a  
need for external crystals of particular values.  
• Auto baud capabilities and FIFO control mechanism that enables software flow  
control implementation.  
• Equipped with standard modem interface signals. This module also provides full  
support for hardware flow control.  
• Support for RS-485/9-bit/EIA-485 mode (UART1).  
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• DMA support.  
7.18.2 USART0/2/3  
The LPC4350/30/20/10 contain three USARTs. In addition to standard transmit and  
receive data lines, the USARTs support a synchronous mode.  
The USARTs include a fractional baud rate generator. Standard baud rates such as  
115200 Bd can be achieved with any crystal frequency above 2 MHz.  
7.18.2.1 Features  
• Maximum UART data bit rate of 8 MBit/s.  
• 16 B Receive and Transmit FIFOs.  
• Register locations conform to 16C550 industry standard.  
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.  
• Built-in fractional baud rate generator covering wide range of baud rates without a  
need for external crystals of particular values.  
• Auto baud capabilities and FIFO control mechanism that enables software flow  
control implementation.  
• Support for RS-485/9-bit/EIA-485 mode.  
• USART3 includes an IrDA mode to support infrared communication.  
• All USARTs have DMA support.  
• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.  
• Smart card mode conforming to ISO7816 specification  
7.18.3 SPI serial I/O controller  
The LPC4350/30/20/10 contain one SPI controller. SPI is a full-duplex serial interface  
designed to handle multiple masters and slaves connected to a given bus. Only a single  
master and a single slave can communicate on the interface during a given data transfer.  
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and  
the slave always sends 8 bits to 16 bits of data to the master.  
7.18.3.1 Features  
• Maximum SPI data bit rate 25 Mbit/s.  
• Compliant with SPI specification  
• Synchronous, serial, full-duplex communication  
• Combined SPI master and slave  
• Maximum data bit rate of one eighth of the input clock rate  
• 8 bits to 16 bits per transfer  
7.18.4 SSP serial I/O controller  
Remark: The LPC4350/30/20/10 contain two SSP controllers.  
The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with  
multiple masters and slaves on the bus. Only a single master and a single slave can  
communicate on the bus during a given data transfer. The SSP supports full-duplex  
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transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and  
from the slave to the master. In practice, often only one of these data flows carries  
meaningful data.  
7.18.4.1 Features  
• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s  
(master) and 17 Mbit/s (slave).  
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National  
Semiconductor Microwire buses  
• Synchronous serial communication  
• Master or slave operation  
• 8-frame FIFOs for both transmit and receive  
• 4-bit to 16-bit frame  
• DMA transfers supported by GPDMA  
7.18.5 I2C-bus interface  
Remark: The LPC4350/30/20/10 contain two I2C-bus interfaces.  
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line  
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and  
can operate as either a receiver-only device (for example an LCD driver) or a transmitter  
with the capability to both receive and send information (such as memory). Transmitters  
and/or receivers can operate in either master or slave mode, depending on whether the  
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and  
can be controlled by more than one bus master connected to it.  
7.18.5.1 Features  
• I2C0 is a standard I2C-compliant bus interface with open-drain pins. I2C0 also  
supports Fast mode plus with bit rates up to 1 Mbit/s.  
• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).  
• Easy to configure as master, slave, or master/slave.  
• Programmable clocks allow versatile rate control.  
• Bidirectional data transfer between masters and slaves.  
• Multi-master bus (no central master).  
• Arbitration between simultaneously transmitting masters without corruption of serial  
data on the bus.  
• Serial clock synchronization allows devices with different bit rates to communicate via  
one serial bus.  
• Serial clock synchronization can be used as a handshake mechanism to suspend and  
resume serial transfer.  
• The I2C-bus can be used for test and diagnostic purposes.  
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.  
7.18.6 I2S interface  
Remark: The LPC4350/30/20/10 contain two I2S-bus interfaces.  
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The I2S-bus provides a standard communication interface for digital audio applications.  
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,  
and one word select signal. The basic I2S-bus connection has one master, which is  
always the master, and one slave. The I2S-bus interface provides a separate transmit and  
receive channel, each of which can operate as either a master or a slave.  
7.18.6.1 Features  
• The I2S interface has separate input/output channels, each of which can operate in  
master or slave mode.  
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.  
• Mono and stereo audio data supported.  
• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,  
96, 192) kHz.  
• Support for an audio master clock.  
• Configurable word select period in master mode (separately for I2S-bus input and  
output).  
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.  
• Generates interrupt requests when buffer levels cross a programmable boundary.  
• Two DMA requests controlled by programmable buffer levels. The DMA requests are  
connected to the GPDMA block.  
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus  
output.  
7.18.7 C_CAN  
Remark: The LPC4350/30/20/10 contain two C_CAN controllers.  
Controller Area Network (CAN) is the definition of a high performance communication  
protocol for serial data communication. The C_CAN controller is designed to provide a full  
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The  
C_CAN controller can create powerful local networks with low-cost multiplex wiring by  
supporting distributed real-time control with a high level of reliability.  
7.18.7.1 Features  
• Conforms to protocol version 2.0 parts A and B.  
• Supports bit rate of up to 1 Mbit/s.  
• Supports 32 Message Objects.  
• Each Message Object has its own identifier mask.  
• Provides programmable FIFO mode (concatenation of Message Objects).  
• Provides maskable interrupts.  
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN  
applications.  
• Provides programmable loop-back mode for self-test operation.  
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7.19 Counter/timers and motor control  
7.19.1 General purpose 32-bit timers/external event counters  
The LPC4350/30/20/10 include four 32-bit timer/counters. The timer/counter is designed  
to count cycles of the system derived clock or an externally-supplied clock. It can  
optionally generate interrupts, generate timed DMA requests, or perform other actions at  
specified timer values, based on four match registers. Each timer/counter also includes  
two capture inputs to trap the timer value when an input signal transitions, optionally  
generating an interrupt.  
7.19.1.1 Features  
• A 32-bit timer/counter with a programmable 32-bit prescaler.  
• Counter or timer operation.  
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value  
when an input signal transitions. A capture event can also generate an interrupt.  
• Four 32-bit match registers that allow:  
– Continuous operation with optional interrupt generation on match.  
– Stop timer on match with optional interrupt generation.  
– Reset timer on match with optional interrupt generation.  
• Up to four external outputs corresponding to match registers, with the following  
capabilities:  
– Set LOW on match.  
– Set HIGH on match.  
– Toggle on match.  
– Do nothing on match.  
• Up to two match registers can be used to generate timed DMA requests.  
7.19.2 Motor control PWM  
The motor control PWM is a specialized PWM supporting 3-phase motors and other  
combinations. Feedback inputs are provided to automatically sense rotor position and use  
that information to ramp speed up or down. An abort input causes the PWM to release all  
motor drive outputs immediately . At the same time, the motor control PWM is highly  
configurable for other generalized timing, counting, capture, and compare applications.  
7.19.3 Quadrature Encoder Interface (QEI)  
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular  
displacement into two pulse signals. By monitoring both the number of pulses and the  
relative phase of the two signals, the user code can track the position, direction of rotation,  
and velocity. In addition, a third channel, or index signal, can be used to reset the position  
counter. The quadrature encoder interface decodes the digital pulses from a quadrature  
encoder wheel to integrate position over time and determine direction of rotation. In  
addition, the QEI can capture the velocity of the encoder wheel.  
7.19.3.1 Features  
• Tracks encoder position.  
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• Increments/decrements depending on direction.  
• Programmable for 2or 4position counting.  
• Velocity capture using built-in timer.  
• Velocity compare function with “less than” interrupt.  
• Uses 32-bit registers for position and velocity.  
• Three position-compare registers with interrupts.  
• Index counter for revolution counting.  
• Index compare register with interrupts.  
• Can combine index and position interrupts to produce an interrupt for whole and  
partial revolution displacement.  
• Digital filter with programmable delays for encoder input signals.  
• Can accept decoded signal inputs (clk and direction).  
7.19.4 Repetitive Interrupt (RI) timer  
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to  
a selectable value, generating an interrupt when a match occurs. Any bits of the  
timer/compare function can be masked such that they do not contribute to the match  
detection. The repetitive interrupt timer can be used to create an interrupt that repeats at  
predetermined intervals.  
7.19.4.1 Features  
• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.  
• 32-bit compare value.  
• 32-bit compare mask. An interrupt is generated when the counter value equals the  
compare value, after masking. This mechanism allows for combinations not possible  
with a simple compare.  
7.19.5 Windowed WatchDog Timer (WWDT)  
The purpose of the watchdog is to reset the controller if software fails to periodically  
service it within a programmable time window.  
7.19.5.1 Features  
• Internally resets chip if not periodically reloaded during the programmable time-out  
period.  
• Optional windowed operation requires reload to occur between a minimum and  
maximum time period, both programmable.  
• Optional warning interrupt can be generated at a programmable time prior to  
watchdog time-out.  
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be  
disabled.  
• Incorrect feed sequence causes reset or interrupt if enabled.  
• Flag to indicate watchdog reset.  
• Programmable 24-bit timer with internal prescaler.  
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• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in  
multiples of Tcy(WDCLK) 4.  
• The Watchdog Clock (WDCLK) uses the IRC as the clock source.  
7.20 Analog peripherals  
7.20.1 Analog-to-Digital Converter (ADC0/1)  
7.20.1.1 Features  
• 10-bit successive approximation analog to digital converter.  
• Input multiplexing among 8 pins.  
• Power-down mode.  
• Measurement range 0 to VDDA.  
• Sampling frequency up to 400 kSamples/s.  
• Burst conversion mode for single or multiple inputs.  
• Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer  
outputs 8 or 15, or the PWM output MCOA2.  
• Individual result registers for each A/D channel to reduce interrupt overhead.  
• DMA support.  
7.20.2 Digital-to-Analog Converter (DAC)  
7.20.2.1 Features  
• 10-bit resolution  
• Monotonic by design (resistor string architecture)  
• Controllable conversion speed  
• Low-power consumption  
7.21 Peripherals in the RTC power domain  
7.21.1 RTC  
The Real-Time Clock (RTC) is a set of counters for measuring time when system power is  
on, and optionally when it is off. It uses little power when the CPU does not access its  
registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the  
RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own  
power supply pin, VBAT.  
7.21.1.1 Features  
• Measures the passage of time to maintain a calendar and clock. Provides seconds,  
minutes, hours, day of month, month, year, day of week, and day of year.  
• Ultra-low power design to support battery powered systems. Uses power from the  
CPU power supply when it is present.  
• Dedicated battery power supply pin.  
• RTC power supply is isolated from the rest of the chip.  
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• Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.  
• Periodic interrupts can be generated from increments of any field of the time registers.  
• Alarm interrupt can be generated for a specific date/time.  
7.21.2 Alarm timer  
The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating  
alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00  
and asserts an interrupt if enabled.  
The alarm timer is part of the RTC power domain and can be battery powered.  
7.22 System control  
7.22.1 Configuration registers (CREG)  
The following settings are controlled in the configuration register block:  
• BOD trip settings  
• Oscillator output  
• DMA-to-peripheral muxing  
• Ethernet mode  
• Memory mapping  
• Timer/USART inputs  
• Enabling the USB controllers  
In addition, the CREG block contains the part identification and part configuration  
information.  
7.22.2 System Control Unit (SCU)  
The system control unit determines the function and electrical mode of the digital pins. By  
default function 0 is selected for all pins with pull-up enabled. For pins that support a  
digital and analog function, the ADC function select registers in the SCU enable the  
analog function.  
A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are  
located on separate pads and are not controlled through the SCU.  
In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that  
select the pin interrupts are located in the SCU.  
7.22.3 Clock Generation Unit (CGU)  
The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be  
unrelated in frequency and phase and can have different clock sources within the CGU.  
One CGU base clock is routed to the CLKOUT pins. The base clock that generates the  
CPU clock is referred to as CCLK.  
Multiple branch clocks are derived from each base clock. The branch clocks offer flexible  
control for power-management purposes. All branch clocks are outputs of one of two  
Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived  
from the same base clock are synchronous in frequency and phase.  
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7.22.4 Internal RC oscillator (IRC)  
The IRC is used as the clock source for the WWDT and/or as the clock that drives the  
PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 %  
accuracy over the entire voltage and temperature range.  
Upon power-up or any chip reset, the LPC4350/30/20/10 use the IRC as the clock source.  
The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the  
PLL0USB or PLL0AUDIO as needed if an external boot source is selected.  
7.22.5 PLL0USB (for USB0)  
PLL0 is a dedicated PLL for the USB0 High-speed controller.  
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz  
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current  
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.  
7.22.6 PLL0AUDIO (for audio)  
The audio PLL PLL0AUDIO is a general-purpose PLL with a small step size. This PLL  
accepts an input clock frequency derived from an external oscillator or internal IRC. The  
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator  
(CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired  
output frequency. The output frequency can be set as a multiple of the sampling frequency  
fs to 32fs, 64fs, 128 fs, 256 fs, 384 fs, 512 fs and the sampling frequency fs can  
range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other  
frequencies are possible as well using the integrated fractional divider.  
7.22.7 System PLL1  
The PLL1 accepts an input clock frequency from an external oscillator in the range of  
10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current  
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO  
operates in the range of 156 MHz to 320 MHz. This range is possible through an  
additional divider in the loop to keep the CCO within its frequency range while the PLL is  
providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,  
or 16 to produce the output clock. Since the minimum output divider value is 2, it is  
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed  
following a chip reset. After reset, software can enable the PLL. The program must  
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a  
clock source. The PLL settling time is 100 s.  
7.22.8 Reset Generation Unit (RGU)  
The RGU allows generation of independent reset signals for individual blocks and  
peripherals on the LPC4350/30/20/10.  
7.22.9 Power control  
The LPC4350/30/20/10 feature several independent power domains to control power to  
the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the  
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event  
router) are located in the RTC power-domain. The main regulator or a battery supply can  
power the RTC. A power selector switch ensures that the RTC block is always powered  
on.  
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LPC43xx  
VDDIO  
to I/O pads  
to cores  
VSS  
REGULATOR  
to memories,  
peripherals,  
oscillators,  
PLLs  
VDDREG  
MAIN POWER DOMAIN  
to RTC  
ULTRA LOW-POWER  
REGULATOR  
domain  
VBAT  
peripherals  
RESET  
WAKEUP0/1/2/3  
RESET/WAKE-UP  
to RTC I/O  
pads (V  
CONTROL  
)
ps  
BACKUP REGISTERS  
REAL-TIME CLOCK  
RTCX1  
RTCX2  
32 kHz  
OSCILLATOR  
ALARM  
ALWAYS-ON/RTC POWER DOMAIN  
DAC  
VDDA  
VSSA  
ADC  
ADC POWER DOMAIN  
OTP  
VPP  
OTP POWER DOMAIN  
USB0_VDDA3V_DRIVER  
USB0_VDDA3V3  
USB0  
USB0 POWER DOMAIN  
002aag378  
Fig 9. Power domains  
7.22.10 Power Management Controller (PMC)  
The PMC controls the power to the cores, peripherals, and memories.  
The LPC4350/30/20/10 support the following power modes in order from highest to lowest  
power consumption:  
1. Active mode  
2. Sleep mode  
3. Power-down modes:  
a. Deep-sleep mode  
b. Power-down mode  
c. Deep power-down mode  
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Active mode and sleep mode apply to the state of the core. In a dual-core system, either  
core can be in active or sleep mode independently of the other core.  
If the core is in Active mode, it is fully operational and can access peripherals and  
memories as configured by software. If the core is in Sleep mode, it receives no clocks,  
but peripherals and memories remain running.  
Either core can enter sleep mode from active mode independently of the other core and  
while the other core remains in active mode or is in sleep mode.  
Power-down modes apply to the entire system. In the Power-down modes, both cores and  
all peripherals except for peripherals in the always-on power domain are shut down.  
Memories can remain powered for retaining memory contents as defined by the individual  
power-down mode.  
Either core in active mode can put the part into one of the three power down modes if the  
core is enabled to do so. If both cores are enabled for putting the system into power-down,  
then the system enters power-down only once both cores have received a WFI or WFE  
instruction.  
Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The  
interrupt is captured in the NVIC and an event is captured in the Event router. Both cores  
can wake up from sleep mode independently of each other.  
Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down,  
is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.  
When waking up from Deep power-down mode, the part resets and attempts to boot.  
7.23 Serial Wire Debug/JTAG  
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and  
trace functions are supported in addition to a standard JTAG debug and parallel trace  
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four  
watch points.  
Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only,  
The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM  
Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0  
cores separately or both cores simultaneously.  
Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the  
RGU block.  
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LPC43xx  
TCK  
TMS  
TRST  
TDI  
TCK  
ARM Cortex-M4  
TCK  
TMS  
TRST  
TDI  
ARM Cortex-M0  
TMS  
TRST  
TDI  
TDO  
TDO  
JTAG ID = 0x4BA0 0477  
JTAG ID = 0x0BA0 1477  
TDO  
DBGEN  
RESET  
DBGEN = HIGH  
RESET = HIGH  
002aah448  
Fig 10. Dual-core debug configuration  
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8. Limiting values  
Table 6.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]  
Symbol Parameter Conditions  
Min  
Max  
Unit  
VDD(REG)(3V3) regulator supply voltage on pin VDDREG  
(3.3 V)  
0.5  
3.6  
V
VDD(IO)  
input/output supply  
voltage  
on pin VDDIO  
0.5  
0.5  
3.6  
3.6  
V
V
VDDA(3V3)  
analog supply voltage  
(3.3 V)  
on pin VDDA  
VBAT  
battery supply voltage  
on pin VBAT  
on pin VPP  
0.5  
0.5  
3.6  
3.6  
V
V
Vprog(pf)  
polyfuse programming  
voltage  
[2]  
VI  
input voltage  
only valid when VDD(IO) 2.2 V  
5 V tolerant I/O pins  
0.5  
0.5  
5.5  
V
V
ADC/DAC pins and digital I/O  
pins configured for an analog  
function  
VDDA(3V3)  
USB0 pins USB0_DP;  
USB0_DM;USB0_VBUS  
0.3  
0.3  
0.3  
5.25  
3.6  
V
V
V
USB0 pins USB0_ID;  
USB0_RREF  
USB1 pins USB1_DP and  
USB1_DM  
5.25  
[3]  
[3]  
IDD  
supply current  
per supply pin  
-
-
-
100  
100  
100  
mA  
mA  
mA  
ISS  
ground current  
I/O latch-up current  
per ground pin  
Ilatch  
(0.5VDD(IO)) < VI < (1.5VDD(IO));  
Tj < 125 C  
[4]  
[5]  
Tstg  
storage temperature  
65  
+150  
1.5  
C  
Ptot(pack)  
total power dissipation  
(per package)  
based on package heat transfer,  
not device power consumption  
-
W
VESD  
electrostatic discharge  
voltage  
human body model; all pins  
2000  
+2000  
V
[1] The following applies to the limiting values:  
a) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static  
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.  
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless  
otherwise noted.  
[2] Including voltage on outputs in 3-state mode.  
[3] The peak current is limited to 25 times the corresponding maximum current.  
[4] Dependent on package type.  
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kseries resistor.  
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9. Thermal characteristics  
The average chip junction temperature, Tj (C), can be calculated using the following  
equation:  
Tj = Tamb + PD Rthj – a  
(1)  
• Tamb = ambient temperature (C),  
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)  
• PD = sum of internal and I/O power dissipation  
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of  
the I/O pins is often small and many times can be negligible. However it can be significant  
in some applications.  
Table 7.  
Thermal characteristics  
VDD = 2.2 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified;  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tj(max)  
maximum junction  
temperature  
-
-
125  
C  
Table 8.  
Symbol  
Thermal resistance (LQFP packages)  
Parameter  
Conditions  
Thermal resistance  
in C/W ±15 %  
LQFP144  
Rth(j-a)  
thermal resistance from JEDEC (4.5 in 4 in); still air 38  
junction to ambient  
Single-layer (4.5 in 3 in);  
still air  
50  
11  
Rth(j-c)  
thermal resistance from  
junction to case  
Table 9.  
Symbol  
Thermal resistance value (BGA packages)  
Parameter  
Conditions  
Thermal resistance in C/W ±15 %  
LBGA256  
TFBGA180  
TFBGA100  
Rth(j-a)  
thermal resistance from  
junction to ambient  
JEDEC (4.5 in 4 in); still air 29  
38  
46  
8-layer (4.5 in 3 in); still air 24  
30  
11  
37  
11  
Rth(j-c)  
thermal resistance from  
junction to case  
14  
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10. Static characteristics  
Table 10. Static characteristics  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ[1]  
Max  
Unit  
Supply pins  
VDD(IO)  
input/output supply  
voltage  
2.2  
2.2  
-
-
3.6  
3.6  
V
V
[2]  
VDD(REG)(3V3)  
VDDA(3V3)  
regulator supply voltage  
(3.3 V)  
analog supply voltage  
(3.3 V)  
on pin VDDA  
2.2  
3.0  
-
3.6  
3.6  
V
V
on pins  
3.3  
USB0_VDDA3V3_  
DRIVER and  
USB0_VDDA3V3  
[2]  
[3]  
VBAT  
battery supply voltage  
2.2  
2.7  
-
-
3.6  
3.6  
V
V
Vprog(pf)  
polyfuse programming on pin VPP (for OTP)  
voltage  
Iprog(pf)  
polyfuse programming on pin VPP; OTP  
-
-
30  
mA  
current  
programming time   
1.6 ms  
IDD(REG)(3V3)  
regulator supply current Active mode; M0-core in  
(3.3 V) reset; code  
while(1){}  
executed from RAM; all  
peripherals disabled;  
PLL1 enabled  
[4]  
[4]  
[4]  
[4]  
[4]  
CCLK = 12 MHz  
CCLK = 60 MHz  
CCLK = 120 MHz  
CCLK = 180 MHz  
CCLK = 204 MHz  
-
6.6  
-
-
-
-
-
mA  
mA  
mA  
mA  
mA  
25.3  
48.4  
72.0  
81.5  
-
-
-
IDD(REG)(3V3)  
regulator supply current after WFE/WFI instruction  
(3.3 V)  
executed from RAM; all  
peripherals disabled; M0  
core in reset  
[4][5]  
[4]  
sleep mode  
-
-
-
-
5.0  
30  
-
-
-
-
mA  
A  
A  
A  
deep-sleep mode  
power-down mode  
[4]  
15  
[4][6]  
deep power-down  
mode  
0.03  
deep power-down  
mode; VBAT floating  
[4]- -  
2
0
-
-
A  
[7]  
IBAT  
battery supply current  
active mode; VBAT  
=
-
nA  
3.2 V; VDD(REG)(3V3)  
3.6 V.  
=
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 10. Static characteristics …continued  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ[1]  
Max  
Unit  
[8]  
IBAT  
battery supply current  
VDD(REG)(3V3) = 3.3 V;  
VBAT = 3.6 V  
deep-sleep mode  
power-down mode  
-
-
2
2
-
-
A  
A  
[8]  
[8]  
deep power-down  
mode  
-
2
-
-
-
-
-
A  
A  
A  
A  
IDD(IO)  
I/O supply current  
deep sleep mode  
power-down mode  
deep power-down mode  
on pin VDDA;  
- -  
- -  
1
1
[9]  
-
-
0.05  
0.4  
[11]  
IDDA  
Analog supply current  
deep sleep mode  
power-down mode  
A  
A  
[11]  
[11]  
-
-
0.4  
-
-
deep power-down  
mode  
0.007  
A  
RESET,RTC_ALARM, WAKEUPn pins  
[10]  
[10]  
[10]  
[10]  
VIH  
HIGH-level input  
voltage  
0.8 (Vps  
0.35)  
-
5.5  
V
V
V
V
VIL  
LOW-level input voltage  
hysteresis voltage  
output voltage  
0
-
0.3 (Vps   
0.1)  
Vhys  
Vo  
0.05 (Vps  
0.35)  
-
-
-
-
Vps - 0.2  
Standard I/O pins - normal drive strength  
CI  
input capacitance  
-
-
-
2
-
pF  
nA  
ILL  
LOW-level leakage  
current  
VI = 0 V; on-chip pull-up  
resistor disabled  
3
ILH  
HIGH-level leakage  
current  
VI = VDD(IO); on-chip  
pull-down resistor  
disabled  
-
3
-
nA  
VI = 5 V  
-
-
-
20  
-
nA  
nA  
IOZ  
OFF-state output  
current  
VO = 0 V to VDD(IO)  
;
3
on-chip pull-up/down  
resistors disabled;  
absolute value  
VI  
input voltage  
pin configured to provide  
a digital function;  
0
-
5.5  
V
VDD(IO) 2.2 V  
VDD(IO) = 0 V  
0
0
-
-
-
3.6  
V
V
V
VO  
output voltage  
output active  
VDD(IO)  
5.5  
VIH  
HIGH-level input  
voltage  
0.7   
VDD(IO)  
VIL  
LOW-level input voltage  
0
-
-
0.3   
VDD(IO)  
V
V
Vhys  
hysteresis voltage  
0.1   
-
VDD(IO)  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 10. Static characteristics …continued  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ[1]  
Max  
Unit  
VOH  
HIGH-level output  
voltage  
IOH = 6 mA  
VDD(IO)  
0.4  
-
-
V
VOL  
IOH  
IOL  
LOW-level output  
voltage  
IOL = 6 mA  
-
-
0.4  
V
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
VOL = 0.4 V  
6  
6
-
-
-
mA  
mA  
mA  
mA  
A  
A  
LOW-level output  
current  
-
-
[12]  
[12]  
IOHS  
IOLS  
Ipd  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
-
86.5  
LOW-level short-circuit drive LOW; connected to  
output current  
-
-
76.5  
VDD(IO)  
[14][15]  
[16]  
pull-down current  
VI = 5 V  
-
93  
62  
-
-
-
[14][15]  
[16]  
Ipu  
pull-up current  
VI = 0 V  
-
VDD(IO) < VI 5 V  
-
10  
A  
Rs  
series resistance  
on I/O pins with analog  
function; analog function  
enabled  
200  
I/O pins - high drive strength  
CI  
input capacitance  
-
-
-
2
-
pF  
nA  
ILL  
LOW-level leakage  
current  
VI = 0 V; on-chip pull-up  
resistor disabled  
3
ILH  
HIGH-level leakage  
current  
VI = VDD(IO); on-chip  
pull-down resistor  
disabled  
-
3
-
nA  
VI = 5 V  
-
-
-
20  
-
nA  
nA  
IOZ  
OFF-state output  
current  
VO = 0 V to VDD(IO)  
;
3
on-chip pull-up/down  
resistors disabled;  
absolute value  
VI  
input voltage  
pin configured to provide  
a digital function;  
VDD(IO) 2.2 V  
VDD(IO) = 0 V  
0
0
0
-
-
-
-
5.5  
V
V
V
V
3.6  
VO  
output voltage  
output active  
VDD(IO)  
5.5  
VIH  
HIGH-level input  
voltage  
0.7   
VDD(IO)  
VIL  
Vhys  
Ipd  
LOW-level input voltage  
hysteresis voltage  
pull-down current  
0
-
0.3   
VDD(IO)  
V
0.1   
VDD(IO)  
-
-
-
V
[14][15]  
[16]  
VI = VDD(IO)  
-
62  
A  
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Table 10. Static characteristics …continued  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ[1]  
Max  
Unit  
[14][15]  
[16]  
Ipu  
pull-up current  
VI = 0 V  
-
62  
-
A  
VDD(IO) < VI 5 V  
-
10  
-
A  
I/O pins - high drive strength: standard drive mode  
IOH  
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
4  
4
-
-
-
-
-
-
mA  
mA  
mA  
mA  
IOL  
LOW-level output  
current  
VOL = 0.4 V  
-
[12]  
[12]  
IOHS  
IOLS  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
32  
32  
LOW-level short-circuit drive LOW; connected to  
output current VDD(IO)  
-
I/O pins - high drive strength: medium drive mode  
IOH  
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
8  
8
-
-
-
-
-
-
mA  
mA  
mA  
mA  
IOL  
LOW-level output  
current  
VOL = 0.4 V  
-
[12]  
[12]  
IOHS  
IOLS  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
65  
63  
LOW-level short-circuit drive LOW; connected to  
output current VDD(IO)  
-
I/O pins - high drive strength: high drive mode  
IOH  
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
14  
-
-
-
-
-
mA  
mA  
mA  
mA  
IOL  
LOW-level output  
current  
VOL = 0.4 V  
14  
-
-
[12]  
[12]  
IOHS  
IOLS  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
113  
110  
LOW-level short-circuit drive LOW; connected to  
output current VDD(IO)  
-
I/O pins - high drive strength: ultra-high drive mode  
IOH  
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
20  
-
-
-
-
-
mA  
mA  
mA  
mA  
IOL  
LOW-level output  
current  
VOL = 0.4 V  
20  
-
-
[12]  
[12]  
IOHS  
IOLS  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
165  
156  
LOW-level short-circuit drive LOW; connected to  
-
output current  
VDD(IO)  
I/O pins - high-speed  
CI  
input capacitance  
-
-
-
2
-
pF  
nA  
ILL  
LOW-level leakage  
current  
VI = 0 V; on-chip pull-up  
resistor disabled  
3
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Table 10. Static characteristics …continued  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ[1]  
Max  
Unit  
ILH  
HIGH-level leakage  
current  
VI = VDD(IO); on-chip  
pull-down resistor  
disabled  
-
3
-
nA  
VI = 5 V  
-
-
-
20  
-
nA  
nA  
IOZ  
OFF-state output  
current  
VO = 0 V to VDD(IO)  
;
3
on-chip pull-up/down  
resistors disabled;  
absolute value  
VI  
input voltage  
pin configured to provide  
a digital function;  
VDD(IO) 2.2 V  
VDD(IO) = 0 V  
0
0
0
-
-
-
-
5.5  
V
V
V
V
3.6  
VO  
output voltage  
output active  
VDD(IO)  
5.5  
VIH  
HIGH-level input  
voltage  
0.7   
VDD(IO)  
VIL  
LOW-level input voltage  
0
-
0.3   
V
VDD(IO)  
Vhys  
VOH  
VOL  
IOH  
IOL  
hysteresis voltage  
0.1   
VDD(IO)  
-
-
V
HIGH-level output  
voltage  
IOH = 8 mA  
VDD(IO)  
0.4  
-
-
V
LOW-level output  
voltage  
IOL = 8 mA  
-
-
0.4  
V
HIGH-level output  
current  
VOH = VDD(IO) 0.4 V  
VOL = 0.4 V  
8  
8
-
-
-
mA  
mA  
mA  
mA  
A  
A  
A  
LOW-level output  
current  
-
-
[12]  
[12]  
IOHS  
IOLS  
Ipd  
HIGH-level short-circuit drive HIGH; connected to  
output current ground  
-
86  
76  
-
LOW-level short-circuit drive LOW; connected to  
output current  
-
-
VDD(IO)  
[14][15]  
[16]  
pull-down current  
VI = VDD(IO)  
-
62  
62  
0
[14][15]  
[16]  
Ipu  
pull-up current  
VI = 0 V  
-
-
VDD(IO) < VI 5 V  
-
-
Open-drain I2C0-bus pins  
VIH  
HIGH-level input  
voltage  
0.7   
VDD(IO)  
-
-
V
V
V
V
VIL  
LOW-level input voltage  
0
0.14  
0.3   
VDD(IO)  
Vhys  
VOL  
hysteresis voltage  
0.1   
VDD(IO)  
-
-
-
LOW-level output  
voltage  
IOLS = 3 mA  
-
0.4  
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Table 10. Static characteristics …continued  
Tamb = 40 C to +85 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
VI = VDD(IO)  
VI = 5 V  
Min  
Typ[1]  
4.5  
-
Max  
-
Unit  
A  
[13]  
ILI  
input leakage current  
-
-
10  
A  
Oscillator pins  
Vi(XTAL1)  
input voltage on pin  
XTAL1  
0.5  
0.5  
-
-
-
-
1.2  
1.2  
0.8  
V
Vo(XTAL2)  
Cio  
output voltage on pin  
XTAL2  
V
[17]  
input/output  
capacitance  
pF  
USB0 pins[18]  
VI  
input voltage  
on pins USB0_DP;  
USB0_DM; USB0_VBUS  
VDD(IO) 2.2 V  
VDD(IO) = 0 V  
0
-
5.25  
3.6  
V
0
-
V
Rpd  
VIC  
pull-down resistance  
on pin USB0_VBUS  
high-speed mode  
48  
50  
800  
64  
200  
-
80  
k  
mV  
mV  
common-mode input  
voltage  
500  
2500  
full-speed/low-speed  
mode  
chirp mode  
50  
-
600  
mV  
mV  
Vi(dif)  
differential input voltage  
100  
400  
1100  
USB1 pins (USB1_DP/USB1_DM)[18]  
[18]  
[19]  
IOZ  
OFF-state output  
current  
0 V < VI < 3.3 V  
-
-
10  
A  
VBUS  
VDI  
bus supply voltage  
-
-
-
5.25  
-
V
V
differential input  
(D+) (D)  
0.2  
sensitivity voltage  
VCM  
differential common  
mode voltage range  
includes VDI range  
0.8  
0.8  
-
-
2.5  
2.0  
V
V
Vth(rs)se  
single-ended receiver  
switching threshold  
voltage  
VOL  
LOW-level output  
voltage for  
low-/full-speed  
RL of 1.5 kto 3.6 V  
RL of 15 kto GND  
-
-
-
0.18  
3.5  
V
V
VOH  
HIGH-level output  
voltage (driven) for  
low-/full-speed  
2.8  
Ctrans  
ZDRV  
transceiver capacitance pin to GND  
-
-
-
20  
pF  
[20]  
driver output  
with 33 series resistor;  
steady state drive  
36  
44.1  
impedance for driver  
which is not high-speed  
capable  
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.  
[2] Dynamic characteristics for peripherals are provided for VDD(REG)(3V) 2.7 V.  
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[3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure  
the same ramp-up time for both supply voltages.  
[4] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb = 25 C.  
[5] PLL1 disabled; IRC running; CCLK = 12 MHz.  
[6]  
VBAT = 3.6 V.  
[7] VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz.  
[8] On pin VBAT; Tamb = 25 C.  
[9] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. Input leakage increases when VDD(IO) is floating or grounded. It is recommended to keep  
VDD(REG)(3V3) and VDD(IO) powered in deep power-down mode.  
[10] Vps corresponds to the output of the power switch (see Figure 9) which is determined by the greater of VBAT and VDD(Reg)(3V3)  
.
[11] VDDA(3V3) = 3.3 V; Tamb = 25 C.  
[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.  
[13] To VSS  
.
[14] The values specified are simulated and absolute values.  
[15] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.  
[16] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO)  
[17] The parameter value specified is a simulated value excluding bond capacitance.  
[18] For USB operation 3.0 V VDD((IO) 3.6 V. Guaranteed by design.  
[19] VDD(IO) present.  
.
[20] Includes external resistors of 33   1 % on D+ and D.  
LPC4350_30_20_10  
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32-bit ARM Cortex-M4/M0 microcontroller  
10.1 Power consumption  
002aah611  
100  
IDD(REG)(3V3)  
DD(REG)(3V3)  
(mA()mA)  
204 MHz  
180 MHz  
80  
60  
40  
20  
120 MHz  
60 MHz  
12 MHz  
0
2.2  
2.4  
2.6  
2.8  
3
3.2  
3.4  
3.6  
V
(V)  
DD(REG)(3V3)  
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from SRAM; M0-core in  
reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all  
peripheral clocks disabled.  
Fig 11. Typical supply current versus regulator supply voltage VDD(REG)(3V3) in active  
mode  
002aah612  
100  
IDD(REG)(3V3)  
DD(REG)(3V3)  
(mA()mA)  
204 MHz  
180 MHz  
80  
60  
40  
20  
120 MHz  
60 MHz  
12 MHz  
0
-40  
-15  
10  
35  
60  
85  
temperature (°C)  
Conditions: VDD(REG)(3V3) = 3.3 V, Active mode entered executing code while(1){} from SRAM;  
M0-core in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals  
disabled; all peripheral clocks disabled.  
Fig 12. Typical supply current versus temperature in Active mode  
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002aah613  
100  
85 °CC  
25 °CC  
-40 °CC  
IDD(REG)(3V3)  
DD(REG)(3V3)  
(mA()mA)  
80  
60  
40  
20  
0
12  
36  
60  
84  
108  
132  
156  
180  
204  
CCLK frequency (MHz)  
Conditions: VDD(REG)(3V3) = 3.3 V; Active mode entered executing code while(1){} from SRAM;  
M0-core in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals  
disabled; all peripheral clocks disabled.  
Fig 13. Typical supply current versus frequency in Active mode  
002aah153  
10  
I
DD(REG)(3V3)  
(mA)  
8
6
4
2
0
-40  
-15  
10  
35  
60  
temperature (°C)  
85  
Conditions: VDD(REG)(3V3) = 3.3 V; M0-core in reset; internal pull-up resistors disabled; PLL1  
enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled; core clock CCLK =  
12 MHz.  
Fig 14. Typical supply current versus temperature in Sleep mode  
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32-bit ARM Cortex-M4/M0 microcontroller  
002aah154  
300  
I
DD(REG)(3V3)  
(μA)  
240  
180  
120  
60  
0
-40  
-15  
10  
35  
60  
85  
temperature (°C)  
Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V.  
Fig 15. Typical supply current versus temperature in Deep-sleep mode  
002aah155  
50  
I
DD(REG)(3V3)  
(μA)  
40  
30  
20  
10  
0
-40  
-15  
10  
35  
60  
85  
temperature (°C)  
Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V.  
Fig 16. Typical supply current versus temperature in Power-down mode  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
002aah156  
10  
I
DD(REG)(3V3)  
(μA)  
8
6
4
2
0
-40  
-15  
10  
35  
60  
85  
temperature (°C)  
Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V.  
Fig 17. Typical supply current versus temperature in Deep power-down mode  
002aah150  
80  
60  
40  
20  
0
I
BAT  
(μA)  
-0.4  
-0.2  
0
0.2  
0.4  
0.6  
V
- V  
(V)  
BAT  
DD(REG)(3V3)  
Conditions: VDD(REG)(3V3) = 3.0 V; CCLK = 12 MHz.  
Fig 18. Typical battery supply current in Active mode  
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32-bit ARM Cortex-M4/M0 microcontroller  
002aah157  
10  
8
I
BAT  
(μA)  
6
V
=
3.6 V  
3.0 V  
2.2 V  
BAT  
4
2
0
-40  
-15  
10  
35  
60  
85  
temperature (°C)  
Conditions: VDD(REG)(3V3), VDD(IO) floating.  
Fig 19. Typical battery supply versus temperature in Deep power-down mode  
10.2 Peripheral power consumption  
The typical power consumption at T = 25 C for each individual peripheral is measured as  
follows:  
1. Enable all branch clocks and measure the current IDD(REG)(3V3)  
.
2. Disable the branch clock to the peripheral to be measured and keep all other branch  
clocks enabled.  
3. Calculate the difference between measurement 1 and 2. The result is the peripheral  
power consumption.  
Table 11. Peripheral power consumption  
Peripheral  
Branch clock  
IDD(REG)(3V3) in mA  
Branch clock  
Branch clock  
frequency = 48 MHz  
frequency = 96 MHz  
M0 core  
I2C1  
CLK_M4_M0APP  
CLK_APB3_I2C1  
CLK_APB1_I2C0  
CLK_APB3_DAC  
CLK_APB3_ADC0  
CLK_APB3_ADC1  
CLK_APB3_CAN0  
CLK_APB1_CAN1  
CLK_APB1_MOTOCON  
CLK_APB1_I2S  
3.3  
6.6  
0.01  
0.02  
0.01  
0.05  
0.04  
0.17  
0.17  
0.05  
0.11  
0.95  
0.02  
0.01  
0.02  
0.05  
0.04  
0.17  
0.17  
0.05  
0.11  
1.85  
I2C0  
DAC  
ADC0  
ADC1  
CAN0  
CAN1  
MOTOCON  
I2S  
SPIFI  
CLK_SPIFI,  
CLK_M4_SPIFI  
GPIO  
CLK_M4_GPIO  
0.66  
1.31  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 11. Peripheral power consumption  
Peripheral  
Branch clock  
IDD(REG)(3V3) in mA  
Branch clock  
Branch clock  
frequency = 48 MHz  
frequency = 96 MHz  
LCD  
CLK_M4_LCD  
0.85  
1.05  
0.3  
1.72  
2.09  
0.38  
ETHERNET  
UART0  
CLK_M4_ETHERNET  
CLK_M4_UART0,  
CLK_APB0_UART0  
UART1  
UART2  
UART3  
CLK_M4_UART1,  
CLK_APB0_UART1  
0.27  
0.27  
0.29  
0.48  
0.47  
0.49  
CLK_M4_UART2,  
CLK_APB2_UART2  
CLK_M4_USART3,  
CLK_APB2_UART3  
TIMER0  
TIMER1  
TIMER2  
TIMER3  
SDIO  
CLK_M4_TIMER0  
CLK_M4_TIMER1  
CLK_M4_TIMER2  
CLK_M4_TIMER3  
0.07  
0.07  
0.07  
0.06  
0.79  
0.14  
0.14  
0.15  
0.11  
1.37  
CLK_M4_SDIO,  
CLK_SDIO  
SCT  
CLK_M4_SCT  
0.52  
0.12  
1.05  
0.21  
SSP0  
CLK_M4_SSP0,  
CLK_APB0_SSP0  
SSP1  
CLK_M4_SSP1,  
0.15  
0.28  
CLK_APB2_SSP1  
DMA  
CLK_M4_DMA  
CLK_M4_WWDT  
CLK_M4_QEI  
1.88  
0.05  
0.33  
1.46  
3.71  
0.08  
0.68  
3.32  
WWDT  
QEI  
USB0  
CLK_M4_USB0,  
CLK_USB0  
USB1  
CLK_M4_USB1,  
CLK_USB1  
2.83  
5.03  
RITIMER  
EMC  
CLK_M4_RITIMER  
0.04  
3.6  
0.08  
6.97  
CLK_M4_EMC,  
CLK_M4_EMC_DIV  
SCU  
CLK_M4_SCU  
CLK_M4_CREG  
CLK_PERIPH_SGPIO  
CLK_SPI  
0.09  
0.37  
0.1  
0.23  
0.72  
0.17  
0.11  
CREG  
SGPIO  
SPI  
0.07  
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10.3 BOD  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 12. BOD static characteristics[1]  
Tamb = 25 C; simulated values for nominal processing.  
Symbol Parameter Conditions  
Min  
Typ  
Max  
Unit  
Vth  
threshold voltage interrupt level 0  
assertion  
-
-
2.75  
2.92  
-
-
V
V
de-assertion  
interrupt level 1  
assertion  
-
-
2.85  
3.00  
-
-
V
V
de-assertion  
interrupt level 2  
assertion  
-
-
2.95  
3.12  
-
-
V
V
de-assertion  
interrupt level 3  
assertion  
-
-
3.05  
3.19  
-
-
V
V
de-assertion  
reset level 0  
assertion  
-
-
1.70  
1.85  
-
-
V
V
de-assertion  
reset level 1  
assertion  
-
-
1.80  
1.95  
-
-
V
V
de-assertion  
reset level 2  
assertion  
-
-
1.90  
2.05  
-
-
V
V
de-assertion  
reset level 3  
assertion  
-
-
2.00  
2.15  
-
-
V
V
de-assertion  
[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see  
the LPC43xx user manual.  
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10.4 Electrical pin characteristics  
002aah030  
15  
12  
9
-40 °C  
25 °C  
85 °C  
I
OL  
(mA)  
6
3
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
V
(V)  
OL  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.  
Fig 20. Normal-drive pins; typical LOW level output current IOL versus LOW level output  
voltage VOL  
002aah039  
3.6  
V
OH  
(V)  
3.2  
2.8  
2.4  
2.0  
T = 85 °C  
25 °C  
-40 °C  
0
12  
24  
36  
I
(mA)  
OH  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.  
Fig 21. Normal-drive pins; typical HIGH level output voltage VOL versus HGH level output  
current IOH  
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002aah040  
002aah041  
15  
25  
20  
15  
10  
5
-40 °C  
25 °C  
85 °C  
I
I
OL  
(mA)  
OL  
(mA)  
12  
9
-40 °C  
25 °C  
85 °C  
6
3
0
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
(V)  
0.6  
0
0.1  
0.2  
0.3  
0.4  
0.5  
(V)  
0.6  
V
OL  
V
OL  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;  
normal-drive; EHD = 0x0.  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;  
medium-drive; EHD = 0x1.  
002aah043  
002aah044  
40  
32  
24  
16  
8
60  
45  
30  
15  
0
I
I
OL  
(mA)  
OL  
(mA)  
-40 °C  
25 °C  
85 °C  
-40 °C  
25 °C  
85 °C  
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
(V)  
0.6  
0
0.1  
0.2  
0.3  
0.4  
0.5  
(V)  
0.6  
V
OL  
V
OL  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive;  
EHD = 0x2.  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra  
high-drive; EHD = 0x3.  
Fig 22. High-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL  
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002aah047  
002aah048  
3.6  
3.6  
V
(V)  
3.2  
V
OH  
(V)  
3.2  
OH  
-40 °C  
25 °C  
85 °C  
-40 °C  
25 °C  
85 °C  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
0
8
16  
24  
0
16  
32  
48  
I
(mA)  
I
(mA)  
OH  
OH  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;  
normal-drive; EHD = 0x0.  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;  
medium-drive; EHD = 0x1.  
002aah049  
002aah050  
3.6  
3.6  
V
(V)  
3.2  
V
OH  
(V)  
3.2  
OH  
-40 °C  
25 °C  
85 °C  
-40 °C  
25 °C  
85 °C  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
0
32  
64  
96  
0
40  
80  
120  
I
(mA)  
I
(mA)  
OH  
OH  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive;  
EHD = 0x2.  
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra  
high-drive; EHD = 0x3.  
Fig 23. High-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH  
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002aah450  
20  
0
Ipu  
pu  
(μA)  
+85 °C  
+25 °C  
-40 °C  
-20  
-40  
-60  
-80  
0
1
2
3
4
5
V (V)  
I
Conditions: VDD(IO) = 3.3 V. Simulated values.  
Fig 24. Typical pull-up current Ipu versus input voltage VI  
002aah449  
120  
Ippdd  
pd  
(μA)  
-40 °C  
+25 °C  
+85 °C  
90  
60  
30  
0
0
1
2
3
4
5
V (V)  
I
Conditions: VDD(IO) = 3.3 V. Simulated values.  
Fig 25. Typical pull-down current Ipd versus input voltage VI  
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11. Dynamic characteristics  
11.1 Wake-up times  
Table 13. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep  
power-down modes  
Tamb = 40 C to +85 C  
Symbol Parameter  
Conditions  
Min  
Typ[1]  
Max Unit  
[2]  
twake  
wake-up time from Sleep mode  
3   
5 Tcy(clk)  
-
ns  
Tcy(clk)  
from Deep-sleep and  
Power-down mode  
12  
51  
-
s  
from Deep power-down mode  
after reset  
-
-
250  
250  
-
-
s  
s  
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply  
voltages.  
[2] Tcy(clk) = 1/CCLK with CCLK = CPU clock frequency.  
11.2 External clock for oscillator in slave mode  
Remark: The input voltage on the XTAL1/2 pins must be 1.2 V (see Table 10). For  
connecting the oscillator to the XTAL pins, also see Section 13.2 and Section 13.4.  
Table 14. Dynamic characteristic: external clock  
Tamb = 40 C to +85 C; VDD(IO) over specified ranges.[1]  
Symbol  
fosc  
Parameter  
Conditions  
Min  
Max  
25  
Unit  
MHz  
ns  
oscillator frequency  
clock cycle time  
clock HIGH time  
clock LOW time  
1
Tcy(clk)  
tCHCX  
tCLCX  
40  
1000  
Tcy(clk) 0.4  
Tcy(clk) 0.4  
Tcy(clk) 0.6 ns  
Tcy(clk) 0.6 ns  
[1] Parameters are valid over operating temperature range unless otherwise specified.  
t
CHCX  
t
CLCX  
T
cy(clk)  
002aag698  
Fig 26. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)  
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11.3 Crystal oscillator  
Table 15. Dynamic characteristic: oscillator  
Tamb = 40 C to +85 C; VDD(IO) over specified ranges; 2.2 V VDD(REG)(3V3) 3.6 V.[1]  
Symbol  
Parameter  
Conditions  
Min  
Typ[2]  
Max  
Unit  
Low-frequency mode (1 MHz - 20 MHz)[5]  
[3][4]  
[3][4]  
tjit(per)  
period jitter time  
5 MHz crystal  
10 MHz crystal  
15 MHz crystal  
-
-
-
13.2  
6.6  
-
-
-
ps  
ps  
ps  
4.8  
High-frequency mode (20 MHz - 25 MHz)[6]  
tjit(per)  
period jitter time  
20 MHz crystal  
25 MHz crystal  
-
-
4.3  
3.7  
-
-
ps  
ps  
[1] Parameters are valid over operating temperature range unless otherwise specified.  
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply  
voltages.  
[3] Indicates RMS period jitter.  
[4] PLL-induced jitter is not included.  
[5] Select HF = 0 in the XTAL_OSC_CTRL register.  
[6] Select HF = 1 in the XTAL_OSC_CTRL register.  
11.4 IRC oscillator  
Table 16. Dynamic characteristic: IRC oscillator  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V.[1]  
Symbol Parameter  
fosc(RC) internal RC oscillator  
frequency  
Conditions  
Min  
Typ[2]  
Max  
Unit  
-
11.88  
12.0  
12.12  
MHz  
[1] Parameters are valid over operating temperature range unless otherwise specified.  
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply  
voltages.  
11.5 RTC oscillator  
Table 17. Dynamic characteristic: RTC oscillator  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V or 2.2 V VBAT 3.6 V[1]; typical CRTCX1/2  
20 pF; also see Section 13.3.  
=
Symbol Parameter  
Conditions  
Min  
Typ[2]  
32.768  
280  
Max  
-
Unit  
kHz  
nA  
fi(RTC)  
RTC input frequency  
RTC supply current  
-
-
IDD(RTC)  
800  
[1] Parameters are valid over operating temperature range unless otherwise specified.  
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply  
voltages.  
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11.6 I2C-bus  
Table 18. Dynamic characteristic: I2C-bus pins  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V.[1]  
Symbol  
Parameter  
Conditions  
Min  
Max  
100  
400  
1
Unit  
kHz  
kHz  
MHz  
ns  
fSCL  
SCL clock frequency  
Standard-mode  
Fast-mode  
0
0
0
-
Fast-mode Plus  
[3][4][5][6]  
tf  
fall time  
of both SDA and  
SCL signals  
300  
Standard-mode  
Fast-mode  
20 + 0.1 Cb  
300  
ns  
ns  
s  
s  
s  
s  
s  
s  
s  
s  
s  
ns  
ns  
ns  
Fast-mode Plus  
Standard-mode  
Fast-mode  
-
120  
tLOW  
LOW period of the SCL clock  
HIGH period of the SCL clock  
data hold time  
4.7  
1.3  
0.5  
4.0  
0.6  
0.26  
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus  
Standard-mode  
Fast-mode  
tHIGH  
Fast-mode Plus  
Standard-mode  
Fast-mode  
[2][3][7]  
[8][9]  
tHD;DAT  
0
Fast-mode Plus  
Standard-mode  
Fast-mode  
0
tSU;DAT  
data set-up time  
250  
100  
50  
Fast-mode Plus  
[1] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.  
[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.  
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to  
bridge the undefined region of the falling edge of SCL.  
[4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.  
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at  
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines  
without exceeding the maximum specified tf.  
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should  
allow for this when considering bus timing.  
[7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or  
t
VD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If  
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.  
[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the  
acknowledge.  
[9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.  
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the  
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the  
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.  
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t
f
t
SU;DAT  
70 %  
30 %  
70 %  
30 %  
SDA  
SCL  
t
t
HD;DAT  
VD;DAT  
t
f
t
HIGH  
70 %  
30 %  
70 %  
30 %  
70 %  
30 %  
70 %  
30 %  
t
LOW  
1 / f  
S
SCL  
002aaf425  
Fig 27. I2C-bus pins clock timing  
11.7 I2S-bus interface  
Table 19. Dynamic characteristics: I2S-bus interface pins  
Tamb = 40 C to +85 C ; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.  
Conditions and data refer to I2S0 and I2S1 pins. Simulated values.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
common to input and output  
tr  
rise time  
-
4
4
-
-
-
-
ns  
ns  
ns  
tf  
fall time  
-
tWH  
pulse width HIGH  
on pins I2Sx_TX_SCK  
and I2Sx_RX_SCK  
36  
tWL  
pulse width LOW  
on pins I2Sx_TX_SCK  
and I2Sx_RX_SCK  
36  
-
-
ns  
output  
[1]  
tv(Q)  
data output valid time on pin I2Sx_TX_SDA  
on pin I2Sx_TX_WS  
-
-
4.4  
4.3  
-
-
ns  
ns  
input  
[1]  
[1]  
tsu(D)  
data input set-up time on pin I2Sx_RX_SDA  
on pin I2Sx_RX_WS  
-
0
-
ns  
ns  
ns  
ns  
0.20  
3.7  
3.9  
th(D)  
data input hold time  
on pin I2Sx_RX_SDA  
on pin I2Sx_RX_WS  
-
-
-
-
[1] Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface  
PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns; corresponds to the SCK signal in the  
I2S-bus specification.  
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T
t
f
t
r
cy(clk)  
I2Sx_TX_SCK  
t
t
WL  
WH  
I2Sx_TX_SDA  
I2Sx_TX_WS  
t
v(Q)  
002aag497  
t
v(Q)  
Fig 28. I2S-bus timing (transmit)  
T
t
f
t
r
cy(clk)  
I2Sx_RX_SCK  
I2Sx_RX_SDA  
I2Sx_RX_WS  
t
t
WL  
WH  
t
t
h(D)  
su(D)  
002aag498  
t
t
su(D)  
su(D)  
Fig 29. I2S-bus timing (receive)  
11.8 USART interface  
Table 20. Dynamic characteristics: USART interface  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.  
Simulated values.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tcy(clk)  
clock cycle time  
on pins Ux_UCLK  
-
0.1  
-
s  
output  
tv(Q)  
data output valid time on pin Ux_TXD  
-
6.5  
-
ns  
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11.9 SSP interface  
Table 21. Dynamic characteristics: SSP pins in SPI mode  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Simulated values.  
Symbol Parameter  
Conditions  
Min  
Typ  
40  
Max  
Unit  
ns  
[1]  
Tcy(clk)  
clock cycle time  
full-duplex mode  
-
-
-
-
when only  
20  
ns  
transmitting  
SSP master  
tDS  
data set-up time  
data hold time  
in SPI mode  
in SPI mode  
13.3  
-
-
-
-
-
ns  
ns  
ns  
ns  
tDH  
3.5  
-
tv(Q)  
data output valid time in SPI mode  
data output hold time in SPI mode  
-
-
6.0  
0
th(Q)  
SSP slave  
Tcy(PCLK) PCLK cycle time  
10  
ns  
ns  
ns  
ns  
ns  
ns  
[2]  
Tcy(clk)  
tDS  
clock cycle time  
data set-up time  
data hold time  
120  
-
-
-
-
-
-
in SPI mode  
in SPI mode  
-
-
-
-
10.5  
1
tDH  
tv(Q)  
th(Q)  
data output valid time in SPI mode  
data output hold time in SPI mode  
4.0  
0.2  
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the  
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0  
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).  
[2] Tcy(clk) = 12 Tcy(PCLK)  
.
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Product data sheet  
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111 of 150  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
11.10 SPI interface  
Table 22. Dynamic characteristics: SPI  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Simulated values.  
Symbol Parameter  
Conditions  
Min  
5
Typ  
Max  
Unit  
ns  
Tcy(PCLK) PCLK cycle time  
[1]  
Tcy(clk)  
Master  
tDS  
clock cycle time  
40  
-
-
ns  
data set-up time  
7.2  
-
-
-
-
-
ns  
ns  
ns  
ns  
tDH  
data hold time  
0
-
-
tv(Q)  
th(Q)  
Slave  
tDS  
data output valid time  
data output hold time  
3.7  
1.2  
-
data set-up time  
1.2  
-
-
-
-
-
-
ns  
ns  
tDH  
data hold time  
3 x Tcy(PCLK) + 0.54  
tv(Q)  
data output valid time  
data output hold time  
-
-
3 x Tcy(PCLK) + 9.7 ns  
2 x Tcy(PCLK) + 7.1 ns  
th(Q)  
[1] Tcy(clk) = 8/BASE_SPI_CLK. Tcy(PCLK) = 1/BASE_SPI_CLK.  
11.11 SSP/SPI timing diagrams  
T
cy(clk)  
SCK (CPOL = 0)  
SCK (CPOL = 1)  
MOSI  
t
t
h(Q)  
v(Q)  
DATA VALID  
DATA VALID  
CPHA = 1  
t
t
DH  
DS  
DATA VALID  
DATA VALID  
MISO  
t
t
h(Q)  
v(Q)  
DATA VALID  
DATA VALID  
t
MOSI  
MISO  
t
CPHA = 0  
DS  
DH  
DATA VALID  
DATA VALID  
002aae829  
Fig 30. SSP in SPI mode and SPI master timing  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
T
cy(clk)  
SCK (CPOL = 0)  
SCK (CPOL = 1)  
t
t
DH  
DS  
MOSI  
MISO  
DATA VALID  
DATA VALID  
t
t
h(Q)  
v(Q)  
CPHA = 1  
DATA VALID  
DATA VALID  
t
t
DH  
DS  
MOSI  
MISO  
DATA VALID  
DATA VALID  
DATA VALID  
t
t
h(Q)  
CPHA = 0  
v(Q)  
DATA VALID  
002aae830  
Fig 31. SSP in SPI mode and SPI slave timing  
11.12 SGPIO timing  
The following considerations apply to SGPIO timing:  
• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To  
guarantee that no samples are missed, all input signals should have a duration of at  
least one SGPIO_CLOCK cycle plus the set-up and hold times.  
• When an external clock input is used to generate output data, synchronization causes  
a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one  
output every two SGPIO_CLOCK cycles.  
• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling  
several inputs. This may cause inputs with very similar timings to be sampled with a  
difference of one SGPIO_CLOCK cycle.  
LPC4350_30_20_10  
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Product data sheet  
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113 of 150  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 23. Dynamic characteristics: SGPIO  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Simulated values.  
Symbol Parameter  
tsu(D) data input set-up time  
th(D) data input hold time  
data input set-up time sampled by  
SGPIO_CLOCK  
sampled by  
SGPIO_CLOCK  
Conditions  
Min  
Typ  
Max  
Unit  
ns  
2
-
-
-
-
-
-
[1]  
[1]  
TSGPIO + 2  
TSGPIO + 2  
ns  
tsu(D)  
ns  
[1]  
th(D)  
data input hold time  
TSGPIO + 2  
-
-
ns  
[1]  
[1]  
[1]  
tv(Q)  
th(Q)  
tv(Q)  
data output valid time  
data output hold time  
-
-
-
-
2 x TSGPIO  
ns  
ns  
ns  
TSGPIO  
-3  
data output valid time sampled by  
SGPIO_CLOCK  
3
3
[1]  
th(Q)  
data output hold time sampled by  
SGPIO_CLOCK  
-3  
-
ns  
[1] SGPIO_CLOCK is the internally generated SGPIO clock. TSGPIO = 1/fSGPIO_CLOCK  
.
SGPIO_CLOCK  
CLKINext  
t
h(D)  
sync(CLKINext) = CLKINi  
t
su(D)  
DIN  
DINi  
sync(DIN)  
DINi  
t
v(Q)  
CLKout  
Dout  
t
h(Q)  
DQi  
002aah668  
Fig 32. SGPIO timing  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
11.13 External memory interface  
Table 24. Dynamic characteristics: Static asynchronous external memory interface  
CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V;  
2.7 V VDD(IO) 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a  
normal read operation, the EMC changes the address while CS is asserted resulting in multiple memory accesses.  
Symbol  
Read cycle parameters  
Parameter[1]  
Conditions  
Min  
Typ  
Max  
Unit  
tCSLAV  
CS LOW to address valid  
time  
3.1  
-
-
1.6  
ns  
ns  
[2]  
[2]  
tCSLOEL  
CS LOW to OE LOW time  
0.6 + Tcy(clk)  
WAITOEN  
1.3 + Tcy(clk)  
WAITOEN  
tCSLBLSL  
tOELOEH  
CS LOW to BLS LOW time PB = 1  
OE LOW to OE HIGH time  
0.7  
-
-
1.8  
ns  
ns  
0.6 +  
0.4 +  
(WAITRD   
WAITOEN + 1)   
(WAITRD   
WAITOEN + 1)   
Tcy(clk)  
Tcy(clk)  
tam  
memory access time  
data input hold time  
-
-
16 +  
ns  
(WAITRD   
WAITOEN +1)   
Tcy(clk)  
th(D)  
16  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
tCSHBLSH CS HIGH to BLS HIGH time PB = 1  
0.4  
0.4  
2.0  
2.0  
1.9  
1.4  
2.6  
0
tCSHOEH  
tOEHANV  
tCSHEOR  
CS HIGH to OE HIGH time  
OE HIGH to address invalid PB = 1  
[3]  
[4]  
CS HIGH to end of read  
time  
tCSLSOR  
CS LOW to start of read  
time  
0
-
-
1.8  
1.6  
ns  
ns  
Write cycle parameters  
tCSLAV  
CS LOW to address valid  
3.1  
time  
tCSLDV  
CS LOW to data valid time  
CS LOW to WE LOW time  
3.1  
1.5  
0.7  
-
-
-
-
1.5  
0.2  
1.8  
ns  
ns  
ns  
ns  
tCSLWEL  
tCSLBLSL  
tWELWEH  
PB = 1  
CS LOW to BLS LOW time PB = 1  
WE LOW to WE HIGH time PB = 1  
[2]  
[2]  
0.6 +  
0.4 +  
(WAITWR   
WAITWEN + 1)   
Tcy(clk)  
(WAITWR   
WAITWEN + 1)   
Tcy(clk)  
tWEHDNV  
WE HIGH to data invalid  
time  
PB = 1  
PB = 1  
PB = 0  
0.9 + Tcy(clk)  
0.4 + Tcy(clk)  
0.7  
-
-
2.3 + Tcy(clk)  
0.3 + Tcy(clk)  
1.8  
ns  
ns  
[2]  
[5]  
tWEHEOW WE HIGH to end of write  
time  
tCSLBLSL  
CS LOW to BLS LOW  
-
-
ns  
ns  
[2]  
tBLSLBLSH BLS LOW to BLS HIGH time PB = 0  
0.9 +  
0.1 +  
(WAITWR   
WAITWEN + 1)   
Tcy(clk)  
(WAITWR   
WAITWEN + 1)   
Tcy(clk)  
LPC4350_30_20_10  
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32-bit ARM Cortex-M4/M0 microcontroller  
Table 24. Dynamic characteristics: Static asynchronous external memory interface …continued  
CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V;  
2.7 V VDD(IO) 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a  
normal read operation, the EMC changes the address while CS is asserted resulting in multiple memory accesses.  
Symbol  
Parameter[1]  
Conditions  
Min  
Typ  
Max  
Unit  
[2]  
[5]  
tBLSHEOW BLS HIGH to end of write  
time  
PB = 0  
1.9 + Tcy(clk)  
-
0.5 + Tcy(clk)  
ns  
[1]  
[2]  
tBLSHDNV BLS HIGH to data invalid  
time  
PB = 0  
2.5 + Tcy(clk)  
2.0  
-
-
-
-
1.4 + Tcy(clk)  
ns  
ns  
ns  
ns  
[5]  
tCSHEOW  
CS HIGH to end of write  
time  
0
tBLSHDNV BLS HIGH to data invalid  
time  
PB = 1  
2.5  
1.4  
tWEHANV  
WE HIGH to address invalid PB = 1  
time  
0.9 + Tcy(clk)  
2.4 + Tcy(clk)  
[1] Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.  
[2] Tcy(clk) = 1/CCLK (see LPC43xx User manual).  
[3] End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH  
.
[4] Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL  
.
[5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.  
EMC_An  
t
CSLAV  
t
CSHEOW  
t
t
t
CSLAV  
OEHANV  
EMC_CSn  
EMC_OE  
t
CSLOEL  
t
t
OELOEH  
t
BLSHEOW  
CSHOEH  
t
t
CSLBLSL BLSLBLSH  
EMC_BLSn  
EMC_WE  
t
CSLDV  
am  
t
t
CSHEOR  
BLSHDNV  
t
CSLSOR  
t
h(D)  
EMC_Dn  
EOW  
SOR  
EOR  
002aag699  
Fig 33. External static memory read/write access (PB = 0)  
LPC4350_30_20_10  
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Product data sheet  
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32-bit ARM Cortex-M4/M0 microcontroller  
EMC_An  
t
CSLAV  
t
t
t
CSLAV  
OEHANV  
t
CSHEOW  
EMC_CSn  
EMC_OE  
t
CSLOEL  
t
OELOEH  
t
CSLBLSL  
CSHOEH  
t
CSLBLSL  
EMC_BLSn  
EMC_WE  
t
CSHBLSH  
t
t
CSLWEL WELWEH  
t
WEHEOW  
t
t
BLSHDNV  
am  
t
CSHEOR  
t
CSLDV  
t
t
h(D)  
WEHDNV  
t
CSLSOR  
EMC_Dn  
EOR  
SOR  
EOW  
002aag700  
Fig 34. External static memory read/write access (PB = 1)  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 25. Dynamic characteristics: Dynamic external memory interface  
Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,  
EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 85 C;  
2.2 V VDD(REG)(3V3) 3.6 V; VDD(IO) =3.3 V 10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY  
= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Tcy(clk)  
clock cycle time  
8.4  
-
-
ns  
Common to read and write cycles  
td(DYCSV)  
th(DYCS)  
td(RASV)  
th(RAS)  
DYCS delay time  
-
3.1 + 0.5 Tcy(clk)  
5.1 + 0.5 Tcy(clk) ns  
ns  
4.9 + 0.5 Tcy(clk) ns  
ns  
4.6 + 0.5 Tcy(clk) ns  
ns  
5.9 + 0.5 Tcy(clk) ns  
ns  
5.0 + 0.5 Tcy(clk) ns  
ns  
6.3 + 0.5 Tcy(clk) ns  
ns  
5.1 + 0.5 Tcy(clk) ns  
DYCS hold time  
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)  
3.1 + 0.5 Tcy(clk)  
0.5 + 0.5 Tcy(clk) 1.1 + 0.5 Tcy(clk)  
2.9 + 0.5 Tcy(clk)  
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)  
3.2 + 0.5 Tcy(clk)  
1.3 + 0.5 Tcy(clk) 1.4 + 0.5 Tcy(clk)  
3.1 + 0.5 Tcy(clk)  
0.2 + 0.5 Tcy(clk) 0.8 + 0.5 Tcy(clk)  
3.8 + 0.5 Tcy(clk)  
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)  
-
row address strobe valid delay time  
row address strobe hold time  
column address strobe valid delay time  
column address strobe hold time  
WE valid delay time  
-
-
td(CASV)  
th(CAS)  
td(WEV)  
th(WE)  
-
-
-
WE hold time  
-
td(DQMOUTV) DQMOUT valid delay time  
-
th(DQMOUT)  
td(AV)  
DQMOUT hold time  
address valid delay time  
address hold time  
-
-
th(A)  
-
td(CKEOUTV) CKEOUT valid delay time  
th(CKEOUT) CKEOUT hold time  
Read cycle parameters  
tsu(D) data input set-up time  
th(D) data input hold time  
Write cycle parameters  
td(QV) data output valid delay time  
th(Q) data output hold time  
-
3.1 + 0.5 Tcy(clk)  
0.7 + 0.5 Tcy(clk)  
0.5 Tcy(clk)  
-
ns  
1.5  
0.5  
-
ns  
ns  
-
0.8  
2.2  
-
3.8 + 0.5 Tcy(clk)  
0.7 + 0.5 Tcy(clk)  
6.2 + 0.5 Tcy(clk) ns  
- ns  
0.5 Tcy(clk)  
Table 26. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0]  
delay values  
Tamb = 40 C to 85 C; VDD(IO) =3.3 V 10 %; 2.2 V VDD(REG)(3V3) 3.6 V.  
Symbol Parameter  
td delay time  
Conditions  
delay value  
Min  
Typ  
Max  
Unit  
[1]  
CLKn_DELAY = 0  
CLKn_DELAY = 1  
CLKn_DELAY = 2  
CLKn_DELAY = 3  
CLKn_DELAY = 4  
CLKn_DELAY = 5  
CLKn_DELAY = 6  
CLKn_DELAY = 7  
0.0  
0.4  
0.7  
1.1  
1.4  
1.7  
2.1  
2.5  
0.0  
0.5  
1.0  
1.6  
2.0  
2.6  
3.1  
3.6  
0.0  
0.8  
1.7  
2.5  
3.3  
4.1  
4.9  
5.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
[1] Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual).  
The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =  
CLK2_DELAY = CLK3_DELAY.  
LPC4350_30_20_10  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
EMC_CLKn  
delay > 0  
EMC_CLKn delay t ; programmable CLKn_DELAY  
d
T
cy(clk)  
EMC_CLKn  
delay = 0  
t
- t  
d
t
- t  
d
d(xV)  
h(x)  
t
t
EMC_DYCSn,  
EMC_RAS,  
d(xV)  
h(x)  
EMC_CAS,  
EMC_WE,  
EMC_CKEOUTn,  
EMC_A[22:0],  
EMC_DQMOUTn  
t
- t  
d
t
- t  
d
d(QV)  
h(Q)  
t
d(QV)  
t
h(Q)  
EMC_D[31:0]  
write  
t
t
su(D)  
h(D)  
EMC_D[31:0]  
read; delay > 0  
t
t
su(D)  
h(D)  
EMC_D[31:0]  
read; delay = 0  
002aag703  
For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 26.  
Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK  
register.  
Fig 35. SDRAM timing  
LPC4350_30_20_10  
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Product data sheet  
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LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
11.14 USB interface  
Table 27. Dynamic characteristics: USB0 and USB1 pins (full-speed)  
CL = 50 pF; Rpu = 1.5 kon D+ to VDD(IO); 3.0 V VDD(IO) 3.6 V.  
Symbol  
Parameter  
rise time  
fall time  
Conditions  
10 % to 90 %  
10 % to 90 %  
tr / tf  
Min  
8.5  
7.7  
-
Typ  
Max  
13.8  
13.7  
109  
Unit  
ns  
tr  
-
-
-
tf  
ns  
tFRFM  
differential rise and fall time  
matching  
%
VCRS  
output signal crossover voltage  
source SE0 interval of EOP  
1.3  
160  
2  
-
-
-
2.0  
175  
+5  
V
tFEOPT  
tFDEOP  
see Figure 36  
ns  
ns  
source jitter for differential transition see Figure 36  
to SE0 transition  
tJR1  
receiver jitter to next transition  
18.5  
9  
-
-
-
+18.5  
ns  
ns  
ns  
tJR2  
receiver jitter for paired transitions  
EOP width at receiver  
10 % to 90 %  
+9  
-
[1]  
[1]  
tEOPR1  
must reject as  
EOP; see  
Figure 36  
40  
tEOPR2  
EOP width at receiver  
must accept as  
EOP; see  
82  
-
-
ns  
Figure 36  
[1] Characterized but not implemented as production test. Guaranteed by design.  
T
PERIOD  
crossover point  
extended  
crossover point  
differential  
data lines  
source EOP width: t  
FEOPT  
differential data to  
SE0/EOP skew  
n × T  
+ t  
PERIOD  
FDEOP  
receiver EOP width: t  
, t  
EOPR1 EOPR2  
002aab561  
Fig 36. Differential data-to-EOP transition skew and EOP width  
LPC4350_30_20_10  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 28. Static characteristics: USB0 PHY pins[1]  
Symbol Parameter  
High-speed mode  
Conditions  
Min  
Typ  
Max  
Unit  
[2]  
[3]  
Pcons  
power consumption  
-
68  
-
mW  
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;  
total supply current  
during transmit  
-
-
-
-
-
18  
31  
14  
14  
7
-
-
-
-
-
mA  
mA  
mA  
mA  
mA  
during receive  
with driver tri-stated  
IDDD  
Full-speed/low-speed mode  
Pcons power consumption  
digital supply current  
[2]  
-
15  
-
mW  
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;  
total supply current  
during transmit  
-
-
-
-
-
3.5  
5
-
-
-
-
-
mA  
mA  
mA  
mA  
mA  
during receive  
3
with driver tri-stated  
3
IDDD  
digital supply current  
3
Suspend mode  
IDDA(3V3) analog supply current (3.3 V)  
-
-
-
-
24  
24  
3
-
-
-
-
A  
A  
mA  
A  
with driver tri-stated  
with OTG functionality enabled  
IDDD  
digital supply current  
30  
VBUS detector outputs  
Vth  
threshold voltage  
for VBUS valid  
for session end  
for A valid  
4.4  
0.2  
0.8  
2
-
-
V
-
0.8  
2
V
-
V
for B valid  
-
4
V
Vhys  
hysteresis voltage  
for session end  
A valid  
-
150  
200  
200  
10  
10  
10  
mV  
mV  
mV  
-
B valid  
-
[1] Characterized but not implemented as production test.  
[2] Total average power consumption.  
[3] The driver is active only 20 % of the time.  
11.15 Ethernet  
Table 29. Dynamic characteristics: Ethernet  
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Values guaranteed by  
design.  
Symbol Parameter  
RMII mode  
Conditions  
Min  
Max  
Unit  
[1]  
[1]  
fclk  
clock frequency for ENET_RX_CLK  
clock duty cycle  
-
50  
50  
MHz  
%
clk  
50  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 29. Dynamic characteristics: Ethernet  
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Values guaranteed by  
design.  
Symbol Parameter  
Conditions  
Min  
Max  
Unit  
[1][2]  
[1][2]  
tsu  
set-up time  
for ENET_TXDn, ENET_TX_EN,  
ENET_RXDn, ENET_RX_ER,  
ENET_RX_DV  
4
-
ns  
th  
hold time  
for ENET_TXDn, ENET_TX_EN,  
ENET_RXDn, ENET_RX_ER,  
ENET_RX_DV  
2
-
ns  
MII mode  
[1]  
fclk  
clk  
tsu  
clock frequency for ENET_TX_CLK  
clock duty cycle  
-
25  
50  
-
MHz  
%
[1]  
50  
4
[1][2]  
set-up time  
for ENET_TXDn, ENET_TX_EN,  
ns  
ENET_TX_ER  
[1][2]  
th  
hold time  
for ENET_TXDn, ENET_TX_EN,  
ENET_TX_ER  
2
-
ns  
[1]  
fclk  
clk  
tsu  
clock frequency for ENET_RX_CLK  
clock duty cycle  
-
25  
50  
-
MHz  
%
[1]  
50  
4
[1][2]  
set-up time  
for ENET_RXDn, ENET_RX_ER,  
ns  
ENET_RX_DV  
[1][2]  
th  
hold time  
for ENET_RXDn, ENET_RX_ER,  
ENET_RX_DV  
2
-
ns  
[1] Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input  
capacitance of the receiving device.  
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or  
output level.  
ENET_RX_CLK  
ENET_TX_CLK  
t
su  
t
h
ENET_RXD[n]  
ENET_RX_DV  
ENET_RX_ER  
ENET_TXD[n]  
ENET_TX_EN  
ENET_TX_ER  
002aag210  
Fig 37. Ethernet timing  
LPC4350_30_20_10  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
11.16 SD/MMC  
Table 30. Dynamic characteristics: SD/MMC  
Tamb = 40 C to 85 C, 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V, CL = 20 pF. Simulated  
values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC43xx  
user manual UM10430).  
Symbol Parameter  
fclk clock frequency  
tr  
Conditions  
Min  
Max Unit  
on pin SD_CLK; data transfer mode  
52  
2
2
-
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
rise time  
0.5  
0.5  
6
tf  
fall time  
tsu(D)  
data input set-up time  
on pins SD_DATn as inputs  
on pins SD_CMD as inputs  
on pins SD_DATn as inputs  
on pins SD_CMD as inputs  
on pins SD_DATn as outputs  
on pins SD_CMD as outputs  
on pins SD_DATn as outputs  
on pins SD_CMD as outputs  
7
-
th(D)  
data input hold time  
-1  
1  
-
-
td(QV)  
data output valid delay  
time  
17  
18  
-
-
th(Q)  
data output hold time  
4
4
-
T
cy(clk)  
SD_CLK  
t
t
h(Q)  
d(QV)  
SD_CMD (O)  
SD_DATn (O)  
t
t
su(D)  
h(D)  
SD_CMD (I)  
SD_DATn (I)  
002aag204  
Fig 38. SD/MMC timing  
11.17 LCD  
Table 31. Dynamic characteristics: LCD  
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.  
Simulated values.  
Symbol Parameter  
Conditions  
Min  
Typ  
50  
-
Max Unit  
fclk  
clock frequency  
on pin LCD_DCLK  
-
-
MHz  
ns  
td(QV)  
data output valid  
delay time  
17  
th(Q)  
data output hold time  
8.5  
-
ns  
LPC4350_30_20_10  
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Product data sheet  
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11.18 SPIFI  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 32. Dynamic characteristics: SPIFI  
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. CL = 10 pF. Simulated  
values.  
Symbol  
Tcy(clk)  
tDS  
Parameter  
Min  
9.6  
3.4  
Max  
Unit  
ns  
clock cycle time  
data set-up time  
data hold time  
-
-
ns  
tDH  
-
ns  
tv(Q)  
data output valid time  
data output hold time  
-
8
-
ns  
th(Q)  
5
ns  
T
cy(clk)  
SPIFI_SCK  
t
t
h(Q)  
v(Q)  
DATA VALID  
DATA VALID  
SPIFI data out  
SPIFI data in  
t
t
DH  
DS  
DATA VALID  
DATA VALID  
002aah409  
Fig 39. SPIFI timing  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
12. ADC/DAC electrical characteristics  
Table 33. ADC characteristics  
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
V
VIA  
Cia  
analog input voltage  
0
-
-
-
VDDA(3V3)  
2
analog input  
capacitance  
pF  
[1][2]  
[3]  
ED  
differential linearity error 2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
-
-
-
-
-
-
-
-
-
-
-
0.8  
1.0  
0.8  
1.5  
0.15  
0.15  
0.3  
0.35  
3  
-
-
-
-
-
-
-
-
-
-
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
%
EL(adj)  
integral non-linearity  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
[4]  
EO  
offset error  
[5]  
EG  
gain error  
%
[6]  
ET  
absolute error  
LSB  
LSB  
4  
Rvsi  
Ri  
voltage source interface see Figure 41  
resistance  
-
1/(7 fclk(ADC) k  
Cia)  
[7][8]  
input resistance  
-
-
-
-
-
-
1.2  
4.5  
400  
M  
fclk(ADC) ADC clock frequency  
fs sampling frequency  
MHz  
10-bit resolution; 11 clock  
cycles  
kSamples/s  
2-bit resolution; 3 clock  
cycles  
1.5  
MSamples/s  
[1] The ADC is monotonic, there are no missing codes.  
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 40.  
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after  
appropriate adjustment of gain and offset errors. See Figure 40.  
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the  
ideal curve. See Figure 40.  
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset  
error, and the straight line which fits the ideal transfer curve. See Figure 40.  
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated  
ADC and the ideal transfer curve. See Figure 40.  
[7]  
Tamb = 25 C.  
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 2 k+ 1 / (fs Cia).  
LPC4350_30_20_10  
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32-bit ARM Cortex-M4/M0 microcontroller  
offset  
error  
gain  
error  
E
E
O
G
1023  
1022  
1021  
1020  
1019  
1018  
(2)  
7
code  
out  
(1)  
6
5
4
3
2
1
0
(5)  
(4)  
(3)  
1 LSB  
(ideal)  
1018 1019 1020 1021 1022 1023 1024  
1
2
3
4
5
6
7
V
(LSB  
)
ideal  
IA  
offset error  
E
O
V
− V  
SSA  
DDA(3V3)  
1 LSB =  
1024  
002aaf959  
(1) Example of an actual transfer curve.  
(2) The ideal transfer curve.  
(3) Differential linearity error (ED).  
(4) Integral non-linearity (EL(adj)).  
(5) Center of a step of the actual transfer curve.  
Fig 40. 10-bit ADC characteristics  
LPC4350_30_20_10  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
R
vsi  
LPC43xx  
2 kΩ (analog pin)  
2.2 kΩ (multiplexed pin)  
ADC0_n/ADC1_n  
R
s
ADC  
COMPARATOR  
C
= 2 pF  
ia  
V
EXT  
V
SS  
002aag704  
Rs 1/((7 fclk(ADC) Cia) 2 k  
Fig 41. ADC interface to pins  
Table 34. DAC characteristics  
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
LSB  
LSB  
LSB  
[1]  
[1]  
ED  
differential linearity error 2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
-
-
-
0.8  
1.0  
1.0  
-
-
-
EL(adj)  
integral non-linearity  
code = 0 to 975  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
2.7 V VDDA(3V3) 3.6 V  
2.2 V VDDA(3V3) < 2.7 V  
-
-
-
-
-
-
1
1.5  
0.8  
1.0  
0.3  
1.0  
-
-
LSB  
LSB  
LSB  
%
[1]  
[1]  
EO  
EG  
offset error  
gain error  
-
-
-
-
%
CL  
RL  
ts  
load capacitance  
load resistance  
settling time  
200  
-
pF  
-
k  
s  
[2]  
0.4  
[1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual).  
[2] Settling time is calculated within 1/2 LSB of the final value.  
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32-bit ARM Cortex-M4/M0 microcontroller  
13. Application information  
13.1 LCD panel signal usage  
Table 35. LCD panel connections for STN single panel mode  
External pin  
4-bit mono STN single panel  
8-bit mono STN single panel  
Color STN single panel  
LPC43xx pin  
used  
LCD function LPC43xx pin  
LCD function  
LPC43xx pin  
used  
LCD function  
used  
LCD_VD[23:8]  
LCD_VD7  
LCD_VD6  
LCD_VD5  
LCD_VD4  
LCD_VD3  
LCD_VD2  
LCD_VD1  
LCD_VD0  
LCD_LP  
-
-
-
-
-
-
-
-
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
UD[7]  
UD[6]  
UD[5]  
UD[4]  
UD[3]  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
UD[7]  
UD[6]  
UD[5]  
UD[4]  
UD[3]  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
-
-
-
-
-
-
P4_2  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
UD[3]  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
LCD_ENAB/  
LCDM  
LCDENAB/  
LCDM  
LCDENAB/  
LCDM  
LCDENAB/  
LCDM  
LCD_FP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
LCD_DCLK  
LCD_LE  
LCDDCLK  
LCDLE  
LCDDCLK  
LCDLE  
LCDDCLK  
LCDLE  
LCD_PWR  
GP_CLKIN  
CDPWR  
LCDCLKIN  
LCDPWR  
LCDCLKIN  
LCDPWR  
LCDCLKIN  
Table 36. LCD panel connections for STN dual panel mode  
External pin  
4-bit mono STN dual panel  
8-bit mono STN dual panel  
Color STN dual panel  
LPC43xx pin  
used  
LCD function LPC43xx pin  
LCD function  
LPC43xx pin  
used  
LCD function  
used  
LCD_VD[23:16]  
LCD_VD15  
LCD_VD14  
LCD_VD13  
LCD_VD12  
LCD_VD11  
LCD_VD10  
LCD_VD9  
LCD_VD8  
LCD_VD7  
LCD_VD6  
LCD_VD5  
LCD_VD4  
LCD_VD3  
-
-
-
-
-
-
-
-
PB_4  
PB_5  
PB_6  
P8_3  
P4_9  
P4_10  
P4_8  
P7_5  
LD[7]  
LD[6]  
LD[5]  
LD[4]  
LD[3]  
LD[2]  
LD[1]  
LD[0]  
UD[7]  
UD[6]  
UD[5]  
UD[4]  
UD[3]  
PB_4  
PB_5  
PB_6  
P8_3  
P4_9  
P4_10  
P4_8  
P7_5  
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
LD[7]  
LD[6]  
LD[5]  
LD[4]  
LD[3]  
LD[2]  
LD[1]  
LD[0]  
UD[7]  
UD[6]  
UD[5]  
UD[4]  
UD[3]  
-
-
-
-
-
-
P4_9  
LD[3]  
P4_10  
LD[2]  
P4_8  
LD[1]  
P7_5  
LD[0]  
-
-
-
-
P8_5  
P8_6  
P8_7  
P4_2  
-
-
-
-
P4_2  
UD[3]  
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Product data sheet  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 36. LCD panel connections for STN dual panel mode …continued  
External pin  
4-bit mono STN dual panel  
8-bit mono STN dual panel  
Color STN dual panel  
LPC43xx pin  
used  
LCD function LPC43xx pin  
LCD function  
LPC43xx pin  
used  
LCD function  
used  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
LCD_VD2  
LCD_VD1  
LCD_VD0  
LCD_LP  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
P4_3  
P4_4  
P4_1  
P7_6  
P4_6  
UD[2]  
UD[1]  
UD[0]  
LCDLP  
LCD_ENAB/  
LCDM  
LCDENAB/  
LCDM  
LCDENAB/  
LCDM  
LCDENAB/  
LCDM  
LCD_FP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
P4_5  
P4_7  
P7_0  
P7_7  
PF_4  
LCDFP  
LCD_DCLK  
LCD_LE  
LCDDCLK  
LCDLE  
LCDDCLK  
LCDLE  
LCDDCLK  
LCDLE  
LCD_PWR  
GP_CLKIN  
LCDPWR  
LCDCLKIN  
LCDPWR  
LCDCLKIN  
LCDPWR  
LCDCLKIN  
Table 37. LCD panel connections for TFT panels  
External  
pin  
TFT 12 bit (4:4:4  
mode)  
TFT 16 bit (5:6:5 mode)  
TFT 16 bit (1:5:5:5 mode) TFT 24 bit  
LPC43xx LCD  
LPC43xx  
pin used  
LCD  
function  
LPC43xxpin LCD  
LPC43xx  
pin used  
LCD  
function  
pin used  
function  
used  
PB_0  
PB_1  
PB_2  
PB_3  
P7_1  
P7_2  
-
function  
LCD_VD23 PB_0  
LCD_VD22 PB_1  
LCD_VD21 PB_2  
LCD_VD20 PB_3  
BLUE3  
PB_0  
PB_1  
PB_2  
PB_3  
P7_1  
-
BLUE4  
BLUE3  
BLUE2  
BLUE1  
BLUE0  
-
BLUE4  
BLUE3  
BLUE2  
BLUE1  
BLUE0  
intensity  
-
BLUE7  
BLUE6  
BLUE5  
BLUE4  
BLUE3  
BLUE2  
BLUE1  
BLUE0  
GREEN7  
GREEN6  
GREEN5  
GREEN4  
GREEN3  
GREEN2  
GREEN1  
GREEN0  
RED7  
BLUE2  
BLUE1  
BLUE0  
LCD_VD19  
LCD_VD18  
LCD_VD17  
LCD_VD16  
-
-
-
-
-
-
-
-
-
P7_3  
P7_4  
PB_4  
PB_5  
PB_6  
P8_3  
P4_9  
P4_10  
P4_8  
P7_5  
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
P4_3  
P4_4  
-
-
-
-
-
LCD_VD15 PB_4  
LCD_VD14 PB_5  
LCD_VD13 PB_6  
LCD_VD12 P8_3  
GREEN3  
PB_4  
PB_5  
PB_6  
P8_3  
P4_9  
P4_10  
-
GREEN5  
GREEN4  
GREEN3  
GREEN2  
GREEN1  
GREEN0  
-
PB_4  
PB_5  
PB_6  
P8_3  
P4_9  
P4_10  
-
GREEN4  
GREEN3  
GREEN2  
GREEN1  
GREEN0  
intensity  
-
GREEN2  
GREEN1  
GREEN0  
LCD_VD11  
LCD_VD10  
LCD_VD9  
LCD_VD8  
LCD_VD7  
LCD_VD6  
LCD_VD5  
LCD_VD4  
LCD_VD3  
LCD_VD2  
LCD_VD1  
-
-
-
-
-
-
-
-
-
-
-
-
P8_4  
RED3  
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
-
RED4  
RED3  
RED2  
RED1  
RED0  
-
P8_4  
P8_5  
P8_6  
P8_7  
P4_2  
P4_3  
-
RED4  
RED3  
RED2  
RED1  
RED0  
intensity  
-
P8_5  
RED2  
RED6  
P8_6  
RED1  
RED5  
P8_7  
RED0  
RED4  
-
-
-
-
-
-
RED3  
RED2  
-
-
RED1  
LPC4350_30_20_10  
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Table 37. LCD panel connections for TFT panels …continued  
External  
pin  
TFT 12 bit (4:4:4  
mode)  
TFT 16 bit (5:6:5 mode)  
TFT 16 bit (1:5:5:5 mode) TFT 24 bit  
LPC43xx LCD  
LPC43xx  
pin used  
LCD  
function  
LPC43xxpin LCD  
LPC43xx  
pin used  
LCD  
function  
pin used  
function  
used  
function  
LCD_VD0  
LCD_LP  
-
-
-
-
-
-
P4_1  
P7_6  
RED0  
P7_6  
LCDLP  
P7_6  
LCDLP  
P7_6  
LCDLP  
LCDLP  
LCD_ENAB P4_6  
/LCDM  
LCDENAB/ P4_6  
LCDM  
LCDENAB/ P4_6  
LCDM  
LCDENAB/ P4_6  
LCDM  
LCDENAB/  
LCDM  
LCD_FP  
LCD_DCLK P4_7  
LCD_LE P7_0  
P4_5  
LCDFP  
LCDDCLK P4_7  
LCDLE P7_0  
P4_5  
LCDFP  
P4_5  
P4_7  
P7_0  
P7_7  
LCDFP  
LCDDCLK P4_7  
LCDLE P7_0  
P4_5  
LCDFP  
LCDDCLK  
LCDLE  
LCDDCLK  
LCDLE  
LCD_PWR P7_7  
GP_CLKIN PF_4  
LCDPWR P7_7  
LCDCLKIN PF_4  
LCDPWR  
LCDPWR P7_7  
LCDCLKIN PF_4  
LCDPWR  
LCDCLKIN  
LCDCLKIN PF_4  
13.2 Crystal oscillator  
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see  
LPC43xx user manual).  
The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be  
boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.  
The oscillator can operate in one of two modes: slave mode and oscillation mode.  
• In slave mode, couple the input clock signal with a capacitor of 100 pF (CC in  
Figure 42), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this  
configuration can be left unconnected.  
• External components and models used in oscillation mode are shown in Figure 43,  
and in Table 38 and Table 39. Since the feedback resistance is integrated on chip,  
only a crystal and the capacitances CX1 and CX2 need to be connected externally in  
case of fundamental mode oscillation L, CL and RS represent the fundamental  
frequency). The capacitance CP in Figure 43 represents the parallel package  
capacitance and must not be larger than 7 pF. Parameters FC, CL, RS and CP are  
supplied by the crystal manufacturer.  
Table 38. Recommended values for CX1/X2 in oscillation mode (crystal and external  
components parameters) low frequency mode  
Fundamental oscillation  
frequency  
Maximum crystal series  
resistance RS  
External load capacitors  
CX1, CX2  
2 MHz  
4 MHz  
8 MHz  
< 200   
< 200   
< 200   
< 200   
< 200   
< 200   
< 200   
< 200   
33 pF, 33 pF  
39 pF, 39 pF  
56 pF, 56 pF  
18 pF, 18 pF  
39 pF, 39 pF  
56 pF, 56 pF  
18 pF, 18 pF  
39 pF, 39 pF  
LPC4350_30_20_10  
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Table 38. Recommended values for CX1/X2 in oscillation mode (crystal and external  
components parameters) low frequency mode …continued  
Fundamental oscillation  
frequency  
Maximum crystal series  
resistance RS  
External load capacitors  
CX1, CX2  
12 MHz  
16 MHz  
20 MHz  
< 160   
< 160   
< 120   
< 80   
18 pF, 18 pF  
39 pF, 39 pF  
18 pF, 18 pF  
33 pF, 33 pF  
18 pF, 18 pF  
33 pF, 33 pF  
<100   
< 80   
Table 39. Recommended values for CX1/X2 in oscillation mode (crystal and external  
components parameters) high frequency mode  
Fundamental oscillation  
frequency  
Maximum crystal series  
resistance RS  
External load capacitors CX1  
Cx2  
,
15 MHz  
20 MHz  
< 80   
< 80   
< 100   
18 pF, 18 pF  
39 pF, 39 pF  
47 pF, 47 pF  
LPC43xx  
XTAL1  
C
i
C
g
100 pF  
002aag379  
Fig 42. Slave mode operation of the on-chip oscillator  
LPC43xx  
L
XTAL1  
XTAL2  
C
C
P
=
L
XTAL  
R
S
C
C
X2  
X1  
002aag380  
Fig 43. Oscillator modes with external crystal model used for CX1/CX2 evaluation  
LPC4350_30_20_10  
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Product data sheet  
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13.3 RTC oscillator  
In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and  
C
C
RTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and  
RTCX2 are CRTCX1/2 = 20 (typical) 4 pF.  
An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended  
amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of  
5 pF to 10 pF. Vi(RMS) must be lower than 450 mV. See Figure 42 for a similar slave-mode  
set-up that uses the crystal oscillator.  
LPC43xx  
RTCX1  
RTCX2  
XTAL  
C
C
RTCX2  
RTCX1  
002aah148  
Fig 44. RTC 32 kHz oscillator circuit  
13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines  
Connect the crystal on the PCB as close as possible to the oscillator input and output pins  
of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone  
crystal usage have a common ground plane. Also connect the external components to the  
ground plain. To keep the noise coupled in via the PCB as small as possible, make loops  
and parasitics as small as possible. Choose smaller values of Cx1 and Cx2 if parasitics  
increase in the PCB layout.  
Ensure that no high-speed or high-drive signals are near the RTCX1/2 signals.  
13.5 Standard I/O pin configuration  
Figure 45 shows the possible pin modes for standard I/O pins with analog input function:  
• Digital output driver enabled/disabled  
• Digital input: Pull-up enabled/disabled  
• Digital input: Pull-down enabled/disabled  
• Digital input: Repeater mode enabled/disabled  
• Digital input: Input buffer enabled/disabled  
• Analog input  
The default configuration for standard I/O pins is input buffer disabled and pull-up  
enabled. The weak MOS devices provide a drive capability equivalent to pull-up and  
pull-down resistors.  
LPC4350_30_20_10  
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VDDIO  
ESD  
enable output driver  
data output from core  
PIN  
slew rate bit EHS  
input buffer enable bit EZI  
data input to core  
glitch  
filter  
filter select bit ZIF  
pull-up enable bit EPUN  
ESD  
pull-down enable bit EPD  
analog I/O  
VSSIO  
002aah028  
The glitch filter rejects pulses of typical 12 ns width.  
Fig 45. Standard I/O pin configuration with analog input  
13.6 Reset pin configuration  
V
ps  
V
ps  
V
ps  
R
pu  
ESD  
20 ns RC  
GLITCH FILTER  
reset  
PIN  
ESD  
V
SS  
002aag702  
Fig 46. Reset pin configuration  
LPC4350_30_20_10  
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Product data sheet  
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14. Package outline  
LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm  
SOT740-2  
B
A
D
ball A1  
index area  
A
2
A
E
A
1
detail X  
C
e
1
y
1 C  
y
∅ v M  
∅ w M  
b
C
C
A
B
e
1/2 e  
T
R
N
L
P
M
K
H
F
e
J
e
2
G
E
C
A
1/2 e  
D
B
ball A1  
index area  
1
3
5
7
9
11  
13  
15  
2
4
6
8
10  
12  
14  
16  
X
5
scale  
10 mm  
0
DIMENSIONS (mm are the original dimensions)  
A
UNIT  
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max  
0.45  
0.35  
1.1  
0.9  
0.55 17.2 17.2  
0.45 16.8 16.8  
mm  
1.55  
1
15  
15  
0.25  
0.1  
0.12 0.35  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
- - -  
JEDEC  
JEITA  
05-06-16  
05-08-04  
SOT740-2  
MO-192  
- - -  
Fig 47. Package outline LBGA256 package  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
134 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
TFBGA180: thin fine-pitch ball grid array package; 180 balls  
SOT570-3  
D
B
A
ball A1  
index area  
A
2
E
A
A
1
detail X  
e
1
C
M
M
∅ v  
∅ w  
C
C
A
B
e
1/2 e  
b
y
1
y
C
P
N
M
K
H
L
J
e
e
2
G
E
F
1/2 e  
D
B
C
A
ball A1  
index area  
1
3
5
7
9
11  
13  
2
4
6
8
10  
12  
14  
X
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max 1.20 0.40 0.80 0.50 12.1 12.1  
nom 1.06 0.35 0.71 0.45 12.0 12.0  
mm  
0.8  
10.4 10.4 0.15 0.05 0.12  
0.1  
min  
0.95 0.30 0.65 0.40 11.9 11.9  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
JEITA  
08-07-09  
10-04-15  
SOT570-3  
Fig 48. Package outline of the TFBGA180 package  
LPC4350_30_20_10  
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Product data sheet  
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135 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm  
SOT926-1  
D
B
A
ball A1  
index area  
A
2
E
A
A
1
detail X  
e
1
C
M
∅ v  
∅ w  
C
C
A
B
b
e
1/2 e  
y
1
y
M
C
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e  
ball A1  
index area  
1
2
3
4
5
6
7
8
9
10  
X
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
UNIT  
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max  
0.4  
0.3  
0.8  
0.65  
0.5  
0.4  
9.1  
8.9  
9.1  
8.9  
mm  
1.2  
0.8  
7.2  
7.2  
0.15 0.05 0.08  
0.1  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
- - -  
JEDEC  
JEITA  
05-12-09  
05-12-22  
SOT926-1  
- - -  
- - -  
Fig 49. Package outline of the TFBGA100 package  
LPC4350_30_20_10  
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Product data sheet  
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136 of 150  
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32-bit ARM Cortex-M4/M0 microcontroller  
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm  
SOT486-1  
y
X
A
108  
109  
73  
72  
Z
E
e
H
A
E
2
A
E
(A )  
3
A
1
θ
w M  
p
L
p
b
L
pin 1 index  
detail X  
37  
144  
1
36  
v
M
A
Z
w M  
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
Z
E
θ
1
2
3
p
D
max.  
7o  
0o  
0.15 1.45  
0.05 1.35  
0.27 0.20 20.1 20.1  
0.17 0.09 19.9 19.9  
22.15 22.15  
21.85 21.85  
0.75  
0.45  
1.4  
1.1  
1.4  
1.1  
mm  
1.6  
0.25  
1
0.2 0.08 0.08  
0.5  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-03-14  
03-02-20  
SOT486-1  
136E23  
MS-026  
Fig 50. Package outline for the LQFP144 package  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
137 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
15. Soldering  
Footprint information for reflow soldering of LBGA256 package  
SOT740-2  
Hx  
P
P
Hy  
see detail X  
Generic footprint pattern  
Refer to the package outline drawing for actual layout  
solder land  
solder paste deposit  
solder land plus solder paste  
SL  
SP  
SR  
occupied area  
solder resist  
detail X  
DIMENSIONS in mm  
P
SL  
SP  
SR  
Hx  
Hy  
1.00  
0.450 0.450 0.600 17.500 17.500  
sot740-2_fr  
Fig 51. Reflow soldering of the LBGA256 package  
LPC4350_30_20_10  
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Product data sheet  
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138 of 150  
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NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Footprint information for reflow soldering of TFBGA180 package  
SOT570-3  
Hx  
P
P
Hy  
see detail X  
Generic footprint pattern  
Refer to the package outline drawing for actual layout  
solder land  
solder paste deposit  
solder land plus solder paste  
SL  
SP  
SR  
occupied area  
solder resist  
detail X  
DIMENSIONS in mm  
P
SL  
SP  
SR  
Hx  
Hy  
0.80  
0.400 0.400 0.550 12.575 12.575  
sot570-3_fr  
Fig 52. Reflow soldering of the TFBGA180 package  
LPC4350_30_20_10  
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Product data sheet  
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139 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Footprint information for reflow soldering of LQFP144 package  
SOT486-1  
Hx  
Gx  
(0.125)  
P2  
P1  
Hy Gy  
By  
Ay  
C
D2 (8×)  
D1  
Bx  
Ax  
Generic footprint pattern  
Refer to the package outline drawing for actual layout  
solder land  
occupied area  
DIMENSIONS in mm  
P1 P2 Ax  
Ay  
Bx  
By  
C
D1  
D2  
Gx  
Gy  
Hx  
Hy  
0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550  
sot486-1_fr  
Fig 53. Reflow soldering of the LQFP144 package  
LPC4350_30_20_10  
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Product data sheet  
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140 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Footprint information for reflow soldering of TFBGA100 package  
SOT926-1  
Hx  
P
P
Hy  
see detail X  
Generic footprint pattern  
Refer to the package outline drawing for actual layout  
solder land  
solder paste deposit  
solder land plus solder paste  
SL  
SP  
SR  
occupied area  
solder resist  
detail X  
DIMENSIONS in mm  
P
SL  
SP  
SR  
Hx  
Hy  
0.80  
0.330 0.400 0.480 9.400 9.400  
sot926-1_fr  
Fig 54. Reflow soldering of the TFBGA100 package  
LPC4350_30_20_10  
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Product data sheet  
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32-bit ARM Cortex-M4/M0 microcontroller  
16. Abbreviations  
Table 40. Abbreviations  
Acronym  
ADC  
Description  
Analog-to-Digital Converter  
AHB  
Advanced High-performance Bus  
Advanced Peripheral Bus  
APB  
API  
Application Programming Interface  
BrownOut Detection  
BOD  
CAN  
Controller Area Network  
CMAC  
CSMA/CD  
DAC  
Cipher-based Message Authentication Code  
Carrier Sense Multiple Access with Collision Detection  
Digital-to-Analog Converter  
Direct Current-to-Direct Current  
Direct Memory Access  
DC-DC  
DMA  
GPIO  
IRC  
General-Purpose Input/Output  
Internal RC  
IrDA  
Infrared Data Association  
JTAG  
LCD  
Joint Test Action Group  
Liquid Crystal Display  
LSB  
Least Significant Bit  
MAC  
MCU  
MIIM  
n.c.  
Media Access Control  
MicroController Unit  
Media Independent Interface Management  
not connected  
OHCI  
OTG  
PHY  
Open Host Controller Interface  
On-The-Go  
Physical Layer  
PLL  
Phase-Locked Loop  
PMC  
PWM  
RIT  
Power Mode Control  
Pulse Width Modulator  
Repetitive Interrupt Timer  
RMII  
Reduced Media Independent Interface  
Synchronous Dynamic Random Access Memory  
Single Instruction Multiple Data  
Serial Peripheral Interface  
Serial Synchronous Interface  
Synchronous Serial Port  
SDRAM  
SIMD  
SPI  
SSI  
SSP  
UART  
ULPI  
USART  
USB  
Universal Asynchronous Receiver/Transmitter  
UTMI+ Low Pin Interface  
Universal Synchronous Asynchronous Receiver/Transmitter  
Universal Serial Bus  
UTMI  
USB2.0 Transceiver Macrocell Interface  
LPC4350_30_20_10  
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32-bit ARM Cortex-M4/M0 microcontroller  
17. References  
[1] ES_LPC43X0_A (LPC4350, LPC4330, LPC4320, LPC4310 Rev A errata).  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
143 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
18. Revision history  
Table 41. Revision history  
Document ID  
Release date Data sheet status  
20131211 Product data sheet  
• Description of RESET pin updated in Table 3.  
Change notice Supersedes  
LPC4350_30_20_10 v.4.1  
Modifications:  
-
LPC4350_30_20_10 v.4  
• Layout of local SRAM at address 0x1008 0000 clarified in Figure 7  
“LPC4350/30/20/10 Memory mapping (overview)”.  
• Maximum value for Vi(RMS) added in Section 13.3 “RTC oscillator”.  
• VO for RTC_ALARM pin added in Table 10.  
• RTC_ALARM and WAKEUPn pins added to Table 10.  
• Table note 9 added in Table 10.  
• Timing parameters in Table 30 “Dynamic characteristics: SD/MMC” corrected.  
• Band gap characteristics removed.  
• OTP memory size available for general purpose use corrected.  
• Part LPC4350FBD208 removed.  
LPC4350_30_20_10 v.4  
20130326  
Product data sheet  
-
LPC4350_30_20_10 v.3.7  
• Parameter ILH (High-level leakage current) for condition VI = 5 V changed to 20 nA  
(max). See Table 10.  
• Parameter VDDA(3V3) added for pins USB0_VDDA3V3_DRIVER and  
USB0_VDDA3V3 in Table 10.  
• SPI timing data added. See Table 22.  
• SGPIO timing data added. See Table 23.  
• SPI and SGPIO peripheral power consumption added in Table 11.  
• Data sheet status changed to Product data sheet.  
• Corrected max voltage on pins USB0_DP, USB0_DM, USB0_VBUS, USB1_DP, and  
USB1_DM in Table 6 and Table 10 to be consistent with USB specifications.  
LPC4350_30_20_10 v.3.7  
Modifications:  
20130131  
Preliminary data sheet  
-
LPC4350_30_20_10 v.3.6  
• SGPIO and SPI location corrected in Figure 1.  
• SGPIO-to-DMA connection corrected in Figure 7.  
• Power consumption in active mode corrected. See parameter IDD(REG)(3V3) in Table 10  
and graphs Figure 12, Figure 13, and Figure 14.  
• Parameter name IDD(ADC) changed to IDDA in Table 10.  
• Figure 21 “Band gap voltage for different temperatures and process conditions” and  
Table 13 “Band gap characteristics” corrected.  
• Added note to limit data in Table 24 “Dynamic characteristics: Static asynchronous  
external memory interface” to single memory accesses.  
• Value of parameter IDD(REG)(3V3) in deep power-down increased to 0.03 μA in  
Table 10.  
• Value of parameter IDD(IO) in deep power-down increased to 0.05 μA in Table 10.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
144 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 41. Revision history …continued  
Document ID  
Release date Data sheet status  
20121119 Preliminary data sheet  
• Table 13 “Band gap characteristics” added.  
Change notice Supersedes  
LPC4350_30_20_10 v.3.6  
Modifications:  
-
LPC4350_30_20_10 v.3.5  
• Power consumption for M0 core added in Table 11 “Peripheral power consumption”.  
• Section 7.22.10 “Power Management Controller (PMC)” added.  
• Table 10, added Table note 2: “Dynamic characteristics for peripherals are provided  
for VDD(REG)(3V3) 2.7 V.”  
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC  
is connected to ADC0 and ADC1. See Table 3.  
• Use of C_CAN peripheral restricted in Section 2.  
• ADC channels limited to a total of 8 channels shared between ADC0 and ADC1.  
• Minimum value for parameter VIL changed to 0 V in Table 10 “Static characteristics”.  
LPC4350_30_20_10 v.3.5  
Modifications:  
20121011  
Preliminary data sheet  
-
LPC4350_30_20_10 v.3.4  
• Temperature range for simulated timing characteristics corrected to Tamb = 40 C to  
+85 C in Section 11 “Dynamic characteristics”.  
• SPIFI timing added. See Section 11.15.  
• SPIFI maximum data rate changed to 52 MB per second.  
• Editorial updates.  
• Figure 25 and Figure 26 updated for full temperature range.  
• Section 7.23 “Serial Wire Debug/JTAG” updated.  
• The following changes were made on the TFBGA180 pinout in Table 3:  
–
–
–
–
–
–
P1_13 moved from ball D6 to L8.  
P7_5 moved from ball C7 to A7.  
PF_4 moved from ball L8 to D6.  
RESET moved from ball B7 to C7.  
RTCX2 moved from ball A7 to B7.  
Ball G10 changed from VSS to VDDIO.  
LPC4350_30_20_10 v.3.4  
Modifications:  
20120904  
Preliminary data sheet  
-
LPC4350_30_20_10 v.3.3  
• SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin  
P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.  
• Minimum value for all supply voltages changed to -0.5 V in Table 6.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
145 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Table 41. Revision history …continued  
Document ID  
Release date Data sheet status  
20120821 Preliminary data sheet  
Change notice Supersedes  
LPC4350_30_20_10 v.3.3  
Modifications:  
-
LPC4350_30_20_10 v.3.2  
• Parameter twake updated in Table 13 for wake-up from deep power-down mode and  
reset.  
• Dynamic characteristics of the SD/MMC controller updated in Table 28.  
• Dynamic characteristics of the LCD controller updated in Table 29.  
• Dynamic characteristics of the SSP controller updated in Table 21.  
• Minimum value of VI for conditions “USB0 pins USB0_DP; USB0_DM;  
USB0_VBUS”,“USB0 pins USB0_ID; USB0_RREF”, and “USB1 pins USB1_DP and  
USB1_DM” changed to 0.3 V in Table 6.  
• Parameters IIL and IIH renamed to ILL and ILH in Table 10.  
• AES removed. AES is available on parts LPC43Sxx only.  
• Pin configuration diagrams corrected for LQFP packages (Figure 5 and Figure 6).  
• Figure 10 updated.  
• All power consumption data updated in Table 10 and Section 10.1 “Power  
consumption”.  
• BOD levels updated in Table 12.  
• SWD debug option removed for Cortex-M0 core.  
LPC4350_30_20_10 v.3.2  
LPC4350_30_20_10 v.3.1  
LPC4350_30_20_10 v.3  
LPC4350_30_20_10 v.2.1  
LPC4350_30_20_10 v.2  
LPC4350_30_20_10 v.1  
20120604  
20120105  
20111205  
20110923  
20110714  
20101029  
Preliminary data sheet  
Objective data sheet  
Objective data sheet  
Objective data sheet  
Objective data sheet  
Objective data sheet  
-
-
-
-
-
-
LPC4350_30_20_10 v.3.1  
LPC4350_30_20_10 v.3  
LPC4350_30_20_10 v.2.1  
LPC4350_30_20_10 v.2  
LPC4350_30_20_10 v.1  
-
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
146 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
19. Legal information  
19.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
19.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
19.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
147 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
19.4 Trademarks  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
LPC4350_30_20_10  
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Product data sheet  
Rev. 4.1 — 11 December 2013  
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21. Contents  
1
General description. . . . . . . . . . . . . . . . . . . . . . 1  
7.17.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
7.17.7  
7.17.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
7.17.8 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
7.17.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 73  
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Ordering information. . . . . . . . . . . . . . . . . . . . . 5  
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 5  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
4
4.1  
5
7.18  
Digital serial peripherals. . . . . . . . . . . . . . . . . 74  
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
7.18.1  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7  
7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
7.18.2 USART0/2/3. . . . . . . . . . . . . . . . . . . . . . . . . . 75  
7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
7.18.3 SPI serial I/O controller . . . . . . . . . . . . . . . . . 75  
7.18.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
7.18.4 SSP serial I/O controller. . . . . . . . . . . . . . . . . 75  
7.18.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
7.18.5  
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 76  
7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
7.18.6  
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
7.18.7 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
7.18.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
7
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.6.1  
7.6.2  
7.7  
7.8  
7.9  
7.9.1  
7.10  
7.11  
7.12  
7.13  
7.14  
7.15  
7.15.1  
7.16  
7.16.1  
Functional description . . . . . . . . . . . . . . . . . . 61  
Architectural overview . . . . . . . . . . . . . . . . . . 61  
ARM Cortex-M4 processor . . . . . . . . . . . . . . . 61  
ARM Cortex-M0 co-processor . . . . . . . . . . . . 61  
Interprocessor communication . . . . . . . . . . . . 61  
AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 62  
Nested Vectored Interrupt Controller (NVIC) . 62  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 63  
System Tick timer (SysTick) . . . . . . . . . . . . . . 63  
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Global Input Multiplexer Array (GIMA) . . . . . . 63  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 64  
In-System Programming (ISP) . . . . . . . . . . . . 64  
Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 65  
One-Time Programmable (OTP) memory . . . 68  
General-Purpose I/O (GPIO) . . . . . . . . . . . . . 68  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
Configurable digital peripherals . . . . . . . . . . . 68  
State Configurable Timer (SCT) subsystem . . 68  
7.19  
7.19.1  
Counter/timers and motor control . . . . . . . . . 78  
General purpose 32-bit timers/external  
event counters . . . . . . . . . . . . . . . . . . . . . . . . 78  
7.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
7.19.2  
7.19.3  
Motor control PWM . . . . . . . . . . . . . . . . . . . . 78  
Quadrature Encoder Interface (QEI) . . . . . . . 78  
7.19.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
7.19.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 79  
7.19.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
7.19.5 Windowed WatchDog Timer (WWDT) . . . . . . 79  
7.19.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
7.20  
7.20.1  
Analog peripherals. . . . . . . . . . . . . . . . . . . . . 80  
Analog-to-Digital Converter (ADC0/. . . . . . . 1) 80  
7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
7.16.2 Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 69  
7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
7.17  
7.17.1  
7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
7.17.2 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 70  
7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
7.17.3  
7.17.4  
7.20.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
7.20.2 Digital-to-Analog Converter (DAC). . . . . . . . . 80  
7.20.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 70  
General-Purpose DMA (GPDMA). . . . . . . . . . 70  
7.21  
7.21.1  
Peripherals in the RTC power domain. . . . . . 80  
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
7.21.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
7.21.2  
7.22  
Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
System control . . . . . . . . . . . . . . . . . . . . . . . . 81  
Configuration registers (CREG). . . . . . . . . . . 81  
System Control Unit (SCU) . . . . . . . . . . . . . . 81  
Clock Generation Unit (CGU) . . . . . . . . . . . . 81  
Internal RC oscillator (IRC) . . . . . . . . . . . . . . 82  
PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 82  
PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 82  
System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 82  
SD/MMC card interface . . . . . . . . . . . . . . . . . 71  
External Memory Controller (EMC). . . . . . . . . 71  
7.22.1  
7.22.2  
7.22.3  
7.22.4  
7.22.5  
7.22.6  
7.22.7  
7.17.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
7.17.5  
High-speed USB Host/Device/OTG  
interface (USB0). . . . . . . . . . . . . . . . . . . . . . . 72  
7.17.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
7.17.6  
High-speed USB Host/Device interface  
with ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . 72  
continued >>  
LPC4350_30_20_10  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4.1 — 11 December 2013  
149 of 150  
LPC4350/30/20/10  
NXP Semiconductors  
32-bit ARM Cortex-M4/M0 microcontroller  
7.22.8  
7.22.9  
Reset Generation Unit (RGU). . . . . . . . . . . . . 82  
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 82  
19.4  
20  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 148  
Contact information . . . . . . . . . . . . . . . . . . . 148  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149  
7.22.10 Power Management Controller (PMC) . . . . . . 83  
7.23  
21  
Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 84  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 86  
Thermal characteristics . . . . . . . . . . . . . . . . . 87  
8
9
10  
Static characteristics. . . . . . . . . . . . . . . . . . . . 88  
Power consumption . . . . . . . . . . . . . . . . . . . . 95  
Peripheral power consumption. . . . . . . . . . . . 99  
BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101  
Electrical pin characteristics . . . . . . . . . . . . . 102  
10.1  
10.2  
10.3  
10.4  
11  
11.1  
11.2  
11.3  
11.4  
11.5  
11.6  
11.7  
Dynamic characteristics . . . . . . . . . . . . . . . . 106  
Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 106  
External clock for oscillator in slave mode . . 106  
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 107  
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107  
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107  
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108  
I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . 109  
USART interface. . . . . . . . . . . . . . . . . . . . . . 110  
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 111  
SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . 112  
SSP/SPI timing diagrams . . . . . . . . . . . . . . . 112  
SGPIO timing . . . . . . . . . . . . . . . . . . . . . . . . 113  
External memory interface . . . . . . . . . . . . . . 115  
USB interface . . . . . . . . . . . . . . . . . . . . . . . 120  
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
SD/MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123  
SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124  
11.8  
11.9  
11.10  
11.11  
11.12  
11.13  
11.14  
11.15  
11.16  
11.17  
11.18  
12  
ADC/DAC electrical characteristics . . . . . . . 125  
13  
Application information. . . . . . . . . . . . . . . . . 128  
LCD panel signal usage . . . . . . . . . . . . . . . . 128  
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 130  
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 132  
XTAL and RTCX Printed Circuit Board  
13.1  
13.2  
13.3  
13.4  
(PCB) layout guidelines . . . . . . . . . . . . . . . . 132  
Standard I/O pin configuration . . . . . . . . . . . 132  
Reset pin configuration. . . . . . . . . . . . . . . . . 133  
13.5  
13.6  
14  
15  
16  
17  
18  
Package outline . . . . . . . . . . . . . . . . . . . . . . . 134  
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 142  
References . . . . . . . . . . . . . . . . . . . . . . . . . . . 143  
Revision history. . . . . . . . . . . . . . . . . . . . . . . 144  
19  
Legal information. . . . . . . . . . . . . . . . . . . . . . 147  
Data sheet status . . . . . . . . . . . . . . . . . . . . . 147  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 147  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 147  
19.1  
19.2  
19.3  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 11 December 2013  
Document identifier: LPC4350_30_20_10  

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