935299507518 [NXP]
IC TRANSCEIVER CAN 14HVSON;
| 型号： | 935299507518 |
| 厂家： | 
NXP |
| 描述： | IC TRANSCEIVER CAN 14HVSON 电信 电信集成电路 |
| 文件： | 总27页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1043
High-speed CAN transceiver
Rev. 3 — 24 April 2013
Product data sheet
1. General description
The TJA1043 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the
automotive industry, providing differential transmit and receive capability to (a
microcontroller with) a CAN protocol controller.
The TJA1043 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1041A. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and
passive behavior when the supply voltage is turned off. Advanced features include:
• Low-power management controls the power supply throughout the node while
supporting local and remote wake-up with wake-up source recognition
• Several protection and diagnostic functions including bus line short-circuit detection
and battery connection detection
• Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V
These features make the TJA1043 the ideal choice for high speed CAN networks
containing nodes that need to be available all times, even when the internal VIO and VCC
supplies are switched off.
2. Features and benefits
2.1 General
Fully ISO 11898-2 and ISO 11898-5 compliant
Suitable for 12 V and 24 V systems
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
VIO input allows for direct interfacing with 3 V and 5 V microcontrollers
SPLIT voltage output for stabilizing the recessive bus level
Listen-only mode for node diagnosis and failure containment
Available in SO14 and HVSON14 packages
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
TJA1043
NXP Semiconductors
High-speed CAN transceiver
2.2 Low-power management
Very low current Standby and Sleep modes, with local and remote wake-up
Capability to power down the entire node while supporting local, remote and host
wake-up
Wake-up source recognition
Transceiver disengages from the bus (zero load) when VBAT absent
Functional behavior predictable under all supply conditions
2.3 Protection and diagnosis (detection and signalling)
High ESD handling capability on the bus pins
Bus pins and VBAT protected against transients in automotive environments
Transmit Data (TXD) dominant time-out function with diagnosis
TXD-to-RXD short-circuit handler with diagnosis
Thermal protection with diagnosis
Undervoltage detection and recovery on pins VCC, VIO and VBAT
Bus line short-circuit diagnosis
Bus dominant clamping diagnosis
Cold start diagnosis (first battery connection)
3. Quick reference data
Table 1.
Symbol Parameter
VCC supply voltage
Quick reference data
Conditions
Min
4.5
3
Typ Max Unit
-
5.5
V
V
Vuvd(VCC) undervoltage detection voltage on pin
VCC
3.5 4.3
ICC
supply current
Normal mode; bus dominant
30
3
48
6
65
9
mA
mA
Normal or Listen-only mode; bus
recessive
Standby or Sleep mode
0
0.75
2
A
kV
V
VESD
VCANH
VCANL
Tvj
electrostatic discharge voltage
voltage on pin CANH
IEC 61000-4-2 at pins CANH and CANL
no time limit; DC limiting value
no time limit; DC limiting value
8
-
-
-
-
+8
58
58
40
+58
+58
voltage on pin CANL
V
virtual junction temperature
+150 C
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
plastic small outline package; 14 leads; body width 3.9 mm
Version
TJA1043T
SO14
SOT108-1
SOT1086-2
TJA1043TK
HVSON14 plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
2 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
5. Block diagram
V
V
V
BAT
CC
3
IO
5
10
V
CC
TJA1043
TEMPERATURE
PROTECTION
13
12
CANH
CANL
V
IO
SLOPE
CONTROL
+
1
TIME-OUT
DRIVER
TXD
V
BAT
9
WAKE
11
MODE
CONTROL
+
WAKE-UP
CONTROL
+
SPLIT
SPLIT
V
BAT
8
ERR_N
14
ERROR
DETECTION
STB_N
7
INH
6
EN
4
RXD
MUX
+
DRIVER
WAKE-UP
FILTER
2
GND
015aaa061
Fig 1. Block diagram
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
3 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
6. Pinning information
6.1 Pinning
terminal 1
index area
TXD
1
2
3
4
5
6
7
14 STB_N
13 CANH
12 CANL
1
2
3
4
5
6
7
14
13
12
11
10
9
TXD
STB_N
CANH
CANL
SPLIT
GND
GND
V
CC
V
CC
TJA1043TK
RXD
11 SPLIT
RXD
TJA1043T
V
10
9
V
BAT
V
V
IO
IO
BAT
EN
WAKE
EN
WAKE
INH
8
ERR_N
8
INH
ERR_N
015aaa062
015aaa376
Fig 2. Pin configuration diagram: SO14
Fig 3. Pin configuration diagram: HVSON14
6.2 Pin description
Table 3.
Symbol
TXD
Pin description
Pin
1
Description
transmit data input
GND[1]
2
ground supply
VCC
3
transceiver supply voltage
RXD
4
receive data output; reads out data from the bus lines
supply voltage for I/O level adaptor
enable control input
VIO
5
EN
6
INH
7
inhibit output for switching external voltage regulators
error and power-on indication output (active LOW)
local wake-up input
ERR_N
WAKE
VBAT
8
9
10
11
12
13
14
battery supply voltage
SPLIT
CANL
CANH
STB_N
common-mode stabilization output
LOW-level CAN bus line
HIGH-level CAN bus line
standby control input (active LOW)
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package
should be soldered to board ground (and not to any other voltage level).
7. Functional description
The TJA1043 is a stand-alone high-speed CAN transceiver with a number of operating
modes, fail-safe features and diagnostic features that offer enhanced system reliability
and advanced power management. The transceiver combines the functionality of the
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
4 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
TJA1041A with improved EMC and ESD capability and quiescent current performance.
Improved slope control and high DC handling capability on the bus pins provide additional
application flexibility.
7.1 Operating modes
The TJA1043 supports five operating modes. Control pins STB_N and EN are used to
select the operating mode. Switching between modes allows access to a number of
diagnostics flags via pin ERR_N. Table 4 describes how to switch between modes.
Figure 4 illustrates the mode transitions when VCC, VIO and VBAT are valid.
Table 4.
Operating mode selection
Internal flags
Control pins
Operating mode
Pin INH
[1]
UVNOM
UVBAT
Wake[2]
STB_N[3] EN
From Normal, Listen-only, Standby and Go-to-Sleep modes
set
X
X
X
X
Sleep mode
floating
HIGH
HIGH
HIGH
HIGH[4]
HIGH
HIGH
cleared
cleared
cleared
cleared
cleared
cleared
set
X
HIGH
LOW
LOW
LOW
HIGH
HIGH
X
Standby mode
Standby mode
Standby mode
Go-to-Sleep mode[4]
Listen-only mode
Normal mode
X
set
X
X
cleared
cleared
X
LOW
HIGH
LOW
HIGH
X
cleared
cleared
X
From Sleep mode
set
X
X
X
X
Sleep mode
floating
HIGH
HIGH
floating
HIGH
HIGH
cleared
cleared
cleared
cleared
cleared
set
X
HIGH
LOW
LOW
HIGH
HIGH
X
Standby mode
Standby mode
Sleep mode
X
set
X
X
cleared
X
cleared
cleared
X
X
LOW
HIGH
Listen-only mode
Normal mode
[1] Setting the UVNOM flag will clear the WAKE flag.
[2] Setting the Wake flag will clear the UVNOM flag.
[3] A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag
[4] After the minimum hold time, in Go-to-Sleep mode, th(min), the transceiver will enter Sleep mode and pin
INH will be set floating.
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
5 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
STB_N = H
and
EN = H
STB_N = H
and
EN = L
LISTEN-
ONLY MODE
NORMAL
MODE
STB_N = H
and
EN = H
STB_N = H
and
STB_N = H
and
EN = H
STB_N = H
and
EN = L
EN = L
STB_N = L
and
(EN = L or Wake flag set)
STB_N = L
and
EN = H
STB_N = L and EN = H
and
Wake flag cleared
STB_N = L
and
EN = L
STB_N = L and EN = H
STANDBY
MODE
GO-TO-SLEEP
MODE
and
Wake flag cleared
STB_N = L
and
(EN = L or Wake flag set)
Wake flag cleared
and
STB_N = L
and
Wake flag set
STB_N = H and EN = H
STB_N = H and EN = L
t > t
h(min)
SLEEP
MODE
LEGEND:
= H, = L
logical state of pin
015aaa063
Fig 4. Mode transitions when valid VCC, VIO and VBAT voltages are present
7.1.1 Normal mode
In Normal mode, the transceiver can transmit and receive data via the bus lines CANH
and CANL (see Figure 1 for the block diagram). The differential receiver converts the
analog data on the bus lines into digital data which is output to pin RXD. The slope of the
output signals on the bus lines is controlled and optimized in a way that guarantees the
lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH is active, so
voltage regulators controlled by pin INH (see Figure 7) will be active too.
7.1.2 Listen-only mode
In Listen-only mode, the transceiver’s transmitter is disabled, effectively providing a
transceiver listen-only feature. The receiver will still convert the analog bus signal on
pins CANH and CANL into digital data, available for output on pin RXD. As in Normal
mode, the bus pins are biased at 0.5VCC and pin INH remains active.
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
6 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
7.1.3 Standby mode
Standby mode is the TJA1043’s first-level power saving mode, offering reduced current
consumption. In Standby mode, the transceiver is unable to transmit or receive data and
the low-power receiver is activated to monitor bus activity. The bus pins are biased at
ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will
also be active.
Pins RXD and ERR_N will reflect any active wake-up requests (provided that VIO and
V
BAT are present).
7.1.4 Go-to-Sleep mode
Go-to-Sleep mode is the controlled route for entering Sleep mode. In Go-to-Sleep mode,
the transceiver behaves as in Standby mode, with the addition that a go-to-sleep
command is issued to the transceiver. The transceiver will remain in Go-to-Sleep mode for
the minimum hold time (th(min)) before entering Sleep mode. The transceiver will not enter
Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set
before th(min) has elapsed.
7.1.5 Sleep mode
Sleep mode is the TJA1043’s second-level power saving mode. Sleep mode is entered
via Go-to-Sleep mode, and also when the undervoltage detection time on either VCC or
V
IO elapses before the relevant voltage level has recovered. In Sleep mode, the
transceiver behaves as described for Standby mode, with the exception that pin INH is set
floating. Voltage regulators controlled by this pin will be switched off, and the current into
pin VBAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to
wake up a node from Sleep mode (see Table 4).
7.2 Internal flags
The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and
system diagnosis support. Five of these flags can be polled by the controller via pin
ERR_N. Which flag is available on pin ERR_N at any time depends on the active
operating mode and on a number of other conditions. Table 5 describes how to access
these flags.
Table 5.
Accessing internal flags via pin ERR_N
Flag is available on pin ERR_N[1]
Internal
flag
Flag is cleared
UVNOM
no
by setting the Pwon or Wake flags, by a
LOW-to-HIGH transition on STB_N or
when both VIO and VBAT have
recovered.
UVBAT
Pwon
no
when VBAT has recovered
in Listen-only mode (coming from Standby on entering Normal mode
mode, Go-to-Sleep mode, or Sleep mode)
Wake
in Standby mode, Go-to-Sleep mode, and on entering Normal mode or by setting
Sleep mode (provided that VIO and VBAT
are present)
the UVNOM flag
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
7 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
Table 5.
Accessing internal flags via pin ERR_N …continued
Internal
flag
Flag is available on pin ERR_N[1]
Flag is cleared
Wake-up
source
in Normal mode (before the fourth
dominant-to-recessive edge on pin TXD[2])
on leaving Normal mode
Bus failure in Normal mode (after the fourth
on re-entering Normal mode or by
dominant-to-recessive edge on pin TXD[2]) setting the Pwon flag
Local failure in Listen-only mode (coming from Normal on entering Normal mode or when RXD
mode)
is dominant while TXD is recessive
(provided that all local failures are
resolved) or by setting the Pwon flag
[1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a
cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.
7.2.1 UVNOM flag
UVNOM is the VCC and VIO undervoltage detection flag. The flag is set when the voltage on
pin VCC drops below the VCC undervoltage detection voltage, Vuvd(VCC), for longer than the
undervoltage detection time, tdet(uv), or when the voltage on pin VIO drops below Vuvd(VIO)
for longer than tdet(uv). When the UVNOM flag is set, the transceiver enters Sleep mode to
save power and to ensure the bus is not disturbed. In Sleep mode the voltage regulators
connected to pin INH are disabled, avoiding any extra power consumption that might be
generated as a result of a short-circuit condition.
Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will
clear UVNOM and the timers, allowing the voltage regulators to be reactivated (at least until
UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer
than the undervoltage recovery time, trec(uv). The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.2 UVBAT flag
UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on
pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter
Standby mode to save power and will disengage from the bus (zero load). UVBAT is
cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.3 Pwon flag
Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers
after previously dropping below Vuvd(VBAT) (usually because the battery was
disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and
Wake-up source flags are set to ensure consistent system power-up under all supply
conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 5).
The flag is cleared when the transceiver enters Normal mode.
7.2.4 Wake flag
The Wake flag is set when the transceiver detects a local or remote wake-up request. A
local wake-up request is detected when the logic level on pin WAKE changes, and the
new level remains stable for at least twake. A remote wake-up request is triggered by two
bus dominant states of at least twake(busdom), with the first dominant state followed by a
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
8 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
recessive state of at least twake(busrec) (provided the complete
dominant-recessive-dominant pattern is completed within tto(wake)bus). The Wake flag can
be set in Standby mode, Go-to-Sleep mode or Sleep mode. Setting the Wake flag clears
the UVNOM flag and timers. Once set, the Wake flag status is immediately available on
pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at
power-on and cleared when the UVNOM flag is set or the transceiver enters Normal mode.
7.2.5 Wake-up source flag
Wake-up source recognition is provided via the Wake-up source flag, which is set when
the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source
flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is also set at
power-on and cleared when the transceiver leaves Normal mode.
7.2.6 Bus failure flag
The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to
V
BAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while
trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N
pin in Normal mode (see Table 5). This flag is cleared at power-on or when the transceiver
re-enters Normal mode.
7.2.7 Local failure flag
In Normal and Listen-only modes, the transceiver can distinguish four different local
failure events, any of which will cause the Local failure flag to be set. The four local failure
events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping
and an overtemperature event. The nature and detection of these local failures is
described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in
Listen-only mode (see Table 5). This flag is cleared at power-on, when entering Normal
mode or when RXD is dominant while TXD is recessive, provided that all local failures
have been resolved.
7.3 Local failures
The TJA1043 can detect four different local failure conditions. Any of these failures will set
the Local failure flag, and in most cases the transmitter of the transceiver will be disabled.
7.3.1 TXD dominant clamping detection
A permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communications. The TXD dominant time-out function prevents such a network lock-up by
disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant
time-out time tto(dom)TXD. The tto(dom)TXD timer defines the minimum possible bit rate of
40 kbit/s. The transmitter remains disabled until the Local failure flag has been cleared.
7.3.2 TXD-to-RXD short-circuit detection
A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant
state once it had been driven dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD
short-circuit detection prevents such a network lock-up by disabling the transmitter. The
transmitter remains disabled until the Local failure flag has been cleared.
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
9 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
7.3.3 Bus dominant clamping detection
A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The Local failure flag is set if the dominant state on the bus persists for
longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped bus
is blocking network communications. There is no need to disable the transmitter. Note that
the Local failure flag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
7.3.4 Overtemperature detection
If the junction temperature becomes excessive, the transmitter will shut down in time to
protect the output drivers from overheating without compromising the maximum operating
temperature. The transmitter will remain disabled until the Local failure flag has been
cleared.
7.4 SPLIT pin
Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see
Figure 5 and Figure 7) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a
DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is
floating.
V
CC
TJA1043
CANH
SPLIT
CANL
R
60 Ω
60 Ω
V
= 0.5V
CC
SPLIT
V
SPLIT
in normal mode
and pwon/listen-only
mode;
R
otherwise floating
GND
015aaa064
Fig 5. Stabilization circuit and application
7.5 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage (see Figure 7). This will
cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the
I/O levels of the microcontroller, facilitating direct interfacing without the need for glue
logic.
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
10 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
7.6 WAKE pin
A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the
WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To
minimize current consumption, the internal bias voltage will follow the logic state on the
pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to
V
BAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In
applications that don’t make use of the local wake-up facility, it is recommended that the
WAKE pin be connected to VBAT or GND to ensure optimal EMI performance.
TJA1043
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
11 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
0.3
-
Max
+58
58
Unit
V
VBAT
battery supply voltage
no time limit
load dump
V
Vx
voltage on pin x
no time limit; DC value
on pins CANH, CANL and SPLIT
on pins INH and WAKE
58
+58
+58
+7
V
V
V
0.3
0.3
on pins VCC, VIO, TXD, RXD, STB_N, EN,
ERR_N
IWAKE
Vtrt
current on pin WAKE
transient voltage
DC value
-
15
mA
V
[1]
[2]
[3]
[4]
on pins CANH, CANL, SPLIT and VBAT
200
+200
VESD
electrostatic discharge
voltage
IEC 61000-4-2
at pins CANH and CANL
HBM
8
+8
kV
at pins CANH and CANL
at any other pin
MM
8
4
+8
+4
kV
kV
[5]
[6]
at any pin
300
+300
V
CDM
at corner pins
at any pin
750
500
40
+750
+500
+150
+150
V
V
[7]
Tvj
virtual junction temperature
storage temperature
C
C
Tstg
55
[1] Verified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 part 3 automotive transient test
pulses 1, 2a, 3a and 3b.
[2] IEC 61000-4-2 (150 pF, 330 ); direct coupling.
[3] ESD performance of pins CANH and CANL according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house.
The result is equal to or better than 8 kV (unaided).
[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).
[5] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).
[6] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF); grade C3B.
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 7.
Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol
Parameter
Conditions
Typ
68
Unit
K/W
K/W
Rth(vj-a)
thermal resistance from virtual junction to ambient
SO14 package; in free air
HVSON14 package; in free air
44
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10. Static characteristics
Table 8.
CC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1]
Static characteristics
V
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply pin VCC
VCC
supply voltage
4.5
3
-
5.5
4.3
V
V
Vuvd(VCC)
undervoltage detection
voltage on pin VCC
VBAT > 4.5 V
3.5
ICC
supply current
Normal mode; VTXD = 0 V (dominant)
30
3
48
6
65
9
mA
mA
Normal or Listen-only mode;
VTXD = VIO (recessive)
Standby or Sleep mode; VBAT > VCC
0
0.75
2
A
I/O level adapter supply; pin VIO
VIO
supply voltage on pin VIO
2.8
0.8
-
5.5
2.5
V
V
Vuvd(VIO)
undervoltage detection
voltage on pin VIO
VBAT or VCC > 4.5 V
1.8
IIO
supply current on pin VIO
Normal mode; VTXD = 0 V (dominant)
-
150
1
500
4
A
A
Normal or Listen-only mode;
VTXD = VIO (recessive)
0
Standby or Sleep mode
0
1
4
A
Supply pin VBAT
VBAT
battery supply voltage
4.5
3
-
40
V
V
Vuvd(VBAT)
undervoltage detection
voltage on pin VBAT
3.5
4.3
IBAT
battery supply current
Normal or Listen-only mode
15
5
40
18
70
30
A
A
Standby mode; VCC > 4.5 V
VINH = VWAKE = VBAT
Sleep mode; VINH = VCC = VIO = 0 V;
VWAKE = VBAT
5
18
30
A
CAN transmit data input; pin TXD
VIH
VIL
IIH
IIL
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
LOW-level input current
input capacitance
0.7VIO
0.3
5
-
VIO + 0.3 V
-
+0.3VIO
+5
V
VTXD = VIO
0
A
A
pF
Normal mode; VTXD = 0 V
not tested
300
-
200
30
Ci
5
10
CAN receive data output; pin RXD
IOH HIGH-level output current VRXD = VIO 0.4 V; VIO = VCC
IOL
12
6
0
mA
mA
LOW-level output current
VRXD = 0.4 V; VTXD = VIO;
bus dominant
0
6
14
Standby and enable control inputs; pins STB_N and EN
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
0.7VIO
0.3
1
-
VIO + 0.3 V
-
0.3VIO
10
V
VSTB_N = VEN = 0.7VIO
4
A
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Table 8. Static characteristics …continued
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1]
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL
LOW-level input current
VSTB_N = VEN = 0 V
1
0
+1
A
Error and power-on indication output; pin ERR_N
IOH HIGH-level output current VERR_N = VIO 0.4 V; VIO = VCC
IOL LOW-level output current VERR_N = 0.4 V
Local wake-up input; pin WAKE
50
20
4
A
0.1
0.5
2
mA
IIH
IIL
HIGH-level input current
LOW-level input current
threshold voltage
VWAKE = VBAT 1.9 V
VWAKE = VBAT 3.1 V
VSTB_N = 0 V
10
5
1
A
A
V
1
5
10
Vth
VBAT 3 VBAT 2.5 VBAT 2
Inhibit output; pin INH
VH
HIGH-level voltage drop
leakage current
IINH = 0.18 mA
0
0.25
0
0.8
+2
V
IL
Sleep mode
2
A
Bus lines; pins CANH and CANL
VO(dom) dominant output voltage
VTXD = 0 V; t < tto(dom)TXD
pin CANH
2.75
0.5
3.5
1.5
-
4.5
V
pin CANL
2.25
+400
V
Vdom(TX)sym transmitter dominant
voltage symmetry
Vdom(TX)sym = VCC VCANH VCANL
400
mV
VO(dif)bus
VO(rec)
IO(sc)
bus differential output
voltage
VTXD = 0 V; VCC = 4.75 V to 5.25 V;
45 < RL < 65 ; dominant
1.5
-
3.0
V
VTXD = VIO; recessive; no load
50
-
+50
3
mV
V
recessive output voltage
Normal or Listen-only mode;
VTXD = VIO; no load
2
0.5VCC
Standby or Sleep mode; no load
0.1
0
+0.1
V
short-circuit output current VTXD = 0 V (dominant); VCC = 5 V
pin CANH; VCANH = 0 V
100
40
70
70
-
40
100
+3
mA
mA
mA
pin CANL; VCANL = 40 V
IO(rec)
recessive output current
27 V < VCAN < 32 V
3
[2]
[2]
Vth(RX)dif
differential receiver
threshold voltage
Vcm(CAN) = 30 V to +30 V
Normal or Listen-only mode
Standby or Sleep mode
0.5
0.4
50
0.7
0.7
120
0.9
V
1.15
400
V
Vhys(RX)dif
ILI
differential receiver
hysteresis voltage
Normal or Listen-only mode
Vcm(CAN) = 30 V to +30 V
mV
input leakage current
VCC = 0 V; VCANH = VCANL = 5 V
VBAT = 0 V; VCANH = VCANL = 5 V
100
2
9
170
-
250
+2
28
+3
52
20
A
A
k
%
Ri
input resistance
15
0
Ri
input resistance deviation between VCANH and VCANL
differential input resistance
3
19
-
Ri(dif)
Ci(cm)
30
-
k
pF
[3]
[3]
common-mode input
capacitance
VTXD = VCC
Ci(dif)
differential input
capacitance
VTXD = VCC
-
-
10
pF
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Table 8.
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1]
Static characteristics …continued
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Common-mode stabilization output; pin SPLIT
VO
output voltage
Normal or Listen-only mode;
500 A < ISPLIT < 500 A
0.3VCC
0.5VCC
0.7VCC
0.55VCC
+3
V
Normal or Listen-only mode
RL = 1 M
0.45VCC 0.5VCC
V
IL
leakage current
Standby or Sleep mode;
3
0
A
58 V < VSPLIT < +58 V
Temperature detection
Tj(sd) shutdown junction
temperature
[3]
-
190
-
C
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Vcm(CAN) is the common mode voltage of CANH and CANL.
[3] Not tested in production; guaranteed by design.
11. Dynamic characteristics
Table 9.
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device[1]
Dynamic characteristics;
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Timing characteristics; Figure 6
td(TXD-busdom) delay time from TXD to bus dominant Normal mode
td(TXD-busrec) delay time from TXD to bus recessive Normal mode
td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-only mode
-
-
-
-
70
90
60
70
-
-
-
-
ns
ns
ns
ns
td(busrec-RXD) delay time from bus recessive to
RXD
Normal or Listen-only mode
tPD(TXD-RXD)
tdet(uv)
propagation delay from TXD to RXD VSTB_N = 0 V
40
100
1
-
240
350
5
ns
undervoltage detection time
undervoltage recovery time
TXD dominant time-out time
bus dominant time-out time
hold time
-
ms
ms
ms
ms
s
trec(uv)
-
tto(dom)TXD
tto(dom)bus
th
VTXD = 0 V
0.3
0.3
0.6
0.6
35
1.5
1.5
50
VO(dif)(bus) > 0.9 V
from issuing go-to-sleep command to 20
entering Sleep mode
twake(busdom) bus dominant wake-up time
Standby or Sleep mode; VBAT = 12 V 0.5
Standby or Sleep mode; VBAT = 12 V 0.5
0.5
1.75
1.75
-
5
s
s
ms
s
twake(busrec)
tto(wake)bus
twake
bus recessive wake-up time
bus wake-up time-out time
wake-up time
5
2
in response to a falling or rising edge
on pin WAKE; Standby or Sleep
mode
5
25
50
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
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HIGH
LOW
TXD
CANH
CANL
dominant
0.9 V
V
O(dif)(bus)
0.5 V
recessive
HIGH
0.7V
IO
RXD
0.3V
IO
LOW
t
t
d(TXD-busrec)
d(TXD-busdom)
t
t
d(busrec-RXD)
d(busdom-RXD)
t
t
PD(TXD-RXD)
PD(TXD-RXD)
015aaa025
Fig 6. CAN transceiver timing diagram
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12. Application information
3 V
5 V
BAT
V
BAT
V
V
IO
CC
INH
V
10
7
3
5
CC
STB_N
WAKE
GND
14
6
9
EN
Port x, y, z
ERR_N
8
MICRO-
CONTROLLER
TJA1043
RXD
RXD
4
1
2
TXD
TXD
13
CANH
12
CANL
11
SPLIT
CAN bus wires
015aaa060
Fig 7. Typical application with 3 V microcontroller
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13. Test information
V
RXD
HIGH
LOW
hysteresis
0.5
0.9
V
(V)
i(dif)(bus)
mgs378
Fig 8. Hysteresis of the receiver
+12 V
+5 V
47 μF
100 nF
V
IO
V
V
BAT
10 μF
CC
5
3
10
TXD
EN
CANH
1
13
11
SPLIT
CANL
R
L
6
100 pF
STB_N
WAKE
14
9
12
8
TJA1043
ERR_N
INH
7
RXD
4
2
15 pF
GND
015aaa163
Fig 9. Test circuit for timing characteristics
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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14. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
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HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
D
B
A
E
A
A
1
c
terminal 1
index area
detail X
e
1
terminal 1
index area
C
v
C
C
A
B
e
b
y
1
y
w
C
1
7
L
k
E
h
14
8
D
h
0
2.5
5 mm
w
scale
Dimensions
Unit
A
A
b
c
D
D
h
E
E
e
e
1
k
L
v
y
y
1
1
h
max 1.00 0.05 0.35
mm nom 0.85 0.03 0.32 0.2 4.5 4.20 3.0 1.60 0.65 3.9 0.30 0.40 0.1 0.05 0.05 0.1
min 0.80 0.00 0.29 4.4 4.15 2.9 1.55 0.25 0.35
4.6 4.25 3.1 1.65
0.35 0.45
sot1086-2
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-07-14
10-07-15
SOT1086-2
MO-229
Fig 11. Package outline SOT1086 (HVSON14)
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15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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18. Revision history
Table 12. Revision history
Document ID
TJA1043 v.3
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20130424
Product data sheet
-
TJA1043 v.2
• Section 2.1: revised
• Added HVSON14 package (Table 2, Figure 3, Table 7, Figure 11)
• Table 3: table note section added
• Section 13.1 text revised
• Section 17: added
TJA1043 v.2
TJA1043 v.1
20110620
Product data sheet
Product data sheet
-
-
TJA1043 v.1
-
20100330
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
19.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1043
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
25 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1043
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 24 April 2013
26 of 27
TJA1043
NXP Semiconductors
High-speed CAN transceiver
21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
16.1
16.2
16.3
16.4
Introduction to soldering. . . . . . . . . . . . . . . . . 21
Wave and reflow soldering. . . . . . . . . . . . . . . 21
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 22
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Low-power management . . . . . . . . . . . . . . . . . 2
Protection and diagnosis (detection and
2.1
2.2
2.3
17
18
Soldering of HVSON packages . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . 24
signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
19
Legal information . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26
19.1
19.2
19.3
19.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 26
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Listen-only mode . . . . . . . . . . . . . . . . . . . . . . . 6
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Go-to-Sleep mode . . . . . . . . . . . . . . . . . . . . . . 7
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Internal flags. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wake-up source flag. . . . . . . . . . . . . . . . . . . . . 9
Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . . 9
Local failure flag . . . . . . . . . . . . . . . . . . . . . . . . 9
Local failures . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TXD dominant clamping detection . . . . . . . . . . 9
TXD-to-RXD short-circuit detection . . . . . . . . . 9
Bus dominant clamping detection. . . . . . . . . . 10
Overtemperature detection. . . . . . . . . . . . . . . 10
SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . 10
WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.6
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal characteristics . . . . . . . . . . . . . . . . . 12
Static characteristics. . . . . . . . . . . . . . . . . . . . 13
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Application information. . . . . . . . . . . . . . . . . . 17
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Quality information . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Handling information. . . . . . . . . . . . . . . . . . . . 21
Soldering of SMD packages . . . . . . . . . . . . . . 21
9
10
11
12
13
13.1
14
15
16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 April 2013
Document identifier: TJA1043
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