935299677551 [NXP]
RISC Microcontroller;
| 型号： | 935299677551 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总71页 (文件大小：1629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC11E3x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up
to 12 kB SRAM and 4 kB EEPROM; USART
Rev. 2.3 — 11 September 2014
Product data sheet
1. General description
The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11E3x operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to
12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up
to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on http://www.LPCware.com.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access.
4 kB on-chip EEPROM data memory; byte erasable and byte programmable;
on-chip API support.
12 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
ROM-based 32-bit integer division routines.
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Debug options:
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
Serial Wire Debug.
Digital peripherals:
Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin.
High-current sink driver (20 mA) on true open-drain pins.
Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
I/O Handler for hardware emulation of serial interfaces and DMA; supported through
software libraries.(LPC11E37HFBD64/401 only.)
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power profiles residing in boot ROM provide optimized performance and minimized
power consumption for any given application through one simple function call.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, or the watchdog interrupt.
Processor wake-up from Deep power-down mode using one special function pin.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
2 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range 40 C to +85 C.
Available as LQFP64, LQFP48, and HVQFN33 packages.
3. Applications
Consumer peripherals
Medical
Handheld scanners
Industrial control
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11E35FHI33/501
HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 5 5 0.85 mm
LPC11E36FBD64/501
LPC11E36FHN33/501
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 7 7 0.85 mm
LPC11E37FBD48/501
LPC11E37FBD64/501
LQFP48
LQFP64
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11E37HFBD64/401 LQFP64
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
3 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Type number
LPC11E35FHI33/501
LPC11E36FBD64/501
LPC11E36FHN33/501
LPC11E37FBD48/501
LPC11E37FBD64/501
64
4
4
4
4
4
4
8
8
8
8
8
8
2
2
2
2
2
2
2[1]
2[1]
2[1]
2[1]
2[1]
2[2]
12
12
12
12
12
10
no
no
no
no
no
yes
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
8
8
8
8
8
8
26
54
28
40
54
54
96
96
128
128
LPC11E37HFBD64/401 128
[1] For general-purpose use.
[2] For I/O Handler use only.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
4 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
RESET
LPC11E3x
SYSTEM OSCILLATOR
TEST/DEBUG
INTERFACE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
IRC, WDO
BOD
CLKOUT
ARM
FUNCTIONS
CORTEX-M0
POR
PLL0
EEPROM
4 kB
FLASH
96/128 kB
SRAM
10/12 kB
ROM
16 kB
system bus
slave
slave
slave
slave
HIGH-SPEED
GPIO
GPIO ports 0/1
IOH_[20:0]
AHB-LITE BUS
master
I/O
HANDLER
(3)
slave
AHB TO APB
BRIDGE
RXD
TXD
DCD, DSR , RI
CTS, RTS, DTR
SCLK
USART/
SMARTCARD INTERFACE
(1)
(1)
AD[7:0]
10-bit ADC
SCL, SDA
2
I C-BUS
CT16B0_MAT[2:0]
16-bit COUNTER/TIMER 0
(2)
CT16B0_CAP[1:0]
SCK0, SSEL0,
MISO0, MOSI0
SSP0
CT16B1_MAT[1:0]
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
(2)
CT16B1_CAP[1:0]
SCK1, SSEL1,
MISO1, MOSI1
CT32B0_MAT[3:0]
SSP1
(2)
CT32B0_CAP[1:0]
IOCON
CT32B1_MAT[3:0]
32-bit COUNTER/TIMER 1
(2)
CT32B1_CAP[1:0]
SYSTEM CONTROL
PMU
WINDOWED WATCHDOG
TIMER
GPIO pins
GPIO INTERRUPTS
GPIO pins
GPIO pins
GPIO GROUP0 INTERRUPTS
GPIO GROUP1 INTERRUPTS
002aah401
(1) Not available on HVQFN33 packages.
(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available LQFP48, and LQFP64
packages only; CT32B1_CAP1 available in LQFP64 packages only.
(3) LPC11E37HFBD64/401 only.
Fig 1. Block diagram
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
5 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIO1_19/DTR/SSEL1
RESET/PIO0_0
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_1/CLKOUT/CT32B0_MAT2
XTALIN
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
33 V
SS
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_8/MISO0/CT16B0_MAT0
002aah404
Transparent top view
For parts LPC11E36FHN33/501
Fig 2. Pin configuration (HVQFN33, 7x7)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
6 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIO1_19/DTR/SSEL1
RESET/PIO0_0
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
XTALIN
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
33 V
SS
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_8/MISO0/CT16B0_MAT0
aaa-014397
Transparent top view
For parts LPC11E35FHI33/501
Fig 3. Pin configuration (HVQFN33, 5x5)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
7 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PIO1_14/DSR/CT16B0_MAT1/RXD
PIO1_28/CT32B0_CAP0/SCLK
PIO0_7/CTS
PIO1_22/RI/MOSI1
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
PIO0_6/SCK0
PIO1_24/CT32B0_MAT0
n.c.
V
SS
LPC11E37FBD48/501
PIO0_23/AD7
n.c.
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO1_23/CT16B1_MAT1/SSEL1
PIO0_21/CT16B1_MAT0/MOSI1
PIO0_5/SDA
V
DD
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_18/RXD/CT32B0_MAT0
PIO0_19/TXD/CT32B0_MAT1
PIO1_16/RI/CT16B0_CAP0
PIO0_4/SCL
PIO0_3
PIO1_20/DSR/SCK1
002aah402
Fig 4. Pin configuration (LQFP48)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
8 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO1_14 49
32 PIO1_5
31 PIO1_28
30 PIO0_7
29 PIO0_6
28 PIO1_18
27 PIO1_24
26 n.c.
PIO1_3 50
PIO1_22 51
SWDIO/PIO0_15 52
PIO0_16 53
V
SS
54
PIO1_9 55
PIO0_23 56
PIO1_15 57
LPC11E36FBD64/501
LPC11E37FBD64/501
LPC11E37HFBD64/401
25 n.c.
24 PIO1_23
23 PIO1_17
22 PIO0_21
21 PIO0_5
20 PIO0_4
19 PIO0_3
18 PIO1_20
17 PIO1_1
V
DD
58
PIO1_12 59
PIO0_17 60
PIO0_18 61
PIO0_19 62
PIO1_16 63
PIO1_6 64
002aah403
See Table 3 for the full pin name.
Fig 5. Pin configuration (LQFP64)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
9 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[2]
RESET/PIO0_0
2
2
3
4
I; PU
I
RESET — External reset input with 20 ns glitch
filter. A LOW-going pulse as short as 50 ns on this
pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH level
selects the ARM SWD debug mode.
-
I/O
I/O
PIO0_0 — General purpose digital input/output
pin.
[3]
PIO0_1/CLKOUT/
CT32B0_MAT2
3
8
3
8
4
5
I; PU
PIO0_1 — General purpose digital input/output
pin. A LOW level on this pin during reset starts the
ISP command handler.
-
-
O
O
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer
0.
[3]
PIO0_2/SSEL0/
10 13
I; PU
I/O
PIO0_2 — General purpose digital input/output
CT16B0_CAP0/IOH_0
pin.
-
-
I/O
I
SSEL0 — Slave select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer
0.
-
I/O
I/O
IOH_0 — I/O Handler input/output 0.
LPC11E37HFBD64/401 only.
[3]
PIO0_3/R/IOH_1
9
9
14 19
I; PU
PIO0_3 — General purpose digital input/output
pin.
-
-
-
R — Reserved.
I/O
IOH_1 — I/O Handler input/output 1.
LPC11E37HFBD64/401 only.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
10 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[4]
[4]
[3]
PIO0_4/SCL/IOH_2
PIO0_5/SDA/IOH_3
10
11
15
10
11
15
15 20
16 21
22 29
I; IA
-
I/O
I/O
PIO0_4 — General purpose digital input/output
pin (open-drain).
SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
-
I/O
I/O
I/O
IOH_2 — I/O Handler input/output 2.
LPC11E37HFBD64/401 only.
I; IA
-
PIO0_5 — General purpose digital input/output
pin (open-drain).
SDA — I2C-bus data input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
-
I/O
I/O
IOH_3 — I/O Handler input/output 3.
LPC11E37HFBD64/401 only.
PIO0_6/R/
I; PU
PIO0_6 — General purpose digital input/output
SCK0/IOH_4
pin.
-
-
-
-
R — Reserved.
I/O
I/O
SCK0 — Serial clock for SSP0.
IOH_4 — I/O Handler input/output 4.
LPC11E37HFBD64/401 only.
[5]
[3]
PIO0_7/CTS/IOH_5
16
17
16
17
23 30
I; PU
I/O
PIO0_7 — General purpose digital input/output
pin (high-current output driver).
-
-
I
CTS — Clear To Send input for USART.
I/O
IOH_5 — I/O Handler input/output 5.
LPC11E37HFBD64/401 only.
PIO0_8/MISO0/
27 36
I; PU
I/O
PIO0_8 — General purpose digital input/output
CT16B0_MAT0/R/IOH_6
pin.
-
-
I/O
O
MISO0 — Master In Slave Out for SSP0.
CT16B0_MAT0 — Match output 0 for 16-bit timer
0.
-
-
-
Reserved.
I/O
IOH_6 — I/O Handler input/output 6.
LPC11E37HFBD64/401 only.
[3]
PIO0_9/MOSI0/
18
18
28 37
I; PU
I/O
PIO0_9 — General purpose digital input/output
CT16B0_MAT1/R/IOH_7
pin.
-
-
I/O
O
MOSI0 — Master Out Slave In for SSP0.
CT16B0_MAT1 — Match output 1 for 16-bit timer
0.
-
-
-
Reserved.
I/O
IOH_7 — I/O Handler input/output 7.
LPC11E37HFBD64/401 only.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
11 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[3]
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2
19
19
29 38
I; PU
-
I
SWCLK — Serial wire clock and test clock TCK
for JTAG interface.
I/O
PIO0_10 — General purpose digital input/output
pin.
-
-
O
O
SCK0 — Serial clock for SSP0.
CT16B0_MAT2 — Match output 2 for 16-bit timer
0.
[6]
[6]
[6]
[6]
[6]
TDI/PIO0_11/AD0/
CT32B0_MAT3
21
22
23
24
25
21
22
23
24
25
32 42
33 44
34 45
35 46
39 52
I; PU
-
I
TDI — Test Data In for JTAG interface.
I/O
PIO0_11 — General purpose digital input/output
pin.
-
-
I
AD0 — A/D converter, input 0.
O
CT32B0_MAT3 — Match output 3 for 32-bit timer
0.
TMS/PIO0_12/AD1/
CT32B1_CAP0
I; PU
-
I
TMS — Test Mode Select for JTAG interface.
I/O
PIO_12 — General purpose digital input/output
pin.
-
-
I
I
AD1 — A/D converter, input 1.
CT32B1_CAP0 — Capture input 0 for 32-bit timer
1.
TDO/PIO0_13/AD2/
CT32B1_MAT0
I; PU
-
O
TDO — Test Data Out for JTAG interface.
I/O
PIO0_13 — General purpose digital input/output
pin.
-
-
I
AD2 — A/D converter, input 2.
O
CT32B1_MAT0 — Match output 0 for 32-bit timer
1.
TRST/PIO0_14/AD3/
CT32B1_MAT1
I; PU
-
I
TRST — Test Reset for JTAG interface.
I/O
PIO0_14 — General purpose digital input/output
pin.
-
-
I
AD3 — A/D converter, input 3.
O
CT32B1_MAT1 — Match output 1 for 32-bit timer
1.
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
I; PU
-
I/O
I/O
SWDIO — Serial wire debug input/output.
PIO0_15 — General purpose digital input/output
pin.
-
-
I
AD4 — A/D converter, input 4.
O
CT32B1_MAT2 — Match output 2 for 32-bit timer
1.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
12 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[6]
PIO0_16/AD5/
CT32B1_MAT3/IOH_8/
WAKEUP
26
26
40 53
I; PU
I/O
PIO0_16 — General purpose digital input/output
pin.
-
-
I
AD5 — A/D converter, input 5.
O
CT32B1_MAT3 — Match output 3 for 32-bit timer
1.
-
-
I/O
I
IOH_8 — I/O Handler input/output 8.
LPC11E37HFBD64/401 only.
WAKEUP — Deep power-down mode wake-up
pin with 20 ns glitch filter. Pull this pin HIGH
externally before entering Deep power-down
mode, then pull LOW to exit Deep power-down
mode. A LOW-going pulse as short as 50 ns
wakes up the part.
[3]
PIO0_17/RTS/
30
30
45 60
I; PU
I/O
PIO0_17 — General purpose digital input/output
CT32B0_CAP0/SCLK
pin.
-
-
O
I
RTS — Request To Send output for USART.
CT32B0_CAP0 — Capture input 0 for 32-bit timer
0.
-
I/O
I/O
I
SCLK — Serial clock input/output for USART in
synchronous mode.
[3]
PIO0_18/RXD/
CT32B0_MAT0
31
32
7
31
32
46 61
I; PU
PIO0_18 — General purpose digital input/output
pin.
-
RXD — Receiver input for USART. Used in UART
ISP mode.
-
O
CT32B0_MAT0 — Match output 0 for 32-bit timer
0.
[3]
PIO0_19/TXD/
CT32B0_MAT1
47 62
I; PU
I/O
O
PIO0_19 — General purpose digital input/output
pin.
-
TXD — Transmitter output for USART. Used in
UART ISP mode.
-
O
CT32B0_MAT1 — Match output 1 for 32-bit timer
0.
[3]
[3]
PIO0_20/CT16B1_CAP0
7
9
11
I; PU
I/O
I
PIO0_20 — General purpose digital input/output
pin.
-
CT16B1_CAP0 — Capture input 0 for 16-bit timer
1.
PIO0_21/CT16B1_MAT0/ 12
MOSI1
12
17 22
I; PU
I/O
O
PIO0_21 — General purpose digital input/output
pin.
-
-
CT16B1_MAT0 — Match output 0 for 16-bit timer
1.
I/O
MOSI1 — Master Out Slave In for SSP1.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
13 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[6]
PIO0_22/AD6/
20
20
30 40
I; PU
I/O
PIO0_22 — General purpose digital input/output
CT16B1_MAT1/MISO1
pin.
-
-
I
AD6 — A/D converter, input 6.
O
CT16B1_MAT1 — Match output 1 for 16-bit timer
1.
-
I/O
I/O
MISO1 — Master In Slave Out for SSP1.
[6]
[3]
PIO0_23/AD7/IOH_9
27
27
42 56
I; PU
PIO0_23 — General purpose digital input/output
pin.
-
-
I
AD7 — A/D converter, input 7.
I/O
IOH_9 — I/O Handler input/output 9.
LPC11E37HFBD64/401 only.
PIO1_0/CT32B1_MAT0/
IOH_10
-
-
-
-
-
-
-
1
I; PU
I/O
O
PIO1_0 — General purpose digital input/output
pin.
-
CT32B1_MAT0 — Match output 0 for 32-bit timer
1.
-
I/O
I/O
O
IOH_10 — I/O Handler input/output 10.
LPC11E37HFBD64/401 only.
[3]
[3]
[3]
[3]
PIO1_1/CT32B1_MAT1/
IOH_11
-
-
-
-
-
-
-
-
17
34
50
16
I; PU
PIO1_1 — General purpose digital input/output
pin.
-
CT32B1_MAT1 — Match output 1 for 32-bit timer
1.
-
I/O
I/O
O
IOH_11 — I/O Handler input/output 11.
LPC11E37HFBD64/401 only.
PIO1_2/CT32B1_MAT2/
IOH_12
I; PU
PIO1_2 — General purpose digital input/output
pin.
-
CT32B1_MAT2 — Match output 2 for 32-bit timer
1.
-
I/O
I/O
O
IOH_12 — I/O Handler input/output 12.
LPC11E37HFBD64/401 only.
PIO1_3/CT32B1_MAT3/
IOH_13
I; PU
PIO1_3 — General purpose digital input/output
pin.
-
CT32B1_MAT3 — Match output 3 for 32-bit timer
1.
-
I/O
I/O
I
IOH_13 — I/O Handler input/output 13.
(LPC11E37HFBD64/401 only.)
PIO1_4/CT32B1_CAP0/
IOH_14
I; PU
PIO1_4 — General purpose digital input/output
pin.
-
-
CT32B1_CAP0 — Capture input 0 for 32-bit timer
1.
I/O
IOH_14 — I/O Handler input/output 14.
(LPC11E37HFBD64/401 only.)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
14 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[3]
PIO1_5/CT32B1_CAP1/
IOH_15
-
-
-
32
I; PU
-
I/O
I
PIO1_5 — General purpose digital input/output
pin.
CT32B1_CAP1 — Capture input 1 for 32-bit timer
1.
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH_15 — I/O Handler input/output 15.
(LPC11E37HFBD64/401 only.)
[3]
[3]
[3]
PIO1_6/IOH_16
PIO1_7/IOH_17
PIO1_8/IOH_18
-
-
-
-
-
-
-
-
-
64
6
I; PU
-
PIO1_6 — General purpose digital input/output
pin.
IOH_16 — I/O Handler input/output 16.
(LPC11E37HFBD64/401 only.)
I; PU
-
PIO1_7 — General purpose digital input/output
pin.
IOH_17 — I/O Handler input/output 17.
(LPC11E37HFBD64/401 only.)
39
I; PU
-
PIO1_8 — General purpose digital input/output
pin.
IOH_18 — I/O Handler input/output 18.
(LPC11E37HFBD64/401 only.)
[3]
[3]
[3]
[3]
[3]
PIO1_9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
12
43
59
I; PU
I; PU
I; PU
I; PU
I; PU
PIO1_9 — General purpose digital input/output
pin.
PIO1_10
PIO1_11
PIO1_12
PIO1_10 — General purpose digital input/output
pin.
PIO1_11 — General purpose digital input/output
pin.
PIO1_12 — General purpose digital input/output
pin.
PIO1_13/DTR/
36 47
PIO1_13 — General purpose digital input/output
CT16B0_MAT0/TXD
pin.
-
-
O
O
DTR — Data Terminal Ready output for USART.
CT16B0_MAT0 — Match output 0 for 16-bit timer
0.
-
O
TXD — Transmitter output for USART.
[3]
PIO1_14/DSR/
-
-
37 49
I; PU
I/O
PIO1_14 — General purpose digital input/output
CT16B0_MAT1/RXD
pin.
-
-
I
DSR — Data Set Ready input for USART.
O
CT16B0_MAT1 — Match output 1 for 16-bit timer
0.
-
I
RXD — Receiver input for USART.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
15 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[3]
PIO1_15/DCD/
CT16B0_MAT2/SCK1
28
28
43 57
I; PU
-
I/O
PIO1_15 — General purpose digital input/output
pin.
I
DCD — Data Carrier Detect input for USART.
O
CT16B0_MAT2 — Match output 2 for 16-bit timer
0.
-
I/O
I/O
SCK1 — Serial clock for SSP1.
[3]
[3]
[3]
PIO1_16/RI/
CT16B0_CAP0
-
-
-
-
-
-
48 63
I; PU
PIO1_16 — General purpose digital input/output
pin.
-
-
I
I
RI — Ring Indicator input for USART.
CT16B0_CAP0 — Capture input 0 for 16-bit timer
0.
PIO1_17/CT16B0_CAP1/
RXD
-
23
28
3
I; PU
-
I/O
I
PIO1_17 — General purpose digital input/output
pin.
CT16B0_CAP1 — Capture input 1 for 16-bit timer
0.
-
I
RXD — Receiver input for USART.
PIO1_18/CT16B1_CAP1/
TXD
-
I; PU
I/O
PIO1_18 — General purpose digital input/output
pin.
-
I
CT16B1_CAP1 — Capture input 1 for 16-bit timer
1.
-
O
TXD — Transmitter output for USART.
[3]
[3]
[3]
[3]
PIO1_19/DTR/SSEL1
PIO1_20/DSR/SCK1
PIO1_21/DCD/MISO1
PIO1_22/RI/MOSI1
1
-
1
-
2
I; PU
I/O
PIO1_19 — General purpose digital input/output
pin.
-
O
DTR — Data Terminal Ready output for USART.
SSEL1 — Slave select for SSP1.
-
I/O
I/O
13 18
26 35
38 51
I; PU
PIO1_20 — General purpose digital input/output
pin.
-
I
DSR — Data Set Ready input for USART.
SCK1 — Serial clock for SSP1.
-
I/O
I/O
-
-
I; PU
PIO1_21 — General purpose digital input/output
pin.
-
I
DCD — Data Carrier Detect input for USART.
MISO1 — Master In Slave Out for SSP1.
-
I/O
I/O
-
-
I; PU
PIO1_22 — General purpose digital input/output
pin.
-
-
I
RI — Ring Indicator input for USART.
MOSI1 — Master Out Slave In for SSP1.
I/O
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
16 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[3]
PIO1_23/CT16B1_MAT1/
SSEL1
-
13
18 24
I; PU
-
I/O
O
PIO1_23 — General purpose digital input/output
pin.
CT16B1_MAT1 — Match output 1 for 16-bit timer
1.
-
I/O
I/O
SSEL1 — Slave select for SSP1.
[3]
[3]
[3]
PIO1_24/CT32B0_MAT0
PIO1_25/CT32B0_MAT1
-
-
-
14
-
21 27
I; PU
PIO1_24 — General purpose digital input/output
pin.
-
O
CT32B0_MAT0 — Match output 0 for 32-bit timer
0.
1
2
I; PU
I/O
O
PIO1_25 — General purpose digital input/output
pin.
-
CT32B0_MAT1 — Match output 1 for 32-bit timer
0.
PIO1_26/CT32B0_MAT2/
RXD/IOH_19
-
11 14
I; PU
-
I/O
O
PIO1_26 — General purpose digital input/output
pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer
0.
-
-
I
RXD — Receiver input for USART.
I/O
IOH_19 — I/O Handler input/output 18.
(LPC11E37HFBD64/401 only.)
[3]
PIO1_27/CT32B0_MAT3/
TXD/IOH_20
-
-
12 15
I; PU
-
I/O
O
PIO1_27 — General purpose digital input/output
pin.
CT32B0_MAT3 — Match output 3 for 32-bit timer
0.
-
-
O
TXD — Transmitter output for USART.
I/O
IOH_20 — I/O Handler input/output 20.
(LPC11E37HFBD64/401 only.)
[3]
PIO1_28/CT32B0_CAP0/
SCLK
-
-
24 31
I; PU
I/O
I
PIO1_28 — General purpose digital input/output
pin.
-
CT32B0_CAP0 — Capture input 0 for 32-bit timer
0.
-
I/O
I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
[3]
[3]
PIO1_29/SCK0/
CT32B0_CAP1
-
-
-
-
31 41
I; PU
PIO1_29 — General purpose digital input/output
pin.
-
-
I/O
I
SCK0 — Serial clock for SSP0.
CT32B0_CAP1 — Capture input 1 for 32-bit timer
0.
PIO1_31
25
-
I; PU
I/O
PIO1_31 — General purpose digital input/output
pin.
n.c.
n.c.
-
-
-
-
19 25
20 26
-
-
-
-
Not connected.
Not connected.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
17 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type Description
state
[1]
[7]
[7]
XTALIN
4
5
4
5
6
8
-
-
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.8 V.
XTALOUT
VDD
7
9
-
-
-
-
Output from the oscillator amplifier.
6; 29 6;
29
8;
10;
Supply voltage to the internal regulator, the
external rail, and the ADC. Also used as the ADC
reference voltage.
44 33;
48;
58
VSS
33;
13;
14
33
5;
7;
-
-
Ground.
41 54
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 29 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28).
[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28);
includes high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 28); includes digital
input glitch filter.
[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating.
7. Functional description
7.1 On-chip flash programming memory
The LPC11E3x contain up to 128 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages can be erased using the IAP erase page command.
7.2 EEPROM
The LPC11E3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip boot loader software.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
18 of 71
LPC11E3x
NXP Semiconductors
7.3 SRAM
32-bit ARM Cortex-M0 microcontroller
The LPC11E3x contain a total of 10 kB (LPC11E37HFBD64/401) or 12 kB on-chip static
RAM memory.
On the LPC11E37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to
0x2000 07FFF is used for the I/O Handler software library. Do not use this memory
location for data or other user code.
7.4 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
• IAP support for EEPROM.
• Power profiles for configuring power consumption and PLL settings.
• 32-bit integer division routines.
7.5 Memory map
The LPC11E3x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This addressing scheme allows simplifying the address
decoding for each peripheral.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
19 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC11E3x
4 GB
0xFFFF FFFF
reserved
0xE010 0000
0xE000 0000
private peripheral bus
reserved
GPIO
0x5000 4000
0x5000 0000
APB peripherals
0x4008 0000
reserved
0x4008 4000
0x4008 0000
0x4000 0000
25 - 31 reserved
0x4006 4000
reserved
GPIO GROUP1 INT
24
0x4006 0000
0x4005 C000
APB peripherals
GPIO GROUP0 INT
23
22
1 GB
SSP1
0x4005 8000
0x4004 C000
20 - 21 reserved
reserved
GPIO interrupts
19
0x2000 4800
0x2000 4000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
2 kB SRAM2
reserved
system control
IOCON
18
17
16
SSP0
0x2000 0800
0x2000 0000
15 flash/EEPROM controller
2 kB SRAM1/
I/O Handler code area
for LPC11E37HFBD64/401
0x4003 C000
0x4003 8000
14
PMU
0.5 GB
10 - 13 reserved
reserved
0x1FFF 4000
0x1FFF 0000
0x4002 8000
0x4002 4000
0x4002 0000
16 kB boot ROM
reserved
9
reserved
8
reserved
ADC
7
6
5
4
3
2
0x4001 C000
0x4001 8000
0x1000 2000
0x1000 0000
32-bit counter/timer 1
8 kB SRAM0
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
USART/SMART CARD
WWDT
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
reserved
1
0
0x4000 4000
0x4000 0000
2
0x0002 0000
0x0001 8000
I C-bus
128 kB on-chip flash (LPC11E37)
96 kB on-chip flash (LPC11E36)
0x0000 00C0
active interrupt vectors
0x0000 0000
0x0000 0000
0 GB
002aah405
Fig 6. LPC11E3x memory map
7.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11E3x, the NVIC supports 24 vectored interrupts.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
20 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but can have several
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
7.7 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Connect peripherals to the appropriate pins before activating the peripheral and before
enabling any related interrupt. . Activity of any enabled peripheral function that is not
mapped to a related pin is treated as undefined.
7.7.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
7.8 General-Purpose Input/Output GPIO
The GPIO registers control device pin functions that are not connected to a specific
peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple
outputs can be set or cleared in one write operation.
LPC11E3x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.
2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
pins.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
21 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.8.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Any pin or pins in each port can trigger a port interrupt.
7.9 I/O Handler (LPC11E37HFBD64/401 only)
The I/O Handler is a software library-supported hardware engine for emulating serial
interfaces and DMA. The I/O Handler can emulate serial interfaces such as UART, I2C, or
I2S with no or very low additional CPU load. The software libraries are available with
supporting application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil,
and IAR IDEs are supported. I/O Handler library code must be executed from the memory
area 0x2000 0000 to 0x2000 07FF. This memory is not available for other use.
For application examples, see Section 11.7 “I/O Handler software library applications”.
7.10 USART
The LPC11E3x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16 byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
22 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.11 SSP serial I/O controller
The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode).
• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments
SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
7.12 I2C-bus serial I/O controller
The LPC11E3x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and
more than one bus master connected to the interface can be controlled the bus.
7.12.1 Features
• The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
23 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.13 10-bit ADC
The LPC11E3x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD
.
• 10-bit conversion time 2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 General purpose external event counter/timers
The LPC11E3x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.14.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
24 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.15 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.16 Windowed WatchDog Timer (WWDT)
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.16.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
• Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
• Incorrect feed sequence causes reset or interrupt, if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
7.17 Clocking and power control
7.17.1 Integrated oscillators
The LPC11E3x include three independent oscillators: the system oscillator, the Internal
RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more
than one purpose as required in a particular application.
Following reset, the LPC11E3x operates from the internal RC oscillator until software
switches to a different clock source. The IRC allows the system to operate without any
external crystal and the bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC11E3x clock generation.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
25 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
CPU, system control,
PMU
system clock
n
SYSTEM CLOCK
DIVIDER
memories,
peripheral clocks
SYSAHBCLKCTRLn
(AHB clock enable)
IRC oscillator
main clock
SSP0 PERIPHERAL
CLOCK DIVIDER
SSP0
UART
SSP1
watchdog oscillator
USART PERIPHERAL
CLOCK DIVIDER
MAINCLKSEL
(main clock select)
SSP1 PERIPHERAL
CLOCK DIVIDER
IRC oscillator
SYSTEM PLL
system oscillator
SYSPLLCLKSEL
(system PLL clock select)
IRC oscillator
system oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
watchdog oscillator
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator
WDT
watchdog oscillator
WDCLKSEL
(WDT clock select)
002aah406
Fig 7. LPC11E3x clocking generation block diagram
7.17.1.1 Internal RC oscillator
The IRC can be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and then the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11E3x
use the IRC as the clock source. Software can later switch to one of the other available
clock sources.
7.17.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
26 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.17.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 % (see also Table 13).
7.17.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL
as a clock source. The PLL settling time is 100 s.
7.17.3 Clock output
The LPC11E3x feature a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.17.4 Wake-up process
The LPC11E3x begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode. This mechanism allows
chip operation to resume quickly. If the application uses the main oscillator or the PLL,
software must enable these components and wait for them to stabilize. Only then can the
system use the PLL and main oscillator as a clock source.
7.17.5 Power control
The LPC11E3x support various power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
7.17.5.1 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11E3x for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
27 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.17.5.2 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and can generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, by memory systems and related controllers, and by
internal buses.
7.17.5.3 Deep-sleep mode
In Deep-sleep mode, the LPC11E3x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for the IRC. The IRC output is disabled unless the IRC is
selected as input to the watchdog timer. In addition all analog blocks are shut down and
the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog
oscillator and the BOD circuit running for self-timed wake-up and BOD protection.
The LPC11E3x can wake up from Deep-sleep mode via reset, selected GPIO pins or a
watchdog timer interrupt.
Deep-sleep mode saves power and allows for short wake-up times.
7.17.5.4 Power-down mode
In Power-down mode, the LPC11E3x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for watchdog oscillator if selected. In addition all analog
blocks and the flash are shut down. In Power-down mode, the application can keep the
BOD circuit running for BOD protection.
The LPC11E3x can wake up from Power-down mode via reset, selected GPIO pins or a
watchdog timer interrupt.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.17.5.5 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin. The LPC11E3x can wake up from Deep power-down mode via the WAKEUP pin.
The LPC11E3x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
28 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.17.6 System control
7.17.6.1 Reset
Reset has four sources on the LPC11E3x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
7.17.6.2 Brownout detection
The LPC11E3x includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
7.17.6.3 Code security (Code Read Protection - CRP)
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Exx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
29 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Exx user manual.
7.17.6.4 APB interface
The APB peripherals are located on one APB bus.
7.17.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.17.6.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
30 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.18 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11E3x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
31 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
[2]
VDD
supply voltage (core and
external rail)
0.5
+4.6
V
[5][2]
VI
input voltage
5 V tolerant digital I/O pins;
VDD 1.8 V
0.5
+5.5
V
V
VDD = 0 V
0.5
0.5
+3.6
+5.5
[2][4]
5 V tolerant open-drain pins
PIO0_4 and PIO0_5
[2]
[3]
VIA
analog input voltage
pin configured as analog input
0.5
4.6
V
IDD
supply current
per supply pin
-
-
-
100
100
100
mA
mA
mA
ISS
ground current
I/O latch-up current
per ground pin
(0.5VDD) < VI < (1.5VDD);
Tj < 125 C
Ilatch
[6]
Tstg
storage temperature
non-operating
65
+150
150
C
C
Tj(max)
maximum junction
temperature
-
Ptot(pack)
total power dissipation (per
package)
based on package heat
transfer, not device power
consumption
-
-
1.5
W
V
[7]
VESD
electrostatic discharge
voltage
human body model; all pins
+6500
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 5.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 6 for maximum operating voltage.
[4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5] Including voltage on outputs in 3-state mode.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
32 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9. Static characteristics
Table 5.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
VDD
supply voltage (core
and external rail)
1.8
3.3
3.6
V
IDD
supply current
Active mode; VDD = 3.3 V;
Tamb = 25 C; code
while(1){}
executed from flash;
system clock = 12 MHz
[2][3][4]
[5][6]
-
-
-
2
7
1
-
-
-
mA
mA
mA
[3][4][5]
[6]
system clock = 50 MHz
[2][3][4]
[5][6]
Sleep mode;
VDD = 3.3 V; Tamb = 25 C;
system clock = 12 MHz
[3]
Deep-sleep mode; VDD = 3.3 V;
Tamb = 25 C
-
-
-
300
2
-
-
-
A
A
nA
Power-down mode; VDD = 3.3 V;
Tamb = 25 C
[8]
Deep power-down mode;
220
VDD = 3.3 V; Tamb = 25 C
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
0.5
0.5
-
10
10
10
5.0
nA
nA
nA
V
IIH
IOZ
VI
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
[9]
input voltage
pin configured to provide a digital
0
[10]
function; VDD 1.8 V
VDD = 0 V
0
-
-
-
3.6
VDD
-
V
V
V
VO
output voltage
output active
0
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
VOH
-
0.4
-
V
HIGH-level output
voltage
2.0 V VDD 3.6 V; IOH = 4 mA
1.8 V VDD < 2.0 V; IOH = 3 mA
2.0 V VDD 3.6 V; IOL = 4 mA
1.8 V VDD < 2.0 V; IOL = 3 mA
VOH = VDD 0.4 V;
VDD 0.4
-
-
-
-
-
-
V
VDD 0.4
-
V
VOL
LOW-level output
voltage
-
0.4
0.4
-
V
-
V
IOH
HIGH-level output
current
4
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
mA
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
33 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 5.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
IOL
LOW-level output
current
VOL = 0.4 V
4
-
-
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
-
-
mA
mA
[11]
[11]
IOHS
IOLS
HIGH-level short-circuit VOH = 0 V
output current
45
LOW-level short-circuit VOL = VDD
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V;
10
50
150
A
A
15
50
85
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
10
50
85
A
A
VDD < VI < 5 V
0
0
0
High-drive output pin (PIO0_7)
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
0.5
0.5
-
10
10
10
5.0
nA
nA
nA
V
IIH
IOZ
VI
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
[9]
input voltage
pin configured to provide a digital
function
0
[10]
V
DD = 0 V
0
-
-
-
3.6
VDD
-
V
V
V
VO
output voltage
output active
0
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
-
-
-
-
-
-
0.3VDD
V
Vhys
VOH
0.4
-
V
HIGH-level output
voltage
2.5 V VDD 3.6 V; IOH = 20 mA
1.8 V VDD < 2.5 V; IOH = 12 mA
2.0 V VDD 3.6 V; IOL = 4 mA
1.8 V VDD < 2.0 V; IOL = 3 mA
VDD 0.4
-
V
VDD 0.4
-
V
VOL
LOW-level output
voltage
-
0.4
0.4
-
V
-
V
IOH
HIGH-level output
current
VOH = VDD 0.4 V;
2.5 V VDD 3.6 V
20
mA
1.8 V VDD < 2.5 V
VOL = 0.4 V
12
4
-
-
-
-
mA
mA
IOL
LOW-level output
current
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
-
-
mA
mA
[11]
IOLS
Ipd
LOW-level short-circuit VOL = VDD
output current
50
pull-down current
VI = 5 V
10
50
150
A
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
34 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 5.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Ipu pull-up current
Conditions
Min
Typ[1]
Max
Unit
VI = 0 V
15
50
85
A
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VDD < VI < 5 V
10
50
85
A
A
0
0
0
I2C-bus pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
IOL
-
0.05VDD
-
-
-
V
LOW-level output
current
VOL = 0.4 V; I2C-bus pins configured
as standard mode pins
3.5
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VOL = 0.4 V; I2C-bus pins configured
as Fast-mode Plus pins
3
-
-
-
-
IOL
LOW-level output
current
20
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VI = VDD
16
-
-
-
[12]
ILI
input leakage current
2
4
A
A
VI = 5 V
-
10
22
Oscillator pins
Vi(xtal) crystal input voltage
Vo(xtal) crystal output voltage
Pin capacitance
Cio input/output
capacitance
0.5
0.5
1.8
1.8
1.95
1.95
V
V
pins configured for analog function
I2C-bus pins (PIO0_4 and PIO0_5)
pins configured as GPIO
-
-
-
-
-
-
7.1
2.5
2.8
pF
pF
pF
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] IRC enabled; system oscillator disabled; system PLL disabled.
[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] BOD disabled.
[5] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block.
[6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[7] IRC disabled; system oscillator enabled; system PLL enabled.
[8] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[9] Including voltage on outputs in 3-state mode.
[10] 3-state outputs go into 3-state mode in Deep power-down mode.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[12] To VSS
.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
35 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
ADC static characteristics
Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
VIA
Parameter
Conditions
Min
Typ
Max
VDD
1
Unit
V
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cia
pF
[1][2]
[3]
ED
1
LSB
LSB
LSB
%
EL(adj)
EO
1.5
3.5
0.6
4
[4]
[5]
EG
gain error
[6]
ET
absolute error
LSB
k
Rvsi
voltage source interface
resistance
40
[7][8]
Ri
input resistance
-
-
2.5
M
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 8.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 8.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 8.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 8.
[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
36 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
offset error
E
O
V
− V
SS
DD
1 LSB =
1024
002aaf426
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 8. ADC characteristics
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
37 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9.1 BOD static characteristics
Table 7.
BOD static characteristics[1]
Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage interrupt level 1
assertion
-
-
2.22
2.35
-
-
V
V
de-assertion
interrupt level 2
assertion
-
-
2.52
2.66
-
-
V
V
de-assertion
interrupt level 3
assertion
-
-
2.80
2.90
-
-
V
V
de-assertion
reset level 0
assertion
-
-
1.46
1.63
-
-
V
V
de-assertion
reset level 1
assertion
-
-
2.06
2.15
-
-
V
V
de-assertion
reset level 2
assertion
-
-
2.35
2.43
-
-
V
V
de-assertion
reset level 3
assertion
-
-
2.63
2.71
-
-
V
V
de-assertion
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the
LPC11Exx user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see the LPC11Exx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
38 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aag749
9
6
3
0
(2)
48 MHz
I
DD
(mA)
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
1.8
2.4
3.0
3.6
V
(V)
DD
Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash;
internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9. Typical supply current versus regulator supply voltage VDD in active mode
002aag750
9
(2)
48 MHz
I
DD
(mA)
6
3
0
(2)
36 MHz
(2)
(1)
24 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal
pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL
register; all peripheral clocks disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 10. Typical supply current versus temperature in Active mode
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
39 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aag751
4
3
2
1
0
I
DD
(mA)
(2)
48 MHz
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD
disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled;
low-current mode..
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 11. Typical supply current versus temperature in Sleep mode
002aag745
385
I
DD
(µA)
375
V
V
= 3.6 V
= 3.3 V
DD
DD
365
355
345
V
V
= 2.0 V
= 1.8 V
DD
DD
-40
-15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register.
Fig 12. Typical supply current versus temperature in Deep-sleep mode
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
40 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aag746
20
I
DD
V
= 3.6 V, 3.3 V
DD
(µA)
V
DD
= 2.0 V
V
DD
= 1.8 V
15
10
5
0
-40
-15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register.
Fig 13. Typical supply current versus temperature in Power-down mode
002aag747
0.8
I
DD
V
DD
V
DD
V
DD
V
DD
= 3.6 V
= 3.3 V
= 2.0 V
= 1.8 V
(µA)
0.6
0.4
0.2
0
-40
-15
10
35
60
85
temperature (°C)
Fig 14. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
41 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 8.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in
mA
Notes
n/a
12 MHz 48 MHz
IRC
0.27
-
-
-
-
-
-
System oscillator running; PLL off; independent
of main clock frequency.
System oscillator 0.22
at 12 MHz
IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.004
System oscillator running; PLL off; independent
of main clock frequency.
BOD
0.051
-
-
Independent of main clock frequency.
Main PLL
ADC
-
-
-
0.21
0.08
0.12
-
-
-
0.29
0.47
CLKOUT
Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0
CT16B1
CT32B0
CT32B1
GPIO
-
-
-
-
-
0.02
0.02
0.02
0.02
0.23
0.06
0.06
0.07
0.06
0.88
-
-
-
-
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCONFIG
I2C
-
-
-
-
-
-
-
0.03
0.04
0.04
0.12
0.12
0.22
0.02
0.10
0.13
0.15
0.45
0.45
0.82
0.06
-
-
-
-
-
-
ROM
SPI0
SPI1
UART
WWDT
Main clock selected as clock source for the
WDT.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
42 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9.4 Electrical pin characteristics
002aae990
3.6
V
(V)
OH
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
I
(mA)
OH
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH
.
002aaf019
60
I
T = 85 °C
25 °C
−40 °C
OL
(mA)
40
20
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
43 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aae991
15
I
OL
T = 85 °C
25 °C
−40 °C
(mA)
10
5
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL
002aae992
3.6
V
OH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
I
(mA)
OH
Conditions: VDD = 3.3 V; standard port pins.
Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
44 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aae988
10
I
pu
(μA)
−10
−30
−50
−70
T = 85 °C
25 °C
−40 °C
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 19. Typical pull-up current Ipu versus input voltage VI
002aae989
80
T = 85 °C
I
pd
25 °C
(μA)
−40 °C
60
40
20
0
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 20. Typical pull-down current Ipd versus input voltage VI
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
45 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10. Dynamic characteristics
10.1 Flash memory
Table 9.
Flash characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
Typ
Max
Unit
[1]
10000 100000
-
cycles
years
years
ms
retention time
powered
10
20
95
-
-
unpowered
-
-
ter
erase time
sector or multiple
100
105
consecutive sectors
[2]
tprog
programming time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
Table 10. EEPROM characteristics
Tamb = 40 C to +85 C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate <
10 ppm for parts as specified below.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
100000
100
150
-
Typ
Max
Unit
1000000
200
-
-
-
-
cycles
years
years
ms
retention time
powered
unpowered
300
tprog
programming time 64 bytes
2.9
10.2 External clock
Table 11. Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
Symbol
fosc
Parameter
Min
Typ[2]
Max
Unit
MHz
ns
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
1
-
-
-
-
-
-
25
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
40
1000
Tcy(clk) 0.4
-
ns
Tcy(clk) 0.4
-
ns
-
-
5
5
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
46 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
10.3 Internal oscillators
Table 12. Dynamic characteristics: IRC
amb = 40 C to +85 C; 2.7 V VDD 3.6 V[1].
T
Symbol
fosc(RC)
Parameter
Conditions
Min
Typ[2]
Max
Unit
internal RC oscillator
frequency
-
11.88
12
12.12
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aaf403
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
12.05
2.4 V
2.0 V
11.95
11.85
−40
−15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 22. Internal RC oscillator frequency versus temperature
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
47 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 13. Dynamic characteristics: Watchdog oscillator
Symbol Parameter Conditions
fosc(int) internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
Min Typ[1] Max Unit
[2][3]
[2][3]
-
9.4
-
kHz
frequency
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
-
2300
-
kHz
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3] See the LPC11Exx user manual.
10.4 I/O pins
Table 14. Dynamic characteristics: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V.
Symbol Parameter Conditions
Min
3.0
2.5
Typ
Max
5.0
Unit
ns
tr
tf
rise time
fall time
pin configured as output
pin configured as output
-
-
5.0
ns
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
100
400
1
Unit
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
0
0
0
-
kHz
kHz
MHz
ns
Fast-mode Plus
[3][4][5][6]
tf
fall time
of both SDA and SCL
signals
300
Standard-mode
Fast-mode
20 + 0.1 Cb
300
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of the
SCL clock
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
HIGH period of the
SCL clock
Fast-mode Plus
Standard-mode
Fast-mode
[3][7][8]
[9][10]
tHD;DAT
data hold time
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up time
250
100
50
Fast-mode Plus
[1] See the I2C-bus specification UM10204 for details.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
48 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
f
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 23. I2C-bus pins clock timing
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
49 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10.6 SSP interface
Table 16. Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
[1]
[1]
[2]
Tcy(clk)
clock cycle time
data set-up time
full-duplex mode
when only transmitting
in SPI mode
50
40
15
-
-
-
-
ns
ns
ns
tDS
2.4 V VDD 3.6 V
2.0 V VDD < 2.4 V
1.8 V VDD < 2.0 V
in SPI mode
[2]
[2]
[2]
[2]
[2]
20
24
0
ns
ns
ns
ns
ns
-
-
-
-
-
tDH
data hold time
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
10
-
0
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time
20
-
-
-
-
-
-
ns
ns
ns
ns
ns
[3][4]
[3][4]
[3][4]
[3][4]
tDS
data set-up time
data hold time
in SPI mode
in SPI mode
0
-
tDH
3 Tcy(PCLK) + 4
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
-
3 Tcy(PCLK) + 11
2 Tcy(PCLK) + 5
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2]
[3] Tcy(clk) = 12 Tcy(PCLK)
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
Tamb = 40 C to 85 C.
.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
50 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
DATA VALID
MISO
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Fig 24. SSP master timing in SPI mode
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
51 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
v(Q)
DATA VALID
002aae830
Fig 25. SSP slave timing in SPI mode
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
52 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
11. Application information
11.1 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.
LPC1xxx
XTALIN
C
i
C
g
100 pF
002aae788
Fig 26. Slave mode operation of the on-chip oscillator
In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 26), with an
amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a
square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin
in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 27 and in
Table 17 and Table 18. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (L, CL and RS represent the fundamental frequency).
Capacitance CP in Figure 27 represents the parallel package capacitance and must not be
larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
53 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC1xxx
L
XTALIN
XTALOUT
C
L
C
P
=
XTAL
R
S
C
X2
C
X1
002aaf424
Fig 27. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 17. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
1 MHz to 5 MHz
10 pF
< 300
< 300
< 300
< 300
< 200
< 100
< 160
< 60
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
20 pF
30 pF
5 MHz to 10 MHz
10 pF
20 pF
30 pF
10 MHz to 15 MHz
15 MHz to 20 MHz
10 pF
20 pF
10 pF
< 80
Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
15 MHz to 20 MHz
10 pF
< 180
< 100
< 160
< 80
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
20 pF
20 MHz to 25 MHz
10 pF
20 pF
11.2 XTAL Printed-Circuit Board (PCB) layout guidelines
Follow these guidelines for PCB layout:
• Connect the crystal on the PCB as close as possible to the oscillator input and output
pins of the chip.
• Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal
use have a common ground plane.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
54 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
• Connect the external components to the ground plain.
• To keep parasitics and the noise coupled in via the PCB as small as possible, keep
loops as small as possible.
• Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase.
11.3 Standard I/O pad configuration
Figure 28 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver.
• Digital input: Pull-up enabled/disabled.
• Digital input: Pull-down enabled/disabled.
• Digital input: Repeater mode enabled/disabled.
• Analog input.
V
DD
V
DD
open-drain enable
output enable
data output
strong
pull-up
ESD
pin configured
as digital output
driver
PIN
strong
pull-down
ESD
V
SS
V
DD
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
10 ns RC
GLITCH FILTER
select data
inverter
select glitch
filter
select analog input
pin configured
as analog input
analog input
002aaf695
Fig 28. Standard I/O pad configuration
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
55 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
11.4 Reset pad configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 29. Reset pad configuration
11.5 ADC effective input impedance
A simplified diagram of the ADC input channels can be used to determine the effective
input impedance seen from an external voltage source. See Figure 30.
ADC Block
Source
R
mux
R
sw
R
s
ADC
COMPARATOR
<2 kΩ
<1.3 kΩ
R
in
C
ia
V
C
io
EXT
V
SS
002aah615
Fig 30. ADC input channel
The effective input impedance, Rin, seen by the external voltage source, VEXT, is the
parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated
using Equation 1 with
fs = sampling frequency
Cia = ADC analog input capacitance
Rmux = analog mux resistance
Rsw = switch resistance
Cio = pin capacitance
1
1
-----------------
Rin
=
+ Rmux + R
(1)
-----------------
sw
fs Cio
fs Cia
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
56 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Under nominal operating condition VDD = 3.3 V and with the maximum sampling
frequency fs = 400 kHz, the parameters assume the following values:
Cia = 1 pF (max)
Rmux = 2 kΩ (max)
Rsw = 1.3 kΩ (max)
Cio = 7.1 pF (max)
The effective input impedance with these parameters is Rin = 308 kΩ.
11.6 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the LPC11E3x chip.
• Shield The ADC input traces from fast switching digital signals and noisy power
supply lines.
• The ADC and the digital core share the same power supply. Therefore, filter the power
supply line adequately.
• To improve the ADC performance in a noisy environment, put the device in Sleep
mode during the ADC conversion.
11.7 I/O Handler software library applications
The following sections provide application examples for the I/O Handler software library.
All library examples make use of the I/O Handler hardware to extend the functionality of
the part through software library calls. The library is available on
http://www.LPCware.com.
11.7.1 I/O Handler I2S
The I/O Handler software library provides functions to emulate an I2S master transmit
interface using the I/O Handler hardware block.
The emulated I2S interface loops over a 1 kB buffer, transmitting the datawords according
to the I2S protocol. Interrupts are generated every time when the first 512 bytes have been
transmitted and when the last 512 bytes have been transmitted. This allows the ARM core
to load the free portion of the buffer with new data, thereby enabling streaming audio.
Two channels with 16-bit per channel are supported. The code size of the software library
is 1 kB and code must be executed from the SRAM1 memory area reserved for the I/O
Handler code.
11.7.2 I/O Handler UART
The I/O Handler UART library emulates one additional full-duplex UART. The emulated
UART can be configured for 7 or 8 data bits, no parity and 1 or 2 stop bits. The baud rate
is configurable up to 115200 baud. The RXD signal is available on three I/O Handler pins
(IOH_6, IOH_16, IOH_20), while TXD and CTS are available on all 21 I/O Handler pins.
The code size of the software library is about 1.2 kB and code must be executed from the
SRAM1 memory area reserved for the I/O Handler code.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
57 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
11.7.3 I/O Handler I2C
The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write
and combined I2C read/write are supported. Data is automatically read from and written to
user-defined buffers.
The I/O Handler I2C library combined with the on-chip I2C module allows to have two
distinct I2C buses, allowing to separate low-speed from high-speed devices or bridging
two I2C buses.
11.7.4 I/O Handler DMA
The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are
supported: memory to memory, memory to peripheral, peripheral to memory and
peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO.
DMA transfers can be triggered by the source/target peripheral, software, counter/timer
module CT16B1, or I/O Handler pin PIO1_6/IOH_16.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
58 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
v
C
C
A
B
e
b
y
1
y
w
C
9
16
L
8
17
e
E
e
2
h
33
1
24
X
terminal 1
index area
32
25
0
D
h
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
b
c
D
D
E
E
e
e
1
e
2
L
w
y
y
1
1
h
h
max 1.00 0.05 0.35
mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1
min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45
7.1 4.85 7.1 4.85
0.75
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
09-03-17
09-03-23
Fig 31. Package outline HVQFN33 (7 x 7 x 0.85 mm)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
59 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
v
C
C
A
B
C
1
e
1/2 e
b
w
9
16
L
17
8
e
e
E
h
2
1/2 e
24
1
terminal 1
index area
32
25
X
D
h
0
2.5
scale
5 mm
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
Unit
A
A
1
b
c
D
D
h
E
E
e
e
1
e
2
L
v
w
y
y
1
h
max
0.05 0.30
5.1 3.75 5.1 3.75
0.5
mm nom 0.85
min
0.2
0.5 3.5 3.5
0.1 0.05 0.05 0.1
0.00 0.18
4.9 3.45 4.9 3.45
0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33f_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-10-11
11-10-17
MO-220
Fig 32. Package outline HVQFN33 (5 x 5 x 0.85 mm)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
60 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 33. Package outline LQFP48 (SOT313-2)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
61 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT314-2
136E10
MS-026
Fig 34. Package outline LQFP64 (SOT314-2)
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
62 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
13. Soldering
Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
By
SLy
Hy Gy
nSPy
C
D
SLx
Bx
Ax
0.60
0.30
solder land
solder paste
occupied area
detail X
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
Hx
Hy
6.2
SLx
SLy
nSPx nSPy
0.5
5.95
5.95
4.25
4.25
0.85
0.27
5.25
5.25
6.2
3.75
3.75
3
3
11-11-15
11-11-20
Issue date
002aag766
Fig 35. Reflow soldering for the HVQFN33 (5x5) package
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
63 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
chamfer (4×)
W = 0.30 CU
e = 0.65
SPD = 1.00 SP
0.45 DM
GapD = 0.70 SP
evia = 2.40
B-side
SDhtot = 2.70 SP
Solder resist
covered via
4.55 SR
DHS = 4.85 CU
LbD = 5.80 CU
LaD = 7.95 CU
0.30 PH
0.60 SR cover
0.60 CU
(A-side fully covered)
number of vias: 20
solder land
solder land plus solder paste
solder paste deposit
occupied area
solder resist
Remark:
Stencil thickness: 0.125 mm
Dimensions in mm
001aao134
Fig 36. Reflow soldering for the HVQFN33 (7x7) package
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
64 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650
sot313-2_fr
Fig 37. Reflow soldering for the LQFP48 package
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
65 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of LQFP64 package
SOT314-2
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550
sot314-2_fr
Fig 38. Reflow soldering for the LQFP64 package
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
66 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
14. Revision history
Table 19. Revision history
Document ID
LPC11E3X v.2.3
Modifications:
LPC11E3X v.2.2
Modifications:
LPC11E3X v.2.1
Modifications:
Release date
20140911
Data sheet status
Change notice
Supersedes
Product data sheet
LPC11E3X v.2.2
Added part LPC11E35FHI33/501.
20140114 Product data sheet
ISP mode removed from pin PIO0_3 in Table 3.
20131230 Product data sheet
-
-
LPC11E3X v.2.1
LPC11E3X v.2
Add reserved function to pins PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 and
PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7.
LPC11E3X v.2
Modifications:
20131121
Product data sheet
-
LPC11E3X v.1.1
• Parts LPC11E3HFBD64/401 added.
• 8 kB SRAM block at 0x1000 000 renamed to SRAM0 in Figure 5.
• I/O Handler pins added in Table 3.
• Typical range of watchdog oscillator frequency changed to 9.4 kHz to 2.3 MHz.
• Section 11.7 “I/O Handler software library applications” added.
• Condition VDD = 0 V added to Parameter VI in Table 5 for clarity.
LPC11E3X v.1.1
Modifications:
20130924
Product data sheet
-
LPC11E3X v.1
• Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note.
• Table 7: Removed BOD interrupt level 0.
• Added Section 11.5 “ADC effective input impedance”.
• Programmable glitch filter is enabled by default. See Section 7.7.1.
• Table 5 “Static characteristics” added Pin capacitance section.
• Table 4 “Limiting values”:
–
Updated VDD min and max.
–
Updated VI conditions.
• Table 10 “EEPROM characteristics”:
–
Removed fclk and ter; the user does not have control over these parameters.
–
Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always does an erase and
program, thus the total program time is ter + tprog
.
LPC11E3X v.1
20121107 Objective data sheet
-
-
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
67 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
68 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
15.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
69 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
17. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.17.4
7.17.5
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 27
Power control. . . . . . . . . . . . . . . . . . . . . . . . . 27
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.17.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 27
7.17.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.17.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 28
7.17.5.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 28
7.17.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 28
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
7.17.6
System control . . . . . . . . . . . . . . . . . . . . . . . . 29
7.17.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.17.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 29
7.17.6.3 Code security
(Code Read Protection - CRP) . . . . . . . . . . . 29
7.17.6.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 30
7.17.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.17.6.6 External interrupt inputs. . . . . . . . . . . . . . . . . 30
7
Functional description . . . . . . . . . . . . . . . . . . 18
On-chip flash programming memory . . . . . . . 18
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Nested Vectored Interrupt Controller
7.1
7.2
7.3
7.4
7.5
7.6
7.18
Emulation and debugging . . . . . . . . . . . . . . . 31
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose Input/Output GPIO . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Handler
(LPC11E37HFBD64/401 only) . . . . . . . . . . . . 22
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SSP serial I/O controller . . . . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C-bus serial I/O controller . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General purpose external event
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
System tick timer . . . . . . . . . . . . . . . . . . . . . . 25
Windowed WatchDog Timer
(WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clocking and power control . . . . . . . . . . . . . . 25
Integrated oscillators . . . . . . . . . . . . . . . . . . . 25
9
Static characteristics . . . . . . . . . . . . . . . . . . . 33
BOD static characteristics . . . . . . . . . . . . . . . 38
Power consumption . . . . . . . . . . . . . . . . . . . 38
Peripheral power consumption . . . . . . . . . . . 41
Electrical pin characteristics. . . . . . . . . . . . . . 43
7.6.1
7.6.2
7.7
7.7.1
7.8
9.1
9.2
9.3
9.4
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 46
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SSP interface. . . . . . . . . . . . . . . . . . . . . . . . . 50
7.8.1
7.9
10.1
10.2
10.3
10.4
10.5
10.6
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
11
11.1
11.2
Application information . . . . . . . . . . . . . . . . . 53
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
XTAL Printed-Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . . 54
Standard I/O pad configuration . . . . . . . . . . . 55
Reset pad configuration. . . . . . . . . . . . . . . . . 56
ADC effective input impedance . . . . . . . . . . . 56
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 57
I/O Handler software library
applications . . . . . . . . . . . . . . . . . . . . . . . . . . 57
I/O Handler I2S. . . . . . . . . . . . . . . . . . . . . . . . 57
I/O Handler UART . . . . . . . . . . . . . . . . . . . . . 57
I/O Handler I2C. . . . . . . . . . . . . . . . . . . . . . . . 58
I/O Handler DMA . . . . . . . . . . . . . . . . . . . . . . 58
7.13.1
7.14
11.3
11.4
11.5
11.6
11.7
7.14.1
7.15
7.16
11.7.1
11.7.2
11.7.3
11.7.4
7.16.1
7.17
7.17.1
7.17.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 26
7.17.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26
7.17.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 27
12
13
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 59
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Revision history . . . . . . . . . . . . . . . . . . . . . . . 67
7.17.2
7.17.3
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27
continued >>
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.3 — 11 September 2014
70 of 71
LPC11E3x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 68
15.1
15.2
15.3
15.4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 68
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 69
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2014
Document identifier: LPC11E3X
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明