935309359557 [NXP]
Digital Signal Processor;型号: | 935309359557 |
厂家: | NXP |
描述: | Digital Signal Processor 外围集成电路 |
文件: | 总140页 (文件大小:1251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
56F8323/56F8123
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8323
Rev. 17
04/2007
freescale.com
Document Revision History
Version History
Rev 1.0
Description of Change
Pre-Release version, Alpha customers only
Rev 2.0
Rev 3.0
Initial Public Release
Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar
issues.
Rev 4.0
Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in Table 10-5.
Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of
language throughout family. Updated values in Regulator Parameters, Table 10-9, External Clock
Operation Timing Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters,
Table 10-24, and IO Loading Coefficients at 10MHz, Table 10-25.
Rev 5.0
Rev 6.0
Updated values in Power-On Reset Low Voltage, Table 10-6.
Correcting package pin numbers in Table 2-2, PhaseA0 changed from 38 to 52, PhaseB0 changed
from 37 to 51, Index0 changed from 36 to 50, and Home0 changed from 35 to 49. All pin changes in
Table 2-2 were do to data entry errors - This package pin-out has not changed
Rev 7.0
Added Part 4.8, added addition text to Part 6.9 on POR reset, added the word “access” to FM Error
Interrupt in Table 4-3, removed min and max numbers; only documenting Typ. numbers for LVI in
Table 10-6.
Rev 8.0
Rev 9.0
Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in Table 10-3 in
Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; changed example in Part
2.2; added note on VREFH and VREFLO in Table 2-2 and Table 11-1; added note to Vcap pin in
Table 2-2; corrected typo FIVAL1 and FIVAH1 in Table 4-12; removed unneccessary notes in
Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to
Table 10-24 and new graphs in Figure 10-21.
Rev 10.0
Rev. 11.0
Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
Added 56F8123 information; edited to indicate differences in 56F8323 and 56F8123.Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of
electrical tables for consistency throughout the family. Clarified I/O power description in Table 2-2,
added note to Table 10-7 and clarified Section 12.3 .
Rev 12.0
Rev 13.0
Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be determined by
reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3.
Corrected note about average value for Flash Data Retention in Table 10-4. Added new
RoHS-compliant orderable part numbers in Table 13-1.
Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating
Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back
cover.
56F8323 Technical Data, Rev. 17
2
Freescale Semiconductor
Preliminary
Document Revision History
Version History
Rev 14.0
Description of Change
Added information/corrected state during reset in Table 2-2. Clarified external reference crystal
frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz.
Rev 15.0
Rev. 16
Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2.
• Added the following note to the description of the TMS signal in Table 2-2:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Added the following note to the description of the TRST signal in Table 2-2:
Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging
environment, TRST may be tied to VSS through a 1K resistor.
Rev. 17
Changed the “Frequency Accuracy” specification in Table 10-16 (was ±2.0%, is +2 / -3%).
Please see http://www.freescale.com for the most current data sheet revision.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
3
56F8323 Technical Data, Rev. 17
4
Freescale Semiconductor
Preliminary
56F8323/56F8123 General Description
Note: Features in italics are NOT available in the 56F8123 device.
• Up to 60 MIPS at 60MHz core frequency
• One Quadrature Decoder
• DSP and MCU functionality in a unified,
C-efficient architecture
• One FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• One 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Temperature Sensor
• Up to 27 GPIO lines
• 64-pin LQFP Package
OCR_DIS
V
V
V
V
V
SSA
RESET
CAP
DD
SS
DDA
5
4
4
4
2
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
6
PWM Outputs
PWMA or
Low Voltage
Supervisor
16-Bit
3
SPI1 or
GPIOA
Current Sense Inputs
56800E Core
3
Fault Inputs
Data ALU
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
16 x 16 + 36 −> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
PAB
PDB
CDBR
CDBW
4
4
AD0
AD1
R/W Control
Memory
XDB2
XAB1
XAB2
5
Program Memory
16K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
VREF
TEMP_SENSE
PAB
System Bus
Control
PDB
CDBR
CDBW
Quadrature
Decoder 0 or
Quad
Timer A or
GPIO B
Data Memory
4K x 16 Flash
4K x 16 RAM
4
IPBus Bridge (IPBB)
Quad
Timer C or
SCI0 or
GPIOC
Peripheral
Device Selects
3
2
RW
Control
IPAB IPWDB
IPRDB
Decoding
Peripherals
FlexCANor
GPIOC
Clock
resets
PLL
P
O
R
SPI0 or
SCI1 or
GPIOB
Interrupt
Controller
COP/
Watchdog
System
Integration
Module
XTAL or GPIOC
EXTAL or GPIOC
O
Clock
Generator*
S
C
*Includes On-Chip
Relaxation Oscillator
4
IRQA
56F8323/56F8123 Block Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
5
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . .7
Part 8: General Purpose Input/Output
1.1. 56F8323/56F8123 Features . . . . . . . . . . . . . 7
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 9
1.3. Award-Winning Development Environment 10
1.4. Architecture Block Diagram . . . . . . . . . . . . 11
1.5. Product Documentation . . . . . . . . . . . . . . . 15
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 15
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 102
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 102
8.2. Configuration. . . . . . . . . . . . . . . . . . . . . . . 102
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . .104
Part 9: Joint Test Action Group (JTAG) . . 104
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 104
Part 2: Signal/Connection Descriptions . . 16
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part 10: Specifications. . . . . . . . . . . . . . . . 105
10.1. General Characteristics . . . . . . . . . . . . . .105
10.2. DC Electrical Characteristics. . . . . . . . . . 109
10.3. AC Electrical Characteristics . . . . . . . . . .113
10.4. Flash Memory Characteristics. . . . . . . . . 114
10.5. External Clock Operation Timing . . . . . . 114
10.6. Phase Locked Loop Timing . . . . . . . . . . .115
10.7. Crystal Oscillator Parameters . . . . . . . . .115
10.8. Reset, Stop, Wait, Mode Select, and
Part 3: On-Chip Clock Synthesis (OCCS) . .30
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2. External Clock Operation . . . . . . . . . . . . . . 30
3.3. Use of On-Chip Relaxation Oscillator . . . . . 31
3.4. Internal Clock Operation . . . . . . . . . . . . . . . 32
3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt Timing . . . . . . . . . . . . . 117
Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 33
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . 33
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 34
4.4. Data Map. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 37
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 39
4.7. Peripheral Memory Mapped Registers . . . . 40
4.8. Factory Programmed Memory. . . . . . . . . . . 56
10.9. Serial Peripheral Interface (SPI) Timing . .119
10.10. Quad Timer Timing . . . . . . . . . . . . . . . .122
10.11. Quadrature Decoder Timing . . . . . . . . . .122
10.12. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . .123
10.13. Controller Area Network (CAN) Timing. 124
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 124
10.15. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . 126
10.16. Equivalent Circuit for ADC Inputs . . . . . 129
10.17. Power Consumption . . . . . . . . . . . . . . . .129
Part 5: Interrupt Controller (ITCN) . . . . . . . .57
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3. Functional Description . . . . . . . . . . . . . . . . 57
5.4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 59
5.5. Operating Modes. . . . . . . . . . . . . . . . . . . . . 59
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 60
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Part 11: Packaging 131
11.1. 56F8323 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .131
11.2. 56F8123 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 133
Part 12: Design Considerations . . . . . . . . 136
12.1. Thermal Design Considerations . . . . . . . 136
12.2. Electrical Design Considerations . . . . . . .137
12.3. Power Distribution and I/O Ring
Part 6: System Integration Module (SIM) . .83
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 84
6.4. Operating Mode Register . . . . . . . . . . . . . . 84
6.5. Register Descriptions . . . . . . . . . . . . . . . . . 85
6.6. Clock Generation Overview. . . . . . . . . . . . . 97
6.7. Power-Down Modes . . . . . . . . . . . . . . . . . . 97
6.8. Stop and Wait Mode Disable Function . . . . 98
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Implementation. . . . . . . . . . . . . . 138
Part 13: Ordering Information . . . . . . . . . . 139
Part 7: Security Features . . . . . . . . . . . . . . 99
7.1. Operation with Security Enabled . . . . . . . . 99
7.2. Flash Access Blocking Mechanisms . . . . . . 99
56F8323 Technical Data, Rev. 17
6
Freescale Semiconductor
Preliminary
56F8323/56F8123 Features
Part 1 Overview
1.1 56F8323/56F8123 Features
1.1.1
Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800E family engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1 outlines the key differences between the 56F8323 and 56F8123 devices.
Table 1-1 Device Differences
Feature
56F8323
56F8123
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
40MHz/40 MIPS
Not Available
Not Available
Not Available
Not Available
Not Available
Not Available
10
4KB
8KB
1 x 6
1
PWM
CAN
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
1 x 4
1
—
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
7
1.1.3
Memory
Note: Features in italics are NOT available in the 56F8123 device.
•
•
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection
On-chip memory, including a low-cost, high-volume Flash solution
— 32KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
•
EEPROM emulation capability
1.1.4
Peripheral Circuits
Note: Features in italics are NOT available in the 56F8123 device.
•
•
•
•
One Pulse Width Modulator module with six PWM outputs, three Current Sense inputs and three Fault
inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual,
4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channel 2
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip
temperature
Two 16-bit Quad Timer modules (TMR) totaling seven pins:
— In the 56F8323, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction
with the PWMA and ADCA
— In the 56F8123, Timer C works in conjunction with ADCA
One Quadature Decoder which works in conjunction with Quad Timer A
FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
Up to two Serial Communication Interfaces (SCIs)
•
•
•
•
•
•
•
•
•
Up to two Serial Peripheral Interfaces (SPIs)
Computer Operating Properly (COP)/Watchdog timer
One dedicated external interrupt pin
27 General Purpose I/O (GPIO) pins
Integrated Power-On Reset and Low-Voltage Interrupt Module
JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent, real-time
debugging
•
•
Software-programmable, Phase Lock Loop (PLL)
On-chip relaxation oscillator
56F8323 Technical Data, Rev. 17
8
Freescale Semiconductor
Preliminary
Device Description
1.1.5
Energy Information
•
•
•
•
•
•
Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8323 and 56F8123 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of their low cost, configuration flexibility, and compact program code, the 56F8323 and 56F8123 are
well-suited for many applications. The devices include many peripherals that are especially useful for
automotive control (56F8323 only); industrial control and networking; motion control; home appliances;
general purpose inverters; smart sensors; fire and security systems; power management; and medical
monitoring applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model
and optimized instruction set allow straightforward generation of efficient, compact DSP and control
code. The instruction set is also highly efficient for C Compilers to enable rapid development of
optimized control applications.
The 56F8323 and 56F8123 support program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. These devices also provide one external
dedicated interrupt line and up to 27 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
1.2.1
56F8323 Features
The 56F8323 controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable
through the JTAG port, with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash
is incorporated for easy customer inclusion of field-programmable software routines that can be used to
program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be
independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash
page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8323 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and is also capable of supporting six independent PWM functions to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion correction
via current sensing by software, and separate top and bottom output polarity control. The up-counter value
is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
9
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from
1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the
Analog-to-Digital Converters (ADCs) through Quad Timer C, Channel 2.
The 56F8323 incorporates one Quadrature Decoder capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers, and
FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function
is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and
an internal interrupt controller are also a part of the 56F8323.
1.2.2
56F8123 Features
The 56F8123 controller includes 32KB of Program Flash, programmable through the JTAG port, and 8KB
of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of
field-programmable software routines that can be used to program the main Program Flash memory area.
The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page
erase size is 1KB. The Boot Flash memory can also be either bulk or page erased.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8123.
1.3 Award-Winning Development Environment
TM
Processor Expert
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
56F8323 Technical Data, Rev. 17
10
Freescale Semiconductor
Preliminary
Architecture Block Diagram
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8123 device and are shaded in the following figures.
The 56F8323/56F8123 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the
internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the
on-board regulator and power and ground signals. They also do not show the multiplexing between
peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which
signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
11
5
JTAG / EOnCE
Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
Program
RAM
cdbw[31:0]
56800E
CHIP
TAP
Controller
TAP
Linking
Module
Data RAM
Data Flash
xab1[23:0]
xab2[23:0]
External
JTAG Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Control
Logic
IPBus
Bridge
Flash
Memory
Module
NOT available on the 56F8123 device.
IPBus
Figure 1-1 System Bus Interfaces
Note:
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8323 Technical Data, Rev. 17
12
Freescale Semiconductor
Preliminary
Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC/PLL)
(ROSC)
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
RESET
Timer A
4
Quadrature Decoder 0
SIM
COP Reset
COP
SPI 1
2
FlexCAN
4
2
SCI 1
SPI 0
4
8
PWM A
SYNC Output
2
GPIO A
GPIO B
GPIO C
SCI 0
ch2i
3
Timer C
ch2o
8
ADCA
TEMP_SENSE
NOT available on the 56F8123 device.
IPBus
Figure 1-2 Peripheral Subsystem
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
13
Table 1-2 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0]
cdbw[15:0]
Program data bus for instruction word fetches or read operations.
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0]
cdbw[31:0]
xab1[23:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
to 0.
56F8323 Technical Data, Rev. 17
14
Freescale Semiconductor
Preliminary
Product Documentation
1.5 Product Documentation
The documents listed in Table 1-3 are required for a complete description and proper design with the
56F8323 and 56F8123 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com/semiconductors.
Table 1-3 Chip Documentation
Topic
DSP56800E
Description
Order Number
DSP56800ERM
Detailed description of the 56800E family architecture,
16-bit controller core processor, and the instruction set
Reference Manual
56F8300 Peripheral User Detailed description of peripherals of the 56800E family MC56F8300UM
Manual
of devices
56F8300 SCI/CAN
Detailed description of the SCI/CAN Bootloaders
MC56F83xxBLUM
Bootloader User Manual 56F8300 family of devices
56F8323/56F8123
Electrical and timing specifications, pin descriptions, and MC56F8323
Technical Data Sheet
package descriptions (this document)
Errata
Details any chip issues that might be present
MC56F8323E
MC56F8123E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for V , V , V , and V are defined by individual product specifications.
IL
OL
IH
OH
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
15
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as
detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row
describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8323
56F8123
Power (VDD or VDDA
)
6
6
Power Option Control
1
5
1
5
Ground (VSS or VSSA
)
Supply Capacitors1 & VPP
2
4
4
PLL and Clock
2
2
2
2
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports3
Serial Peripheral Interface (SPI) Port 04
12
—
4
4
8
Quadrature Decoder Port 05
CAN Ports
—
2
13
3
—
13
3
Analog-to-Digital Converter (ADC) Ports
Timer Module Port C6
Timer Module Port A
—
5
4
5
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sensse
1
—
10
Dedicated GPIO
—
1. If the on-chip regulator is disabled, the V
pins serve as 2.5V V
power inputs
CAP
DD_CORE
2. The V input shares the IRQA input
PP
3. Pins in this section can function as SPI #1 and GPIO
4. Pins in this section can function as SCI #1 and GPIO
5. Alternately, can function as Quad Timer A pins or GPIO
6. Two pins can function as SCI #0 and GPIO
Note: See Table 1-1 for 56F8123 functional differences.
56F8323 Technical Data, Rev. 17
16
Freescale Semiconductor
Preliminary
Introduction
VDD_IO
VDDA_OSC_PLL
VSS
PHASEA0 (TA0, GPIOB7)
PHASEB0 (TA1, GPIOB6)
INDEX0 (TA2, GPIOB5)
HOME0 (TA3, GPIOB4)
Quadrature
Power
Power
1
1
1
1
4
1
Decoder 0
or Quad
Timer A or
GPIO
Ground
Power
Ground
4
VDDA_ADC
1
1
VSSA_ADC
SCLK0 (GPIOB3)
MOSI0 (GPIOB2)
1
V
CAP1 - VCAP
4
Other
Supply
Ports
SPI0 or
SCI1 or
GPIO
1
1
1
4
1
MISO0 (RXD1, GPIOB1)
SS0 (TXD1, GPIOB0)
OCR_DIS
56F8323
EXTAL (GPIOC0)
XTAL (GPIOC1)
PLL and
Clock or
GPIO
1
1
PWMA0-1 (GPIOA0-1)
2
1
1
1
PWMA2 (SS1, GPIOA2)
PWMA3 (MISO1, GPIOA3)
PWMA4 (MOSI1, GPIOA4)
PWMA5 (SCLK1, GPIOA5)
FAULTA0 - 2 (GPIOA6-8)
ISA0 - 2 (GPIOA9-11)
PWMA or
SPI1 or
GPIO
1
3
3
TEMP_SENSE
1
Temperature
Sensor
ANA0 - 7
VREF
8
5
ADCA
CAN_RX (GPIOC2)
CAN_TX (GPIOC3)
FlexCAN
or GPIO
1
1
TC0 (TXD0, GPIOC6)
TC1 (RXD0, GPIOC5)
TC3 (GPIOC4)
QUAD
TIMER C or
SCI0
1
1
1
TCK
TMS
TDI
1
1
1
JTAG/
EOnCE
Port
or GPIO
IRQA (VPP
RESET
)
TDO
INTERRUPT/
PROGRAM
CONTROL
1
1
1
1
TRST
Figure 2-1 56F8323 Signals Identified by Functional Group (64-Pin LQFP)
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
17
VDD_IO
VDDA_OSC_PLL
VSS
TA0 (GPIOB7)
TA1 (GPIOB6)
TA2 (GPIOB5)
TA3 (GPIOB4)
Power
Power
1
1
1
1
4
1
Quad
Timer A or
GPIO
Ground
Power
Ground
4
VDDA_ADC
1
1
VSSA_ADC
SCLK0 (GPIOB3)
MOSI0 (GPIOB2)
1
SPI0 or
SCI1 or
GPIO
V
CAP1 - VCAP
4
Other
Supply
Ports
1
1
1
4
1
MISO0 (RXD1, GPIOB1)
SS0 (TXD1, GPIOB0)
OCR_DIS
56F8123
EXTAL (GPIOC0)
XTAL (GPIOC1)
PLL and
Clock or
GPIO
1
1
GPIOA0-1
2
1
1
1
SS1 (GPIOA2)
MISO1 (GPIOA3)
MOSI1 (GPIOA4)
SCLK1 (GPIOA5)
GPIOA6-8
SPI1 or
GPIO
1
3
3
GPIOA9-11
ANA0 - 7
VREF
8
5
ADCA
GPIO
GPIOC2
GPIOC3
1
1
TC0 (TXD0, GPIOC6)
TC1 (RXD0, GPIOC5)
TC3 (GPIOC4)
QUAD
TIMER C or
SCI0 or GPIO
1
1
1
TCK
TMS
TDI
1
1
1
JTAG/
EOnCE
Port
IRQA (VPP
RESET
)
TDO
INTERRUPT/
PROGRAM
CONTROL
1
1
1
1
TRST
Figure 2-2 56F8123 Signals Identified by Functional Group (64-Pin LQFP)
56F8323 Technical Data, Rev. 17
18
Freescale Semiconductor
Preliminary
Signal Pins
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). In the 56F8123, after reset, each
pin must be configured for the desired function. The initialization software will configure each pin for the
function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed.
Note: Signals in italics are not available in the 56F8123 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3
pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of
the pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
VDD_IO
VDD_IO
6
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator, if
it is enabled.
20
48
59
42
VDD_IO
VDD_IO
VDDA_OSC_PLL
Supply
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power supply.
VDDA_ADC
41
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSS
VSS
11
17
44
60
39
Ground — These pins provide ground for chip logic and I/O drivers.
VSS
VSS
VSSA_ADC
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
19
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
VCAP
VCAP
VCAP
1
2
3
57
23
5
Supply
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order to
bypass the core logic voltage regulator, required for proper chip
operation.
When OCR_DIS is tied to VDD, (regulator disabled), these pins
become VDD_CORE and should be connected to a regulated 2.5V
power supply.
VCAP4
43
Note: This bypass is required even if the chip is powered with
an external supply.
OCR_DIS
45
46
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
EXTAL
Input
Input
Output
Input,
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
(GPIOC0)
XTAL
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
47
Output
Crystal Oscillator Output — This output can be connected to an
8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
(GPIOC1)
TCK
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
53
Schmitt
Input
Test Clock Input — This input pin provides a gated clock to
pulled low synchronize the test logic and shift serial data to the JTAG/EOnCE
internally port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
56F8323 Technical Data, Rev. 17
20
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
TMS
Pin No.
Type
Signal Description
Reset
54
Schmitt
Input
Input,
Test Mode Select Input — This input pin is used to sequence the
pulled high JTAG TAP controller’s state machine. It is sampled on the rising
internally edge of TCK and has an on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
55
56
Schmitt
Input
Input,
Test Data Input — This input pin provides a serial input data stream
pulled high to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
internally has an on-chip pull-up resistor.
TDO
Output
In reset,
output is
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
disabled, shift-IR and shift-DR controller states, and changes on the falling
pull-up is edge of TCK.
enabled
TRST
58
Schmitt
Input
Input,
Test Reset — As an input, a low signal on this pin provides a reset
pulled high signal to the JTAG TAP controller. To ensure complete hardware
internally reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware
device reset is required and the EOnCE/JTAG module must not be
reset. In this case, assert RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: For normal operation, connect TRST directly to VSS. If the design
is to be used in a debugging environment, TRST may be tied to VSS through
a 1K resistor.
PHASEA0
52
Schmitt
Input
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
(TA0)
Schmitt
Input/
TA0 — Timer A, Channel 0
Output
(GPIOB7)
Schmitt
Input/
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
(oscillator_
clock)
Output
Clock Output - can be used to monitor the internal oscillator clock
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is PHASEA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
21
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
PHASEB0
51
Schmitt
Input
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
(TA1)
Schmitt
Input/
TA1 — Timer A ,Channel 1
Output
(GPIOB6)
(SYS_CLK2)
Schmitt
Input/
Output
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
Clock Output - can be used to monitor the internal SYS_CLK2
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is PHASEB0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
INDEX0
(TA2)
50
Schmitt
Input
Input,
pull-up
enabled
Index — Quadrature Decoder 0, INDEX input
Schmitt
Input/
TA2 — Timer A, Channel 2
Output
(GPIOB5)
(SYS_CLK)
Schmitt
Input/
Output
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
Clock Output - can be used to monitor the internal SYS_CLK signal
(see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is INDEX0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
56F8323 Technical Data, Rev. 17
22
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
HOME0
49
Schmitt
Input
Input,
pull-up
enabled
Home — Quadrature Decoder 0, HOME input
(TA3)
Schmitt
Input/
TA3 — Timer A, Channel 3
Output
(GPIOB4)
Schmitt
Input/
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
(prescaler_
clock)
Output
Clock Output - can be used to monitor the internal prescaler_clock
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is HOME0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
SCLK0
25
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
(GPIOB3)
MOSI0
Schmitt
Input/
Output
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
24
Schmitt
Input/
In reset,
output is
SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
Output
disabled, places data on the MOSI line a half-cycle before the clock edge the
pull-up is slave device uses to latch the data.
enabled
(GPIOB2)
Schmitt
Input/
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is MOSI0.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
23
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
MISO0
Pin No.
Type
Signal Description
Reset
22
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
(RXD1)
Schmitt
Input
Receive Data — SCI1 receive data input
(GPIOB1)
Schmitt
Input/
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is MISO0.
SS0
21
Schmitt
Input
Input,
pull-up
enabled
SPI 0 Slave Select — SS0 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
(TXD1)
Output
Transmit Data — SCI1 transmit data output
(GPIOB0)
Schmitt
Input/
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is SS0.
PWMA0
3
Output
In reset,
output is
PWMA0 — This is one of six PWMA output pins.
(GPIOA0)
Schmitt
Input/
disabled, Port A GPIO — This GPIO pin can be individually programmed as
pull-up is an input or output pin.
Output
enabled
In the 56F8323, the default state after reset is PWMA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
PWMA1
4
Output
In reset,
output is
PWMA1 — This is one of six PWMA output pins.
(GPIOA1)
Schmitt
Input/
disabled, Port A GPIO — This GPIO pin can be individually programmed as
pull-up is an input or output pin.
Output
enabled
In the 56F8323, the default state after reset is PWMA1.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured
56F8323 Technical Data, Rev. 17
24
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
PWMA2
7
Output
In reset,
output is
PWMA2 — This is one of six PWMA output pins.
(SS1)
Schmitt
Input
disabled, SPI 1 Slave Select — SS1 is used in slave mode to indicate to the
pull-up is SPI module that the current transfer is to be received.
enabled
(GPIOA2)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is PWMA2.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
PWMA3
8
Output
In reset,
output is
PWMA3 — This is one of six PWMA output pins.
(MISO1)
Schmitt
Input/
disabled, SPI 1 Master In/Slave Out — This serial data pin is an input to a
pull-up is master device and an output from a slave device. The MISO line of a
Output
enabled
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
(GPIOA3)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is PWMA3.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
PWMA4
9
Output
In reset,
output is
PWMA4 — This is one of six PWMA output pins.
(MOSI1)
Schmitt
Input/
disabled, SPI 1 Master Out/Slave In — This serial data pin is an output from a
pull-up is master device and an input to a slave device. The master device
Output
enabled
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
(GPIOA4)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is PWMA4.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
25
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
PWMA5
10
Output
In reset,
output is
PWMA5 — This is one of six PWMA output pins.
(SCLK1)
Schmitt
Input/
disabled, SPI 1 Serial Clock — In the master mode, this pin serves as an
pull-up is output, clocking slaved listeners. In slave mode, this pin serves as
Output
enabled
the data clock input. A Schmitt trigger input is used for noise
immunity.
(GPIOA5)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is PWMA5.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
FAULTA0
13
14
15
Schmitt
Input
Input
FAULTA0 — This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-chip.
(GPIOA6)
Schmitt
Input/
Output
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is FAULTA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
FAULTA1
Schmitt
Input
Input
FAULTA1 — This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-chip.
(GPIOA7)
Schmitt
Input/
Output
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is FAULTA1.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
FAULTA2
Schmitt
Input
Input
FAULTA2 — This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-chip.
(GPIOA8)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is FAULTA2.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
56F8323 Technical Data, Rev. 17
26
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
ISA0
16
Schmitt
Input
Input,
pull-up
enabled
ISA0 — This input current status pin is used for top/bottom pulse
width correction in complementary channel operation for PWMA.
(GPIOA9)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is ISA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
ISA1
18
Schmitt
Input
Input,
pull-up
enabled
ISA1 — This input current status pin is used for top/bottom pulse
width correction in complementary channel operation for PWMA.
(GPIOA10)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is ISA1.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
ISA2
19
Schmitt
Input
Input,
pull-up
enabled
ISA2 — This input current status pin is used for top/bottom pulse
width correction in complementary channel operation for PWMA.
(GPIOA11)
Schmitt
Input/
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is ISA2.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
VREFH
26
27
28
29
30
31
32
33
40
Input
Input
Analog Input ANA0 - 3 — Analog inputs to ADCA, Channel 0
Analog Input ANA4 - 7 — Analog inputs to ADCA, Channel 1
Analog Input VREFH — Analog Reference Voltage High
Schmitt
Input
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
27
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
VREFP
VREFMID
VREFN
37
36
35
38
Input/
Output
Analog Input/ VREFP, VREFMID & VREFN — Internal pins for voltage reference which
Output
are brought off-chip so that they can be bypassed. Connect to a
0.1μF ceramic low ESR capacitor
VREFLO
Schmitt
Input
Analog Input VREFLO — Analog Reference Voltage Low. This should normally be
connected to a low-noise VSS
.
TEMP_SENSE
34
61
Output
Analog
Output
Temperature Sense Diode — This signal connects to an on-chip
diode that can be connected to one of the ADC inputs and used to
monitor the temperature of the die. Must be bypassed with a 0.01μF
capacitor
CAN_RX
Schmitt
Input
Input,
pull-up
enabled
FlexCAN Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
(GPIOC2)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is CAN_RX.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
CAN_TX
62
Open
Drain
Open
Drain
FlexCAN Transmit Data — CAN output with internal pull-up enable
at reset.*
Output
Output
* Note: If a pin is configured as open drain output mode, internal
pull-up will automatically be disabled when it outputs low. Internal
pull-up will be enabled unless it has been manually disabled by
clearing the corresponding bit in the PUREN register of the GPIO
module, when it outputs high.
If a pin is configured as push-pull output mode, internal pull-up will
automatically be disabled, whether it outputs low or high.
(GPIOC3)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8323, the default state after reset is CAN_TX.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
56F8323 Technical Data, Rev. 17
28
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 64-Pin LQFP
StateDuring
Signal Name
TC0
Pin No.
Type
Signal Description
TC0 — Timer C, Channel 0
Reset
1
Schmitt
Input/
Output
Input,
pull-up
enabled
(TXD0)
Input
Transmit Data — SCI0 transmit data output
(GPIOC6)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is TC0.
TC1
64
Schmitt
Input/
Output
Input,
pull-up
enabled
TC1 — Timer C, Channel 1
(RXD0)
Schmitt
Input
Receive Data — SCI0 receive data input
(GPIOC5)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is TC1.
TC3
63
Schmitt
Input/
Output
Input,
pull-up
enabled
TC3 — Timer C Channel 3
(GPIOC4)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is TC3.
IRQA
12
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A — The IRQA input is an
asynchronous external interrupt request during Stop and Wait mode
operation. During other operating modes, it is a synchronized
external interrupt request which indicates an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered
(VPP
)
Input
VPP — This pin is used for Flash debugging purposes.
RESET
2
Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET,
but do not assert TRST.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
29
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design.
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-1. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
EXTAL XTAL
Rz
Sample External Crystal Parameters:
Rz = 750 KΩ
Note: If the operating temperature range is limited to
CLKMODE = 0
below 85oC (105oC junction), then Rz = 10 Meg Ω
CL1
CL2
Figure 3-1 Connecting to a Crystal Oscillator
Note:
The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-2.
Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components.
The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins.
56F8323 Technical Data, Rev. 17
30
Freescale Semiconductor
Preliminary
Use of On-Chip Relaxation Oscillator
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
3 Terminal
2 Terminal
EXTAL XTAL
Rz
Sample External Ceramic Resonator Parameters:
Rz = 750 KΩ
EXTAL XTAL
Rz
CLKMODE = 0
CL1
CL2
C1
C2
Figure 3-2 Connecting a Ceramic Resonator
Note:
The OCCS_COHL bit must be set to 0 when a crystal resonator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.3
External Clock Source
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is
connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a
relatively low impedance driver, as the XTAL pin is actually the output pin of the oscillator (it has a very
weak driver).
Note: When using an external clocking
XTAL
EXTAL
source with this configuration, the
“CLKMODE” and COHL bits of the OSCTL
register should be set to 1.
V
External
Clock
SS
Figure 3-3 Connecting an External Clock Signal
3.3 Use of On-Chip Relaxation Oscillator
An internal relaxtion oscillator can supply the reference frequency when an external frequency source of
crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, and the
PRECS bit in the PLLCR word is set to 0. If an external oscillator is connected, the relaxation oscillator
can be deselected instead by setting the PRECS bit in the PLLCR to 1. If a changeover between internal
and external oscillators is required at start up, internal device circuits compensate for any asynchronous
transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip.
When changing clocks, the user must ensure that the clock source is not switched until the desired clock
is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the
OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
31
to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit
added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the
desired frequency accuracy is achieved.
The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash
information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the
boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information,
see the 56F8300 Peripherals User Manual.
3.4 Internal Clock Operation
At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock
reference for the PLL. Software should power down the block not being used and program the PLL for the
correct frequency.
CLK_MODE
Relaxation
OSC
XTAL
ZSRC
MUX
PRECS
Crystal
OSC
SYS_CLK2
EXTAL
source to
the SIM
PLLCID
PLLDB
PLLCOD
F
F
/2
Prescaler
÷ (1, 2, 4, 8)
OUT
PLL
x (1 to 128)
OUT
Postscaler
÷ (1, 2, 4, 8)
÷ 2
Postscaler CLK
Bus Interface
& Control
Bus
Interface
LCK
Lock
Detector
Loss of
Reference
Clock
loss of reference
clock interrupt
Detector
Figure 3-4 Internal Clock Operation
56F8323 Technical Data, Rev. 17
32
Freescale Semiconductor
Preliminary
Registers
3.5 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions with the internal Relaxation Oscillator, since the 56F8323 and 56F8123 contain this
oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8323 and 56F8123 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
•
•
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8123 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8323
56F8123
Use Restrictions
Program Flash
Erase / Program via Flash interface unit and word
writes to CDBW
32KB
32KB
Data Flash
Erase / Program via Flash interface unit and word
writes to CDBW. Data Flash can be read via either
CDBR or XDB2, but not by both simultaneously
8KB
—
Program RAM
Data RAM
None
None
4KB
8KB
8KB
—
8KB
8KB
Program Boot Flash
Erase / Program via Flash Interface unit and word
writes to CDBW
4.2 Program Map
The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the
Operating Mode Register (OMR) control the Program Memory map. Because the 56F8323 and 56F8123
do not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no
effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After
reset, changing the OMR MB bit will have no effect on the Program Flash.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
33
Note: Program RAM is NOT available on the 56F8123 device.
Table 4-2 Program Memory Map at Reset
Begin/End Address
Memory Allocation
P: $1F FFFF
P: $03 0000
RESERVED
P: $02 FFFF
P: $02 F800
On-Chip Program RAM
4KB
P: $02 F7FF
P: $02 1000
RESERVED
P: $02 0FFF
P: $02 0000
Boot Flash
8KB
Cop Reset Address = $02 0002
Boot Location = $02 0000
P: $01 FFFF
P: $00 4000
RESERVED
P: $00 3FFF
P: $00 0000
Internal Program Flash
32KB
4.3 Interrupt Vector Table
Table 4-3 provides the device’s reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Part 5.6.11
for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, CAN and Quadrature Decoder are NOT available on the 56F8123 device.
1
Table 4-3 Interrupt Vector Table Contents
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved for Reset Overlay2
Reserved for COP Reset Overlay2
Illegal Instruction
core
core
2
3
3
3
P:$04
P:$06
SW Interrupt 3
56F8323 Technical Data, Rev. 17
34
Freescale Semiconductor
Preliminary
Interrupt Vector Table
1
Table 4-3 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
core
core
core
core
4
5
6
7
3
3
P:$08
P:$0A
P:$0C
P:$0E
HW Stack Overflow
Misaligned Long Word Access
OnCE Step Counter
OnCE Breakpoint Unit 0
Reserved
1-3
1-3
core
core
core
9
1-3
1-3
1-3
P:$12
P:$14
P:$16
OnCE Trace Buffer
OnCE Transmit Register Empty
OnCE Receive Register Full
Reserved
10
11
core
core
core
core
14
15
16
17
2
P:$1C
P:$1E
P:$20
P:$22
SW Interrupt 2
1
SW Interrupt 1
0
SW Interrupt 0
0-2
IRQA
Reserved
LVI
PLL
FM
FM
FM
20
21
22
23
24
0-2
0-2
0-2
0-2
0-2
P:$28
P:$2A
P:$2C
P:$2E
P:$30
Low-Voltage Detector (power sense)
PLL
FM Access Error Interrupt
FM Command Complete
FM Command, data and address Buffers Empty
Reserved
FLEXCAN 26
FLEXCAN 27
FLEXCAN 28
FLEXCAN 29
0-2
0-2
0-2
0-2
P:$34
P:$36
P:$38
P:$3A
FLEXCAN Bus Off
FLEXCAN Error
FLEXCAN Wake Up
FLEXCAN Message Buffer Interrupt
Reserved
GPIOC
GPIOB
GPIOA
33
34
35
0-2
0-2
0-2
P:$42
P:$44
P:$46
GPIO C
GPIO B
GPIO A
Reserved
SPI1
SPI1
SPI0
SPI0
SCI1
SCI1
38
39
40
41
42
43
0-2
0-2
0-2
0-2
0-2
0-2
P:$4C
P:$4E
P:$50
P:$52
P:$54
P:$56
SPI 1 Receiver Full
SPI 1 Transmitter Empty
SPI 0 Receiver Full
SPI 0 Transmitter Empty
SCI 1 Transmitter Empty
SCI 1Transmitter Idle
Reserved
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
35
1
Table 4-3 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
SCI1
SCI1
45
0-2
P:$5A
P:$5C
SCI 1 Receiver Error
SCI 1 Receiver Full
Reserved
46
0-2
DEC0
DEC0
49
50
0-2
0-2
P:$62
P:$64
Quadrature Decoder #0 Home Switch or Watchdog
Quadrature Decoder #0 INDEX Pulse
Reserved
TMRC
TMRC
TMRC
TMRC
56
57
58
59
0-2
0-2
0-2
0-2
P:$70
P:$72
P:$74
P:$76
Timer C Channel 0
Timer C Channel 1
Timer C Channel 2
Timer C Channel 3
Reserved
TMRA
TMRA
TMRA
TMRA
SCI0
64
65
66
67
68
69
0-2
0-2
0-2
0-2
0-2
0-2
P:$80
P:$82
P:$84
P:$86
P:$88
P:$8A
Timer A Channel 0
Timer A Channel 1
Timer A Channel 2
Timer A Channel 3
SCI 0 Transmitter Empty
SCI 0 Transmitter Idle
Reserved
SCI0
SCI0
SCI0
71
72
0-2
0-2
P:$8E
P:$90
SCI 0 Receiver Error
SCI 0 Receiver Full
Reserved
ADCA
ADCA
PWMA
74
76
78
0-2
0-2
0-2
P:$94
P:$98
P:$9C
ADC A Conversion Complete / End of Scan
Reserved
ADC A Zero Crossing or Limit Error
Reserved
Reload PWM A
Reserved
PWMA
80
81
82
0-2
- 1
P:$A0
P:$A2
P:$A4
PWM A Fault
core
SW Interrupt LP
0 - 2
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200, the first two locations of the vector table will overlay the chip reset addresses.
56F8323 Technical Data, Rev. 17
36
Freescale Semiconductor
Preliminary
Data Map
4.4 Data Map
Note: Data Flash is NOT available on the 56F8122 device.
1
Table 4-4 Data Memory Map
Begin/End Address
Memory Allocation
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
RESERVED
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 2000
RESERVED
X:$00 1FFF
X:$00 1000
On-Chip Data Flash
8KB
X:$00 0FFF
X:$00 0000
On-Chip Data RAM
8KB2
1. All addresses are 16-bit Word addresses.
2. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle,
long-word operations.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.
Flash Memory is divided into three functional blocks. The Program and boot memories reside on the
Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides
on the Data Memory buses and is controlled separately by its own set of banked registers.
The top nine words of the Program Memory Flash are treated as special memory locations. The content of
these words is used to control the operation of the Flash controller. Because these words are part of the
Flash Memory content, their state is maintained during power-down and reset. During chip initialization,
the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash
Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located
between $00_3FF7 and $00_3FFF.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
37
Data Memory
Program Memory
BOOT_FLASH_START + $0FFF
FM_BASE + $14
FM_BASE + $00
Banked Registers
8KB
Boot
Unbanked Registers
BOOT_FLASH_START = $02_0000
Reserved
DATA_FLASH_START + $0FFF
DATA_FLASH_START + $0000
8KB
Note: Data Flash is
NOT available in the
56F8123 device.
FM_PROG_MEM_TOP = $00_3FFF
PROG_FLASH_START + $00_3FFF
PROG_FLASH_START + $00_3FF7
PROG_FLASH_START + $00_3FF6
Configure Field
Block 0 Odd
Block 0 Even
32KB
BLOCK 0 Odd (2 Bytes) $00_0003
BLOCK 0 Even (2 Bytes) $00_0002
BLOCK 0 Odd (2 Bytes) $00_0001
BLOCK 0 Even (2 Bytes) $00_0000
PROG_FLASH_START = $00_0000
Figure 4-1 Flash Array Memory Maps
Table 4-5 shows the page and sector sizes used within each Flash memory block on the chip.
Note: Data Flash is NOT available on the 56F8123 device.
Table 4-5. Flash Memory Partitions
Flash Size
Sectors
Sector Size
Page Size
Program Flash
Data Flash
32KB
8KB
8KB
16
16
4
1K x 16 bits
256 x 16 bits
1K x 16 bits
512 x 16 bits
256 x 16 bits
256 x 16 bits
Boot Flash
Please see the 56F8300 Peripheral User Manual for additional Flash information.
56F8323 Technical Data, Rev. 17
38
Freescale Semiconductor
Preliminary
EOnCE Memory Map
4.6 EOnCE Memory Map
Table 4-6 EOnCE Memory Map
Address
Register Acronym
Register Name
Reserved
X:$FF FF8A
OESCR
External Signal Control Register
Reserved
X:$FF FF8E
OBCNTR
Breakpoint Unit [0] Counter
Reserved
X:$FF FF90
X:$FF FF91
X:$FF FF92
X:$FF FF93
X:$FF FF94
X:$FF FF95
X:$FF FF96
X:$FF FF97
X:$FF FF98
X:$FF FF99
X:$FF FF9A
X:$FF FF9B
X:$FF FF9C
X:$FF FF9D
X:$FF FF9E
X:$FF FF9F
X:$FF FFA0
OBMSK (32 bits)
Breakpoint 1 Unit [0] Mask Register
Breakpoint 1 Unit [0] Mask Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint Unit [0] Control Register
Breakpoint Unit [0] Control Register
Trace Buffer Register Stages
Trace Buffer Register Stages
Trace Buffer Pointer Register
Trace Buffer Control Register
Peripheral Base Address Register
Status Register
—
OBAR2 (32 bits)
—
OBAR1 (24 bits)
—
OBCR (24 bits)
—
OTB (21-24 bits/stage)
—
OTBPR (8 bits)
OTBCR
OBASE (8 bits)
OSR
OSCNTR (24 bits)
—
Instruction Step Counter
Instruction Step Counter
OCR (bits)
Control Register
Reserved
X:$FF FFFC
X:$FF FFFD
X:$FF FFFE
X:$FF FFFF
OCLSR (8 bits)
Core Lock / Unlock Status Register
OTXRXSR (8 bits)
OTX / ORX (32 bits)
OTX1 / ORX1
Transmit and Receive Status and Control Register
Transmit Register / Receive Register
Transmit Register Upper Word
Receive Register Upper Word
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
39
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-7 summarizes base addresses for the set of peripherals on the 56F8323 and 56F8123 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available in the 56F8123 device.
Table 4-7 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
X:$00 F040
Table Number
4-8
Timer A
Timer C
PWM A
TMRA
TMRC
PWMA
DEC0
ITCN
X:$00 F0C0
X:$00 F140
X:$00 F180
X:$00 F1A0
X:$00 F200
X:$00 F270
X:$00 F280
X:$00 F290
X:$00 F2A0
X:$00 F2B0
X:$00 F2C0
X:$00 F2D0
X:$00 F2E0
X:$00 F300
X:$00 F310
X:$00 F350
X:$00 F360
X:$00 F400
X:$00 F800
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
Quadrature Decoder 0
ITCN
ADC A
ADCA
Temperature Sensor
SCI #0
TSENSOR
SCI0
SCI #1
SCI1
SPI #0
SPI0
SPI #1
SPI1
COP
COP
PLL, OSC
GPIO Port A
GPIO Port B
GPIO Port C
SIM
CLKGEN
GPIOA
GPIOB
GPIOC
SIM
Power Supervisor
FM
LVI
FM
FlexCAN
FC
56F8323 Technical Data, Rev. 17
40
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-8 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
TMRA0_CMP1
TMRA0_CMP2
TMRA0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 1
Compare Register 2
Capture Register
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_COMSCR
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
Compare Register 1
Compare Register 2
Capture Register
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
TMRA2_CMPLD1
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
41
Table 4-8 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
$29
Register Description
Comparator Load Register 2
TMRA2_CMPLD2
TMRA2_COMSCR
$2A
Comparator Status and Control Register
Reserved
TMRA3_CMP1
TMRA3_CMP2
TMRA3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSCR
Table 4-9 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
$0
Register Description
Compare Register 1
TMRC0_CMP1
TMRC0_CMP2
TMRC0_CAP
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRC0_LOAD
TMRC0_HOLD
TMRC0_CNTR
TMRC0_CTRL
TMRC0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC0_CMPLD1
TMRC0_CMPLD2
TMRC0_COMSCR
TMRC1_CMP1
TMRC1_CMP2
TMRC1_CAP
TMRC1_LOAD
$10
$11
$12
$13
Compare Register 1
Compare Register 2
Capture Register
Load Register
56F8323 Technical Data, Rev. 17
42
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-9 Quad Timer C Registers Address Map (Continued)
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
TMRC1_HOLD
TMRC1_CNTR
TMRC1_CTRL
TMRC1_SCR
$14
$15
$16
$17
$18
$19
$1A
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC1_CMPLD1
TMRC1_CMPLD2
TMRC1_COMSCR
TMRC2_CMP1
TMRC2_CMP2
TMRC2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRC2_LOAD
TMRC2_HOLD
TMRC2_CNTR
TMRC2_CTRL
TMRC2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC2_CMPLD1
TMRC2_CMPLD2
TMRC2_COMSCR
TMRC3_CMP1
TMRC3_CMP2
TMRC3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRC3_LOAD
TMRC3_HOLD
TMRC3_CNTR
TMRC3_CTRL
TMRC3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRC3_CMPLD1
TMRC3_CMPLD2
TMRC3_COMSCR
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
43
Table 4-10 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
PWM is NOT available in the 56F8123 device
Register Acronym
Address Offset
$0
Register Description
PWMA_PMCTRL
PWMA_PMFCTRL
PWMA_PMFSA
Control Register
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
PWMA_PMOUT
PWMA_PMCNT
PWMA_PWMCM
PWMA_PWMVAL0
PWMA_PWMVAL1
PWMA_PWMVAL2
PWMA_PWMVAL3
PWMA_PWMVAL4
PWMA_PWMVAL5
PWMA_PMDEADTM
Counter Modulo Register
Value Register 0
Value Register 1
Value Register 2
Value Register 3
Value Register 4
Value Register 5
Dead Time Register
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
PWMA_PMDISMAP1 $D
PWMA_PMDISMAP2 $E
PWMA_PMCFG
PWMA_PMCCR
PWMA_PMPORT
PWMA_PMICCR
$F
$10
$11
$12
Channel Control Register
Port Register
Internal Correction Control Register
Table 4-11 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Quadrature Decoder is NOT available in the 56F8123 device
Register Acronym
Address Offset
$0
Register Description
Decoder Control Register
DEC0_DECCR
DEC0_FIR
$1
$2
$3
$4
$5
$6
$7
$8
Filter Interval Register
DEC0_WTR
DEC0_POSD
DEC0_POSDH
DEC0_REV
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
Revolution Counter Register
Revolution Hold Register
DEC0_REVH
DEC0_UPOS
DEC0_LPOS
Upper Position Counter Register
Lower Position Counter Register
56F8323 Technical Data, Rev. 17
44
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-11 Quadrature Decoder 0 Registers Address Map (Continued)
(DEC0_BASE = $00 F180)
Quadrature Decoder is NOT available in the 56F8123 device
Register Acronym
Address Offset
$9
Register Description
Upper Position Hold Register
DEC0_UPOSH
DEC0_LPOSH
DEC0_UIR
$A
$B
$C
$D
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC0_LIR
DEC0_IMR
Table 4-12 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym
IPR0
Address Offset
$0
Register Description
Interrupt Priority Register 0
IPR1
$1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt Match Register 0
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match Register 1
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
IPR2
$2
IPR3
$3
IPR4
$4
IPR5
$5
IPR6
$6
IPR7
$7
IPR8
$8
IPR9
$9
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
IRQP5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
ICTL
$1D
Interrupt Control Register
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
45
Table 4-13 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
$0
Register Description
Control Register 1
ADCA_CR1
ADCA_CR2
$1
Control Register 2
ADCA_ZCC
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCA_LST 1
ADCA_LST 2
ADCA_SDIS
$3
$4
$5
ADCA_STAT
$6
ADCA_LSTAT
ADCA_ZCSTAT
ADCA_RSLT 0
ADCA_RSLT 1
ADCA_RSLT 2
ADCA_RSLT 3
ADCA_RSLT 4
ADCA_RSLT 5
ADCA_RSLT 6
ADCA_RSLT 7
ADCA_LLMT 0
ADCA_LLMT 1
ADCA_LLMT 2
ADCA_LLMT 3
ADCA_LLMT 4
ADCA_LLMT 5
ADCA_LLMT 6
ADCA_LLMT 7
ADCA_HLMT 0
ADCA_HLMT 1
ADCA_HLMT 2
ADCA_HLMT 3
ADCA_HLMT 4
ADCA_HLMT 5
ADCA_HLMT 6
ADCA_HLMT 7
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
Result Register 7
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
56F8323 Technical Data, Rev. 17
46
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-13 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
ADCA_OFS 0
ADCA_OFS 1
ADCA_OFS 2
ADCA_OFS 3
ADCA_OFS 4
ADCA_OFS 5
ADCA_OFS 6
ADCA_OFS 7
ADCA_POWER
ADCA_CAL
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
ADC Calibration Register
Table 4-14 Temperature Sensor Register Address Map
(TSENSOR_BASE = $00 F270)
Temperature Sensor is NOT available in the 56F8123 device
Register Acronym
Address Offset
$0
Register Description
TSENSOR_CNTL
Control Register
Table 4-15 Serial Communication Interface 0 Registers Address Map
(SCI0_BASE = $00 F280)
Register Acronym
Address Offset
$0
Register Description
Baud Rate Register
SCI0_SCIBR
SCI0_SCICR
$1
Control Register
Reserved
SCI0_SCISR
SCI0_SCIDR
$3
$4
Status Register
Data Register
Table 4-16 Serial Communication Interface 1 Registers Address Map
(SCI1_BASE = $00 F290)
Register Acronym
Address Offset
$0
Register Description
Baud Rate Register
SCI1_SCIBR
SCI1_SCICR
$1
Control Register
Reserved
SCI1_SCISR
SCI1_SCIDR
$3
$4
Status Register
Data Register
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
47
Table 4-17 Serial Peripheral Interface 0 Registers Address Map
(SPI0_BASE = $00 F2A0)
Register Acronym
Address Offset
$0
Register Description
Status and Control Register
SPI0_SPSCR
SPI0_SPDSR
SPI0_SPDRR
SPI0_SPDTR
$1
$2
$3
Data Size Register
Data Receive Register
Data Transmitter Register
Table 4-18 Serial Peripheral Interface 1 Registers Address Map
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
$0
Register Description
Status and Control Register
SPI1_SPSCR
SPI1_SPDSR
SPI1_SPDRR
SPI1_SPDTR
$1
$2
$3
Data Size Register
Data Receive Register
Data Transmitter Register
Table 4-19 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
$0
Register Description
COPCTL
COPTO
Control Register
$1
$2
Time-Out Register
Counter Register
COPCTR
Table 4-20 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
PLLCR
Address Offset
$0
Register Description
Control Register
PLLDB
PLLSR
$1
$2
Divide-By Register
Status Register
Reserved
SHUTDOWN
OSCTL
$4
$5
Shutdown Register
Oscillator Control Register
56F8323 Technical Data, Rev. 17
48
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-21 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Address Offset
$0
Register Description
Pull-up Enable Register
Reset Value
0 x 0FFF
0 x 0000
0 x 0000
0 x 0FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0FFF
—
Register Acronym
GPIOA_PUR
GPIOA_DR
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Data Register
GPIOA_DDR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
GPIOA_PPMODE
GPIOA_RAWDATA
Table 4-22 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
$0
Register Description
Pull-up Enable Register
Reset Value
GPIOB_PUR
GPIOB_DR
0 x 00FF
0 x 0000
0 x 0000
0 x 00FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 00FF
—
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Data Register
GPIOB_DDR
GPIOB_PER
GPIOB_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
49
Table 4-23 GPIOC Registers Address Map
(GPIOC_BASE = $00 F310)
Register Acronym
Address Offset
$0
Register Description
Pull-up Enable Register
Reset Value
0 x 007C
GPIOC_PUR
GPIOC_DR
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Data Register
0 x 0000
0 x 0000
0 x 007F
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 007F
—
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
GPIOC_IESR
GPIOC_PPMODE
GPIOC_RAWDATA
Table 4-24 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
$0
Register Description
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
Control Register
$1
$2
$3
$4
$5
$6
$7
$8
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
SIM_CLKOSR
SIM_GPS
$A
$B
$C
$D
$E
Clock Out Select Register
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
SIM_PCE
SIM_ISALH
SIM_ISALL
56F8323 Technical Data, Rev. 17
50
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-25 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym
Address Offset
Register Description
LVI_CONTROL
LVI_STATUS
$0
$1
Control Register
Status Register
Table 4-26 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
$0
Register Description
Clock Divider Register
FMCLKD
FMMCR
$1
Module Control Register
Reserved
FMSECH
FMSECL
$3
$4
Security High Half Register
Security Low Half Register
Reserved
Reserved
FMPROT
$10
$11
Protection Register (Banked)
Protection Boot Register (Banked)
Reserved
FMPROTB
FMUSTAT
FMCMD
$13
$14
User Status Register (Banked)
Command Register (Banked)
Reserved
Reserved
FMOPT 0
$1A
16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test
FMOPT 1
FMOPT 2
$1B
$1C
16-Bit Information Option Register 1
Trim cap setting of the relaxation oscillator
16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
51
Table 4-27 FlexCAN Registers Address Map
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8123 device
Register Acronym
FCMCR
Address Offset
$0
Register Description
Module Configuration Register
Reserved
FCCTL0
FCCTL1
FCTMR
$3
$4
$5
$6
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Reserved
FCMAXMB
FCRXGMASK_H
FCRXGMASK_L
FCRX14MASK_H
FCRX14MASK_L
FCRX15MASK_H
FCRX15MASK_L
$8
$9
$A
$B
$C
$D
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
FCSTATUS
$10
$11
$12
$13
Error and Status Register
FCIMASK1
Interrupt Masks 1 Register
Interrupt Flags 1 Register
FCIFLAG1
FCR/T_ERROR_CNTRS
Receive and Transmit Error Counters Register
Reserved
Reserved
Reserved
FCMB0_CONTROL
FCMB0_ID_HIGH
FCMB0_ID_LOW
FCMB0_DATA
$40
$41
$42
$43
$44
$45
$46
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMSB1_CONTROL
FCMSB1_ID_HIGH
FCMSB1_ID_LOW
$48
$49
$4A
Message Buffer 1 Control / Status Register
Message Buffer 1 ID High Register
Message Buffer 1 ID Low Register
56F8323 Technical Data, Rev. 17
52
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-27 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8123 device
Register Acronym
FCMB1_DATA
Address Offset
$4B
Register Description
Message Buffer 1 Data Register
FCMB1_DATA
FCMB1_DATA
FCMB1_DATA
$4C
$4D
$4E
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Reserved
FCMB2_CONTROL
FCMB2_ID_HIGH
FCMB2_ID_LOW
FCMB2_DATA
$50
$51
$52
$53
$54
$55
$56
Message Buffer 2 Control / Status Register
Message Buffer 2 ID High Register
Message Buffer 2 ID Low Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Reserved
FCMB2_DATA
FCMB2_DATA
FCMB2_DATA
FCMB3_CONTROL
FCMB3_ID_HIGH
FCMB3_ID_LOW
FCMB3_DATA
$58
$59
$5A
$5B
$5C
$5D
$5E
Message Buffer 3 Control / Status Register
Message Buffer 3 ID High Register
Message Buffer 3 ID Low Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Reserved
FCMB3_DATA
FCMB3_DATA
FCMB3_DATA
FCMB4_CONTROL
FCMB4_ID_HIGH
FCMB4_ID_LOW
FCMB4_DATA
$60
$61
$62
$63
$64
$65
$66
Message Buffer 4 Control / Status Register
Message Buffer 4 ID High Register
Message Buffer 4 ID Low Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Reserved
FCMB4_DATA
FCMB4_DATA
FCMB4_DATA
FCMB5_CONTROL
FCMB5_ID_HIGH
FCMB5_ID_LOW
FCMB5_DATA
$68
$69
$6A
$6B
Message Buffer 5 Control / Status Register
Message Buffer 5 ID High Register
Message Buffer 5 ID Low Register
Message Buffer 5 Data Register
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
53
Table 4-27 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8123 device
Register Acronym
FCMB5_DATA
Address Offset
$6C
Register Description
Message Buffer 5 Data Register
FCMB5_DATA
FCMB5_DATA
$6D
$6E
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Reserved
FCMB6_CONTROL
FCMB6_ID_HIGH
FCMB6_ID_LOW
FCMB6_DATA
$70
$71
$72
$73
$74
$75
$76
Message Buffer 6 Control / Status Register
Message Buffer 6 ID High Register
Message Buffer 6 ID Low Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Reserved
FCMB6_DATA
FCMB6_DATA
FCMB6_DATA
FCMB7_CONTROL
FCMB7_ID_HIGH
FCMB7_ID_LOW
FCMB7_DATA
$78
$79
$7A
$7B
$7C
$7D
$7E
Message Buffer 7 Control / Status Register
Message Buffer 7 ID High Register
Message Buffer 7 ID Low Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Reserved
FCMB7_DATA
FCMB7_DATA
FCMB7_DATA
FCMB8_CONTROL
FCMB8_ID_HIGH
FCMB8_ID_LOW
FCMB8_DATA
$80
$81
$82
$83
$84
$85
$86
Message Buffer 8 Control / Status Register
Message Buffer 8 ID High Register
Message Buffer 8 ID Low Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Reserved
FCMB8_DATA
FCMB8_DATA
FCMB8_DATA
FCMB9_CONTROL
FCMB9_ID_HIGH
FCMB9_ID_LOW
FCMB9_DATA
$88
$89
$8A
$8B
$8C
Message Buffer 9 Control / Status Register
Message Buffer 9 ID High Register
Message Buffer 9 ID Low Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
FCMB9_DATA
56F8323 Technical Data, Rev. 17
54
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-27 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8123 device
Register Acronym
FCMB9_DATA
Address Offset
$8D
Register Description
Message Buffer 9 Data Register
FCMB9_DATA
$8E
Message Buffer 9 Data Register
Reserved
FCMB10_CONTROL
FCMB10_ID_HIGH
FCMB10_ID_LOW
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
$90
$91
$92
$93
$94
$95
$96
Message Buffer 10 Control / Status Register
Message Buffer 10 ID High Register
Message Buffer 10 ID Low Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Reserved
FCMB11_CONTROL
FCMB11_ID_HIGH
FCMB11_ID_LOW
FCMB11_DATA
FCMB11_DATA
FCMB11_DATA
FCMB11_DATA
$98
$99
$9A
$9B
$9C
$9D
$9E
Message Buffer 11 Control / Status Register
Message Buffer 11 ID High Register
Message Buffer 11 ID Low Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Reserved
FCMB12_CONTROL
FCMB12_ID_HIGH
FCMB12_ID_LOW
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
$A0
$A1
$A2
$A3
$A4
$A5
$A6
Message Buffer 12 Control / Status Register
Message Buffer 12 ID High Register
Message Buffer 12 ID Low Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Reserved
FCMB13_CONTROL
FCMB13_ID_HIGH
FCMB13_ID_LOW
FCMB13_DATA
$A8
$A9
$AA
$AB
$AC
$AD
Message Buffer 13 Control / Status Register
Message Buffer 13 ID High Register
Message Buffer 13 ID Low Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
FCMB13_DATA
FCMB13_DATA
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
55
Table 4-27 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8123 device
Register Acronym
Address Offset
$AE
Register Description
Message Buffer 13 Data Register
FCMB13_DATA
Reserved
FCMB14_CONTROL
FCMB14_ID_HIGH
FCMB14_ID_LOW
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
$B0
$B1
$B2
$B3
$B4
$B5
$B6
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
FCMB15_CONTROL
FCMB15_ID_HIGH
FCMB15_ID_LOW
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
$B8
$B9
$BA
$BB
$BC
$BD
$BE
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
4.8 Factory Programmed Memory
The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader
program. The Serial Bootloader application can be used to load a user application into the Program and
Data Flash (NOT available in the 56F8123) memories of the device. The 56F83xx SCI/CAN Bootloader
User Manual provides detailed information on this firmware. An application note, Production Flash
Programming, details how the Serial Bootloader program can be used to perform production Flash
programming of the on-board Flash memories as well as other optional methods.
Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial
Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained
in the Boot Flash memory.
56F8323 Technical Data, Rev. 17
56
Freescale Semiconductor
Preliminary
Introduction
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-3, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
SR[8]1
Permitted Exceptions Masked Exceptions
0
0
1
1
0
1
0
1
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
None
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
1. Core status register bits indicating current interrupt mask within the core.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
57
Table 5-2. Interrupt Priority Encoding
Current Interrupt
Priority Level
Required Nested
Exception Priority
IPIC_LEVEL[1:0]1
00
No Interrupt or SWILP Priorities 0, 1, 2, 3
01
10
11
Priority 0
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 1
Priorities 2 or 3
1. See IPIC field definition in Section 5.6.30.2
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
56F8323 Technical Data, Rev. 17
58
Freescale Semiconductor
Preliminary
Block Diagram
5.4 Block Diagram
any0
Priority
Level
Level 0
82 -> 7
Priority
Encoder
7
2 -> 4
INT1
Decode
INT
VAB
IPIC
CONTROL
any3
IACK
SR[9:8]
PIC_EN
Level 3
Priority
Level
82 -> 7
Priority
7
Encoder
2 -> 4
Decode
INT82
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
Functional Mode
The ITCN is in this mode by default.
•
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA
signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to
make them falling-edge sensitive. This is because there is no clock available to detect the falling edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop
mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA
and IRQB can wake it up.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
59
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F1A0)
Register Acronym
Base Address +
Register Name
Interrupt Priority Register 0
Section Location
IPR0
$0
$1
5.6.1
5.6.2
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt 0 Match Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High Register
Fast Interrupt 1 Match Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IPR1
IPR2
$2
5.6.3
IPR3
$3
5.6.4
IPR4
$4
5.6.5
IPR5
$5
5.6.6
IPR6
$6
5.6.7
IPR7
$7
5.6.8
IPR8
$8
5.6.9
IPR9
$9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
IRQP5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
Interrupt Control Register
ICTL
$1D
5.6.30
56F8323 Technical Data, Rev. 17
60
Freescale Semiconductor
Preliminary
Register Descriptions
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
BKPT_ U0
IPL
$0
$1
IPR0
IPR1
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
RX_REG IPL
TX_REG IPL
TRBUF IPL
IRQA IPL
W
R
0
0
0
0
$2
IPR2
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
W
R
0
0
0
0
0
0
0
0
FCMSGBUF
IPL
FCWKUP
IPL
$3
IPR3
FCERR IPL
GPIOA IPL
FCBOFF IPL
GPIOB IPL
W
R
0
0
0
0
0
0
0
0
0
0
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
$4
IPR4
GPIOC IPL
W
R
0
0
0
0
0
0
0
0
SCI1_RCV
IPL
SCI1_RERR
IPL
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
$5
IPR5
W
R
0
0
0
0
0
0
0
0
0
0
0
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
$6
IPR6
TMRC0 IPL
TMRA0 IPL
W
R
0
0
$7
IPR7
TMRC3 IPL
TMRA3 IPL
TMRC2 IPL
TMRA2 IPL
TMRC1 IPL
TMRA1 IPL
W
R
SCI0_RCV
IPL
SCI0_RERR
IPL
SCI0_TIDL
IPL
SCI0_XMIT
IPL
$8
IPR8
W
R
0
0
0
0
0
0
0
0
0
0
0
PWMA_RL
IPL
ADCA_ZC
IPL
$9
IPR9
PWMA F IPL
ADCA_CC IPL
W
R
0
0
0
0
$A
$B
$C
$D
$E
$F
VBA
VECTOR BASE ADDRESS
0
W
R
0
0
0
0
FIM0
FAST INTERRUPT 0
W
R
FAST INTERRUPT 0
VECTOR ADDRESS LOW
FIVAL0
FIVAH0
FIM1
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
W
R
FAST INTERRUPT 1
W
R
FAST INTERRUPT 1
VECTOR ADDRESS LOW
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
W
R
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
$10
$11
$12
$13
$14
$15
W
R
PENDING [16:2]
1
W
R
PENDING [32:17]
W
R
PENDING [48:33]
PENDING [64:49]
PENDING [80:65]
W
R
W
R
W
PEND-
ING
[81]
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
$16
$1D
IRQP5
W
Reserved
ICTL
IRQA
STATE
R
INT
IPIC
VAB
INT_
DIS
IRQA
EDG
W
= Reserved
Figure 5-2 ITCN Register Map Summary
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
61
5.6.1
Interrupt Priority Register 0 (IPR0)
Base + $0
Read
15
0
14
0
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0 IPL
STPCNT IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Base + $1
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
RX_REG IPL TX_REG IPL
TRBUF IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-4 Interrupt Priority Register 1 (IPR1)
56F8323 Technical Data, Rev. 17
62
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
IRQA IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
63
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt
Priority Level (FMCBE IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.2
Flash Memory Command Complete Priority Level
(FMCC IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.3
Flash Memory Error Interrupt Priority Level
(FMERR IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
64
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.6
Reserved—Bits 5–2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.3.7
External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3
Read
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FCMSGBUF IPL
FCWKUP IPL
FCERR IPL
FCBOFF IPL
Write
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-6 Interrupt Priority Register 3 (IPR3)
5.6.4.1
Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.4.2
FlexCAN Message Buffer Interrupt Priority Level
(FCMSGBUF IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
65
5.6.4.3
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.4
FlexCAN Error Interrupt Priority Level (FCERR IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
15
14
13
12
11
10
9
0
8
0
7
0
6
0
5
4
3
2
1
0
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
GPIOA IPL
GPIOB IPL
GPIOC IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-7 Interrupt Priority Register 4 (IPR4)
56F8323 Technical Data, Rev. 17
66
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.5.1
SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.2
SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.3
SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.4
Reserved—Bits 9–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5.5
GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
67
5.6.5.6
GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.7
GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6
Interrupt Priority Register 5 (IPR5)
Base + $5
Read
15
0
14
0
13
0
12
0
11
10
9
8
7
0
6
0
5
4
3
2
1
0
SCI1_RCV
IPL
SCI1_RERR
IPL
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.2
SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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68
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.6.3
SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.4
Reserved—Bits 7–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.5
SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.6
SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits
3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.7
SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
69
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
TMRC0 IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Reserved—Bits 13–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.3
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ
IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
70
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.8
Interrupt Priority Register 7 (IPR7)
Base + $7
Read
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
TMRA0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-10 Interrupt Priority Register (IPR7)
5.6.8.1
Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.2
Reserved—Bits 13–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.8.3
Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.4
Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
71
5.6.8.5
Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9
Interrupt Priority Register 8 (IPR8)
Base + $8
Read
15
14
13
12
11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI0_RCV
IPL
SCI0_RERR
IPL
SCI0_TIDL
IPL
SCI0_XMIT
IPL
TMRA3 IPL
TMRA2 IPL
TMRA1 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1
SCI0 Receiver Full Interrupt Priority Level (SCI0 RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0 RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
72
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.9.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.9.4
SCI0 Transmitter Idle Interrupt Priority Level (SCI0 TIDL IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0 XMIT IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.6
Timer A, Channel 3 Interrupt Priority Level (TMRA 3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.7
Timer A, Channel 2 Interrupt Priority Level (TMRA 2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
73
5.6.9.8
Timer A, Channel 1 Interrupt Priority Level (TMRA 1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10 Interrupt Priority Register 9 (IPR9)
Base + $9
Read
15
14
13
0
12
0
11
10
9
0
8
0
7
6
5
0
4
0
3
2
1
0
0
0
PWMA_RL
IPL
ADCA_CC
IPL
PWMA F IPL
ADCA_ZC IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA F IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.2 Reserved—Bits 13–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8323 Technical Data, Rev. 17
74
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.10.4 Reserved—Bits 9–8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level
(ADCA_ZC IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.6 Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.7 ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.8 Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11 Vector Base Address Register (VBA)
Base + $A
Read
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
0
2
0
1
0
0
0
VECTOR BASE ADDRESS
Write
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-13 Vector Base Address Register (VBA)
5.6.11.1 Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
75
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—
Bits 12–0
The contents of this register determine the location of the Vector Address Table. The value in this register
is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are
determined based upon the highest-priority interrupt; see Part 5.3.1 for details.
5.6.12 Fast Interrupt 0 Match Register (FIM0)
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; for details, see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected
results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become
the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being
declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector
number of each IRQ, refer to Table 4-3.
5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
56F8323 Technical Data, Rev. 17
76
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15 Fast Interrupt 1 Match Register (FIM1)
Base + $E
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; for details, see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected
results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become
the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being
declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector
number of each IRQ, refer to Table 4-3.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
77
5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 1
VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $10
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18 IRQ Pending 0 Register (IRQP0)
Base + $11
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
1
1
1
0
1
PENDING [16:2]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1 IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
56F8323 Technical Data, Rev. 17
78
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.18.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19 IRQ Pending 1 Register (IRQP1)
$Base + $12
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
1
1
1
0
1
PENDING [32:17]
Write
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.20 IRQ Pending 2 Register (IRQP2)
Base + $13
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [48:33]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.21 IRQ Pending 3 Register (IRQP3)
Base + $14
Read
15
1
14
1
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [64:49]
Write
RESET
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
79
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers two
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.22 IRQ Pending 4 Register (IRQP4)
Base + $15
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [80:65]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.23 IRQ Pending 5 Register (IRQP5)
Base + $16
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
PEND-
ING
[81]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 Reserved—Bits 96–82
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
5.6.23.2 IRQ Pending (PENDING)—Bit 81
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
56F8323 Technical Data, Rev. 17
80
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.24 Reserved—Base + 17
5.6.25 Reserved—Base + 18
5.6.26 Reserved—Base + 19
5.6.27 Reserved—Base + 1A
5.6.28 Reserved—Base + 1B
5.6.29 Reserved—Base + 1C
5.6.30 ITCN Control Register (ICTL)
Base + $1D
Read
15
14
13
12 11 10
9
8
7
6
0
5
INT_DIS
0
4
1
3
0
2
1
0
0
INT
IPIC
VAB
IRQA STATE
IRQA
EDG
Write
0
0
0
1
0
0
0
0
0
1
1
1
0
0
RESET
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
81
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 Reserved—Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except
the core IRQs with fixed priorities
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
56F8323 Technical Data, Rev. 17
82
Freescale Semiconductor
Preliminary
Introduction
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
•
•
•
•
•
•
•
Reset sequencing
Clock control & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
•
•
•
Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory
Power-saving clock gating for peripherals
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart)
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
•
•
•
•
•
•
Controls to enable/disable the 56800E core WAIT and STOP instructions
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
83
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
•
Reset Mode, which has two submodes:
— Total Reset Mode
– 56800E Core and all peripherals are reset
— Core-Only Reset Mode
– 56800E Core in reset, peripherals are active
– This mode is required to provide the on-chip Flash interface module time to load data from Flash
into FM registers.
•
•
Run Mode
The primary mode of operation for this device, in which the 56800E controls chip operation
Debug Mode
56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs,
continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from
being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
•
•
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
56800E, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped.
For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before
entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated
interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
6.4 Operating Mode Register
Bit
15
NL
R/W
0
14
13
12
11
10
9
0
8
CM
R/W
0
7
XP
R/W
0
6
SD
R/W
0
5
R
4
SA
R/W
0
3
EX
R/W
0
2
0
1
MB
R/W
X
0
MA
R/W
0
R/W
0
Type
0
0
0
0
0
0
RESET
Figure 6-1 OMR
The reset state for MB will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX
bit is not functional in this device since there is no external memory interface. For all other bits, see the
56F8300 Peripheral User Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
56F8323 Technical Data, Rev. 17
84
Freescale Semiconductor
Preliminary
Register Descriptions
6.5 Register Descriptions
Table 6-1 SIM Registers
(SIM_BASE = $00F350)
Address Offset
Address Acronym
Register Name
Section Location
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
Control Register
6.5.1
6.5.2
6.5.3
6.5.3
6.5.3
6.5.3
6.5.4
6.5.5
6.5.6
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
SIM_CLKOSR
SIM_GPS
CLKO Select Register
6.5.7
6.5.7
6.5.8
6.5.9
6.5.10
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
SIM_PCE
SIM_ISALH
SIM_ISALL
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
85
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
0
SIM_
CONTROL
ONCE SW
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
$0
$1
$2
$3
$4
$5
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
RSTSTS
SWR COPR EXTR POR
W
R
SIM_SCR0
SIM_SCR1
SIM_SCR2
SIM_SCR3
FIELD
FIELD
FIELD
FIELD
W
R
W
R
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
0
0
0
1
0
$6 SIM_MSH_ID
W
R
$7
$8
SIM_LSH_ID
W
R
SIM_PUDR
Reserved
RESET IRQ
JTAG
W
R
W
R
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
SIM_
CLKOSR
CLK
DIS
$A
$B
$C
$D
$E
PHSA PHSB INDEX HOME
CLKOSEL
A4
0
1
1
0
SIM_GPS
SIM_PCE
C6
1
C5
B1
B0
A5
A3
1
A2
W
R
ADCA CAN
DEC0
1
TMRC
1
TMRA SCI1 SCI0 SPI1 SPI0
PWMA
W
R
1
1
1
1
1
1
1
1
SIM_ISALH
SIM_ISALL
ISAL[23:22]
W
R
ISAL[21:6]
W
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
SIM Control Register (SIM_CONTROL)
Base + $0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
Read
Write
POR
ONCE SW
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
Reserved—Bits 15–6
6.5.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8323 Technical Data, Rev. 17
86
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.1.2
OnCE Enable (ONCE EBL)—Bit 5
•
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.3
Software Reset (SW RST)—Bit 4
Writing 1 to this field will cause the part to reset.
6.5.1.4
Stop Disable (STOP_DISABLE)—Bits 3–2
•
•
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
•
•
10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 = Same operation as 10
6.5.1.5
Wait Disable (WAIT_DISABLE)—Bits 1–0
•
•
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
•
10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only
be changed by resetting the device
•
11 = Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Base + $1
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
0
0
SWR COPR
EXTR POR
Write
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2
Software Reset (SWR)—Bit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST
bit in the SIM CONTROL register). This bit will be cleared by any hardware reset or by software. Writing
a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
87
6.5.2.3
COP Reset (COPR)—Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
External Reset (EXTR)—Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On
Reset or by software. Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will
clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET
pin being asserted low.
6.5.2.5
Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared
only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the
bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On
Reset.
6.5.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Only SIM SCR0 is shown in this section. SIM SCR1, SIM SCR2, and SIM SCR3 are identical in
functionality.
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FIELD
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
Software Control Data 1 (FIELD)—Bits 15–0
6.5.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F4.
56F8323 Technical Data, Rev. 17
88
Freescale Semiconductor
Preliminary
Register Descriptions
Base + $6
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
1
4
1
3
0
2
1
1
0
0
0
Write
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
RESET
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$001D.
Base + $7
Read
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8
Read
15
0
14
13
12
11
RESET
0
10
IRQ
0
9
8
7
6
5
4
3
JTAG
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
89
6.5.6.3
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA pin.
6.5.6.4
Reserved—Bits 9–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.5
JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS, and TDI pins.
6.5.6.6
Reserved—Bits 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant unspecified latencies at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are
programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional
clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4]
to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX shown
in Figure 6-9.
The CLKOUT pin is not bonded out in the device. Instead, it is offered only as a pad for die-level testing.
Base + $A
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
0
3
0
2
CLKOSEL
0
1
0
0
0
CLK
DIS
PHSA PHSB INDEX HOME
Write
RESET
0
0
0
0
0
0
0
0
0
0
1
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1
Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
PHASEA0 (PHSA)—Bit 9
•
•
0 = Peripheral output function of GPIOB[7] is defined to be PHASEA0
1 = Peripheral output function of GPIOB[7] is defined to be the oscillator clock (MSTR_OSC, see
Figure 3-4)
6.5.7.3
PHASEB0 (PHSB)—Bit 8
•
•
0 = Peripheral output function of GPIOB[6] is defined to be PHASEB0
1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2
56F8323 Technical Data, Rev. 17
90
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.7.4
INDEX0 (INDEX)—Bit 7
•
•
0 = Peripheral output function of GPIOB[5] is defined to be INDEX0
1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK
6.5.7.5
HOME0 (HOME)—Bit 6
•
•
0 = Peripheral output function of GPIOB[4] is defined to be HOME0
1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure 3-4)
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
•
•
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
•
•
•
•
•
•
•
•
•
00000 = SYS_CLK (from ROCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = MSTR_OSC Oscillator output
01000 = Fout (from OCCS)
•
•
•
•
•
•
•
•
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
6.5.8
SIM GPIO Peripheral Select Register (SIM_GPS)
All of the peripheral pins on the 56F8323 and 56F8123 share their I/O with GPIO ports. To select
peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI 1, Quad Timer C and
SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO
functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral
has control. The default peripherals are SPI 0, Quad Timer C, and PWMA.
Note: PWM is NOT available in the 56F8123 device.
As shown in Figure 6-10, the GPIO has the final control over the pin function. SIM_GPS simply decides
which peripheral will be routed to the I/O.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
91
GPIOX_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_GPS Register
0
1
Quad Timer Controlled
SCI Controlled
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
C6
0
6
C5
0
5
B1
0
4
B0
0
3
A5
0
2
A4
0
1
A3
0
0
A2
0
Write
0
0
0
0
0
0
0
0
RESET
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
Reserved—Bits 15–8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
GPIOC6 (C6)—Bit 7
This bit selects the alternate function for GPIOC6.
•
•
0 = TC0 (default)
1 = TXD0
6.5.8.3
GPIOC5 (C5)—Bit 6
This bit selects the alternate function for GPIOC5.
•
•
0 = TC1 (default)
1 = RXD0
6.5.8.4
GPIOB1 (B1)—Bit 5
This bit selects the alternate function for GPIOB1.
•
•
0 = MISO0 (default)
1 = RXD1
56F8323 Technical Data, Rev. 17
92
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.8.5
GPIOB0 (B0)—Bit 4
This bit selects the alternate function for GPIOB0.
•
•
0 = SS0 (default)
1 = TXD1
6.5.8.6
GPIOA5 (A5)—Bit 3
This bit selects the alternate function for GPIOA5.
•
•
0 = PWMA5
1 = SCLK1
6.5.8.7
GPIOA4 (A4)—Bit 2
This bit selects the alternate function for GPIOA4.
•
•
0 = PWMA4
1 = MOS1
6.5.8.8
GPIOA3 (A3)—Bit 1
This bit selects the alternate function for GPIOA3.
•
•
0 = PWMA3
1 = MISO1
6.5.8.9
GPIOA2 (A2)—Bit 0
This bit selects the alternate function for GPIOA2.
•
•
0 = PWMA2
1 = SS1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C
Read
15
1
14
1
13
12
11
1
10
9
1
8
7
1
6
5
4
3
2
1
1
0
ADCA CAN
DEC0
TMRC
TMRA SCI 1 SCI 0 SPI1
SPI0
PWMA
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
Reserved—Bits 15–14
6.5.9.1
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
93
6.5.9.2
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
Reserved—Bit 11
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
6.5.9.5
Decoder 0 Enable (DEC0)—Bit 10
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6
Reserved—Bit 9
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
6.5.9.7
Quad Timer C Enable (TMRC)—Bit 8
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
Reserved—Bit 7
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
6.5.9.9
Quad Timer A Enable (TMRA)—Bit 6
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8323 Technical Data, Rev. 17
94
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14 Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
6.5.9.15 Pulse Width Modulator A Enable (PWMA)—Bit 0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-13.
Note:
If this register is set ot something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
95
Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five cycles.
Base + $D
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
ISAL[23:22]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $E
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
0
1
ISAL[21:6]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
56F8323 Technical Data, Rev. 17
96
Freescale Semiconductor
Preliminary
Clock Generation Overview
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal
oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler
can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks
to be disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip Clock
Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details.
The memory, peripheral and core clocks all operate at the same frequency (60MHz max).
6.7 Power-Down Modes
The 56F8323/56F8123 operate in one of three power-down modes, as shown in Table 6-2.
Table 6-2 Clock Operation in Power-Down Modes
Mode
Core Clocks
Active
Peripheral Clocks
Description
Device is fully functional
Run
Wait
Active
Active
Core and memory
clocks disabled
Peripherals are active and can produce
interrupts if they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in The only possible recoveries from Stop mode
the SIM, but most are gated prior to
are:
reaching memory, core and peripherals.
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts (IRQA)
3. COP reset
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK =
60MHz.
Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system
frequency, which can be controlled through the OCCS.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
97
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable
Disable
STOP_DIS
D
Q
D-FLOP
Clock
Select
C
R
Note: Wait disable
circuit is similar
Reset
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the prescaler output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL) described in Part 6.5.1. This procedure
can be on either a permanent or temporary basis. Permanently assigned applications last only until their
next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and
the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself, by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
to permit proper operation of the device. A POR reset is declared when reset is removed and any of the
three voltage detectors (1.8V POR, 2.2V core voltage, or 2.7V I/O voltage) indicate a low supply voltage
condition. POR will continue to be asserted until all voltage detectors indicate a stable supply is available
(note that as power is removed POR is not declared until the 1.8V core voltage threshold is reached.) A
POR reset is then extended for 64 clock cycles to permit stabilization of the clock source, followed by a
32 clock window in which SIM clocking is initiated. It is then followed by a 32 clock window in which
peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which
the core is initialized. After completion of the described reset sequence, application code will begin
execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the system
clock.
56F8323 Technical Data, Rev. 17
98
Freescale Semiconductor
Preliminary
Operation with Security Enabled
Part 7 Security Features
The 56F8323/56F8123 offer security features intended to prevent unauthorized users from reading the
contents of the Flash memory (FM) array. The Flash security consists of several hardware interlocks that
block the means by which an unauthorized user could gain access to the Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s code that
dumps the contents of the internal program, as this code would defeat the purpose of security. At the same
time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a
security key through the SCI, allowing access to a programming routine that updates parameters stored in
another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the device can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of the FM
array. These non-volatile bytes will keep the part secured through reset and through power-down of the
device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory
section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state
of security. When Flash security mode is enabled in accordance with the method described in the Flash
Memory module specification, the device will disable the EOnCE interface, preventing access to internal
code. Normal program execurtion is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8323/56F8123 have several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be compromised
and read without explicit user permission. Methods to block these are outlined in the next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the device will operate. These are:
•
•
Unsecured Mode
Secure Mode (EOnCE disabled)
When Flash security is enabled as described in the Flash Memory module specification, the device will
disable the EOnCE debug interface.
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port)
is active and provides the chip’s boundary scan capability and access to the ID register.
Proper implementation of Flash security requires that no access to the EOnCE port is provided when
security is enabled. The 56800E core has an input which disables reading of internal memory via the
JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security
bytes.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
99
7.2.3
Flash Lockout Recovery
If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be
used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling
Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory
configuration (.cfg) files. Add, or uncomment the following configuration command:
unlock_flash_on_connect 1
For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to
control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control
the period of the clock used for timed events in the FM erase algorithm. This register must be set with
appropriate values before the lockout sequence can begin. Refer to the 56F8300 Peripheral User Manual
for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides
down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the
PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV
must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD
Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific
equations for calculating the correct values.
Flash Memory
SYS_CLK
2
input
clock
DIVIDER
7
FMCLKD
7
7
FMCLKDIV
FMERASE
JTAG
Figure 7-1 JTAG to FM Connection for Lockout Recovery
Two examples of FM_CLKDIV calculations follow.
56F8323 Technical Data, Rev. 17
100
Freescale Semiconductor
Preliminary
Flash Access Blocking Mechanisms
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up,
the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation
yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This
translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
SYS_CLK
( )
(2)
150[kHz]
200[kHz]
<
<
(DIV + 1)
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM
input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8=FM_CLKDIV[6]=1. Using the
following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of
181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
SYS_CLK
( )
(2)(8)
150[kHz]
200[kHz]
<
<
(DIV + 1)
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence has completed.
For details, see the JTAG Section in the 56F8300 Peripheral User Manual.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured
operation.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed device for product analysis of field failures is via
the backdoor key access. The customer would need to supply Technical Support with the backdoor key
and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows
backdoor key access must be set.
An alternative method for performing analysis on a secured microcontroller would be to mass-erase and
reprogram the Flash with the original code, but to modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the device during programming, it is
recommended that he program the backdoor access key first, his application code second and the security
bytes within the FM configuration field last.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
101
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F8300 Peripheral User Manual.
8.2 Configuration
There are three GPIO ports defined on the 56F8323/56F8123. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8323 GPIO Ports Configuration
Available
Port
GPIO Port
Pins in
Peripheral Function
Reset Function
Width
56F8323
PWM, SPI 1
PWM
A
B
C
12
8
12
8
SPI 0, DEC 0, TMRA, SCI 1
SPI 0, DEC 0
XTAL, EXTAL, CAN, TMRC, SCI 0
XTAL, EXTAL, CAN, TMRC
7
7
Table 8-2 56F8123 GPIO Ports Configuration
Available
Pins in
56F8123
Port
Width
GPIO Port
Peripheral Function
Reset Function
SPI 1
Must be reconfigured
A
B
C
12
8
12
8
SPI 0, SCI 1, TMRA
SPI 0; other pins must be reconfigured
XTAL, EXTAL, TMRC, SCI 0
XTAL, EXTAL, TMRC; other pins must be
reconfigured
7
7
Note: Pins in italics are NOT available in the 56F8123 device.
56F8323 Technical Data, Rev. 17
102
Freescale Semiconductor
Preliminary
Configuration
Table 8-3 GPIO External Signals Map
Package
Pin
Notes
Peripheral
Function
GPIO Function
GPIOA0
GPIOA1
GPIOA2
PWMA0
3
4
7
PWM is NOT available in 56F8123
PWM is NOT available in 56F8123
PWMA1
PWMA2 / SSI
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA3
GPIOA4
GPIOA5
PWMA3 / MISO1
PWMA4 / MOSI1
PWMA5 / SCLK1
8
9
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
10
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
GPIOB0
FAULTA0
FAULTA1
FAULTA2
ISA0
13
14
15
16
18
19
21
ISA0
ISA2
SS0 / TXD1
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
GPIOB1
MISO0 / RXD1
22
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
GPIOB2
GPIOB3
GPIOB4
MOSI0
24
25
49
SCLK0
HOME0 / TA3
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
GPIOB5
GPIOB6
INDEX0 / TA2
50
51
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
PHASEB0 / TA1
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
103
Table 8-3 GPIO External Signals Map (Continued)
Package
Pin
Notes
Peripheral
Function
GPIO Function
GPIOB7
PHASEA0 / TA0
52
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
GPIOC0
GPIOC1
GPIOC2
GPIOC3
GPIOC4
GPIOC5
EXTAL
46
47
61
62
63
64
Pull-ups default to disabled
XTAL
Pull-ups default to disabled
CAN_RX
CAN_TX
TC3
CAN is NOT available in 56F8123
CAN is NOT available in 56F8123
TC1 / RXD0
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
GPIOC6
TC0 / TXD0
1
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOX_PUR and
GPIOX_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values
of these registers.
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
56F8323 Technical Data, Rev. 17
104
Freescale Semiconductor
Preliminary
General Characteristics
Part 10 Specifications
10.1 General Characteristics
The 56F8323/56F8123 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and
5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the
power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Note: All specifications meet both Automotive and Industrial requirements unless individual
specifications are listed.
Note: The 56F8123 device is guaranteed to 40MHz and specified to meet Industrial requirements only.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
105
Note: The 56F8123 device is specified to meet Industrial requirements only; PWM, CAN and
Quad Decoder are NOT available on the 56F8123 device.
Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0)
Characteristic
Supply voltage
Symbol
Notes
Min
- 0.3
- 0.3
Max
4.0
Unit
V
VDD_IO
VDDA_ADC, VREFH VREFH must be less than
or equal to VDDA_ADC
4.0
V
ADC Supply Voltage
VDDA_OSC_PLL
- 0.3
- 0.3
-0.3
-0.3
-0.3
4.0
3.0
6.0
4.0
V
V
V
V
V
Oscillator / PLL Supply Voltage
Internal Logic Core Supply Voltage
Input Voltage (digital)
OCR_DIS is High
Pin Groups 1, 3, 4, 5
Pin Groups 7, 8
VDD_CORE
VIN
VINA
Input Voltage (analog)
Pin Groups 1, 2, 3
VOUT
4.0
6.01
Output Voltage
GPIO pins used in open
drain mode
VOUTOD
-0.3
6.0
V
Output Voltage (open drain)
TA
TA
-40
-40
-40
-40
-55
-55
125
105
150
125
150
150
°C
°C
°C
°C
°C
°C
Ambient Temperature (Automotive)
Ambient Temperature (Industrial)
Junction Temperature (Automotive)
Junction Temperature (Industrial)
TJ
TJ
TSTG
TSTG
Storage Temperature (Automotive)
Storage Temperature (Industrial)
1. If corresponding GPIO pin is configured as open drain.
Note: Pins in italics are NOT available in the 56F8123 device.
Pin Group 1: TC0-1, TC3, FAULTA0-2, ISA0-2, SS0, MISO0, MOSI0, SCLK0, HOME0, INDEX0, PHASEA0, PHASEB0, CAN_RX,
CAN_TX, GPIOC0-1
Pin Group 2: TDO
Pin Group 3: PWMA0-5
Pin Group 4: RESET, TMS, TDI, TRST, IRQA
Pin Group 5: TCK
Pin Group 6: XTAL, EXTAL
Pin Group 7: ANA0-7
Pin Group 8: OCR_DIS
56F8323 Technical Data, Rev. 17
106
Freescale Semiconductor
Preliminary
General Characteristics
Table 10-2 56F8323/56F8123 ElectroStatic Discharge (ESD) Protection
Characteristic
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
Min
2000
200
Typ
Max
Unit
—
—
—
—
—
—
V
V
V
500
ESD for Change Device Model (CDM)
6
Table 10-3 Thermal Characteristics
Value
Characteristic
Comments
Symbol
Unit
Notes
64-pin LQFP
Junction to ambient
Natural Convection
RθJA
41
°C/W
2
RθJMA
34
34
°C/W
°C/W
2
Junction to ambient (@1m/sec)
RθJMA
(2s2p)
1,2
Junction to ambient
Natural Convection
Four layer board
(2s2p)
RθJMA
29
°C/W
1,2
Junction to ambient (@1m/sec)
Four layer board
(2s2p)
RθJC
8
°C/W
°C/W
W
3
Junction to case
ΨJT
2
4, 5
Junction to center of case
I/O pin power dissipation
Power dissipation
P
User-determined
I/O
P
P D = (IDD x VDD
P I/O
+
W
D
)
(TJ - TA) / RθJA7
P
W
Maximum allowed PD
DMAX
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p ther-
mal test board.
2. Junction-to-ambient thermal resistance, Theta-JA (R
), was simulated to be equivalent to the JEDEC specification JESD51-2
θJA
in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes
(2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name
for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3. Junction-to-case thermal resistance, Theta-JC (R
), was simulated to be equivalent to the measured values using the cold
θJC
plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is
described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when
the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (Ψ ), is the "resistance" from junction to reference point thermocouple on top cen-
JT
ter of case as defined in JESD51-2. Ψ is a useful value to estimate junction temperature in steady-state customer environ-
JT
ments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
6. See Part 12.1 for more details on thermal design considerations.
7. TJ = Junction temperature
TA = Ambient temperature
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
107
Note:
The 56F8123 device is guaranteed to 40MHz and specified to meet Industrial requirements
only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device.
Table 10-4 Recommended Operating Conditions
(VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL
)
Characteristic
Symbol
Notes
Min
3
Typ
Max
3.6
Unit
V
V
3.3
3.3
Supply voltage
DD_IO
V
V
VREFH must be less
than or equal to
VDDA_ADC
3
3.6
ADC Supply Voltage
DDA_ADC,
V
REFH
V
V
V
3
3.3
2.5
—
3.6
2.75
Oscillator / PLL Supply Voltage
Internal Logic Core Supply Voltage
Device Clock Frequency
DDA_OSC_PLL
OCR_DIS is High
V
2.25
DD_CORE
MHz
V
FSYSCLK
0
60/40
Pin Groups 1, 3, 4, 5
Pin Group 8
V
2
2
—
5.5
Input High Voltage (digital)
Input High Voltage (analog)
IN
V
V
—
VDDA+0.3
VDDA+0.3
IHA
Pin Group 6
V
V
VDDA-0.8
—
Input High Voltage (XTAL/EXTAL,
XTAL is not driven by an external clock)
IHC
Pin Group 6
V
V
2
—
—
VDDA+0.3
0.8
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
IHC
Pin Groups
1, 3, 4, 5, 6, 8
V
V
-0.3
Input Low Voltage
IL
Pin Groups 1, 2
Pin Group 3
mA
I
—
—
—
—
—
—
—
-4
-12
4
Output High Source Current
VOH = 2.4V (VOH min.)
OH
Pin Groups 1, 2
Pin Group 3
mA
I
—
Output Low Sink Current
VOL = 0.4V (VOL max)
OL
—
12
125
°C
T
-40
Ambient Operating Temperature
(Automotive)
A
105
—
°C
T
-40
10,000
10,000
15
—
—
—
—
Ambient Operating Temperature
(Industrial)
A
TA = -40°C to 125°C
TA = -40°C to 105°C
TJ <= 85°C avg
Cycles
Cycles
Years
N
Flash Endurance (Automotive)
(Program Erase Cycles)
F
N
—
Flash Endurance (Industrial)
(Program Erase Cycles)
F
T
—
Flash Data Retention
R
(Automotive and Industrial)
Note: Total chip source or sink current cannot exceed 150mA.
Note: Pins in italics are NOT available in the 56F8123 device.
See Pin Groups in Table 10-1
56F8323 Technical Data, Rev. 17
108
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
10.2 DC Electrical Characteristics
Note: The 56F8123 device is specified to meet Industrial requirements only; PWM, CAN and Quad
Decoder are NOT available on the 56F8123 device.
Table 10-5 DC Electrical Characteristics
At Recommended Operating Conditions; see Table 10-4
Characteristic
Symbol
Notes
Min
2.4
—
Typ
—
—
0
Max
—
Unit Test Conditions
V
V
IOH = IOHmax
IOL = IOLmax
V
Output High Voltage
Output Low Voltage
OH
V
0.4
OL
Pin Groups 1, 3, 4
Pin Group 5
μA
VIN = 3.0V to 5.5V
I
—
+/- 2.5
Digital Input Current High
pull-up enabled or disabled
IH
μA
VIN = 3.0V to 5.5V
I
40
80
160
Digital Input Current High
with pull-down
IH
Pin Group 8
Pin Group 7
μA
μA
μA
VIN = VDDA
VIN = VDDA
VIN = 0V
I
—
—
0
0
+/- 2.5
+/- 3.5
-50
Analog Input Current High
ADC Input Current High
IHA
I
IHADC
Pin Groups 1, 3, 4
I
-200
-100
Digital Input Current Low
pull-up enabled
IL
Pin Groups 1, 3, 4
Pin Group 5
μA
μA
VIN = 0V
VIN = 0V
I
—
—
0
0
+/- 2.5
+/- 2.5
Digital Input Current Low
pull-up disabled
IL
I
Digital Input Current Low with
pull-down
IL
Pin Group 8
Pin Group 7
μA
μA
μA
VIN = 0V
VIN = 0V
I
—
—
—
0
0
0
+/- 2.5
+/- 3.5
+/- 2.5
Analog Input Current Low
ADC Input Current Low
ILA
I
ILADC
VIN = VDDA or 0V
I
EXTAL Input Current Low
clock input
EXTAL
CLKMODE = High
CLKMODE = Low
Pin Groups 1, 2, 3
μA
μA
μA
VIN = VDDA or 0V
VIN = VDDA or 0V
I
—
—
—
0
—
0
+/- 2.5
200
XTAL Input Current Low
clock input
XTAL
VOUT = 3.0V to
5.5V or 0V
I
+/- 2.5
Output Current
High Impedance State
OZ
Pin Groups
1, 3, 4, 5
V
V
—
—
—
0.3
4.5
5.5
—
—
—
Schmitt Trigger Input
Hysteresis
HYS
pF
pF
C
Input Capacitance
(EXTAL/XTAL)
INC
C
Output Capacitance
(EXTAL/XTAL)
OUTC
pF
pF
C
—
—
6
6
—
—
Input Capacitance
Output Capacitance
IN
C
OUT
See Pin Groups in Table 10-1
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
109
Table 10-6 Power-On Reset Low Voltage Parameters
Characteristic
POR Trip Point Rising1
Symbol
PORR
PORF
Min
—
Typ
—
Max
—
Units
V
POR Trip Point Falling
1.75
—
1.8
1.9
—
V
LVI, 2.5V Supply, trip point2
VEI2.5
VEI3.3
2.14
2.7
V
LVI, 3.3V supply, trip point3
Bias Current
—
—
V
I bias
—
110
130
μA
1. Both V
and V
thresholds must be met for POR to be released on power-up.
EI3.3
EI2.5
2. When V
3. When V
drops below V
drops below V
, an interrupt is generated.
, an interrupt is generated.
DD_CORE
DD_CORE
EI2.5
EI3.3
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
1
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
IDD_IO
• 60MHz Device Clock
• All peripheral clocks are enabled
RUN1_MAC
115mA
25mA
2.5mA
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
Wait3
Stop1
60mA
35μA
0μA
2.5mA
• All peripheral clocks are enabled
• ADC powered off
• 4MHz Device Clock
• All peripheral clocks are off
• Relaxation oscillator is on
• ADC powered off
5.7mA
360μA
• PLL powered off
• Relaxation oscillator is off
• All peripheral clocks are off
• ADC powered off
Stop2
5mA
0μA
145μA
• PLL powered off
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
2. Includes Processor Core current supplied by internal voltage regulator
56F8323 Technical Data, Rev. 17
110
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
1
IDD_Core
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
• 60MHz Device Clock
IDD_IO
RUN1_MAC
110mA
13μA
25mA
2.5mA
• All peripheral clocks are enabled
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
• All peripheral clocks are enabled
• ADC powered off
Wait3
Stop1
55mA
13μA
13μA
35μA
0μA
2.5mA
• 4MHz Device Clock
700μA
360μA
• All peripheral clocks are off
• Relaxation oscillator is on
• ADC powered off
• PLL powered off
• Relaxation oscillator is off
• All peripheral clocks are off
• ADC powered off
Stop2
100μA
13μA
0μA
145μA
• PLL powered off
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
10.2.1 Voltage Regulator Specifications
The 56F8323/56F8123 have two on-chip regulators. One supplies the PLL and has no external pins;
therefore, it has no external characteristics which must be guaranteed (other than proper operation of the
device). The second regulator supplies approximately 2.6V to the device’s core logic. This regulator
requires two external 2.2μF, or greater, capacitors for proper operation. Ceramic and tantalum capacitors
tend to provide better performance tolerances. The output voltage can be measured directly on the V
CAP
pins. The specifications for this regulator are shown in Table 10-9.
Table 10-9. Regulator Parameters
Characteristic
Symbol
VRNL
Min
2.25
Typical
Max
2.75
Unit
Unloaded Output Voltage
(0mA Load)
—
V
V
V
Loaded Output Voltage
(200mA load)
VRL
VR
2.25
2.25
—
—
2.75
2.75
Line Regulation @ 250mA load
(VDD33 ranges from 3.0V to 3.6V)
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
111
Table 10-9. Regulator Parameters (Continued)
Characteristic
Symbol
Iss
Min
Typical
Max
700
Unit
Short Circuit Current
—
—
mA
(output shorted to ground)
Bias Current
I bias
Ipd
—
—
—
5.8
0
7
mA
Power-down Current
2
μA
Short-Circuit Tolerance
TRSC
—
30
minutes
(output shorted to ground)
Table 10-10. PLL Parameters
Characteristics
PLL Start-up time
Symbol
TPS
Min
Typical
0.5
Max
Unit
ms
0.3
0.1
10
1
Resonator Start-up time
Min-Max Period Variation
Peak-to-Peak Jitter
TRS
TPV
TPJ
IBIAS
IPD
0.18
—
ms
120
—
200
175
2
ps
—
ps
Bias Current
—
1.5
100
mA
μA
Quiescent Current, power-down mode
—
150
10.2.2 Temperature Sense
Note: Temperature Sensor is NOT available in the 56F8123 device.
Table 10-11 Temperature Sense Parametrics
Characteristics
Slope (Gain)1
Symbol
m
Min
—
Typical
7.762
26
Max
—
Unit
mV/°C
°C
Room Trim Temp. 1, 2
TRT
24
28
Hot Trim Temp. (Industrial)1,2
Hot Trim Temp. (Automotive)1,2
THT
122
147
—
125
128
153
—
°C
THT
150
°C
Output Voltage @
VDDA_ADC = 3.3V, TJ =0°C1
VTS0
1.370
V
Supply Voltage
VDDA_ADC
3.0
3.3
3.6
V
56F8323 Technical Data, Rev. 17
112
Freescale Semiconductor
Preliminary
AC Electrical Characteristics
Table 10-11 Temperature Sense Parametrics (Continued)
Characteristics
Supply Current - OFF
Symbol
IDD-OFF
IDD-ON
TACC
Min
—
Typical
Max
10
Unit
μA
—
—
0
Supply Current - ON
—
250
6.7
μA
Accuracy3,1 from -40°C to 150°C
Using VTS = mT + VTS0
-6.7
°C
Resolution4, 5,1
RES
—
0.104
—
°C / bit
1. Includes the ADC conversion of the analog Temperature Sense voltage.
2. The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at
FMOPT0 and FMOPT1.
3. See Application Note, AN1980, for methods to increase accuracy.
4. Assuming a 12-bit range from 0V to 3.3V.
5. Typical resolution calculated using equation,
(VREFH - VREFLO) X 1
=
RES
212
m
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in Figure 10-1.
Low
VIL
High
VIH
90%
50%
10%
Input Signal
Midpoint1
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 10-1 Input Signal Measurement References
Figure 10-2 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
113
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 10-2 Signal States
10.4 Flash Memory Characteristics
Table 10-12 Flash Timing Parameters
Characteristic
Symbol
Tprog
Terase
Tme
Min
20
Typ
—
Max
—
Unit
μs
Program time 1
Erase time2
20
—
—
ms
ms
Mass erase time
100
—
—
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual
for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro-
gram Flash module, as it contains two interleaved memories.
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
10.5 External Clock Operation Timing
1
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
0
Typ
—
Max
120
80
Unit
MHz
MHz
ns
Frequency of operation (external clock driver)2—56F8323
Frequency of operation (external clock driver)2—56F8123
Clock Pulse Width3
fosc
0
—
tPW
3.0
—
—
—
—
External clock input rise time4
trise
—
15
ns
External clock input fall time5
tfall
—
15
ns
1. Parameters listed are guaranteed by design.
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%
5. External clock input fall time is measured from 90% to 10%
56F8323 Technical Data, Rev. 17
114
Freescale Semiconductor
Preliminary
Phase Locked Loop Timing
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
8.4
Unit
MHz
MHz
External reference crystal frequency for the PLL1
PLL output frequency2 (fOUT)—56F8323
fop
160
—
260
PLL output frequency2 (fOUT)—56F8123
fop
160
—
—
1
160
10
MHz
ms
PLL stabilization time3 -40° to +125°C
tplls
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
/2), please refer to the OCCS chapter in
OUT
the 56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
10.7 Crystal Oscillator Parameters
Table 10-15 Crystal Oscillator Parameters
Characteristic
Crystal Start-up time
Symbol
TCS
Min
Typ
Max
Unit
4
5
10
1
ms
ms
Resonator Start-up time
Crystal ESR
TRS
RESR
TD
0.1
—
70
0.18
—
120
250
1.5
ohms
ps
Crystal Peak-to-Peak Jitter
Crystal Min-Max Period Variation
Resonator Peak-to-Peak Jitter
—
TPV
TRJ
0.12
—
—
ns
—
300
ps
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
115
Table 10-15 Crystal Oscillator Parameters (Continued)
Characteristic
Symbol
TRP
Min
Typ
Max
300
Unit
Resonator Min-Max Period Variation
Bias Current, high-drive mode
Bias Current, low-drive mode
—
—
—
—
—
ps
IBIASH
IBIASL
IPD
250
80
0
290
110
1
μA
μA
μA
Quiescent Current, power-down mode
Table 10-16 Relaxation Oscillator Parameters
Characteristic
Center Frequency
Min
Typ
Max
Units
MHz
—
—
8
—
—
Minimum Tuning Step Size
(See Note)
82
ps
ns
%
Maximum Tuning Step Size
(See Note)
—
—
41
—
Frequency Accuracy
-50°C to +150°C
+/- 1.78
+2 /-3
(See Figure 10-4)
Maximum Cycle-to-Cycle
Jitter
—
—
—
—
500
4
ps
Stabilization Time from Power-up
μs
Note: An LSB change in the tuning code results in an 82ps shift in the frequency period, while an MSB change in the
tuning code results in a 41ns shift in the frequency period.
56F8323 Technical Data, Rev. 17
116
Freescale Semiconductor
Preliminary
Reset, Stop, Wait, Mode Select, and Interrupt Timing
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
Typical Response
- 50
- 30
+ 10
+ 30
+ 90
- 10
+ 150
+ 50
+ 70
+ 110 + 130
Temperature
Figure 10-4 Frequency versus Temperature
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
tRA
tIRW
16T
1.5T
18T
14T
1.5T
—
—
—
—
—
ns
ns
ns
10-5
10-6
10-7
Minimum RESET Assertion Duration
Edge-sensitive Interrupt Request Width
tIG
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG - FAST
tIW
IRQA Width Assertion to Recover from Stop State3
ns
10-8
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
117
RESET
tRA
tRAZ
tRDA
First Fetch
PAB
PDB
Figure 10-5 Asynchronous Reset Timing
IRQA
tIRW
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
PAB
First Interrupt Instruction Execution
tIDM
IRQA
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA
b) General Purpose I/O
Figure 10-7 External Level-Sensitive Interrupt Timing
tIW
IRQA
tIF
PAB
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing
56F8323 Technical Data, Rev. 17
118
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
10.9 Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure(s)
Cycle time
Master
Slave
tC
10-9, 10-10,
10-11, 10-12
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
10-12
10-12
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-9, 10-10,
10-11, 10-12
17.6
25
—
—
ns
ns
Clock (SCK) low time
Master
Slave
10-12
24.1
25
—
—
ns
ns
Data set-up time required for inputs
Master
Slave
tDS
tDH
tA
10-9, 10-10,
10-11, 10-12
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
10-9, 10-10,
10-11, 10-12
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
10-12
10-12
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-9, 10-10,
10-11, 10-12
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
10-9, 10-10,
10-11, 10-12
0
0
—
—
ns
ns
Rise time
Master
Slave
10-9, 10-10,
10-11, 10-12
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
10-9, 10-10,
10-11, 10-12
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
119
1
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV
Bits 14–1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-9 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV(ref)
tDV
Bits 14– 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 1)
56F8323 Technical Data, Rev. 17
120
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tF
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 10-11 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
Slave LSB out
tDI
tA
tF
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 1)
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
121
10.10 Quad Timer Timing
1, 2
Table 10-19 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
Max
—
Unit
ns
See Figure
10-13
2T + 6
1T + 3
1T - 3
0.5T - 3
Timer input high / low period
Timer output period
PINHL
POUT
—
ns
10-13
—
ns
10-13
Timer output high / low period
POUTHL
—
ns
10-13
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 10-13 Timer Timing
10.11 Quadrature Decoder Timing
Note: The Quadrature Decoder is NOT available in the 56F8123 device.
1, 2
Table 10-20 Quadrature Decoder Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Quadrature input period
PIN
4T + 12
—
ns
ns
ns
10-14
10-14
10-14
Quadrature input high / low period
Quadrature phase period
PHL
PPH
2T + 6
1T + 3
—
—
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.
2. Parameters listed are guaranteed by design.
56F8323 Technical Data, Rev. 17
122
Freescale Semiconductor
Preliminary
Serial Communication Interface (SCI) Timing
PPH PPH PPH PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 10-14 Quadrature Decoder Timing
10.12 Serial Communication Interface (SCI) Timing
1
Table 10-21 SCI Timing
Characteristic
Baud Rate2
Symbol
Min
—
Max
Unit
See Figure
—
BR
(fMAX/16)
Mbps
RXD3 Pulse Width
TXD4 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
1.04/BR
1.04/BR
ns
ns
10-15
10-16
1. Parameters listed are guaranteed by design.
2. f is the frequency of operation of the system clock in MHz, which is 60MHz for the 56F8323 device and 40MHz
MAX
for the 56F8123 device.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 10-15 RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 10-16 TXD Pulse Width
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
123
10.13 Controller Area Network (CAN) Timing
Note: The CAN is NOT available in the 56F8123 device.
1
Table 10-22 CAN Timing
Characteristic
Baud Rate
Bus Wake-up detection
Symbol
Min
—
Max
Unit
See Figure
—
BRCAN
1
Mbps
TWAKEUP
TIPBUS
μs
10-17
—
1. Parameters listed are guaranteed by design
MSCAN_RX
CAN receive
data pin
T WAKEUP
(Input)
Figure 10-17 Bus Wakeup Detection
10.14 JTAG Timing
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
10-18
TCK frequency of operation using
EOnce1
fOP
DC
SYS_CLK/8
MHz
TCK frequency of operation not
using EOnce1
fOP
DC
SYS_CLK/4
MHz
10-18
TCK clock pulse width
TMS, TDI data set up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
tPW
tDS
50
5
—
—
—
30
30
—
ns
ns
ns
ns
ns
ns
10-18
10-19
10-19
10-19
10-19
10-20
tDH
5
tDV
—
—
tTS
2T2
tTRST
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
56F8323 Technical Data, Rev. 17
124
Freescale Semiconductor
Preliminary
JTAG Timing
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-18 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-19 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-20 TRST Timing Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
125
10.15 Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters
Characteristic
Input voltages
Symbol
VADIN
RES
Min
VREFL
12
Typ
—
Max
VREFH
12
Unit
V
Resolution
—
Bits
Integral Non-Linearity1
LSB2
LSB2
INL
—
+/- 2.4
+/- 0.7
+/- 3.2
< +1
Differential Non-Linearity
DNL
—
Monotonicity
GUARANTEED
—
ADC internal clock
fADIC
RAD
0.5
VREFL
5
5
MHz
V
Conversion range
—
6
VREFH
16
tAIC cycles3
ms
ADC channel power-up time
tADPU
ADC reference circuit power-up time4
Conversion time
tVREF
tADC
—
—
—
6
25
—
tAIC cycles3
tAIC cycles3
Sample time
tADS
—
1
—
Input capacitance
CADI
IADI
—
—
—
—
—
—
—
—
—
—
—
—
5
—
3
pF
mA
mA
mA
mA
Input injection current5, per pin
Input injection current, total
—
IADIT
—
20
VREFH current
IVREFH
IADCA
IADCB
IADCQ
EGAIN
VOFFSET
AECAL
CF1
1.2
3
ADC A current
ADC B current
25
—
25
0
—
mA
μA
Quiescent current
10
Uncalibrated Gain Error (ideal = 1)
Uncalibrated Offset Voltage
+/- .004
+/- 26
+/- .01
+/- 32
—
—
mV
LSBs
—
Calibrated Absolute Error6
Calibration Factor 17
See Figure 10-21
0.008597
-2.8
—
Calibration Factor 27
CF2
—
—
Crosstalk between channels
Common Mode Voltage
—
—
—
-60
—
—
dB
V
Vcommon
(VREFH - VREFLO) / 2
Signal-to-noise ratio
SNR
—
64.6
—
db
56F8323 Technical Data, Rev. 17
126
Freescale Semiconductor
Preliminary
Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters (Continued)
Characteristic
Signal-to-noise plus distortion ratio
Total Harmonic Distortion
Symbol
Min
Typ
Max
Unit
SINAD
THD
—
—
—
—
59.1
60.6
61.1
9.6
—
—
—
—
db
db
Spurious Free Dynamic Range
SFDR
ENOB
db
Effective Number Of Bits8
Bits
1. INL measured from V = .1V
to V = .9V
in REFH
in
REFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
127
Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes Before
and After Calibration for VDC = 0.60V and 2.70V
in
Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset
error. The data was taken on 15 parts: three each from four processing corner lots as well as three from one
nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 45 data points
shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates that for the given
population of parts, calibration significantly reduced (by as much as 34%) the collective variation (spread)
of the absolute error of the population. It also significantly reduced (by as much as 80% when VDC was
in
0.6V) the mean (average) of the absolute error and thereby brought it significantly closer to the ideal value
of zero. Although not guaranteed, it is believed that calibration will produce results similar to those shown
above for any population of parts, including those which represent processing and temperature extremes.
56F8323 Technical Data, Rev. 17
128
Freescale Semiconductor
Preliminary
Equivalent Circuit for ADC Inputs
10.16 Equivalent Circuit for ADC Inputs
Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (V
-V
)/2, while the other charges to the analog input voltage. When the
REFH REFLO
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V -V )/2. The switches switch
REFH REFLO
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
and the ADC clock frequency.
REF
Analog Input
3
4
S1
C1
C2
S/H
S3
S2
(VREFH - VREFLO)/2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
Figure 10-22 Equivalent Circuit for A/D Loading
10.17 Power Consumption
See Part 10 for a list of IDD requirements for the 56F8323. This section provides additional detail which
can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, current, PLL,
and voltage references. These sources operate independently of processor state or operating frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
129
2
C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
2
on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two
of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Table 10-25 IO Loading Coefficients at 10MHz
Intercept
Slope
8mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
4mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
1.3
0.11mW / pF
0.11mW / pF
1.15mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-25 provides coefficients for calculating power dissipated
in the IO cells as a function of capacitive load. In these cases:
TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)
where:
•
•
•
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
2
device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V =
0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs
driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
56F8323 Technical Data, Rev. 17
130
Freescale Semiconductor
Preliminary
56F8323 Package and Pin-Out Information
Part 11 Packaging
11.1 56F8323 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8323. This device comes in a 64-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 64-pin LQFP,
Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the
64-pin LQFP case.
ORIENTATION
MARK
VDD_IO
XTAL
TC0
49
RESET
EXTAL
PWMA0
PWMA1
PIN 1
OCR_DIS
VSS
VCAP
3
VCAP
4
VDD_IO
VDDA_OSC_PLL
PWMA2
VDDA_ADC
VREFH
PWMA3
PWMA4
PWMA5
VSSA_ADC
VREFLO
VREFP
VSS
IRQA
VREFMID
FAULTA0
FAULTA1
FAULTA2
VREFN
33
TEMP_SENSE
17
ANA7
ISA0
Figure 11-1 Top View, 56F8323 64-Pin LQFP Package
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
131
Table 11-1 56F8323 64-Pin LQFP Package Identification by Pin Number
Pin No. Signal Name Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
TC0
17
VSS
33
ANA7
49
HOME0
2
3
RESET
PWMA0
18
19
ISA1
ISA2
34
35
TEMP_SENSE
VREFN
50
51
INDEX0
PHASEB0
4
5
PWMA1
20
21
22
23
24
25
26
27
28
VDD_IO
SS0
36
37
38
39
40
41
42
43
44
VREFMID
VREFP
52
53
54
55
56
57
58
59
60
PHASEA0
TCK
VCAP3
6
VDD_IO
PWMA2
PWMA3
PWMA4
PWMA5
VSS
MISO0
VREFLO
TMS
7
VCAP2
VSSA_ADC
VREFH
VDDA_ADC
VDDA_OSC_PLL
VCAP
VSS
TDI
8
MOSI0
SCLK0
ANA0
ANA1
ANA2
TDO
9
VCAP1
10
11
12
TRST
VDD_IO
VSS
4
IRQA
13
14
15
16
FAULTA0
FAULTA1
FAULTA2
ISA0
29
30
31
32
ANA3
ANA4
ANA5
ANA6
45
46
47
48
OCR_DIS
EXTAL
XTAL
61
62
63
64
CAN_RX
CAN_TX
TC3
VDD_IO
TC1
56F8323 Technical Data, Rev. 17
132
Freescale Semiconductor
Preliminary
56F8123 Package and Pin-Out Information
11.2 56F8123 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8123. This device comes in a 64-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 64-pin LQFP,
Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the
64-pin LQFP case.
ORIENTATION
MARK
VDD_IO
XTAL
TC0
49
RESET
EXTAL
GPIOA0
GPIOA1
PIN 1
OCR_DIS
VSS
VCAP
3
VCAP
4
VDD_IO
VDDA_OSC_PLL
SS1
VDDA_ADC
VREFH
MISO1
MOSI1
SCLK1
VSSA_ADC
VREFLO
VREFP
VSS
IRQA
VREFMID
VREFN
NC
GPIOA6
GPIOA7
GPIOA8
33
17
ANA7
GPIOA9
Figure 11-2 Top View, 56F8123 64-Pin LQFP Package
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
133
Table 11-2 56F8123 64-Pin LQFP Package Identification by Pin Number
Pin No. Signal Name Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
TC0
17
VSS
33
ANA7
49
TA3
2
3
RESET
18
19
GPIOA10
GPIOA11
34
35
NC
50
51
TA2
TA1
GPIOA0
VREFN
4
5
GPIOA1
20
21
22
23
24
25
26
27
28
VDD_IO
SS0
36
37
38
39
40
41
42
43
44
VREFMID
VREFP
52
53
54
55
56
57
58
59
60
TA0
TCK
TMS
TDI
VCAP3
6
VDD_IO
SS1
MISO0
VREFLO
7
VCAP
2
VSSA_ADC
VREFH
VDDA_ADC
VDDA_OSC_PLL
VCAP
VSS
8
MISO1
MOSI1
SCLK1
VSS
MOSI0
SCLK0
ANA0
ANA1
ANA2
TDO
9
VCAP1
10
11
12
TRST
VDD_IO
VSS
4
IRQA
13
14
15
16
GPIOA6
GPIOA7
GPIOA8
GPIOA9
29
30
31
32
ANA3
ANA4
ANA5
ANA6
45
46
47
48
OCR_DIS
EXTAL
XTAL
61
62
63
64
GPIOC2
GPIOC3
TC3
VDD_IO
TC1
56F8323 Technical Data, Rev. 17
134
Freescale Semiconductor
Preliminary
56F8123 Package and Pin-Out Information
4X
4X 16 TIPS
0.2
H
A-B
D
0.2
C
A-B D
A2
S
0.05
64
49
(S)
1
48
2X R R1
q 1
0.25
A
B
GAGE PLANE
q
E
E1
(L2)
L
A1
3X
(L1)
E1/2
VIEW Y
E/2
VIEW AA
16
33
17
32
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,
1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE DATUM H IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THELEADEXITSTHEPLASTICBODYATTHE BOTTOM
OF THE PARTING LINE.
D
D1/2
D/2
D1
4. DATUMS A, B AND D TO BE DETERMINED AT DATUM
PLANE DATUM C.
D
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE DATUM C.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.ALLOWABLEPROTRUSIONIS0.25PER
SIDE.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35. MINIMUM
SPACE BETWEEN PROTRUSION AND ADJACENT
LEAD OR PROTRUSION 0.07.
4X (q2)
H
A
0.08 C
MILLIMETERS
4X (q 3)
DIM MIN
MAX
1.60
0.15
1.45
0.27
0.23
0.20
0.16
SEATING
PLANE
C
A
A1
A2
b
b1
c
---
VIEW AA
0.05
1.35
0.17
0.17
0.09
0.09
c1
D
12.00 BSC
BASE METAL
D1
e
E
E1
L
L1
L2
R1
S
10.00 BSC
0.50 BSC
12.00 BSC
10.00 BSC
b1
X
X=A, B OR D
0.45
0.75
c1
c
1.00 REF
0.50 REF
0.10
0.20
C
L
0.20 REF
q
0
0
7
---
AB
AB
°
°
°
e/2
PLATING
q 1
q 2
q 3
b
12 REF
12 REF
°
60X
e
M
0.08
C A-B D
°
VIEW Y
SECTION AB-AB
ROTATED 90 CLOCKWISE
°
Figure 11-3 64-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
135
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
x P )
D
J
A
θJΑ
where:
o
T
R
= Ambient temperature for the package ( C)
A
o
= Junction-to-ambient thermal resistance ( C/W)
θJΑ
P
= Power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single-layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single layer
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low-power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
R
R
R
= Package junction-to-ambient thermal resistance °C/W
= Package junction-to-case thermal resistance °C/W
= Package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For instance, the user can change the size of the heat
θCA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ x P )
J
T
JT
D
where:
o
T
Ψ
= Thermocouple temperature on top of package ( C)
= Thermal characterization parameter ( C)/W
T
o
JT
P
= Power dissipation in package (W)
D
56F8323 Technical Data, Rev. 17
136
Freescale Semiconductor
Preliminary
Electrical Design Considerations
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8323/56F8123:
•
Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the
board ground to each VSS (GND) pin
•
The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
performance tolerances.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS
Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum capacitor
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
137
•
•
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8323/56F8123. This chip
contains two internal power regulators. One of them is powered from the V
pin and cannot
DDA_OSC_PLL
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V pins and provides power to all of the internal digital logic of the core, all
DD_IO
peripherals and the internal memories. This regulator can be turned off, if an external V
voltage
DD_CORE
is externally applied to the V
pins.
CAP
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
•
•
Flash, RAM and internal logic are powered from the core regulator output
VPP1 and VPP2 are not connected in the customer system
•
All circuitry, analog and digital, shares a common VSS bus
V
DDA_OSC_PLL
V
V
DDA_ADC
DD
V
V
V
V
V
REFH
V
CAP
REG
REFP
REG
OCS
I/O
ADC
REFMID
CORE
REFN
ROSC
REFLO
V
V
SS
SSA_ADC
Figure 12-1 Power Management
56F8323 Technical Data, Rev. 17
138
Freescale Semiconductor
Preliminary
Power Distribution and I/O Ring Implementation
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 13-1 Ordering Information
Supply
Voltage
Pin
Count
Frequency Temperature
Part
Package Type
Order Number
(MHz)
Range
MC56F8323
MC56F8323
MC56F8123
3.0–3.6 V
3.0–3.6 V
3.0–3.6 V
64
64
64
60
60
40
-40° to + 105° C
-40° to + 125° C
-40° to + 105° C
MC56F8323VFB60
MC56F8323MFB60
MC56F8123VFB
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
MC56F8323
MC56F8323
MC56F8123
3.0–3.6 V
3.0–3.6 V
3.0–3.6 V
64
64
64
60
60
40
-40° to + 105° C
-40° to + 125° C
-40° to + 105° C
MC56F8323VFBE*
MC56F8323MFBE*
MC56F8123VFBE*
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
*This package is RoHS compliant.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
139
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005, 2006, 2007. All rights reserved.
MC56F8323
Rev. 17
04/2007
相关型号:
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