935311348518_技术文档

Document Number: MC33937

Rev. 11.0, 4/2019

NXP Semiconductors

Technical Data

Three phase field effect transistor

pre-driver

33937A

The 33937A is a field effect transistor (FET) pre-driver designed for three phase

motor control and similar applications. It meets the stringent requirements of

automotive applications and is fully AEC-Q100 grade 1 qualified.

THREE PHASE PRE-DRIVER

The IC contains three high-side FET pre-drivers and three low-side FET pre-

drivers. Three external bootstrap capacitors provide gate charge to the high-

side FETs.

The IC interfaces to a MCU via six direct input control signals, an SPI port for

device setup and asynchronous reset, enable and interrupt signals. Both 5.0

and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are

provided. The integrated circuit (IC) uses SMARTMOS technology.

Features

• Extended operating range from 6.0 V to 58 V covers 12 V and 42 V systems

• Gate drive capability of 1.0 A to 2.5 A

• Fully specified from 8.0 V to 40 V covers 12 and 24 V automotive systems

• Protection against reverse charge injection from CGD and CGS of external

FETs

EK SUFFIX (Pb-FREE)

98ASA99334D

54-PIN SOICW-EP

Applications

Automotive systems

• Includes a charge pump to support full FET drive at low battery voltages

• Dead time is programmable via the SPI port

• Cooling fan

• Water pump

• Actuator controls

• Fuel pump

• Simultaneous output capability enabled via safe SPI command

• AEC-Q100 grade 1 qualified

• Electro-hydraulic and electric power steering

• Engine control

• Motor control

V

SYS

33937

VPUMP

PUMP

VSUP

PA_HS_G

PB_HS_G

PC_HS_G

VPWR

VLS

VDD

VSS

PA_HS_S

PB_HS_S

PC_HS_S

3

PX_HS

PX_LS

PHASEX

CS

PA_LS_G

PB_LS_G

PC_LS_G

MCU

SI

OR

DSP

SCLK

SO

PX_LS_S

RST

INT

EN1

EN2

AMP_P

AMP_N

AMP_OUT

R

SEN

GND

Figure 1. 33937A simplified application diagram

1

Orderable parts

Table 1. Orderable part variations

(1)

Part number

Temperature (T )

Package

A

MC33937APEK

-40 °C to 135 °C

54 SOICW-EP

Notes

1.

To order parts in tape and reel, add the R2 suffix to the part number.

33937A

2

NXP Semiconductors

2

Internal block diagram

PUMP

VPWR

VSUP

VPUMP

MAIN

CHARGE

PUMP

PGND

TRICKLE

CHARGE

PUMP

HOLD

-OFF

CIRCUIT

VLS

REG.

5.0 V

REG.

VDD

OSCILLATOR

VLS

VDD

UV

DETECT

3X

RST

INT

PX_BOOT

PX_HS_G

T-LIM

VSUP

EN1

HIGH-

SIDE

DRIVER

+

1.4 V

-

EN2

DESAT.

COMP

3

CONTROL

LOGIC

PX_HS

PX_LS

CS

+

-

PX_HS_S

SI

+

-

SCLK

SO

PHASE

COMP.

VSUP

LOW-

SIDE

3

PX_LS_G

PX_LS_S

PHASEX

OC_OUT

GND(2)

DRIVER

+

-

+

-

OVERCUR.

COMP.

I-SENSE

AMP.

VSS OC_TH AMP_OUT

AMP_N

AMP_P

VLS_CAP

Figure 2. 33937A simplified internal block diagram

33937A

NXP Semiconductors

3

Pin connections

3.1

Pinout diagram

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

.35

34

33

32

31

30

29

28

PHASEA

PGND

EN1

VPWR

N/C

VLS

N/C

2

3

4

EN2

RST

N/C

5

6

7

PUMP

VPUMP

VSUP

PHASEB

PHASEC

PA_HS

PA_LS

VDD

PB_HS

PB_LS

INT

PA_BOOT

PA_HS_G

PA_HS_S

PA_LS_G

PA_LS_S

PB_BOOT

PB_HS_G

PB_HS_S

PB_LS_G

PB_LS_S

PC_BOOT

PC_HS_G

PC_HS_S

PC_LS_G

PC_LS_S

N/C

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Transparent

Top View

CS

SI

SCLK

SO

PC_LS

PC_HS

AMP_OUT

AMP_N

AMP_P

OC_OUT

VLS_CAP

GND1

GND0

VSS

OC_TH

Figure 3. 33937A pin connections

3.2

Pin definitions

A functional description of each pin can be found in the Functional pin description section beginning on page 21.

Table 2. 33937A pin definitions

Pin name

Pin function

Formal name

Definition

Totem Pole output of Phase A comparator. This output is low when the voltage on

1

PHASEA

Digital Output

Phase A

PA_HS_S (Source of High-side FET) is less than 50% of V

SUP

2

3

4

5

PGND

EN1

Ground

Power Ground

Enable 1

Enable 2

Reset

Power ground for charge pump

Digital Input

Logic signal input must be high (ANDed with EN2) to enable any gate drive output.

Logic signal input must be high (ANDed with EN1) to enable any gate drive output

Reset input

EN2

RST

6, 33, 49, 50,

52, 53

N/C

–

No Connect

Do not connect these pins

Power Drive

Out

7

8

9

PUMP

VPUMP

VSUP

Pump

Charge pump output

Charge pump supply

Power Input

Analog Input

Voltage Pump

Supply Voltage

Supply voltage to the load. This pin is to be connected to the common Drains of the

external high-side FETs

33937A

4

NXP Semiconductors

Table 2. 33937A pin definitions (continued)

Pin name

Pin function

Formal name

Definition

Totem Pole output of Phase B comparator. This output is low when the voltage on

10

PHASEB

Digital Output

Phase B

PB_HS_S (Source of high-side FET) is less than 50% of V

SUP

Totem Pole output of Phase C comparator. This output is low when the voltage on

PC_HS_S (Source of high-side FET) is less than 50% of V

11

PHASEC

Digital Output

Phase C

SUP

12

13

PA_HS

PA_LS

Digital Input

Phase A High-side

Phase A Low-side

Active low input logic signal enables the high-side driver for Phase A

Active high input logic signal enables the low-side driver for Phase A

Analog

Output

14

VDD

VDD Regulator

VDD regulator output capacitor connection.

15

16

17

18

19

20

21

22

23

PB_HS

PB_LS

INT

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Phase B High-side

Phase B Low-side

Interrupt

Active low input logic signal enables the high-side driver for Phase B

Active high input logic signal enables the low-side driver for Phase B

Interrupt pin output

CS

Chip Select

Chip Select input. It frames SPI commands and enables SPI port

Input data for SPI port. Clocked on the falling edge of SCLK, MSB first

Clock for SPI port and typically is 3.0 MHz

SI

Serial In

SCLK

SO

Serial Clock

Serial Out

Output data for SPI port. Tri-state until CS becomes low

Active high input logic signal enables the low-side driver for Phase C

Active low input logic signal enables the high-side driver for Phase C

PC_LS

PC_HS

Phase C Low-side

Phase C High-side

Analog

Output

24

AMP_OUT

Amplifier Output

Output of the current-sensing amplifier

25

26

AMP_N

AMP_P

OC_OUT

OC_TH

VSS

Analog Input

Digital Output

Amplifier Invert

Amplifier Non-Invert

Overcurrent Out

Inverting input of the current-sensing amplifier

Non-inverting input of the current-sensing amplifier

Totem pole digital output of the overcurrent comparator

27

28

Analog Input Overcurrent Threshold Threshold of the overcurrent detector

29

Ground

Voltage Source Supply Ground reference for logic interface and power supplies

30, 31

GND

Ground

Substrate and ESD reference, connect to VSS

VLS Regulator connection for additional output capacitor, providing low-

impedance supply source for low-side gate drive

Analog

Output

VLS Regulator Output

Capacitor

32

34

35

36

VLS_CAP

PC_LS_S

Phase C Low-side

Source

Power Input

Source connection for Phase C low-side FET

Gate drive output for Phase C low-side

Phase C Low-side

Gate Drive

PC_LS_G Power Output

PC_HS_S Power Input

Phase C High-side

Source

Source connection for Phase C high-side FET

Phase C High-side

Gate Drive

37

38

39

PC_HS_G Power Output

PC_BOOT Analog Input

Gate Drive for output Phase C high-side FET

Bootstrap capacitor for Phase C

Phase C Bootstrap

Phase B Low-side

Source

PB_LS_S

PB_LS_G Power Output

PB_HS_S Power Input

PB_HS_G Power Output

Power Input

Source connection for Phase B low-side FET

Phase B Low-side

Gate Drive

40

41

Gate Drive for output Phase B low-side

Phase B High-side

Source

Source connection for Phase B high-side FET

Phase B High-side

Gate Drive

42

43

44

Gate Drive for output Phase B high-side

Bootstrap capacitor for Phase B

PB_BOOT

PA_LS_S

Analog Input

Power Input

Phase B Bootstrap

Phase A Low-side

Source

Source connection for Phase A low-side FET

33937A

NXP Semiconductors

5

Table 2. 33937A pin definitions (continued)

Pin name

PA_LS_G Power Output

PA_HS_S Power Input

PA_HS_G Power Output

Pin function

Formal name

Definition

Gate Drive for output Phase A low-side

Phase A Low-side

Gate Drive

45

Phase A High-side

Source

46

Source connection for Phase A high-side FET

Phase A High-side

Gate Drive

47

48

51

54

Gate Drive for output Phase A high-side

Bootstrap capacitor for Phase A

PA_BOOT

VLS

Analog Input

Phase A Bootstrap

VLS Regulator

Voltage Power

Analog

Output

VLS regulator output. Power supply for the gate drives

Power supply input for gate drives

VPWR

Power Input

Device will perform as specified with the exposed pad un-terminated (floating)

however, it is recommended that the exposed pad be terminated to pin 29 (VSS)

and system ground

EP

Ground

Exposed Pad

33937A

6

NXP Semiconductors

4

Electrical characteristics

4.1

Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to V_SSunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to

the device.

Symbol

Ratings

Value

Unit

Notes

Electrical ratings

VSUP Supply Voltage

V

58

-1.5 to 80

V

• Normal Operation (Steady-state)

• Transient Survival

SUP

(2)

VPWR Supply Voltage

V

58

-1.5 to 80

• Normal Operation (Steady-state)

• Transient Survival

PWR

V

Charge Pump (PUMP, VPUMP)

-0.3 to 40

-0.3 to 18

-0.3 to 7.0

V

PUMP

V

VLS Regulator Outputs (VLS VLS_CAP)

LS

,

V

Logic Supply Voltage

DD

(3)

V

Logic Output (INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT)

Logic Input Pin Voltage (EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST) 10 mA

OUT

V

IN

Amplifier Input Voltage

V

-7.0 to 7.0

-0.3 to 7.0

V

IN_A

• (Both Inputs-GND), (AMP_P - GND) or (AMP_N - GND) 6.0 mA source or sink

V

Overcurrent comparator threshold 10 mA

OC

Driver Output Voltage

V

75

16

• High-side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT)

• High-side (PA_HS_G, PB_HS_G, PC_HS_G)

• Low-side (PA_LS_G, PB_LS_G, PC_LS_G)

BOOT

(4)

(5)

V

HS_G

LS_G

Driver Voltage Transient Survival

V

-7.0 to 75.0

-7.0 to 18.0

-7.0 to 7.0

HS_G

• High-side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_S,

PC_HS_S)

• Low-side (PA_LS_G, PB_LS_G, PC_LS_G, PA_LS_S, PB_LS_S, PC_LS_S)

HS_S

LS_G

V

LS_S

ESD Voltage

• Human Body Model - HBM (All pins except for the pins listed below)

Pins: PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G,

PC_Boot, PC_HS_S, PC_HS_G, VPWR

±2000

±1000

(6)

V

ESD

• Charge Device Model - CDM

• Corner pins

• All other pins

±750

±300

Notes

2.

The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80 V.

3.

Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range.

This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account.

4.

5.

Actual operational limitations may differ from survivability limits. The V - V

differential and the V

- V

differential must be greater

HS_S

LS

LS_S

BOOT

than 3.0 V to insure the output gate drive will maintain a commanded OFF condition on the output.

ESD testing is performed in accordance with the Human Body Model (HBM) (C = 100 pF, R

6.

= 1500 ) and the Charge Device Model

ZAP

(CDM), Robotic (C

= 4.0 pF).

ZAP

33937A

NXP Semiconductors

7

Table 3. Maximum ratings (continued)

All voltages are with respect to V_SSunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to

the device.

Symbol

Ratings

Value

Unit

Notes

Thermal ratings

T

Storage Temperature

-55 to +150

-40 to +150

°C

STG

T

Operating Junction Temperature

J

Thermal Resistance

• Junction-to-Case

(7)

(8)

R

3.0

°C/W

°C

JC

T

Soldering Temperature

Note 9

SOLDER

Notes

7.

Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating mode, the

heat transfer characteristics of the board and layout and the operating voltage. See Figure 24 and Figure 25 for examples of power dissipation

profiles of two common configurations. Operation above the maximum operating junction temperature will result in a reduction in reliability leading

to malfunction or permanent damage to the device.

8.

9.

Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes and enter the core ID) to view all

orderable parts, and review parametrics.

33937A

8

NXP Semiconductors

4.2

Static electrical characteristics

Table 4. Static electrical characteristics

Characteristics noted under conditions 8.0 V  V_PWR= V_SUP 40 V-40 C  T_A 135 C, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Power inputs

(10)

V

VPWR Supply Voltage Startup Threshold

–

6.0

8.0

V

PWR_ST

VSUP Supply Current, V

ENABLE = 5.0 V

= V

= 40 V, RST and

SUP

PWR

I

mA

SUP

–

1.0

–

10

• No output loads on Gate Drive Pins, No PWM

• No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle

VPWR Supply Current, V

ENABLE = 5.0 V

= V

= 40 V, RST and

SUP

PWR

I

mA

PWR_ON

• No output loads on Gate Drive Pins, No PWM, Outputs initialized

• Output Loads = 620 nC per FET, 20 kHz PWM

–

11

–

20

95

(11)

Sleep State Supply Current, RST = 0 V

• V

= 40 V

I

–

14

56

30

100

μA

V

SUP

I

PWR

Sleep State Output Gate Voltage

• IG < 100 μA

V

–

1.3

GATESS

Trickle Charge Pump (Bootstrap Voltage)

(15)

(12)

V

22

–

28

–

32

V

Boot

• V

= 14 V

SUP

V

Bootstrap Diode Forward Voltage at 10 mA

VDD internal regulator

1.2

F

V

Output Voltage, V

= 8 to 40 V, C = 0.47 μF

DD

PWR

V

4.5

–

5.5

12

V

DD

• External Load I

= 0 to 1.0 mA

DD_EXT

I

Internal V Supply Current, V = 5.5 V, No External Load

mA

DD

VLS regulator

I

Peak Output Current, V

= 16 V, V = 10 V

350

13.5

7.5

600

15

800

17

mA

V

PEAK

PWR

LS

Linear Regulator Output Voltage, I

2.0 V

= 0 to 60 mA, V

> V

+

(13)

(14)

VLS

PWR

LS

V

LS

V

VLS Disable Threshold

8.0

8.5

V

THVLS

Notes

10.

Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. V

must exceed this threshold in

PWR

order for the Charge Pump and V regulator to startup and drive V

to > 8.0 V. Once V

exceeds 8.0 V, the circuits will continue to operate

PWR

DD

PWR

even if system voltage drops below 6.0 V.

11.

12.

This parameter is guaranteed by design. It is not production tested.

Minimum external capacitor for stable V operation is 0.47 μF.

DD

13.

14.

Recommended external capacitor for the V regulator is 2.2 μF low ESR at each pin VLS and VLS_CAP.

LS

When V is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery requires initialization when V rises above

LS

this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients on V

See Figure 11 for typical capability to maintain gate voltage with a 5.0 μA load.

.

LS

15.

33937A

NXP Semiconductors

9

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V_SUP 40 V-40 C  T_A 135 C, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Charge pump

Charge Pump

R

V

–

250

6.0

5.0

500

10

9.4

900



mV

• High-side Switch On Resistance

• Low-side Switch On Resistance

• Regulation Threshold Difference

DS(on)_HS

DS(on)_LS

(16), (18)

(17), (18)

THREG

Charge Pump Output Voltage

• I

= 40 mA, 6.0 V < V

< 8.0 V

SYS

V

8.5

12

9.5

–

V

OUT

CP

= 40 mA, V

> = 8.0 V

SYS

Gate drive

High-side Driver On Resistance (Sourcing)

• V

= V

= 16 V, -40 C  T  25 C

R

–

6.0

8.5



PWR

SUP

A

DS(on)_H_SRC

= 16 V, 25 C T  135 C

A

High-side Driver On Resistance (Sinking)

• V = V = 16 V

R

–

3.0

0.5



DS(on)_H_SINK

PWR

SUP

(18), (19)

I

High-side Current Injection Allowed Without Malfunction

Low-side Driver On Resistance (Sourcing)

A

HS_INJ

• V

= V

= 16 V, -40 C  T  25 C

R

–

6.0

8.5



PWR

SUP

A

DS(on)_L_SRC

= 16 V, 25 C T  135 C

A

Low-side Driver On-Resistance (Sinking)

• V = V = 16 V

–

3.0

0.5





DS(on)_L_SINK

PWR

SUP

(18), (19)

(20)

I

Low-side Current Injection Allowed Without Malfunction

Gate Source Voltage, V = V = 40 V

LS_INJ

PWR

SUP

• High-side, I

• Low-side, I

= 0

V

13

14.8

15.4

16.5

17

V

GATE

GS_H

GS_L

Reverse High-side Gate Holding Voltage

Gate Output Holding Current = 2.0 μA

Gate Output Holding Current = 5.0 μA, V

–

10

–

15

(21)

V

HS_G_HOLD

<26 V

<40 V

SUP

Notes

16.

When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled.

V is the system voltage on the input to the charge pump. Recommended external components: 1.0 μF MLC, MUR 120 diode.

SYS

17.

18.

19.

This parameter is a design characteristic, not production tested.

Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of approximately 1.0 μs

after an output switch transition. 1.0 μs is sufficient for all intended applications of this IC.

20.

21.

If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not recover

completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap and the VLS

capacitors.

High-side Gate Holding voltage is the voltage between the Gate and Source of the high-side FET when held in an on condition. The trickle charge

pump supplies bias and holding current for the High-side FET gate driver and output to maintain voltages after bootstrap events. See Figure 11

for typical 100% high-side gate voltage with a 5.0 μA load. This parameter is a design characteristic, not production tested.

33937A

10

NXP Semiconductors

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V_SUP 40 V-40 C  T_A 135 C, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

(23)

Overcurrent comparator

V

Common Mode Input Range

2.0

-50

50

–

V

-0.02

DD

V

CM

V

Input Offset Voltage

50

mV

OS_OC

(22)

V

Overcurrent Comparator Threshold Hysteresis

Output Voltage

300

OC_HYST

• High Level at I = -500 μA

V

0.85 V

–

V

0.5

V

OH

DD

–

• Low Level at I = 500 μA

OL

Hold off circuit

Hold Off Current (At Each GATE Pin)

(24)

I

10

–

300

μA

HOLD

• 3.0 V < V

< 40 V, V

= 1.0 V

GATE

SUP

Phase comparator

V

High Level Input Voltage Threshold

Low Level Input Voltage Threshold

0.5 V

0.3 V

–

0.65 V

0.45 V

V

IH_TH

SUP

V

IL_TH

SUP

V

High Level Output Voltage at I = -500 μA

0.85 V

–

V

DD

V

OH

DD

V

Low Level Output Voltage at I = 500 μA

–

0.5

–

V

OL

(22), (27)

(25)

R

High-side Source Input Resistance

40

k

IN

Desaturation detector

Desaturation Detector Threshold

Current sense amplifier

V

1.2

1.4

1.6

V

DES_TH

R

Recommended External Series Resistor (See Figure 9)

–

1.0

–

kW

S

Recommended External Feedback Resistor (See Figure 9)

• Limited by the Output Voltage Dynamic Range

(28)

R

FB

5.0

15

Maximum Input Differential Voltage (See Figure 9)

V

mV

V

ID

• V = V

- V

AMP_N

-800

-0.5

–

+800

3.0

ID

AMP_P

(22), (26)

V

Input Common Mode Range

Input Offset Voltage

CM

V

mV

μV/°C

nA

OS

• R = 1.0 k, V

= 0.0 V

-15

–

+15

–

S

CM

(22)

V /T

Input Offset Voltage Drift

Input Bias Current

-10

OS

I

b

• V

= 2.0 V

-200

–

+200

CM

Notes

22.

This parameter is a design characteristic, not production tested.

As long as one input is in the common mode range there is no phase inversion on the output.

The hold off circuit is designed to operate over the full operating range of V . The specification indicates the conditions used in production test.

23.

24.

SUP

Hold off is activated at V

or V

THVLS.

POR

25.

26.

Desaturation is measured as the voltage drop below V

FET. See Figure 5.

, thus the threshold is compared to the drain-source voltage of the external High-side

SUP

As long as one input is within V

the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input will not

CM

cause a phase inversion on the output.

27.

28.

Input resistance is impedance from the high-side source and is referenced to V . Approximate tolerance is 20

SS

The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10.

33937A

NXP Semiconductors

11

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V_SUP 40 V-40 C  T_A 135 C, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Current sense amplifier (continued)

Input Offset Current

I

nA

OS

• I = I

- I

AMP_P AMP_N

-80

–

+80

–

OS

(29)

I /T

Input Offset Current Drift

Output Voltage

40

pA/°C

OS

• High Level with R

= 10 k to V

V

-0.2

–

V

0.2

V

LOAD

SS

OH

DD

• Low Level with R

= 10 k to V

OL

LOAD

DD

R

Differential Input Resistance

1.0

5.0

–

M

mA

pF

I

Output Short-circuit Current

SC

(29), (30)

C

Common Mode Input Capacitance at 10 kHz

Common Mode Rejection Ratio at DC

10

I

CMRR

dB

%

• CMRR = 20*Log ((V

/V

_

) * (V

_

/V

_

))

60

–

80

78

–

OUT_DIFF IN DIFF

IN CM OUT CM

(29), (30)

A

Large Signal Open Loop Voltage Gain (DC)

Nonlinearity

OL

NL

• RL = 1.0 k, C = 500 pF, 0.3 < V < 4.8 V, Gain = 5.0 to 15

-1.0

–

+1.0

L

O

Notes

29.

This parameter is a design characteristic, not production tested.

Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.

30.

33937A

12

NXP Semiconductors

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V_SUP 40 V-40 C  T_A 135 C, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Supervisory and control circuits

Logic Inputs (Px_LS, Px_HS, EN1, EN2)

• High Level Input Voltage Threshold

• Low Level Input Voltage Threshold

(32)

V

2.1

–

0.9

V

IH

IL

Logic Inputs (SI, SCLK, CS)

(31), (32)

(31)

V

2.1

–

0.9

• High Level Input Voltage Threshold

• Low Level Input Voltage Threshold

IH

V

IL

Input Logic Threshold Hysteresis

V

100

8.0

10

250

–

450

18

mV

μA

IHYS

• Inputs Px_LS, SI, SCLK, CS, Px_HS, EN1, EN2

Input Pull-down Current, (Px_LS, SI, SCLK, EN1, EN2)

I

INPD

INPU

• 0.3 V  V V_DD

DD

IN

Input Pull-up Current, (CS, Px_HS)

(33)

I

–

25

• 0  V 0.7V

IN

DD

Input Capacitance

(31)

(34)

C

–

15

–

pF

V

IN

• 0.0 V  V 5.5 V

IN

V

RST Threshold

1.0

40

3.4

2.1

85

4.5

–

TH_RST

RST Pull-down Resistance

R

60

4.0

–

kW

V

RST

• 0.3 V  V V

DD

IN

V

Power-OFF RST Threshold, (V Falling)

POR

DD

SO High Level Output Voltage

V

0.9 V

–

V

SOH

DD

• I = 1.0 mA

OH

SO Low Level Output Voltage

V

–

0.1 V

V

μA

pF

V

SOL

DD

• I = 1.0 mA

OL

SO Tri-state Leakage Current

I

SO_LEAK_T

• CS = 0.7 V , 0.3 V  V  0.7 V

DD

-1.0

–

15

–

1.0

–

DD

SO

SO Tri-state Capacitance

(31), (35)

C

SO_T

• 0.0 V  V 5.5 V

–

0.85 V

–

IN

INT High Level Output Voltage

V

OH

• I = -500 μA

V

OH

DD

INT Low Level Output Voltage

V

OL

• I = 500 μA

–

0.5

OL

Thermal warning

(31), (36)

(31)

T

Thermal Warning Temperature

Thermal Hysteresis

150

8.0

170

10

185

12

°C

WARN

T

HYST

Notes

31.

This parameter is guaranteed by design, not production tested.

Logic threshold voltages derived relative to a 3.3 V 10% system.

32.

33.

Pull-up circuits will not allow back biasing of V

DD.

34.

There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the reset from

the internal logic.

35.

36.

This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested.

The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to generate an

interrupt when overtemperature is detected, and the status bit will always indicate if any of the three individual Thermal Warning circuits in the IC

sense a fault.

33937A

NXP Semiconductors

13

4.3

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

Characteristics noted under conditions 8.0 V  V_PWR= V

 40 V, -40 C  T_A 135 C, unless otherwise noted. Typical values noted

SUP

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Internal regulators

V

Power-up Time (Until INT High)

DD

(37), (39)

(38), (39)

t

–

2.0

ms

PU_VDD

• 8.0 V V

PWR

VLS Power-up Time

• 16 V V

t

PU_VLS

PWR

Charge pump

F

Charge Pump Oscillator Frequency

Charge Pump Slew Rate

90

–

125

100

190

–

kHz

OSC

(40)

SR

V/μs

CP

Gate drive

High-side Turn On Time

(41)

(42)

(41)

(42)

(41)

(42)

(41)

(42)

t

–

130

–

20

265

20

35

386

35

ns

• Transition Time from 1.0 V to 10 V, Load: C = 500 pF, Rg = 0,

(Figure 7)

ONH

High-side Turn On Delay

t

D_ONH

• Delay from Command to 1.0 V, (Figure 7)

High-side Turn Off Time

t

• Transition Time from 10 V to 1.0 V, Load: C = 500 pF, Rg = 0,

(Figure 8)

OFFH

High-side Turn Off Delay

t

130

–

265

20

386

35

D_OFFH

• Delay from Command to 10 V, (Figure 8)

Low-side Turn On Time

t

• Transition Time from 1.0 V to 10 V, Load: C = 500 pF, Rg = 0,

(Figure 7)

ONL

Low-side Turn On Delay

t

130

–

265

20

386

35

D_ONL

• Delay from Command to 1.0 V, (Figure 7)

Low-side Turn Off Time

t

• Transition Time from 10 V to 1.0 V, Load: C = 500 pF, Rg = 0,

(Figure 8)

OFFL

Low-side Turn Off Delay

t

130

265

386

D_OFFL

• Delay from Command to 10 V, (Figure 8)

Notes

37.

38.

The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V

.

DD

The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and VLS_CAP.

This delay includes the expected time for V to rise.

DD

39.

40.

This specification is based on capacitance of 0.47 μF on VDD, 2.2 μF on VLS and 2.2 μF on VLS_CAP.

The charge pump operating at 12 V V

, 1.0 F pump capacitor, MUR120 diodes and 47 μF filter capacitor.

SYS

41.

42.

This parameter is guaranteed by characterization, not production tested.

These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes one clock

period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and output driver propagation

delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision block. Synchronization time accounts

for up to one clock period of variation. See Figure 6.

33937A

14

NXP Semiconductors

Table 5. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V

 40 V, -40 C  T_A 135 C, unless otherwise noted. Typical values noted

SUP

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Gate drive (continued)

(43)

(44)

t

Same Phase Command Delay Match

-20

8.0

0.0

–

0.0

–

+20

30

ns

μs

%

s

D_DIFF

t

Thermal Filter Duration

Duty Cycle

DUR

(45), (46)

(47)

t

–

96

DC

100% Duty Cycle Duration

Maximum Programmable Deadtime

–

Unlimited

19.6

t

10.2

15

μs

MAX

Overcurrent comparator

t

Overcurrent Protection Filter Time

0.9

10

–

3.5

μs

ns

OC

Rise Time (OC_OUT)

• 10% - 90%

t

240

ROC

• C = 100 pF

L

Fall Time (OC_OUT)

• 90% - 10%

t

10

–

200

ns

FOC

• C = 100 pF

L

Desaturation detector and phase comparator

Phase Comparator Propagation Delay Time to 50% of V

;

DD

C

100 pF

L

t

–

200

350

R

• Rising Edge Delay

• Falling Edge Delay

t

F

Phase Comparator Match (Prop Delay Mismatch of Three Phases)

(45)

(48)

(45)

t

–

100

9.1

ns

μs

ns

MATCH

• C = 100 pF

L

t

Desaturation and Phase Error Blanking Time

4.7

640

7.1

937

BLANK

Desaturation Filter Time (Filter Time is digital)

• Fault Must be Present for This Time to Trigger

t

1231

FILT

Current sense amplifier

Output Settle Time to 99%

• RL = 1.0 k, C = 500 pF, 0.3 V < V < 4.8 V, Gain = 5 to 15

t

SETTLE

(45), (49)

–

1.0

2.0

μs

L

O

Notes

43.

The maximum separation or overlap of the High and Low-side gate drives, due to propagation delays when commanding one ON and the other

OFF simultaneously, is guaranteed by design.

44.

45.

46.

The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.

This parameter is guaranteed by design, not production tested.

As duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime, propagation delays,

switching times and charge time of the bootstrap capacitor (for the High-side FET). 0% is available by definition (FET always OFF) and unlimited

ON (100%) is possible as long as gate charge maintenance current is within the trickle charge pump capacity.

A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock cycle

duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this value limits at this

value.

47.

48.

49.

Blanking time, t

, is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to system noise

BLANK

during the switching event.

Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.

33937A

NXP Semiconductors

15

Table 5. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V

 40 V, -40 C  T_A 135 C, unless otherwise noted. Typical values noted

SUP

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Current sense amplifier (continued)

Output Rise Time to 90%

(51)

t

–

1.0

μs

IS_RISE

• RL = 1.0 k, C = 500 pF, 0.3 V < V < 4.8 V, Gain = 5.0 to 15

L

O

Output Fall Time to 10%

t

IS_FALL

• RL = 1.0 kC = 500 pF, 0.3 V < V < 4.8 V, Gain = 5.0 to 15

L

O

Slew Rate at Gain = 5.0

(5)

(50)

SR

5.0

–

V/μs

°

• RL = 1.0 k, C = 20 pF

L

f

Phase Margin at Gain = 5.0

Unity Gain Bandwidth

30

20

M

G

–

MHz

BW

• RL = 1.0 k, C = 100 pF

L

Bandwidth at Gain = 15

(50)

BW

MHz

dB

G

• R = 1.0 k, C = 50 pF

2.0

–

L

Common Mode Rejection (CMR) with V

IN

• V

= 400 mV*sin(2**freq*t)

= 0.0 V, RS = 1.0 k

IN_CM

_

IN DIF

• R = 15 k, V

= 0.0 V

REFIN

FB

(50)

CMR

CMR = 20*Log(V

/V

_

)

OUT IN CM

50

40

30

–

• Freq = 100 kHz

• Freq = 1.0 MHz

• Freq = 10 MHz

Supervisory and control circuits

t

EN1 and EN2 Propagation Delay

INT Rise Time CL = 100 pF

INT Fall Time CL = 100 pF

INT Propagation Time

–

10

–

280

250

200

250

1.25

ns

μs

PROP

t

RINT

t

FINT

t

PROPINT

(50),(52)

t

RST Transition Time (Rise and Fall)

–

TRRST

Notes

50.

This parameter is guaranteed by design, not production tested.

Rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage.

t is given as a design guideline. The bounds for this specification are VPWR  58 V, total capacitance on VLS > 1.0 μF.

TRRST

51.

52.

33937A

16

NXP Semiconductors

Table 5. Dynamic electrical characteristics (continued)

Characteristics noted under conditions 8.0 V  V_PWR= V

 40 V, -40 C  T_A 135 C, unless otherwise noted. Typical values noted

SUP

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

SPI interface timing

f

Maximum Frequency of SPI Operation

–

13

-5.0

100

25

–

4.0

25

5.0

–

MHz

%

OP

f

Internal Time Base

17

–

TB

(53)

TC

Internal Time Base drift from value at 25 C

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)

SI to Falling Edge of SCLK (Required Setup Time)

Falling Edge of SCLK to SI (Required Setup Time)

SI, CS, SCLK Signal Rise Time

TB

t

–

ns

LEAD

(53)

t

–

ns

LAG

(53)

t

–

ns

SISU

(53)

t

–

ns

SIHOLD

(53), (54)

(53), (55)

(53), (56)

(53), (57)

(53)

t

5.0

55

100

80

–

ns

RSI

t

SI, CS, SCLK Signal Fall Time

–

ns

FSI

t

Time from Falling Edge of CS to SO Low-impedance

Time from Rising Edge of CS to SO High-impedance

Time from Rising Edge of SCLK to SO Data Valid

Time from Rising Edge of CS to Falling Edge of the next CS

–

100

125

–

ns

SOEN

t

–

ns

SODIS

t

–

ns

VALID

t

200

ns

DT

Notes

53.

This parameter is guaranteed by design, not production tested.

54.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

Time required for valid output status data to be available on SO pin.

55.

56.

Time required for output states data to be terminated at SO pin.

57.

Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

4.4

Timing diagrams

t_LAG

t_SISUt_SIHOLD

t_SOEN

t_SODIS

Figure 4. SPI interface timing

33937A

NXP Semiconductors

17

P _HS

X

DESATURATION

FAULT

P _LS

X

FROM DELAY

TIMER

Figure 5. Desaturation blanking and filtering detail

B

A

MUX

OUT

STATE

MACHINE

P _HS

X

D

Q

D

Q

D

Q

P _HS_G

CLK

X

DEADTIME

CONTROL

P _HS_S

X

P _LS

X

ST

D

Q

D

Q

1

PULSE

CLK

P _LS_G

X

Q

OUT

A

B

MUX

EN1

EN2

RST

Figure 6. Deadtime control delays

Figure 7. Driver turn-on time and turn-on delay

33937A

18

NXP Semiconductors

Figure 8. Driver turn-off time and turn-off delay

-400mV to + 400mV

0V

0μS - 0.5μS 0.5μS - 50μS

0.5μS - 50μS

Figure 9. Current amplifier and input waveform (V_INvoltage across R_SENSE

)

33937A

NXP Semiconductors

19

Phase

Gain

Figure 10. Typical amplifier open-loop gain and phase vs. frequency

TypicalꢀHighꢀSideꢀ100%ꢀOnꢀGateꢀVoltageꢀwithꢀ5PAꢀGateꢀLoad

16

14

12

10

8

V_SUP=ꢀ40V

V_SUP=ꢀ24V

V_SUP=ꢀ14V

V_SUP=ꢀ9V

6

4

2

0

Ͳ50

Ͳ30

Ͳ10

10

30

50

70

90

110

130

150

Temperatureꢀ(°C)

Figure 11. Typical high-side 100% on gate voltage with 5.0 μA gate load

33937A

20

NXP Semiconductors

5

Functional descriptions

5.1

Introduction

The 33937A provides an interface between an MCU and the large FETs used to drive three phase loads. A typical load FET may have

an on resistance of 4.0 m or less and could require a gate charge of over 400 nC to fully turn on. The IC can operate in automotive 12 V

to 42 V environments.

Because there are so many methods of controlling three phase systems, the IC enforces few constraints on driving the FETs. It does

provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both FETs in a phase are not simultaneously

enabled. A SPI port is used to configure the IC modes.

5.2

Functional pin description

5.2.1 Phase A (PHASEA)

This pin is the totem pole output of the Phase A comparator. This output is low when the voltage on Phase A high-side source (source of

the high-side load FET) is less than 50 percent of V_SUP

.

5.2.2 Power ground (PGND)

This pin is power ground for the charge pump. It should be connected to VSS, however routing to a single point ground on the PCB may

help to isolate charge pump noise.

5.2.3 Enable 1 and enable 2 (EN1, EN2)

Both of these logic signal inputs must be high to enable any gate drive output. When either or both are low, the internal logic (SPI port,

etc.) still functions normally, but all gate drives are forced off (external power FET gates pulled low). The signal is asynchronous.

When EN1 and EN2 return high to enable the outputs, each LS driver must be pulsed ON before the corresponding HS driver can be

commanded ON. This ensures that the bootstrap capacitors are charged. See 7.3, Initialization requirements on page 41.

5.2.4 Reset (RST)

When the reset pin is low the integrated circuit (IC) is in a low power state. In this mode, all outputs are disabled, internal bias circuits are

turned off, and a small pull-down current is applied to the output gate drives. The internal logic will be reset within 77 ns of RESET going

low. When RST is low, the IC consumes minimal current.

5.2.5 Charge pump out (PUMP)

This pin is the switching node of the charge pump circuit. The output of the internal charge pump support circuit. When the charge pump

is used, it is connected to the external pumping capacitor. This pin may be left floating if the charge pump is not required.

5.2.6 Charge pump input (VPUMP)

This pin is the input supply for the charge pump circuit. When the charge pump is required, this pin should be connected to a polarity

protected supply. This input should never be connected to a supply greater than 40 V. If the charge pump is not required this pin may be

left floating.

5.2.7 VSUP input (VSUP)

The supply voltage pin should be connected to the common connection of the high-side FETs. It is the reference bias for the Phase

Comparators and Desaturation Comparator. It is also used to provide power to the internal steady state trickle charge pump and to

energize the hold off circuit.

33937A

NXP Semiconductors

21

5.2.8 Phase B (PHASEB)

This pin is the totem pole output of the Phase B comparator. This output is low when the voltage on Phase B high-side source (source of

the high-side load FET) is less than 50 percent of V_SUP

.

5.2.9 Phase C (PHASEC)

This pin is the totem pole output of the Phase C comparator. This output is low when the voltage on Phase C high-side source (source of

the high-side load FET) is less than 50 percent of V_SUP

.

5.2.10 Phase A high-side input (PA_HS)

This input logic signal pin enables the high-side driver for Phase A. The signal is active low, and is pulled up by an internal current source.

5.2.11 Phase A low-side input (PA_LS)

This input logic signal pin enables the low-side driver for Phase A. The signal is active high, and is pulled down by an internal current sink.

5.2.12 VDD Voltage Regulator (VDD)

VDD is an internally generated 5.0 V supply. The internal regulator provides continuous power to the IC and is a supply reference for the

SPI port. A 0.47 μF (min) decoupling capacitor must be connected to this pin. This regulator is intended for internal IC use and can supply

only a small (1.0 mA) external load current. A power-on-reset (POR) circuit monitors this pin and until the voltage rises above the

threshold, the internal logic will be reset; driver outputs are tri-stated and SPI communication is disabled. The VDD regulator can be

disabled by asserting the RST signal low. The VDD regulator is powered from the VPWR pin.

5.2.13 Phase B high-side control input (PB_HS)

This pin is the input logic signal, enabling the high-side driver for Phase B. The signal is active low, and is pulled up by an internal current

source.

5.2.14 Phase B low-side input (PB_LS)

This pin is the input logic signal, enabling the low-side driver for Phase B. The signal is active high, and is pulled down by an internal

current sink.

5.2.15 Interrupt (INT)

The Interrupt pin is a totem pole logic output. When a fault is detected, this pin pulls high until it is cleared by executing the Clear Interrupt

command via the SPI port. The faults capable of causing an interrupt can be masked via the MASK0 and MASK1 SPI registers to

customize the response.

5.2.16 Chip select (CS)

Chip select is a logic input that frames the SPI commands and enables the SPI port. This signal is active low, and is pulled up by an internal

current source.

5.2.17 Serial in (SI)

The Serial In pin is used to input data to the SPI port. Clocked on the falling edge of SCLK, it is the most significant bit (MSB) first. This

pin is pulled down by an internal current sink.

33937A

22

NXP Semiconductors

5.2.18 Serial clock (SCLK)

This logic input is the clock is used for the SPI port. The SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled down by an internal

current sink.

5.2.19 Serial out (SO)

Output data for the SPI port streams from this pin. It is tri-stated until CS is low. New data appears on rising edges of SCLK in preparation

for latching by the falling edge of SCLK on the master.

5.2.20 Phase C low-side input (PC_LS)

This input logic pin enables the low-side driver for Phase C. This pin is an active high, and is pulled down by an internal current sink.

5.2.21 Phase C high-side input (PC_HS)

This input logic pin enables the high-side driver for Phase C. This signal is active low, and is pulled up by an internal current source.

5.2.22 Amplifier output (AMP_OUT)

This pin is the output for the current sensing amplifier. It is also the sense input to the overcurrent comparator.

5.2.23 Amplifier inverting input (AMP_N)

The inverting input to the current sensing amplifier.

5.2.24 Amplifier non-inverting input (AMP_P)

The non-inverting input to the current sensing amplifier.

5.2.25 Overcurrent comparator output (OC_OUT)

The overcurrent comparator output is a totem pole logic level output. A logic high indicates an overcurrent condition.

5.2.26 Overcurrent comparator threshold (OC_TH)

This input sets the threshold level of the overcurrent comparator.

5.2.27 Voltage source supply (VSS)

VSS is the ground reference for the logic interface and power supplies.

5.2.28 Ground (GND0, GND1)

These two pins are connected internally to VSS by a 1.0  resistor. They provide device substrate connections and also the primary return

path for ESD protection.

5.2.29 VLS regulator capacitor (VLS_CAP)

This connection is for a capacitor which provides a low-impedance for switching currents on the gate drive. A low ESR decoupling

capacitor, capable of sourcing the pulsed drive currents must be connected between this pin and VSS. This is the same DC node as VLS,

but it is physically placed on the opposite end of the IC to minimize the source impedance to the gate drive circuits.

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5.2.30 Phase C low-side source (PC_LS_S)

The phase C low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting

this node directly to the source of the low-side FET for phase C.

5.2.31 Phase C low-side gate (PC_LS_G)

This is the gate drive for the Phase C low-side output FET. It provides high-current through a low-impedance to turn on and off the low-

side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the

external FET. This output has also been designed to resist the influence of negative currents.

5.2.32 Phase C high-side source (PC_HS_S)

The source connection for the Phase C high-side output FET is the reference voltage for the gate drive on the high-side FET and also the

low-voltage end of the bootstrap capacitor.

5.2.33 Phase C high-side gate (PC_HS_G)

This is the gate drive for the Phase C high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate

voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not

overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the

influence of negative currents.

5.2.34 Phase C bootstrap (PC_BOOT)

This is the bootstrap capacitor connection for Phase C. A capacitor connected between PC_HS_S and this pin provides the gate voltage

and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage

across this capacitor is limited to about 15 V.

5.2.35 Phase B low-side source (PB_LS_S)

The Phase B low-side source is the pin used to return the gate currents from the Low-side FET. Best performance is realized by

connecting this node directly to the source of the low-side FET for Phase B.

5.2.36 Phase B low-side gate (PC_LS_G)

This is the gate drive for the Phase B low-side output FET. It provides high-current through a low-impedance to turn on and off the low-

side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the

external FET. This output has also been designed to resist the influence of negative currents.

5.2.37 Phase B high-side source (PB_HS_S)

The source connection for the Phase B high-side output FET is the reference voltage for the gate drive on the high-side FET and also the

low-voltage end of the bootstrap capacitor.

5.2.38 Phase B high-side gate (PB_HS_G)

This is the gate drive for the Phase B high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate

voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not

overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the

influence of negative currents.

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5.2.39 Phase B bootstrap (PB_BOOT)

This is the bootstrap capacitor connection for phase B. A capacitor connected between PC_HS_S and this pin provides the gate voltage

and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage

across this capacitor is limited to about 15 V.

5.2.40 PHASE A low-side source (PA_LS_S)

The Phase A low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting

this node directly to the source of the low-side FET for phase A.

5.2.41 Phase A low-side gate (PA_LS_G)

This is the gate drive for the Phase A low-side output FET. It provides high-current through a low-impedance to turn on and off the low-

side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the

external FET. This output has also been designed to resist the influence of negative currents.

5.2.42 Phase A high-side source (PA_HS_S)

The source connection for the Phase A high-side output FET is the reference voltage for the gate drive on the high-side FET and also the

low-voltage end of the bootstrap capacitor.

5.2.43 Phase A high-side gate (PA_HS_G)

This is the gate drive for the Phase A high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate

voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not

overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the

influence of negative currents.

5.2.44 Phase A bootstrap (PA_BOOT)

This is the bootstrap capacitor connection for phase A. A capacitor connected between PC_HS_S and this pin provides the gate voltage

and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage

across this capacitor is limited to about 15 V.

5.2.45 VLS regulator (VLS)

VLS is the gate drive power supply regulated at approximately 15 V. This is an internally generated supply from VPWR. It is the source

for the low-side gate drive voltage, and also the high-side bootstrap source. A low ESR decoupling capacitor, capable of sourcing the

pulsed drive currents, must be connected between this pin and VSS.

5.2.46 VPWR input (VPWR)

VPWR is the power supply input for VLS and VDD. Current flowing into this input recharges the bootstrap capacitors as well as supplying

power to the low-side gate drivers and the VDD regulator. An internal regulator regulates the actual gate voltages. This pin can be

connected to system battery voltage if power dissipation is not a concern.

5.2.47 Exposed pad (EP)

The primary function of the exposed pad is to conduct heat out of the device. This pad may be connected electrically to the substrate of

the device.The device performs as specified with the exposed pad un-terminated (floating). However, it is recommended the exposed pad

be terminated to pin 29 (VSS) and the system ground.

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6

Functional internal block description

MC33937 - Functional Block Diagram

Integrated Supply

Main Charge Pump

5V Regulator

Trickle Charge Pump

VLS Regulator

Sensing & Protection

High Side

and

Hold-off

Temperature

Current Sense

Under-voltage

De-sat

Low Side

Phase

Output

Pre-drivers

Over-current

Logic & Control

Fault Register

Phase Control

Dead Time

Mode Control

SPI Communication

Integrated Supply

Sensing & Protection

Logic & Control

Drivers

Figure 12. Functional internal block description

All functions of the IC can be described as the following five major functional blocks:

• Logic Inputs and Interface

• Bootstrap Supply

• Low-side Drivers

• High-side Drivers

• Charge Pump

6.1

Logic inputs and interface

This section contains the SPI port, control logic, and shoot-through timers.

The IC logic inputs have Schmitt trigger inputs with hysteresis. Logic inputs are 3.0 V compatible. The logic outputs are driven from the

internal supply of approximately 5.0 V. The SPI registers and functionality is described completely in 7.2, Logic commands and registers

on page 35. SPI functionality includes the following:

• Programming of deadtime delay—This delay is adjustable in approximately 50 ns steps from 0 ns to 12 μs. Calibration of the delay,

because of internal IC variations, is performed via the SPI.

• Enabling of simultaneous operation of high-side and low-side FETs—Normally, both FETs would not be enabled simultaneously.

However, for certain applications where the load is connected between the high-side and low-side FETs, this could be advantageous.

If this mode is enabled, the blanking time delay will be disabled. A sequence of commands may be required to enable this function to

prevent inadvertent enabling. In addition, this command can only be executed once after reset to enable or disable simultaneous turn-

on.

• Setting of various operating modes of the IC and enabling of interrupt sources. The 33937A allows different operating modes to be

set and locked by an SPI command (FULLON, Desaturation Fault, Zero Deadtime). SPI commands can also determine how the various

faults are (or are not) reported.

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• Read back of internal registers. The status of the 33937A status registers can be read back by the Master (DSP or MCU).

The Px_HS and Px_LS logic inputs are edge sensitive. This means the leading edge on an input causes the complementary output to

immediately turn off and the selected one to turn on after the deadtime delay as illustrated in Figure 13. The deadtime delay timer always

starts at the time a FET is commanded off and prevents the complementary FET from being commanded on until after the deadtime has

elapsed. Commands to turn on the complementary FET after the deadtime has elapsed are executed immediately without any further

delay (see Figure 6 and Figure 13).

Figure 13. Edge sensitive logic inputs (phase A)

6.1.1 Low-side and bootstrap supply (VLS)

This is the portion of the IC providing current to recharge the bootstrap capacitors. It also supplies the peak currents required for the low-

side gate drivers. The power for the gate drive circuits is provided by VLS which is supplied from the VPWR pin. This pin can be connected

to system battery voltage and is capable of withstanding up to the full load dump voltage of the system. However, the IC only requires a

low-voltage supply on this pin, typically 13 V to 16 V. Higher voltages on this pin increases the IC power dissipation.

In 12 V systems, the supply voltage can fall as low as 6.0 V. This limits the gate voltage capable of being applied to the FETs and reduces

system performance due to the higher FET on-resistance. To allow a higher gate voltage to be supplied, the IC also incorporates a charge

pump. The switches and control circuitry are internal; the capacitors and diodes are external (see Figure 22).

6.1.2 Low-side drivers

These three drivers turn on and off the external Low-side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs

remain off in the presence of high dV/dt transients on their drains. Additionally, these output drivers isolate the other portions of the IC

from currents capable of being injected into the substrate due to rapid dV/dt transients on the FET drains.

Low-side drivers switch power from VLS to the gates of the Low-side FETs. The Low-side drivers are capable of providing a typical peak

current of 2.0 A. This gate drive current may be limited by external resistors in order to achieve a good trade-off between the efficiency

and EMC (Electro-Magnetic Compatibility) compliance of the application. the low-side driver uses high-side PMOS for turn on and low-

side isolated LDMOS for turn off. The circuit ensures the impedance of the driver remains low, even during periods of reduced current.

Current limit is blanked immediately after subsequent input state change to ensure device stays off during dV/dt transients.

6.1.3 High-side drivers

These three drivers switch the voltage across the bootstrap capacitor to the external high-side FETs. The circuits provide a low-impedance

drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their sources. Further, these output drivers

isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FETs.

The high-side drivers deliver power from their bootstrap capacitor to the gate of the external high-side FET, thus turning the high-side FET

on. The high-side driver uses a level shifter, allowing the gate of the external high-side FET to be turned off by switching to the high-side

FET source.

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The gate supply voltage for the high-side drivers is obtained from the bootstrap supply, so, a short time is required after the application of

power to the IC to charge the bootstrap capacitors. To ensure this occurrence, the internal control logic does not allow a high-side switch

to be turned on after entering the ENABLE state until the corresponding low-side switch is enabled at least once. Caution must be

exercised after a long period of inactivity of the low-side switches to verify the bootstrap capacitor is not discharged. It is charged by

activating the low-side switches for a brief period, or by attaching external bleed resistors from the HS_S pins to GND. See 7.3,

Initialization requirements on page 41.

In order to achieve a 100% duty cycle operation of the high-side external FETs, a fully integrated trickle charge pump provides the charge

necessary to maintain the external FET gates at fully enhanced levels. The trickle charge pump has limited ability to supply external

leakage paths while performing it’s primary function. The graph in Figure 11 shows the typical margin for supplying external current loads.

These limits are based on maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this

voltage differential becomes less than 3.0 V, the corresponding high-side FET most likely does not remain fully enhanced and the high-

side driver may malfunction due to insufficient bias voltage between CBOOT and HS_S.

The slew rate of the external output FET is limited by the driver output impedance, overall (external and internal) gate resistance and the

load capacitance. To ensure the low-side FET is not turned on by a large positive dV/dt on the drain of the low-side FET, the turn-on slew

rate of the high-side should be limited. If the slew rate of the high-side is limited by the gate-drain capacitance of the high-side FET, then

the displacement current injected into the low-side gate drive output is approximately the same value. Therefore, to ensure the low-side

drivers can be held off, the voltage drop across the low-side gate driver must be lower than the threshold voltage of the low-side FET (see

Figure 14).

Similarly, during large negative dV/dt, the high-side FET is able to remain off if its gate drive low-side switch, develops a voltage drop less

than the threshold voltage of the high-side FET. The gate drive low-side switch discharges the gate to the source. Additionally, during

negative dV/dt the low-side gate drive could be forced below ground. The low-side FETs must not inject detrimental substrate currents in

this condition. The occurrence of these cases depends on the polarity of the load current during switching.

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Figure 14. Positive DV/dt transient

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6.1.4 Driver fault protection

The 33937A IC integrates several protection mechanisms against various faults. The first of them is the current sense amplifier with the

overcurrent comparator. These two blocks are common for all three driver phases.

6.1.4.1

Current sense amplifier

This amplifier is usually connected as a differential amplifier (see Figure 9). It senses a current flowing through the external FETs as a

voltage across the current sense resistor R_SENSE. Since the amplifier common mode range does not extend below ground, it is necessary

to use an external reference to permit measuring both positive and negative currents. The amplifier output can be monitored directly (e.g.

by the microcontroller’s ADC) at the AMP_OUT pin, providing the means for closed loop control with the 33937A. The output voltage is

internally compared with the overcurrent comparator threshold voltage (see Figure 22).

6.1.4.2

Overcurrent comparator

The amplified voltage across R_SENSEis compared with the preset threshold value by the overcurrent comparator input. If the current sense

amplifier output voltage exceeds the threshold of the overcurrent comparator, it would change the status of its output (OC_OUT pin) and

the fault condition would be latched (see 7.2.3.2Figure 18).

The occurrence of this fault would be signaled by the return value of the Status Register 0. If the proper interrupt mask has been set, this

fault condition generates an interrupt - the INT pin asserts High. The INT is held in the High state until the fault is removed, and the

appropriate bit in the Status Register 0 is cleared by the CLINT0 command. This fault reporting technique is described in detail in 7.2,

Logic commands and registers on page 35.

6.1.4.3

Desaturation detector

The Desaturation Detector is a comparator integrated into the output driver of each phase channel. It provides an additional means to

protect against “Short-to-Ground” fault condition. A short to ground is detected by an abnormally high-voltage drop in VDS of the high-

side FET. Note that if the gate-source voltage of the high-side FET drops below saturation, the device goes into linear mode of conduction,

which can also cause a desaturation error.

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Figure 15. Short to ground detection

When switching from low-side to high-side, the high-side is commanded ON after the end of the deadtime. The deadtime period starts

when the low-side is commanded OFF. If the voltage at Px_HS_S is less than 1.4 V below V_SUPafter the blanking time (t_BLANK), a

desaturation fault is initiated. An additional 1.0 s digital filter is applied from the initiation of the desaturation fault before it is registered,

and all phase drivers are turned OFF (Px_HS_G clamped to Px_HS_S and Px_LS_G clamped to Px_LS_S). If the desaturation fault

condition clears before the filter time expires, the fault is ignored and the filter timer resets.

Valid faults are registered in the fault status register, which can be retrieved by way of the SPI. Additional SPI commands mask the INT

flag and disable an output stage shutdown, due to desaturation and phase errors. See 7.2, Logic commands and registers on page 35

for details on masking INT behavior and disabling the protective function.

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Figure 16. Short to supply detection

6.1.4.4

Phase comparator

Faults could also be detected as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the

drive conditions.

A phase error is detected by a Phase comparator. The Phase comparator compares the voltage at the Px_HS_S node with a reference

of one half the voltage at the VSUP pin. A high-side phase error (which also triggers the Desaturation Detector) occurs when the high-

side FET is commanded on, and Px_HS_S is still low at the end of the deadtime and blanking time duration. Similarly, a LS phase error

occurs when the low-side FET is commanded on, and the Px_HS_S is still high at the end of the deadtime and blanking time duration.

The Phase Error flag is the triple OR of phase errors from each phase. Each phase error is the OR of the high-side and low-side phase

errors. This flag can generate an interrupt if the appropriate mask bit is set. The INT is held in the high state until the fault is removed, and

the appropriate bit in the Status Register 0 is cleared by the CLINT1 command. This fault reporting mechanism is described in detail in

7.2, Logic commands and registers on page 35.

6.1.5 VLS undervoltage

Since VLS supplies both the gate driver circuits and the gate voltage, it is critical it maintains sufficient potential to place the power stage

FETs in saturation. Since proper operation cannot continue with insufficient levels, a low VLS condition shuts down driver operation. The

VLS undervoltage threshold is between 7.5 V and 8.5 V. When a decreasing level reaches the threshold, both the HS and the LS output

gate circuit drive the gates OFF for about 8.0 s before reducing the drive to hold off levels. Since low VLS is a condition for turning on

the Hold Off circuit, Hold Off then provides a weak pull-down on all gates. A filter timeout of about 700 ns insures noise on VLS does not

cause premature protective action.

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When VLS rises above this threshold again, the LS Gate immediately follows the level of the input. However, a short initialization sequence

must be executed to restore operation of the HS Gate. (See 7.3, Initialization requirements on page 41) Since VLS is no longer

undervoltage, the Hold Off circuit is turned off and the HS Gate is in a high-impedance state until the LS Gate responds to an input

command to turn off.

6.1.6 Hold off circuit

The IC guarantees the output FETs are turned off in the absence of V_DDor V_PWRby means of the Hold off circuit. A small current source,

generated from VSUP, typically 100 μA, is mirrored and pulls all the output gate drive pins low when V_DDis less than about 3.0 V, RST is

active (low), or when VLS is lower than the VLS_Disable threshold. A minimum of 3.0 V is required on VSUP to energize the Hold off

circuit.

6.1.7 Charge pump

The charge pump circuit provides the basic switching elements required to implement a charge pump, when combined with external

capacitors and diodes for enhanced low-voltage operation. When the 33937A is connected per the typical application using the charge

pump (see Figure 22), the regulation path for VLS includes the charge pump and a linear regulator. The regulation set point for the linear

regulator is nominally at 15.34 V. As long as VLS output voltage (VLS_OUT) is greater than the VLS analog regulator threshold (VLS_ATH

)

minus V_THREG, the charge pump is not active.

If VLS_OUT< VLS_ATH– V_THREGthe charge pump turns ON until VLS_OUT> VLS_ATH– V_THREG+ V_HYST

V_HYSTis approximately 200 mV. VLS_ATHdoes not interfere with this cycle even when there is overlap in the thresholds, due to the design

of the regulator system. The maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the

pump frequency (nominally 130 kHz), and the R_DS(on)of the pump FETs. The effective charge voltage for the pump capacitor would be

V_SYS– 2 * V_DIODE. The total charge transfer would then be C_PUMP* (V_SYS– 2*V_DIODE). Multiplying by the switch frequency gives the

theoretical current the pump can transfer: F_PUMP* C_PUMP* (V_SYS– 2*V_DIODE).

NOTE: There is also another smaller, fully integrated charge pump (Trickle Charge Pump - see Figure 2), which is used to maintain the

high-side drivers’ gate V_GSin 100 percent duty cycle modes.

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7

Functional device operation

7.1

Operational modes

7.1.1 Reset and enable

The 33937A has three power modes of operation described in Table 6. There are three global control inputs (RST, EN1, EN2), which

together with the status of VDD, VLS, and DESAT/PHASE faults control the behavior of the IC.

The operating status of the IC can be described by the following five modes:

• Sleep Mode - When RST is low, the IC is in Sleep mode. The current consumption of the IC is at minimum.

• Standby Mode - The RST input is high while one of the Enable inputs is low. The IC is fully biased up and operating, all the external

FETs are actively turned off by both high-side and low-side gate drives. The IC is ready to enter the Enable mode.

• Initialization Mode - When EN1, EN2, and RST all go high, the device enters the Initialization mode. Toggling the LS and then the HS

initializes the driver and normal operation in the Enable mode begins. (See 7.3, Initialization requirements on page 41)

• Enable Mode - After initialization is complete, the device goes into the Enable mode and operates normally. Normal operation

continues in this mode as long as both enable pins and RST are high.

• Fault Protection Mode - If a protective fault occurs (either Desat/Phase or VLS UV) the device enters a Fault Protection mode. After

a fault clears, the device requires initialization again before resuming normal Enable mode operation.

Table 6. Functions of RST, EN1, and EN2 pins

EN1,

RST

Mode of operation (driver condition)

EN2

Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error and SPI

registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except SO are clamped to VSS.

0

xx

Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external FETs (after

initialization). The SPI port is functional. Logic level outputs are driven with low-impedance. SO is high-impedance unless CS is low.

0x

x0

1

V

, Charge Pump and V regulators are all operating. The IC is ready to move to Enable mode.

LS

DD

Initialization Mode - Low-side drivers are enabled, SPI is fully operational. Ready for initialization (See 7.3, Initialization requirements

on page 41).

Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs require a pulse

on Px_LS before corresponding HS outputs are turn on to charge the bootstrap capacitor. All error pins and register bits are active if

detected.

11

Fault Protection Mode - Drivers are turned OFF or disabled per the fault and protection mode registers. Recovery requires

initialization (See 7.3, Initialization requirements on page 41).

Table 7. Functional ratings

(T = -40 °C to 150 °C and supply voltage range V

= V

= 5.0 V to 45 V, C = 0.47 μF)

PWR

J

SUP

Characteristic

Value

(58)

Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open

(Driver output is switched off, high-impedance mode)

Low (<1.0 V)

(58)

Default State of input pin Px_HS, CS if left open

High (>2.0 V)

(Driver output is switched off, high-impedance mode)

Notes

58.

To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.

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Sleep Mode

Sleep

Y

N

RST

Standby Mode

STBY

Initialization

ENABLE LS

EN

N

Y

Enable (Normal) Mode

ENABLE

HS

N

Y

LS Toggle

HS Toggle

N

DESAT

Disabled

Y

N

Fault Protection

DESAT/

PHASE

N

DESAT/

PHASE

Driver OFF

Y

N

Y

N

Y

Disable Driver

Holdoff Active

VLS UV

N

VLS UV

Y

Driver OFF

EN

Y

RST

N

Figure 17. Device operational flow diagram

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7.2

Logic commands and registers

7.2.1 Command descriptions

The IC contains internal registers to control the various operating parameters, modes, and interrupt characteristics. These commands are

sent and status is read via 8-bit SPI commands. The IC uses the last eight bits in a SPI transfer, so devices can be daisy-chained. The

first three bits in an SPI word can be considered to be the Command with the trailing five bits being the data. The SPI logic generates a

framing error and ignores the SPI message if the number of received bits is not eight or not a multiple of eight. After RST, the first SPI

result returned is Status Register 0.

Table 8. Command list

Command

Name

Description

These commands are used to read IC status. These commands do not change any internal IC status. Returns Status

Register 0-3, depending on sub command.

000x xxxx

NULL

Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation for this flag.

INT remains asserted if uncleared faults are still present. Returns Status Register 0.

0010 xxxx

MASK0

Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation for this flag.

INT remains asserted if uncleared faults are still present. Returns Status Register 0.

0011 xxxx

010x xxxx

0110 xxxx

MASK1

Mode

Enables Desat/Phase Error mode. Enables FULLON mode. Locks further mode changes. Returns Status Register 0.

Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears the interrupt

latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0.

CLINT0

Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears the interrupt

latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0.

0111 xxxx

100x xxxx

CLINT1

DEADTIME

Set deadtime with calibration technique. Returns Status Register 0.

7.2.2 Fault reporting and interrupt generation

Different fault conditions described in the previous chapters can generate an interrupt - INT pin output signal asserted high. When an

interrupt occurs, the source can be read from Status Register 0, which is also the return word of most SPI messages. Faults are latched

on occurrence, and the interrupt and faults are only cleared by sending the corresponding CLINTx command. A fault still existing continue

to assert an interrupt.

Note: If there are multiple pending interrupts, the INT line does not toggle when one of the faults is cleared. Interrupt processing circuitry

on the host must be level sensitive to correctly detect multiple simultaneous interrupt.

Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags indicating any

faults not cleared since the CLINTx command was last written (rising edge of CS) and the beginning of the current SPI command (falling

edge of CS). The NULL command causes no changes to the state of any of the fault or mask bits.

The logic clearing the fault latches occurs only when:

1. A valid command had been received(i.e. no framing error);

2. A state change did not occur during the SPI message (if the bit is being returned as a 0 and a fault change occurs during the middle

of the SPI message, the latch remains set). The latch is cleared on the trailing (rising) edge of the CS pulse. Note, to prevent

missing any faults the CLINTx command should not generally clear any faults without being observed; i.e. it should only clear faults

returned in the prior NULL response.

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35

7.2.3 NULL commands

This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message 000x xx00

reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers.

Table 9. NULL commands

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

x

0

Reset

NULL Commands are described in detail in the STATUS REGISTERS section of this document.

7.2.3.1

MASK command

This is the mask for interrupts. A bit set to “1” enables the corresponding interrupt. Because of the number of MASK bits, this register is

in two portions:

1. MASK0

2. MASK1

Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure 18 illustrates how interrupts are enabled and faults cleared.

CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch and status

register 0 bit corresponding to the lower nibble of the command.

Table 10. MASK0 register

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

1

0

x

Reset

1

7.2.3.2

Interrupt handling

To Status Register

From MASKx:N Register

net N

INT Source

Fault

Various Faults

S

INT

Latch

INT Clear

From Clint Command

R

net 0

Figure 18. Interrupt handling

Table 11. MASK1 register

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

1

x

Reset

1

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NXP Semiconductors

Table 12. Setting interrupt masks

Mask:bit

Description

MASK0:0

MASK0:1

MASK0:2

MASK0:3

Overtemperature on any gate drive output generates an interrupt if this bit is set.

Desaturation event on any output generates an interrupt if this bit is set.

VLS Undervoltage generates an interrupt if this bit is set.

Overcurrent Error–if the overcurrent comparator threshold is exceeded, an interrupt is generated.

Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is generated.

This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration of the desaturation

blanking interval. In FULLON mode, this signal is blanked and cannot generate an error.

MASK1:0

MASK1:1

MASK1:2

Framing Error–if a framing error occurs, an interrupt is generated.

Write Error after locking.

Reset Event–If the IC is reset or disabled, an interrupt occurs. Since the IC always starts from a reset condition, this can be used to

test the interrupt mechanism, because when the IC comes out of RESET, an interrupt immediately occurs.

MASK1:3

7.2.3.3

Mode command

This command is sent by sending binary 010x xxxx data.

Table 13. Mode Command

SPI Data Bits

Write

7

0

6

1

5

0

4

0

3

2

0

1

0

Desaturation

Fault Mode

FULLON Mode Mode Lock

Reset

0

• Bit 0–Mode Lock is used to enable or disable Mode Lock. This bit can only be cleared with a device reset. Since the Mode Lock mode

can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being

received. If an attempt is made to write to a register when Mode Lock is enabled, a Write Error fault is generated.

• Bit 1–FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high and low-side

drivers in a phase on simultaneously. This could be useful in special applications such as alternator regulators, or switched-reluctance

motor drive applications. There is no deadtime control in FULLON mode. Input signals directly control the output stages, synchronized

with the internal clock. This bit is a “0”, after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents

both outputs from being turned on simultaneously.

• Bit 3– Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to “0”, any desaturation on

any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the CLINT command. When 1,

desaturation faults are completely ignored. Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities

are:

• 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates an Interrupt,

if interrupts are enabled.

• 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.

Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any

further changes.

7.2.3.4

Deadtime command

Deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. The deadtime timer starts when a

FET is commanded off (see Figure 6 and Figure 13). The deadtime control is disabled by enabling the FULLON mode.

The deadtime is set by sending the DEADTIME command (100x xxx1), and then sending a calibration pulse of CS. This pulse must be

16 times longer than the required deadtime (see Figure 19). Deadtime is measured in cycle times of the internal time base, f_TB. This

measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low

gate transactions in the same phase.

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For example: the internal time base is running at 20 MHz and a 1.5 μs deadtime is required. First a DEADTIME command is sent (using

the SPI), then a CS is sent. The CS pulse is 16*1.5 = 24 μs wide. The IC measures this pulse as 24000 ns/50 ns = 480 clock cycles and

stores 480/16 = 30 in the deadtime register. Until the next deadtime calibration is performed, 30 clock cycles separates the turn off and

turn on gate signals in the same phase. The worst case error immediately after calibration is +0/-1 time base cycle, for this example +0 ns/

-50 ns. Note that if the internal time base drifts, the effect on dead time scales directly.

Sending a ZERO DEADTIME command (100x xxx0) sets the deadtime timer to 0. However, simultaneous turn-on of high-side and low-

side FETs in the same phase is still prevented unless the FULLON command has been transmitted. There is no calibration pulse expected

after receiving the ZERO DEADTIME command. After RESET, deadtime is set to the maximum value of 255 time base cycles (typically

15 μs). The IC ignores any SPI data sent during the calibration pulse. If there are any transitions on SI or SCLK while the Deadtime CS

pulse is low, a Framing error is generated, however, the CS pulse is used to calibrate the deadtime

Table 14. Deadtime command

SPI Data Bits

7

6

5

4

3

2

1

0

ZERO/

CALIBRATE

Write

1

0

x

Reset

x

Deadtime Calibration Pulse

CS

SCLK

Deadtime

Command

SI

SO

Figure 19. Deadtime calibration

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NXP Semiconductors

7.2.4 Status registers

After any SPI command, the status of the IC is reported in the return value from the SPI port. There are four variants of the NULL command

used to read various status in the IC. Other commands return a general status word in the Status Register 0. There are four Status

Registers in the IC. Status Register 0 is most commonly used for general status. Registers one through three are used to read or confirm

internal IC settings.

7.2.4.1

Status register 0 (status latch bits)

This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command returns

the following data:

Table 15. Status register 0

SPI Data Bits

7

6

5

4

3

2

1

0

DESAT

Detected on

any Channel

TLIM Detected

on any

Results

Register 0 Read

RESET Event

1

Write Error

0

Framing Error

0

Phase Error

0

Overcurrent

0

Low VLS

0

Channel

Reset

0

All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits set. If the

status is still present, this bit does not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively.

• Bit 0–is a flag for Overtemperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This flag can

generate an interrupt if the appropriate mask bit is set.

• Bit 1–is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal high-side desaturation

detectors and phase error logic. Faults are also detected on the low-side as phase errors. A phase error is generated if the output

signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR of phase errors from each phase.

Each phase error is the OR of the HS and LS phase errors. An HS phase error (which also triggers the desaturation detector) occurs

when the HS FET is commanded on, and the Px_HS_S is still low in the deadtime duration after it is driven ON. Similarly, a LS phase

error occurs when the LS FET is commanded on, and the Px_HS_S is still high in the deadtime duration after the FET is driven ON.

This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 2– is a flag for Low Supply Voltage. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 3–is a flag for the output of the Overcurrent Comparator. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 4–is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the individual high or

Low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output with the output driver state,

and blanked for the duration of the desaturation blanking interval. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 5–is a flag for a Framing Error. A framing error is a SPI message not containing one or more multiples of eight bits. SCLK toggling

while measuring the Deadtime calibration pulse is also a framing error. This would typically be a transient or permanent hardware error,

perhaps due to noise on the SPI lines. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 6–indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a Deadtime

command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one defined in the Table 8.

This would typically be a software error. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 7–is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without

the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.

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7.2.4.2

Status register 1 (mode bits)

This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns the following

data:

Table 16. Status register 1

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Register 1 Read

Desaturation Zero Deadtime

Calibration

Overflow

Deadtime

Calibration

0

FULLON Mode

0

Lock Bit

0

Mode

Set

Reset

0

• Bit 0–Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to these registers

is ignored and sets the Write Error flag.

• Bit 1– is the present status of FULLON Mode. If this bit is set to “0”, the FULLON mode is not allowed. A “1” indicates the IC can

operate in FULLON Mode (both high-side and low-side FETs of one phase can be simultaneously turned on).

• Bit 3–indicates Deadtime Calibration occurred. It is “0” until a successful Deadtime command is executed. This includes the Zero

Deadtime setting, as well as a Calibration Overflow.

• Bit 4–is a flag for a Deadtime Calibration Overflow.

• Bit 5–is set if Zero Deadtime is commanded.

• Bit 6–reflects the current state of the Desaturation/Phase Error turn-off mode.

7.2.4.3

Status register 2 (mask bits)

This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns the following

data:

Table 17. Status register 2

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Register 2 Read

Mask1:3

1

Mask1:2

1

Mask1:1

1

Mask1:0

1

Mask0:3

1

Mask0:2

1

Mask0:1

1

Mask0:0

1

Reset

7.2.4.4

Status register 3 (deadtime)

This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns the following

data:

Table 18. Status register 3

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Register 3 Read

Dead7

0

Dead6

0

Dead5

0

Dead4

0

Dead3

0

Dead2

0

Dead1

0

Dead0

0

Reset

These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not yet

performed, all these bits return 0 even though the actual dead time is the maximum.

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NXP Semiconductors

7.3

Initialization requirements

The 33937A provides safe, dependable gate control for three phase BLDC motor control units when it is properly configured. However, if

improperly initialized, the high-side gate drive can be left in a high-impedance mode which allows charge to accumulate from external

sources, eventually turning on the high-side output transistor. It is prudent to follow a well defined initialization procedure which establishes

known states on the gates of all the phase drivers before any current flows in the motor.

7.3.1 Recovery from sleep mode (RESET)

The output gate drive is pulled low with the hold off circuit as long as VLS is low, there is a Power On Reset condition or +5.0 V is low.

These conditions are present during a reset condition. When first coming out of a reset condition, the gate drive circuits are in a high-

impedance state until the first command is given for operation. After the reset line goes high, the supplies begin to operate and the hold

off circuit is deactivated. The phase input lines do not have any effect on the gate drive until both ENABLE1 and ENABLE2 go high, and

even then the low-side gate must be commanded on before the high-side gate can be operated. This is to insure the bootstrap capacitor

has been charged before commencing normal operation. The high-side gate must then be commanded on and then off to initialize the

output latches. A proper initialization sequence places the output gate drives in a low-impedance known condition prior to releasing the

device for normal operation.

A valid initialization sequence would go something like this:

1. RESET goes high (ENABLE1 and ENABLE2 remain low)

2. SPI commands to configure valid interrupts, DESAT mode and Dead Time are issued

3. SPI command to clear all interrupt conditions

4. ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled)

5. PA_LS, PB_LS, and PC_LS are toggled HIGH for about 1.0 s (HS outputs are enabled, but not latched)

6. Toggle nPA_HS, nPB_HS, and nPC_HS LOW for DEAD TIME plus at least 0.1 s (HS outputs are now latched and operational).

End of initialization.

Doing step 6 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the

time they are ON.

This action forces the high-side gate drive out of tri-state mode and leaves it with the HS_G shorted to HS_S on all phases. The HS output

FETs is OFF and ready for normal motor control.

Step 5 and step 6 can be done on all the stated inputs simultaneously. It may be desirable for the HS (step 6) to be toggled simultaneously

to prevent current from flowing in the motor during initialization.

Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS

drivers, so for the HS drivers to be initialized correctly the edge of the input signal to the HS drivers must come after the LS input toggle.

A failure to do this results in the HS gate output remaining in a high-impedance mode. This can result in an accumulation of charge, from

internal and external leakage sources, on the gate of the HS output FET causing it to turn ON even though the input level to the 33937A

would appear to indicate it should be OFF. When this happens, the logic of the 33937A allows the LS output FET to be turned ON without

taking any action on the HS gate because the logic is still indicating the HS gate is OFF. The initial LS input transition from low to high

needs to be after both ENABLE inputs are high (the device in NORMAL mode) for the same reason. The delay between ENABLE and the

LS input should be 280 ns minimum to insure the device is out of STBY mode. Once initialized the output gate drives continues to operate

in a low-impedance mode as commanded by the inputs until the next reset event.

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41

INT

SPI

CS

Px_HS

Px_LS

EN1-2

RST

VDD

VLS

VPWR

VSUP

t

6

PU_VDD

PU_VLS

1

2

3

4

5

Figure 20. Full initialization

Table 19. Full initialization timing description

Time

Description

Min.

Comments

RESET must remain high long enough for VDD and VLS to reach the full regulated voltage. The

normal time for this to occur is specified as 2.0 ms maximum. If there is more capacitance on

VLS or VDD than the normal values given in the specification, this time may need to be

increased. In general, the time may be safely scaled linearly with the capacitance. If the charge

pump is used, it may also increase this time. An estimate of increased time, due to the charge

pump, would be to add 25%. For example, the nominal VLS capacitance is 2.2 μF on each pin,

the power up time should be increased to 4.0 ms, 5.0 ms if using the charge pump.

t

,

PU_VDD

Power up time from RESET

2.0 ms

PU_VLS

End of SPI communication to

EN1 and EN2 rising edge

t

0 ns

1

EN1 and EN2 rising edge to

first LS output command

280 ns

Restricted by EN1 and EN2 propagation delay

2

Nominally 1.0 μs is more that enough. The calculated value is 5*C

100 ns for default recovery.

(R

+ R

).

DSON_LS

BOOT SENSE

t

Initial LS ON period

LS OF to HS ON

1.0 μs

0 ns

3

No defined maximum, but HS is undefined until beginning of toggle on the HS

Minimum: Dead-time + 100 ns to guarantee the HS is switched.

4

100 ns

+ dead

time

t

Initial HS ON period

Maximum: Same limitations as Normal Operation. Unlimited time if leakage currents are less

than trickle charge pump margin.

5

6

t

HS OFF to Normal Operation 0 ns

Immediately begin Normal Operation

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NXP Semiconductors

7.3.2 Recovery from standby mode or a fault

When the 33937A is placed in Standby mode or a fault condition causes a shutdown, the Gate outputs are all driven low. The high-side

gate drive is then disabled and locked to prevent unauthorized transitions. This requires an initialization sequence to recover normal

operation at the end of this mode of operation. The initialization sequence is nearly identical to recovery from Sleep mode, with the

modification that the initial pulse to the low-side control inputs can be reduced to a 100 ns pulse (the low-side gates may not actually

change state). The initialization is then completed by cycling the high-side gates to re-engage the gate drive and insure that it is in the

proper state prior to resuming normal operation.

A valid initialization sequence would go something like this:

1. SPI command to clear all interrupt conditions

2. ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled)

3. PA_LS, PB_LS and PC_LS are toggled HIGH for at least 100 ns (HS gate drive outputs are enabled) longer if bootstrap capacitors

need charged.

4. Toggle nPA_HS, nPB_HS and nPC_HS LOW for DEAD TIME plus at least 100 ns.

End of initialization.

Doing step 4 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the

time they are ON.

This action restores the high-side gate drive operation and leave it with the HS_G shorted to HS_S on all phases. The HS output FETs

will be OFF and ready for normal motor control.

Step 3 and step 4 can be done on all the stated inputs simultaneously. In fact it is desirable for the HS (step 4) to be toggled simultaneously

to prevent current from flowing in the motor during initialization.

Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS

drivers, so for the HS drivers to be initialized correctly, the edge of the input signal to the HS drivers must come after the LS input toggle.

A failure to do this results in the HS gate output remaining locked out from input control. The initial LS input transition from low to high

needs to be after both ENABLE inputs are high (the device in Normal mode) for the same reason. The delay between ENABLE and the

LS input should be 280 ns minimum to insure the device is out of STBY mode.

INT

SPI

nCS

Clear

0.1μs

Px_Combined

nPx_HS

0.1μs

Px_LS

EN2

EN1

Figure 21. Recovery initialization

The horizontal divisions are not to scale. They are a reference to show the sequence of operation. Either individual nPx_HS and Px_LS

or nPx_Combined may be used. nPx_Combined is defined as both nPx_HS and Px_LS tied together or operated to the same logic level

simultaneously.

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NXP Semiconductors

43

7.3.3 IC initialization

This process flow initializes the IC and its software environment.

1. Apply power (V_SYS) to module

2. Remove RST (RST goes high, EN1 and EN2 are still low)

a) When RST rises above the threshold, the device powers up. The charge pump (if configured) starts and allows V_DDand V_LSto

stabilize.

2. Initialize registers

a) Clear all interrupt status flags (send CINT0 and CINT1)

b) Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts.

c) Set desired dead time either by commanding zero dead time or calibrating the dead time.

d) Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes.

5. Bring EN1 & EN2 high

6. Initialize the outputs

a) Command all Px_HS to logic 1 (High-side OFF)

b) Command all Px_LS to logic 1 (commanding Low-side ON). The input must transition from low to high after EN1 and EN2 have

gone high.

c) Wait for the bootstrap capacitors to charge (about 1.0 s typically)

d) Command all Px_LS to logic 0 (command low-side OFF)

e) Command all Px_HS to logic 0 (command high-side ON)

f) Command all Px_HS to logic 1 (command high-side OFF)

The device is now ready for normal operation.

7.3.4 Interrupt handler

When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take corrective

action (if needed), clear the fault, and return. Because the return value from an SPI command is actually returned in the subsequent

message, main-loop software trying to read SR1, SR2, or SR3, may experience an interrupt between sending the SPI command and the

subsequent read. Thus if these registers are to be read, special care must be taken in the software to ensure the correct results are being

interpreted.

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NXP Semiconductors

8

Typical applications

8.1

Typical 12 V application

to other

two

phases

+12 V nom.

V

SYS

D1

D2

C6

C1

C2

PUMP

VPWR

VSUP

MAIN

CHARGE

PUMP

TRICKLE

CHARGE

PUMP

HOLD

VPUMP

PGND

5 V

reg. VDD

-OFF

VLS reg.

CIRCUIT

VLS

VDD

C3

OSCILLATOR

C4

UV

DETECT

3x

Px_BOOT

Px_HS_G

T-Lim

VSUP

1.4 V

C

HIGH-

SIDE

x_Boot

RST

INT

EN1

EN2

R

g_HS

Q

HS

(optional)

desat.

comp.

DRIVER

CONTROL

LOGIC

3

phase x

output

Px_HS

Px_LS

Px_HS_S

to motor

CS

SI

SCLK

SO

VSUP

LOW-

SIDE

phase

comp.

R

g_LS

Px_LS_G

Px_LS_S

Q

LS

(optional)

DRIVER

3

PHASE_x

phase

return

R1

OC_OUT

R

sense

R3

over-cur.

comp.

GND

R2

I-sense

amp.

OC_TH

AMP_OUT AMP_N AMP_P

VLS_CAP

C5

R

fb

aaa-033850

to ADC

Figure 22. Typical 12 V application diagram using charge pump (+12 V battery system)

33937A

NXP Semiconductors

45

V

SYS

+42V Nom.

To Other

Two Phases

C6

+14V Nom.

C2

PUMP

VPWR

VSUP

VPUMP

Main

Charge

Pump

Trickle

Charge

Pump

Hold

-Off

PGND

5V

Reg.

VDD

Circuit

VLS

Reg.

VLS

Oscillator

C3

VDD

C4

UV

Detect

3 x

T-Lim

Px_BOOT

Px_HS_G

Q

HS

C

RST

x_Boot

R

High

INT

EN1

EN2

g_HS

-Side

VSUP

(Optional)

Driver

Control

Logic

+

1.4V

-

Desat.

Comp.

3

Px_HS

Px_LS

Phase x

Output

To Motor

Px_HS_S

CS

SI

Q

SCLK

SO

LS

Low

R

g_LS

Phase

Comp.

VSUP

-Side

3

PHASE_x

Px_LS_G

Px_LS_S

(Optional)

Driver

Phase

Return

OC_OUT

GND

I-sense

Amp.

Over-Cur.

Comp.

R1

R2

R

Sense

AMP_OUT

AMP_P

R3

OC_TH

VLS_CAP

C5

AMP_N

+

-

R

fb

To ADC

Figure 23. High-voltage application diagram (+42 V battery system)

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NXP Semiconductors

Figure 24. Power dissipation profile of application using charge pump

Reference application with:

• Pump capacitor: 1.0 F MLC

• Pump filter capacitor: 47 F low ESR aluminum electrolytic

• Pump diodes: MUR120

• Output FET gate charge: 240 nC @ 10 V

• PWM Frequency: 20 kHz

• Switching Single Phase

Below approximately 17 V the charge pump is actively regulating V_PWR. The increased power dissipation is due to the charge pump

losses. Above this voltage the charge pump oscillator shuts down and V_SYSis passed through the pump diodes directly to V_PWR

.

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NXP Semiconductors

47

Figure 25. Power dissipation profile of application not using charge pump

Reference application with:

• Output FET gate charge: 240 nC @ 10 V

• PWM Frequency: 20 kHz

• Switching Single Phase

• No connections to PUMP or VPUMP

• VPWR connected to V_SYS

If VPWR is supplied by a separate pre-regulator, the power dissipation profile is nearly flat at the value of the pre-regulator voltage for all

V_SYSvoltages.

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NXP Semiconductors

8.2

Recommended 48 V application

to other

two

phases

+48 V nom.

V

SYS

IN

C6

+16 V nom.

OUT

LIN

REG

C2

PUMP

VPWR

VSUP

MAIN

CHARGE

PUMP

TRICKLE

CHARGE

PUMP

HOLD

VPUMP

5 V

reg. VDD

-OFF

VLS reg.

CIRCUIT

PGND

VLS

VDD

C3

OSCILLATOR

C4

UV

DETECT

3x

Px_BOOT

Px_HS_G

T-Lim

VSUP

1.4 V

C

HIGH-

SIDE

x_Boot

RST

INT

EN1

EN2

R

g_HS

Q

HS

(optional)

desat.

comp.

DRIVER

CONTROL

LOGIC

3

phase x

output

Px_HS

Px_HS_S

to motor

Px_LS

CS

SI

SCLK

SO

VSUP

LOW-

SIDE

phase

comp.

R

g_LS

Px_LS_G

Px_LS_S

Q

LS

(optional)

DRIVER

3

PHASE_x

phase

return

R1

OC_OUT

R

R3

sense

over-cur.

comp.

GND

R2

I-sense

amp.

OC_TH

AMP_OUT AMP_N AMP_P

VLS_CAP

C5

R

fb

aaa-033848

to ADC

Figure 26. Recommended 48 V application diagram

33937A

NXP Semiconductors

49

9

Packaging

9.1

Packaging dimension

For the most current package revision, visit www.nxp.com and perform a keyword search using the “98ASA99334D” listed below. Dimensions shown

are provided for reference ONLY.

33937A

50

NXP Semiconductors

33937A

NXP Semiconductors

51

33937A

52

NXP Semiconductors

10 Revision history

Revision

Date

Description of Changes

1.0

6/2008

• Initial Release

• Updated specifications for current sense amplifier and overcurrent comparator

• Added Gain/Phase curves for current sense amplifier

• Added typical curves for load margin on Px_CBOOT

• Added discussion about bootstrap capacitors and requirements for external bootstrap diodes

• Updated application drawings

2.0

7/2008

• Added VSUP requirement for hold-off

• Updated NXP form and style

• Added note to VLS Regulator Outputs (VLS, VLS_CAP)

• Changed Charge Device Model - CDM

• Corrected title to No output loads on Gate Drive Pins, No PWM, Outputs initialized

• Changed In order to achieve a 100% duty cycle operation of the high-side external FETs, a fully integrated trickle

charge pump provides the charge necessary to maintain the external FET gates at fully enhanced levels. The

trickle charge pump has limited ability to supply external leakage paths while performing it’s primary function. The

graph in Figure 11 shows the typical margin for supplying external current loads. These limits are based on

maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this voltage

differential becomes less than 3.0 V, the corresponding high-side FET most likely does not remain fully enhanced

and the high-side driver may malfunction due to insufficient bias voltage between CBOOT and HS_S. and

associated paragraphs

3.0

11/2008

• Added PCZ33937AEK/R2 Part number throughout.

• Added Note and changed parameters for Desaturation Detector and Phase Comparator to Dynamic Electrical

Characteristics Table.

4.0

12/2008

• Replaced Typical Application Diagrams (Pages 40 and 41).

• Page 10 remove V_DDThreshold (V_DDFalling) change note 23

5.0

6.0

7.0

4/2009

9/2009

3/2011

• Note 41 clarification.

• Changed part number from PCZ33937A to MCZ33937A on page 1. Added Device Variation table on page 2.

• Revised per Specific customer requirements (not published)

• Removed part number MCZ33937AEK and replaced with part number MC33937APEK.

8.0

9.0

8/2012

• Removed part number MCZ33937EK/R2 and specific differences. Noted in ordering information to see

specification MC33937 Rev 6.0 for obsolete parts.

• Clarified Gate Capability feature on page 1.

• Updated NXP form and style.

11/2015

7/2016

8/2018

•

Updated NXP document form and style

10.0

11.0

Added AEC-Q100 grade 1 qualified to general description and features list on page 1

•

Moved content from Section 8 to Section 8.1

Added Section 8.2

4/2019

33937A

NXP Semiconductors

53

33937A

54

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MC33937

Rev. 11.0

4/2019


型号：	935311348518
厂家：	NXP
描述：	Brush DC Motor Controller 电动机控制
文件：	总55页 (文件大小：1143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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