935311454557 [NXP]
Power Supply Support Circuit;
| 型号： | 935311454557 |
| 厂家： | 
NXP |
| 描述： | Power Supply Support Circuit |
| 文件： | 总114页 (文件大小：2288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MMPF0200
Rev. 7, 7/2019
NXP Semiconductors
Data Sheet: Technical Data
12 channel configurable power
management integrated circuit
PF0200
The PF0200 Power Management Integrated Circuit (PMIC) provides a highly
programmable/ configurable architecture, with fully integrated power devices
and minimal external components. With up to four buck converters, one boost
regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200
can provide power for a complete system, including applications processors,
memory, and system peripherals, in a wide range of applications. With on-chip
One Time Programmable (OTP) memory, the PF0200 is available in pre-
programmed standard versions, or non-programmed to support custom
programming. The PF0200 is especially suited to the i.MX 6SoloLite,
POWER MANAGEMENT
i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is
supported by full system level reference designs, and pre-programmed
versions of the device. This device is powered by SMARTMOS technology.
EP SUFFIX (E-TYPE)
ES SUFFIX (WF-TYPE)
56 QFN 8X8
56 QFN 8X8
98ASA00405D
98ASA00589D
Features:
Applications
• Three to four buck converters, depending on configuration
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (One Time Programmable) memory for device configuration
• Coin cell charger and RTC supply
• Tablets
• IPTV
• Industrial Control
• Medical monitoring
• Home automation/ alarm/ energy management
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I2C control
• Individually programmable ON, OFF, and Standby modes
PF0200
VREFDDR
i.MX6X
DDR MEMORY
INTERFACE
DDR Memory
SW3A/B
SW1A/B
SW2
Processor Core
Voltages
External AMP
Microphones
Speakers
SATA - FLASH
SD-MMC/
NAND Mem.
SATA
HDD
NAND
- NOR
Interfaces
SWBST
Audio
Codec
Parallel control/GPIOS
I2C Communication
Control Signals
I2C Communication
Sensors
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
Camera
Camera
GPS
MIPI
uPCIe
WAM
GPS
MIPI
HDMI
LDVS Display
USB
Ethernet
CAN
LICELL
Charger
COINCELL
Main Supply
Front USB
POD
Rear Seat
Infotaiment
Rear USB
POD
Cluster/HUD
Figure 1. Simplified application diagram
© NXP B.V. 2019.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 PF0200 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4
5
6
7
8
9
PF0200
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The PF0200 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device
uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list
the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 8.
Contact your NXP representative for more details.
Table 1. Orderable part variations
Temperature (T )
Part number
MMPF0200NPAEP
MMPF0200F0AEP
MMPF0200F3AEP
MMPF0200F4AEP
MMPF0200F6AEP
MMPF0200F0ANES
MMPF0200F3ANES
MMPF0200F4ANES
Notes
Package
Programming
Reference designs
Qualification tier Notes
A
(2)(1)
NP
F0
F3
F4
F6
F0
F3
F4
N/A
N/A
(2)(1)
56 QFN 8x8 mm - 0.5 mm pitch
E-Type QFN (full lead)
(2)(1)
-40 to 85 °C
N/A
Consumer
(2)(1)
(2)(1)
(2)(1)
N/A
i.MX6SX-SDB
N/A
56 QFN 8x8 mm - 0.5 mm pitch
WF-Type QFN (wettable flank)
(2)(1)
-40 to 105 °C
N/A
Extended Industrial
(2)(1)
N/A
1.
2.
For Tape and Reel add an R2 suffix to the part number.
For programming details see Table 8.
PF0200
NXP Semiconductors
3
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
SW1FB
VGEN1
100 mA
VIN1
PF0200
SW1AIN
SW1ALX
VGEN1
O/P
Drive
SW1A/B
Single/Dual
2500 mA
Buck
VGEN2
250 mA
VGEN2
SW1BLX
SW1BIN
O/P
Drive
VIN2
VGEN3
100 mA
SW1VSSSNS
VGEN3
VGEN4
350 mA
VGEN4
SW2LX
SW2IN
O/P
Drive
SW2
1500 mA
Buck
Core Control logic
VIN3
VGEN5
100 mA
SW2IN
VGEN5
SW2FB
GNDREF1
Initialization State Machine
VGEN6
200 mA
VGEN6
Supplies
Control
OTP
SW3AFB
SW3AIN
SW3ALX
O/P
Drive
VDDOTP
VDDIO
SW3A/B
Single Phase
2500 mA
Buck
CONTROL
I2C
Interface
SW3BLX
SW3BIN
O/P
Drive
SCL
SDA
DVS CONTROL
SW3BFB
DVS Control
SW3VSSSNS
I2C Register
map
Trim-In-Package
SWBSTLX
VCOREDIG
VCOREREF
SWBST
600 mA
Boost
O/P
Drive
SWBSTIN
SWBSTFB
Reference
Generation
Clocks and
resets
VCORE
GNDREF
VREFDDR
VINREFDDR
Clocks
32 kHz and 16 MHz
VHALF
VIN
Best
of
Supply
Li Cell
Charger
LICELL
VSNVS
Figure 2. PF0200 simplified internal block diagram
PF0200
4
NXP Semiconductors
PIN CONNECTIONS
3
Pin connections
3.1
Pinout diagram
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INTB
1
2
3
4
5
6
7
8
9
LICELL
SDWNB
VGEN6
RESETBMCU
STANDBY
ICTEST
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
SW1FB
SW1AIN
EP
SW1ALX
SW1BLX
SW1BIN 10
RSVD1 11
RSVD2 12
RSVD3 13
SW1VSSSNS 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 3. Pinout diagram
PF0200
NXP Semiconductors
5
PIN CONNECTIONS
3.2
Pin definitions
Table 2. PF0200 pin definitions
Pin
number
Pin
function
Pin name
Max rating
Type
Definition
Open drain interrupt signal to processor
1
2
INTB
O
O
3.6 V
3.6 V
Digital
Digital
SDWNB
Open drain signal to indicate an imminent system shutdown
Open drain reset output to processor. Alternatively can be used as a Power Good
output.
3
4
5
RESETBMCU
STANDBY
ICTEST
O
I
3.6 V
3.6 V
7.5 V
Digital
Digital
Standby input signal from processor
Digital/
Analog
I
Reserved pin. Connect to GND in application.
Output voltage feedback for SW1A/B. Route this trace separately from the high-
current path and terminate at the output capacitance.
6
7
SW1FB (4)
SW1AIN (4)
I
I
3.6 V
4.8 V
Analog
Analog
Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
8
9
SW1ALX (4)
SW1BLX (4)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 1A switch node connection
Regulator 1B switch node connection
Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
10
SW1BIN (4)
I
4.8 V
Analog
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
11
12
13
RSVD1
RSVD2
RSVD3
-
-
-
-
-
-
Reserved
Reserved Reserved for pin to pin compatibility. Connect this pin to VIN.
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
Reserved
Ground reference for regulator SW1AB. It is connected externally to GNDREF
through a board ground plane.
14
SW1VSSSNS
GND
-
GND
Ground reference for regulator SW2. It is connected externally to GNDREF, via
board ground plane.
15
16
17
18
19
20
21
GNDREF1
VGEN1
VIN1
GND
-
GND
O
I
2.5 V
Analog
Analog
VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.
VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
3.6 V
VGEN2
RSVD4
RSVD5
RSVD6
O
-
2.5 V
Analog
VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
-
-
-
Reserved
-
Reserved Reserved for pin to pin compatibility. Connect this pin to VIN
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
-
Reserved
22
23
SW2LX (4)
SW2IN (4)
O
I
4.8 V
4.8 V
Analog
Analog
Regulator 2 switch node connection
Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least
a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins
as possible.
24
SW2IN (4)
I
4.8 V
Analog
Output voltage feedback for SW2. Route this trace separately from the high-current
path and terminate at the output capacitance.
25
26
27
SW2FB (4)
VGEN3
VIN2
I
O
I
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible.
PF0200
6
NXP Semiconductors
PIN CONNECTIONS
Table 2. PF0200 pin definitions (continued)
Pin
number
Pin
function
Pin name
Max rating
Type
Definition
28
29
VGEN4
VHALF
O
I
3.6 V
3.6 V
Analog
Analog
VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Half supply reference for VREFDDR
VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor as close
to the pin as possible.
30
31
32
VINREFDDR
VREFDDR
I
3.6 V
3.6 V
-
Analog
Analog
GND
O
VREFDDR regulator output
Ground reference for the SW3 regulator. Connect to GNDREF externally via the
board ground plane.
SW3VSSSNS
GND
Output voltage feedback for SW3B. Route this trace separately from the high-current
path and terminate at the output capacitance.
33
34
SW3BFB (4)
SW3BIN (4)
I
I
3.6 V
4.8 V
Analog
Analog
Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
35
36
SW3BLX (4)
SW3ALX (4)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 3B switch node connection
Regulator 3A switch node connection
Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
37
SW3AIN (4)
I
4.8 V
Analog
Output voltage feedback for SW3A. Route this trace separately from the high-current
path and terminate at the output capacitance.
38
39
40
SW3AFB (4)
VGEN5
VIN3
I
O
I
3.6 V
3.6 V
4.8 V
Analog
Analog
Analog
VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN5, 6 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible.
41
42
43
VGEN6
LICELL
VSNVS
O
I/O
O
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.
Coin cell supply input/output
LDO or coin cell output to processor
Boost regulator feedback. Connect this pin to the output rail close to the load. Keep
this trace away from other noisy traces and planes.
44
SWBSTFB (4)
I
5.5 V
Analog
Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
45
46
47
SWBSTIN (4)
SWBSTLX (4)
VDDOTP
I
O
I
4.8 V
7.5 V
Analog
Analog
SWBST switch node connection
Digital &
Analog
10 V (3)
Supply to program OTP fuses
48
49
50
51
52
53
54
GNDREF
VCORE
VIN
GND
-
GND
Ground reference for the main band gap regulator.
Analog Core supply
O
I
3.6 V
4.8 V
1.5 V
1.5 V
3.6 V
3.6 V
Analog
Analog
Analog
Analog
Digital
Digital
Main chip supply
VCOREDIG
VCOREREF
SDA
O
O
I/O
I
Digital Core supply
Main band gap reference
I2C data line (Open drain)
I2C clock
SCL
Supply for I2C bus. Bypass with 0.1 μF decoupling capacitor as close to the pin as
possible.
55
56
VDDIO
I
I
3.6 V
3.6 V
Analog
Digital
PWRON
Power On/off from processor
PF0200
NXP Semiconductors
7
PIN CONNECTIONS
Table 2. PF0200 pin definitions (continued)
Pin
number
Pin
function
Pin name
Max rating
Type
Definition
Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner
and external ground planes through vias to allow effective thermal dissipation.
-
EP
GND
-
GND
Notes
3.
4.
10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected
to VIN with a 0.1 μF bypass capacitor.
PF0200
8
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
4
General product characteristics
4.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Electrical ratings
VIN
Description
Value
Unit
Notes
Main input supply voltage
-0.3 to 4.8
-0.3 to 10
-0.3 to 3.6
V
V
V
VDDOTP
OTP programming input supply voltage
Coin cell voltage
VLICELL
ESD Ratings
(5)
VESD
Human Body Model
Charge Device Model
±2000
±500
V
Notes
5.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model
(CDM), Robotic (CZAP = 4.0 pF).
PF0200
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
4.2
Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Thermal ratings
Ambient Operating Temperature Range
TA
PF0200A
PF0200AN
-40
-40
85
105
°C
(6)
TJ
Operating Junction Temperature Range
Storage Temperature Range
-40
-65
–
125
150
°C
°C
°C
TST
(7)(8)
TPPRT
Peak Package Reflow Temperature
Note 8
QFN56 Thermal resistance and package dissipation ratings
Junction to Ambient
Natural Convection
Four layer board (2s2p)
Eight layer board (2s6p)
(9)(10)(11)
(9)(11)
RθJA
°C/W
°C/W
–
–
28
15
Junction to Ambient (@200 ft/min)
RθJMA
Four layer board (2s2p)
–
–
–
22
10
(12)
(13)
RθJB
Junction to Board
°C/W
°C/W
RΘJCBOTTOM
Junction to Case Bottom
1.2
Junction to Package Top
Natural Convection
(14)
–
2.0
°C/W
ΨJT
Notes
6.
Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for
thermal protection features.
7.
8.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all
orderable parts, and review parametrics.
9.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
Per JEDEC JESD51-6 with the board horizontal.
10.
11.
12.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
13.
14.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
4.2.1 Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the
thermal management and to avoid overheating, the PF0200 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds
specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0200. This thermal protection will act above
the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured
such that this protection is not tripped under normal conditions.
PF0200
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 5. Thermal protection thresholds
Parameter
Min.
Typ.
Max.
Units
Notes
Thermal 110 °C Threshold (THERM110)
Thermal 120 °C Threshold (THERM120)
Thermal 125 °C Threshold (THERM125)
Thermal 130 °C Threshold (THERM130)
Thermal Warning Hysteresis
100
110
115
120
2.0
110
120
125
130
–
120
130
135
140
4.0
°C
°C
°C
°C
°C
°C
Thermal Protection Threshold
130
140
150
4.3
Electrical characteristics
4.3.1 General specifications
Table 6. General PMIC static characteristics
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external
component values and full load current range, unless otherwise noted.
Pin name
Parameter
Load condition
Min.
Max.
Unit
VIL
VIH
VOL
VOH
VIL
–
0.0
0.8 * VSNVS
0.0
0.2 * VSNVS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PWRON
–
3.6
0.4
-2.0 mA
RESETBMCU
SCL
Open Drain
0.7* VIN
0.0
VIN
–
0.2 * VDDIO
3.6
VIH
VIL
–
0.8 * VDDIO
0.0
–
0.2 * VDDIO
3.6
VIH
VOL
VOH
VOL
VOH
VOL
VOH
VIL
–
0.8 * VDDIO
0.0
SDA
-2.0 mA
0.4
Open Drain
0.7*VDDIO
0.0
VDDIO
0.4
-2.0 mA
INTB
Open Drain
0.7* VIN
0.0
VIN
-2.0 mA
0.4
SDWNB
STANDBY
VDDOTP
Open Drain
0.7* VIN
0.0
VIN
–
–
–
–
0.2 * VSNVS
3.6
VIH
VIL
0.8 * VSNVS
0.0
0.3
VIH
1.1
1.7
PF0200
NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
4.3.2 Current consumption
Table 7. Current consumption summary
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS
= 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V,
LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode
PF0200 conditions
System Conditions
Typ.
Max.
Unit
VSNVS from LICELL
Coin Cell
All other blocks off
VIN = 0.0 V
No load on VSNVS
4.0
7.0
μA
(15),(16),(19)
VSNVSVOLT[2:0] = 110
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
Off (15)(17)
No load on VSNVS, PMIC able to wake-up
17
25
μA
μA
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3A/B PFM
Trimmed 16 MHz RC off
32 k RC on
122
122
220(20)
250(21)
Sleep (18)
No load on VSNVS. DDR memories in self refresh
VREFDDR disabled
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW2 in PFM
SW3A/B combined in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
270
270
430(20)
525(21)
No load on VSNVS. Processor enabled in low power
mode. All rails powered on except boost (load = 0 mA)
Standby (18)
μA
VREFDDR enabled
Notes
15.
16.
17.
18.
19.
At 25 °C only.
Refer to Figure 4 for Coin Cell mode characteristics over temperature.
When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
For PFM operation, headroom should be 300 mV or greater.
Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.
The additional current is <30 μA with a pull up resistor of 100 kΩ. The i.MX 6 processors have an internal pull-up from the POR_B pin to the
VDD_SNVS_IN pin. If additional current in the coin cell mode is not desired for i.MX6 applications, use an external switch to disconnect the
RESETBMCU path when VIN is removed. Pull-up RESETBMCU to a rail that is off in the coin cell mode, for non-i.MX 6 applications.
From -40 to 85 °C, Applicable to Consumer and Extended Industrial part numbers
20.
21.
From -40 to 105 °C, Applicable only to Extended Industrial parts
PF0200
12
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
PF0200
100
10
1
PF0200
-40
-20
0
20
Temperature (oC)
40
60
80
Figure 4. Coin cell mode current versus temperature
PF0200
NXP Semiconductors
13
GENERAL DESCRIPTION
5
General description
The PF0200 is the Power Management Integrated Circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application
processors.
5.1
Features
This section summarizes the PF0200 features.
• Input voltage range to PMIC: 2.8 - 4.5 V
• Buck regulators
•
Three to four channel configurable
• SW1A/B, 2.5 A; 0.3 to 1.875 V
• SW2, 1.5 A; 0.4 to 3.3 V
• SW3A/B, 2.5 A (single phase); 0.4 to 3.3 V
• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V
Dynamic voltage scaling
Modes: PWM, PFM, APS
Programmable output voltage
Programmable current limit
Programmable soft start
Programmable PWM switching frequency
Programmable OCP with fault interrupt
•
•
•
•
•
•
•
• Boost regulator
•
•
•
SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
Modes: PFM and Auto
OCP fault interrupt
• LDOs
•
Six user programable LDO
• VGEN1, 0.80 to 1.55 V, 100 mA
• VGEN2, 0.80 to 1.55 V, 250 mA
• VGEN3, 1.8 to 3.3 V, 100 mA
• VGEN4, 1.8 to 3.3 V, 350 mA
• VGEN5, 1.8 to 3.3 V, 100 mA
• VGEN6, 1.8 to 3.3 V, 200 mA
Soft start
•
•
LDO/Switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA
• DDR memory reference voltage
•
VREFDDR, 0.6 to 0.9 V, 10 mA
• 16 MHz internal master clock
• OTP(One time programmable) memory for device configuration
•
User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
• I2C interface
• User programmable Standby, Sleep, and Off modes
PF0200
14
NXP Semiconductors
GENERAL DESCRIPTION
5.2
Functional block diagram
PF0200 Functional Internal Block Diagram
OTP Startup Configuration
Power Generation
OTP Prototyping
Voltage
Switching Regulators
Linear Regulators
(Try before buy)
VGEN1
(0.8 to 1.55V, 100mA)
Sequence and
timing
Phasing and
Frequency Selection
SW1A/B
(0.3 to 1.875V, 2.5A)
VGEN2
(0.8 to 1.55V, 250mA)
Bias & References
Internal Core Voltage Reference
DDR Voltage Reference
VGEN3
(1.8 to 3.3V, 100mA)
SW2
(0.4 to 3.3V, 1.5A)
VGEN4
(1.8 to 3.3V, 350mA)
Logic and Control
SW3A/B
(0.4 to 3.3V)
Configurable 2.5A or
1.25A+1.25A
VGEN5
(1.8 to 3.3V, 100mA)
Parallel MCU Interface
Regulator Control
I2C Communication & Registers
VGEN6
(1.8 to 3.3V, 200mA)
Fault Detection and Protection
Boost Regulator
(5 to 5.15V, 600mA)
USB OTG Supply
VSNVS
(1.0 to 3.0V, 400uA)
RTC supply with coin cell
charger
Thermal
Current Limit
Short-Circuit
Figure 5. Functional block diagram
5.3
Functional description
5.3.1 Power generation
The PF0200 PMIC features three buck regulators (up to four independent outputs), one boost regulator, six general purpose LDOs, one
switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from three to four, thereby providing flexibility to operate with higher
current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. The SW3
regulator can be configured as a single phase or with two independent outputs. The buck regulators provide the supply to processor cores
and to other low-voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments
for the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The
VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.
5.3.2 Control logic
The PF0200 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by
configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.
The PF0200 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply
of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell
is included as well.
PF0200
NXP Semiconductors
15
GENERAL DESCRIPTION
5.3.2.1
Interface signals
PWRON
PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the
PWRON_CFG bit. Refer to section Turn on events for more details.
STANDBY
STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby
mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section Standby mode for more
details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide
VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode.
RESETBMCU
RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 to
4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used
to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during
start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0200 is turned off if the
fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described
above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located
on Extended page 1 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be
permanently chosen by programming OTP fuses.
SDWNB
SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shutdown. It is asserted low for one 32 kHz
clock cycle before powering down and is then de-asserted in the OFF state.
INTB
INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de-
asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
PF0200
16
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6
Functional block requirements and behaviors
6.1
Start-up
The PF0200 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built into the
device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kohm resistor. The
OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0200 to not start-up. However, the PF0200 can be controlled through the
I2C port for prototyping and programming. Once programmed, the NP device will startup with the customer programmed configuration.
6.1.1 Device start-up configuration
Table 8 shows the Default Configuration which can be accessed on all devices as described above, as well as the pre-programmed OTP
configurations.
Table 8. Start-up configuration
Default configuration
All devices
Pre-programmed OTP configuration
Registers
Default I2C Address
F0
F3
F4
F6
0x08
0x08
3.0 V
1.375 V
1
0x08
0x08
0x08
VSNVS_VOLT
SW1AB_VOLT
SW1AB_SEQ
SW2_VOLT
3.0 V
3.0 V
3.0 V
3.0 V
1.375 V
1.375 V
1.375 V
1.375 V
1
2
2
2
3.0 V
3.3 V
5
3.15 V
3.15 V
3.3 V
SW2_SEQ
2
1
1
4
SW3A_VOLT
SW3A_SEQ
1.5 V
1.5 V
3
1.2 V
1.5 V
1.35 V
3
4
4
3
SW3B_VOLT
SW3B_SEQ
1.5 V
1.5 V
3
1.2 V
1.5 V
1.35 V
3
4
4
3
SWBST_VOLT
SWBST_SEQ
VREFDDR_SEQ
VGEN1_VOLT
VGEN1_SEQ
VGEN2_VOLT
VGEN2_SEQ
VGEN3_VOLT
VGEN3_SEQ
VGEN4_VOLT
VGEN4_SEQ
VGEN5_VOLT
VGEN5_SEQ
VGEN6_VOLT
VGEN6_SEQ
-
5.0 V
13
5.0 V
5.0 V
5.0 V
-
6
6
-
3
3
3
4
4
-
1.5 V
9
1.2 V
1.2 V
1.2 V
5
-
4
4
1.5 V
1.5 V
10
-
-
1.5 V
-
2
-
-
-
2.5 V
11
1.8 V
1.8 V
2.8 V
5
-
1.8 V
3
3
3
1.8 V
7
1.8 V
1.8 V
1.8 V
4
3
3
2.5 V
3
2.8 V
12
2.5 V
2.5 V
3.3 V
5
5
-
5
-
2.8 V
3
3.3 V
8
3.0 V
1
-
-
PF0200
NXP Semiconductors
17
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 8. Start-up configuration (continued)
Default configuration
Pre-programmed OTP configuration
Registers
All devices
F0
F3
F4
F6
PU CONFIG, SEQ_CLK_SPEED
PU CONFIG, SWDVS_CLK
PU CONFIG, PWRON
SW1AB CONFIG
1.0 ms
2.0 ms
1.0 ms
12.5 mV/μs
1.0 ms
0.5 ms
6.25 mV/μs
1.5625 mV/μs
12.5 mV/μs
6.25 mV/μs
Level sensitive
SW1AB Single Phase, 2.0 MHz
2.0 MHz
SW2 CONFIG
SW3A CONFIG
SW3AB Single Phase, 2.0 MHz
2.0 MHz
SW3B CONFIG
PG EN
RESETBMCU in Default Mode
LICELL
VIN
UVDET
tR1
tD1
1V
tD2
tR2
VSNVS
tD3
tR3
PWRON
tD4
tR3
SW1A/B
SW2
VGEN2
tD4
tR3
SW3A/B
VREFDDR
VGEN4
VGEN5
tD5
tR4
VGEN6
RESETBMCU
*VSNVS will start from 1.0 V if LICELL is valid before VIN.
Figure 6. Default start-up sequence
PF0200
18
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 9. Default start-up sequence timing
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
(22)
tD1
tR1
tD2
tR2
Turn-on delay of VSNVS
Rise time of VSNVS
–
–
–
–
5.0
3.0
–
–
–
–
ms
ms
ms
ms
User determined delay
1.0
(23)
(23)
Rise time of PWRON
Turn-on delay of first regulator
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01
–
–
–
–
–
2.0
2.5
4.0
7.0
0.2
–
–
–
–
–
(24)
(25)
tD3
tR3
tD4
ms
ms
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
Rise time of regulators
Delay between regulators
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01
–
–
–
0.5
1.0
2.0
–
–
–
ms
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
–
–
–
4.0
0.2
2.0
–
–
–
tR4
tD5
Rise time of RESETBMCU
ms
ms
Turn-on delay of RESETBMCU
Notes
22.
Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
maximum of 24 ms.
23.
24.
25.
Depends on the external signal driving PWRON.
Default configuration.
Rise time is a function of slew rate of regulators and nominal voltage selected.
6.1.2 One time programmability (OTP)
OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by
programming fuses, a configuration may be prototyped by using the “Try Before Buy” (TBB) feature. An error correction code(ECC)
algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed.
The parameters that can be configured by OTP are listed below.
• General: I2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, single phase or independent mode configuration, switching frequency, and soft start ramp rate
• Boost regulator and LDOs: Output voltage
NOTE: When prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware
configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the
configuration (single phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it
will be gated by the buck regulator in the start-up sequence.
6.1.2.1
Start-up sequence and timing
Each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one
to thirty-one in the start-up sequence. The all zeros code indicates that a regulator is not part of the start-up sequence and will remain off.
See Table 10. The delay between each position is equal; however, four delay options are available. See Table 11. The start-up sequence
will terminate at the last programmed regulator.
PF0200
NXP Semiconductors
19
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 10. Start-up sequence
SWxx_SEQ[4:0]/
VGENx_SEQ[4:0]/
VREFDDR_SEQ[4:0]
Sequence
00000
Off
00001
SEQ_CLK_SPEED[1:0] * 1
00010
SEQ_CLK_SPEED[1:0] * 2
*
*
*
*
*
*
*
*
11111
SEQ_CLK_SPEED[1:0] * 31
Table 11. Start-up sequence clock speed
SEQ_CLK_SPEED[1:0]
Time (μs)
00
01
10
11
500
1000
2000
4000
6.1.2.2
PWRON pin configuration
The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG =
1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into Sleep mode.
As an edge sensitive input, such as when connected to a mechanical switch, a falling edge will turn on the part and if the switch is held
low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode.
Table 12. PWRON configuration
PWRON_CFG
Mode
PWRON pin HIGH = ON
PWRON pin LOW = OFF or Sleep mode
0
PWRON pin pulled LOW momentarily = ON
PWRON pin LOW for 4.0 seconds = OFF or Sleep mode
1
2
6.1.2.3
I C address configuration
The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.
Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address
(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 13.
Table 13. I2C address configuration
I2C_SLV_ADDR[3]
hard coded
I2C device address
(Hex)
I2C_SLV_ADDR[2:0]
1
1
1
1
000
001
010
011
0x08
0x09
0x0A
0x0B
PF0200
20
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 13. I2C address configuration (continued)
I2C_SLV_ADDR[3]
hard coded
I2C device address
(Hex)
I2C_SLV_ADDR[2:0]
1
1
1
1
100
101
110
111
0x0C
0x0D
0x0E
0x0F
6.1.2.4
Soft start ramp rate
The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in Dynamic voltage scaling.
6.1.3 OTP prototyping
It is possible to test the desired configuration by using the “Try Before Buy” feature, before permanently programming fuses. The
configuration is loaded from the OTP registers with this feature. These registers merely serve as temporary storage for the values to be
written to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these
registers will be referred to as the TBBOTP registers. The portion of the register map that concerns OTP is shown in Table 121 and
Table 122.
The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values that are then loaded into the
TBBOTP registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR_XOR bits. Refer to
Table 14.
• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. It is required to set all the
FUSE_PORx bits to load the fuses.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero.
The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP
registers maintained and not loaded from a different source.
The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and
SCL are pulled up, must be powered by a 1.7 to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the
registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V,
TBB_POR = 1 and there is a valid turn-on event.
6.1.4 Reading OTP fuses
As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers. When the following conditions are
met; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0, and FUSE_POR_XOR = 1. If ECC is enabled at the time the fuses were programmed,
the error corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the
PMIC will power on with the configuration programmed in the fuses. Contact your NXP representative for more details on reading the OTP
fuses.
6.1.5 Programming OTP fuses
The parameters that can be programmed are shown in the TBBOTP registers in the Extended page 1 of the register map. The PF0200
offers ECC, the control registers for which functions are located in Extended page 2 of the register map. There are ten banks of twenty-
six fuses, each that can be programmed.
PF0200
NXP Semiconductors
21
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 14. Source of start-up sequence
VDDOTP(V)
TBB_POR FUSE_POR_XOR
Start-up sequence
0
0
0
0
1
x
0
1
x
x
None
OTP fuses
0
TBBOTP registers
Factory defined
1.5
6.2
16 MHz and 32 kHz clocks
There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in SLEEP mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing
In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 25 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
Table 15. 16 MHz clock specifications
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VIN16MHz
f16MHZ
f2MHZ
Operating Voltage From VIN
16 MHz Clock Frequency
2.0 MHz Clock Frequency
2.8
–
16
–
4.5
V
14.7
1.84
17.3
2.16
MHz
MHz
(26)
Notes
26.
2.0 MHz clock is derived from the 16 MHz clock.
6.2.1 Clock adjustment
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16MHz clock, the user may add an offset as small as 3.0% of the nominal frequency.
6.3
Bias and references block description
6.3.1 Internal core voltage references
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and
the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the
bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a
valid supply and/or valid coin cell. Table 16 shows the main characteristics of the core circuitry.
PF0200
22
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 16. Core voltages electrical specifications(28)
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V, and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VCOREDIG (digital core supply)
Output Voltage
(27)
VCOREDIG
ON mode
Coin cell mode and OFF
–
–
1.5
1.3
–
–
V
VCORE (Analog core supply)
Output Voltage
(27)
(27)
VCORE
ON mode and charging
OFF and Coin cell mode
–
–
2.775
0.0
–
–
V
VCOREREF (bandgap / regulator reference)
VCOREREF
Output Voltage
–
–
–
1.2
0.5
–
–
–
V
%
%
VCOREREFACC
Absolute Accuracy
VCOREREFTACC Temperature Drift
0.25
Notes
27.
3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction.
For information only.
28.
6.3.1.1
External components
Table 17. External components for core voltages
Regulator
Capacitor value (μF)
VCOREDIG
VCORE
1.0
1.0
VCOREREF
0.22
6.3.2 VREFDDR voltage reference
VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input
voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low-frequency pole.
This divider then utilizes a voltage follower to drive the load.
VINREFDDR
VINREFDDR
CHALF1
100 nf
VHALF
_
+
CHALF2
100 nf
Discharge
VREFDDR
VREFDDR
CREFDDR
1.0 uf
Figure 7. VREFDDR block diagram
PF0200
NXP Semiconductors
23
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.3.2.1
VREFDDR control register
The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 18.
Table 18. Register VREFDDCRTL - ADDR 0x6A
Name
UNUSED
Bit #
R/W Default
Description
3:0
–
R/W
–
0x00
0x00
0x00
UNUSED
Enable or disables VREFDDR output voltage
0 = VREFDDR Disabled
VREFDDREN
UNUSED
4
1 = VREFDDR Enabled
7:5
UNUSED
External components
Table 19. VREFDDR external components(29)
Capacitor
Capacitance (μF)
VINREFDDR(30) to VHALF
0.1
0.1
1.0
VHALF to GND
VREFDDR
Notes
29.
30.
Use X5R or X7R capacitors.
VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.
VREFDDR specifications
Table 20. VREFDDR electrical characteristics
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical
external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR
1.5 V, and 25 °C, unless otherwise noted.
=
Symbol
VREFDDR
VINREFDDR
IREFDDR
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage Range
1.2
0.0
–
–
1.8
10
V
Operating Load Current Range
mA
Current Limit
IREFDDRLIM
10.5
–
15
25
–
mA
IREFDDR when VREFDDR is forced to VINREFDDR/4
(31)
IREFDDRQ
Quiescent Current
8.0
μA
Active mode – DC
Output Voltage
VINREFDDR
2
/
VREFDDR
1.2 V < VINREFDDR < 1.8 V
0.0 mA < IREFDDR < 10 mA
–
–
V
Output Voltage Tolerance (TA = -40 to 85 °C)
1.2 V < VINREFDDR < 1.8 V
VREFDDRTOL
–1.0
–
–
1.0
%
0.6 mA ≤ IREFDDR ≤ 10 mA
Output Voltage Tolerance (TA = -40 to 85 °C), applicable only to the
extended Industrial version
VREFDDRTOL
–1.20
–
1.2
–
%
1.2 V < VINREFDDR < 1.8 V
0.6 mA ≤ IREFDDR ≤ 10 mA
Load Regulation
VREFDDRLOR
1.0 mA < IREFDDR < 10 mA
1.2 V < VINREFDDR < 1.8 V
0.40
mV/mA
PF0200
24
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 20. VREFDDR electrical characteristics (continued)
Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical
external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR
1.5 V, and 25 °C, unless otherwise noted.
=
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Active mode – AC
Turn-on Time
Enable to 90% of end value
tONREFDDR
–
–
–
–
100
10
μs
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
Turn-off Time
Disable to 10% of initial value
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
tOFFREFDDR
ms
Start-up Overshoot
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
VREFDDROSH
–
–
1.0
5.0
6.0
–
%
Transient Load Response
VINREFDDR = 1.2 V, 1.8 V
VREFDDRTLR
Notes
mV
31.
When VREFDDR is off there is a quiescent current of 1.5 μA typical.
6.4
Power generation
6.4.1 Modes of operation
The operation of the PF0200 can be reduced to five states, or modes: ON, OFF, Sleep, Standby, and Coin Cell. Figure 8 shows the state
diagram of the PF0200, along with the conditions to enter and exit from each state.
PF0200
NXP Semiconductors
25
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Coin Cell
VIN < UVDET
VIN < UVDET
VIN > UVDET
PWRON = 0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
Thermal shutdown
OFF
PWRON=1
& VIN > UVDET
(PWRON_CFG = 0)
Or
VIN < UVDET
Sleep
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
VIN < UVDET
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
PWRON=1
& VIN > UVDET
(PWRON_CFG =0)
Or
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
ON
Thermal shudown
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
STANDBY asserted
STANDBY de-asserted
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
Thermal shutdown
Standby
Figure 8. State diagram
To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 27 for the UVDET thresholds. Additionally, I2C control is not possible in the
Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states.
6.4.1.1
ON mode
The PF0200 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.
6.4.1.2
OFF mode
The PF0200 enters the Off mode after a turn-off event. A thermal shutdown event also forces the PF0200 into the Off mode. Only
VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required. RESETBMCU is
asserted, LOW, in this mode.
6.4.1.3
Standby mode
• Depending on STANDBY pin configuration, Standby is entered when the STANDBY pin is asserted. This is typically used for low-
power mode of operation.
• When STANDBY is de-asserted, Standby mode is exited.
PF0200
26
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level control
of going in and out of such deep sleep modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the
operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is pre-programmed through
the I2C interface.
Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into
account the programmed input polarity as shown in Table 21. When the PF0200 is powered up first, regulator settings for the Standby
mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV
bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY will generally be
referred to as active high throughout this document.
Table 21. Standby Pin and polarity control
STANDBY (Pin)(33)
STANDBYINV (I2C bit)(34)
STANDBY Control (32)
0
0
1
0
1
0
1
1
0
0
1
1
Notes
32.
33.
34.
STANDBY = 0: System is not in Standby, STANDBY = 1: System is in Standby
The state of the STANDBY pin only has influence in On mode.
Bit 6 in Power Control Register (ADDR - 0x1B)
Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond
to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor
and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into
Standby mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 22, STBYDLY will delay the Standby initiated response for the entire IC, until the
STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.
Table 22. STANDBY delay - initiated response
STBYDLY[1:0](35)
Function
00
01
10
11
No Delay
One 32 k period (default)
Two 32 k periods
Three 32 k periods
Notes
35.
Bits [5:4] in Power Control Register (ADDR - 0x1B)
6.4.1.4
Sleep mode
• Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit Sleep mode, assert the PWRON pin.
In the Sleep mode, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and
SW3A/B. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 23 shows the control
bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event.
PF0200
NXP Semiconductors
27
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 23. Regulator mode control
SWxOMODE
Off operational mode (sleep) (36)
0
1
Off
PFM
Notes
36.
For sleep mode, an activated switching regulator, should use the off
mode set point as programmed by SW1ABOFF[5:0] for SW1A/B and
SWxOFF[6:0] for SW2 and SW3A/B.
6.4.1.5
Coin cell mode
In the Coin Cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the Coin Cell
state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.
If the coin cell is depleted, a complete system reset will occur. At the next application of power and the detection of a Turn-on event, the
system will be re-initialized with all I2C bits including those that reset on COINPORB, are restored to their default states.
6.4.2 State machine flow summary
Table 24 provides a summary matrix of the PF0200 flow diagram to show the conditions needed to transition from one state to another.
Table 24. State machine flow summary
Next state
STATE
OFF
Coin cell
VIN < UVDET
X
Sleep
Standby
ON
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
OFF
Coin cell
Sleep
X
X
X
X
X
X
X
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
VIN > UVDET
X
Thermal Shutdown
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
V
IN < UVDET
PWRON_CFG = 1
PWRON = 0 < 4.0 s &
VIN > UNDET
Thermal Shutdown
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Standby
V
IN < UVDET
X
Standby de-asserted
Thermal Shutdown
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
ON
V
IN < UVDET
Standby asserted
X
PF0200
28
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.2.1
Turn on events
From OFF and Sleep modes, the PMIC is powered on by a turn-on event. The type of Turn-on event depends on the configuration of
PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when
PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON
is high (pulled up to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See
the State diagram, Figure 8, and the Table 24 for more details. Any regulator enabled in the Sleep mode will remain enabled when
transitioning from Sleep to ON, i.e., the regulator will not be turned off and then on again to match the start-up sequence. The following
is a more detailed description of the PWRON configurations:
• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and
PWRONS respectively, will be set.
• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits,
PWRONI and PWRONS respectively, will be set.
The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch
debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press.
The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to
both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in the table below.
The interrupt is cleared by software, or when cycling through the OFF mode.
Table 25. PWRON hardware debounce bit settings
Turn on
debounce (ms)
Falling edge INT
debounce (ms)
Rising edge INT
debounce (ms)
Bits
State
00
01
10
11
0.0
31.25
125
31.25
31.25
125
31.25
31.25
31.25
31.25
PWRONDBNC[1:0]
Notes
750
750
37.
The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.
6.4.2.2
Turn off events
PWRON pin
The PWRON pin is used to power off the PF0200. The PWRON pin can be configured with OTP to power off the PMIC under the following
two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit will power off the PMIC to avoid damage. A turn-on event
will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a
given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power dissipation section for more
detailed information.
Undervoltage detection
When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell mode.
PF0200
NXP Semiconductors
29
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.3 Power tree
The PF0200 PMIC features four buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a
DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost
regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they
are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators
depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied
by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR.
VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 26 for a summary of all power supplies provided by the
PF0200.
Table 26. Power tree summary
Supply
Output voltage (V)
Step size (mV)
Maximum load current (mA)
SW1A/B
SW2
0.3 - 1.875
0.4 - 3.3
25
25/50
25/50
50
2500
1500
1250(38)
600
SW3A/B
SWBST
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
VSNVS
VREFDDR
0.4 - 3.3
5.00/5.05/5.10/5.15
0.80 – 1.55
0.80 – 1.55
1.8 – 3.3
50
100
50
250
100
100
100
100
NA
100
1.8 – 3.3
350
1.8 – 3.3
100
1.8 – 3.3
200
1.0 - 3.0
0.4
0.5*SW3A_OUT
NA
10
Notes
38.
Current rating per independent phase, when SW3A/B is set in single phase, current capability is up to
2500 mA.
Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0200, as well as the
typical application voltage domain on the i.MX 6 application processors. Note that each application power tree is dependent upon the
system’s voltage and current requirements, therefore a proper input voltage should be selected for the regulators.
The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial
power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative
tables and text specifying each supply for information on performance metrics and operating ranges. Table 27 summarizes the UVDET
thresholds.
Table 27. UVDET threshold
UVDET Threshold
VIN
Rising
Falling
3.1 V
2.65 V
PF0200
30
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
i.MX6X
MCU
SW1A
CORE
(0.3 to 1.875 V), 1.25 A
VDDARM_IN
VDDSOC_IN
(0.3 to 1.875 V), 1.25 A
SW2
VDDHIGH
VDDHIGH_IN
VIN
2.8 - 4.5 V
(0.4 to 3.3 V), 1.5 A
SW3A
DDR CORE
(0.4 to 3.3 V), 1.25 A
SW3B
DDR IO
VDD_DDR_IO
(0.4 to 3.3 V), 1.25 A
SWBST
5.0 V, 0.6 A
LDO_3p0
VREFDDR
0.5*VDDR, 10 mA
SW3A/B
VIN
VSNVS
MUX /
VSNVS_IN
COIN
CHRG
1.0 to 3.0 V,
400 uA
Coincell
VGEN1
(0.80 to 1.55 V),
100 mA
USB_OTG
VIN
SW2
VINMAX = 3.4 V
VINMAX = 3.6 V
VINMAX = 4.5 V
VGEN2
(0.80 to 1.55 V),
250 mA
DDR3
VGEN3
(1.8 to 3.3 V),
100 mA
Peripherals
VIN
SW2
VGEN4
(1.8 to 3.3 V),
350 mA
VGEN5
(1.8 to 3.3 V),
100 mA
VIN
SW2
VGEN6
(1.8 to 3.3 V),
200 mA
Figure 9. PF0200 typical power map
PF0200
NXP Semiconductors
31
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4 Buck regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
6.4.4.1
Current limit
Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit
condition persists for more than 8.0 ms, a fault interrupt is generated.
6.4.4.2
General control
To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur
by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current
variation. Available switching modes for buck regulators are presented in Table 28.
Table 28. Switching mode description
Mode
Description
The regulator is switched off and the output voltage is discharged.
OFF
PFM
PWM
APS
In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency.
In this mode, the regulator is always in PWM mode operation regardless of load conditions.
In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after
the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching
mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes.
Table 29 summarizes the Buck regulator programmability for Normal and Standby modes.
Table 29. Regulator mode control
SWxMODE[3:0]
Normal mode
Standby mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Off
Off
Off
PWM
Reserved
PFM
Reserved
Off
APS
Off
PWM
PWM
PWM
APS
Reserved
APS
Reserved
APS
Reserved
Reserved
Reserved
APS
Reserved
Reserved
Reserved
PFM
PWM
PFM
Reserved
Reserved
Reserved
Reserved
Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the
output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic voltage scaling. The output voltage
options are the same for Normal and Standby modes for each regulator.
PF0200
32
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected
by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage
programmed in its voltage register.
Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a PWRON turn-off event occurs, and any regulator whose
SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage
register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose
SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state.
Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On
from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings.
Table 23 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point
as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B.
Dynamic voltage scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
1. Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B. A
voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33.
2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1ABSTBY[5:0] for SW1A/B and by bits SWxSTBY[6:0] for SW2
and SW3A/B. Voltage transitions initiated by a Standby event are governed by the SW1ABDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.
3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1ABOFF[5:0] for SW1A/B and by bits SWxOFF[6:0] for SW2,
and SW3A/B. Voltage transitions initiated by a turn-off event are governed by the SW1ABDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.
Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators.
Table 30. DVS control logic for SW1A/B
STANDBY
Set Point Selected by
0
1
SW1AB[5:0]
SW1ABSTBY[5:0]
Table 31. DVS control logic for SW2 and SW3A/B
STANDBY
Set Point Selected by
0
1
SWx[6:0]
SWxSTBY[6:0]
Table 32. DVS speed selection for SW1A/B
SW1ABDVSSPEED[1:0]
Function
00
01 (default)
10
25 mV step each 2.0 μs
25 mV step each 4.0 μs
25 mV step each 8.0 μs
25 mV step each 16 μs
11
PF0200
NXP Semiconductors
33
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 33. DVS speed selection for SW2 and SW3A/B
Function
SWx[6] = 0 or SWxSTBY[6] = 0
Function
SWx[6] = 1 or SWxSTBY[6] = 1
SWxDVSSPEED[1:0]
00
01 (default)
10
25 mV step each 2.0 μs
25 mV step each 4.0 μs
25 mV step each 8.0 μs
25 mV step each 16 μs
50 mV step each 4.0 μs
50 mV step each 8.0 μs
50 mV step each 16 μs
50 mV step each 32 μs
11
The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are
determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in
PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control.
During the DVS period the overcurrent condition on the regulator should be masked.
Requested
Set Point
Output Voltage
with light Load
Internally
Controlled Steps
Example
Output
Voltage
Actual Output
Voltage
Initial
Set Point
Actual
Output Voltage
Internally
Possible
Output Voltage
Window
Controlled Steps
Request for
Higher Voltage
Request for
Lower Voltage
Voltage
Change
Request
Initiated by I2C Programming, Standby Control
Figure 10. Voltage stepping with DVS
Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 34. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1A/B is set to 0 °, SW2 is set to 90 ° and SW3A/B is set to 180 ° by default at power
up.
Table 34. Regulator phase clock selection
Phase of clock sent to regulator
SWxPHASE[1:0]
(degrees)
00
01
10
11
0
90
180
270
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 36 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different
frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and
4.0 MHz, 180 ° are the same in terms of phasing. Table 35 shows the optimum phasing when using more than one switching frequency.
PF0200
34
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 35. Optimum phasing
Frequencies
Optimum phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
Table 36. Regulator frequency configuration
SWxFREQ[1:0]
Frequency
00
01
10
11
1.0 MHz
2.0 MHz
4.0 MHz
Reserved
Programmable maximum current
The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents
are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The
SWx_PWRSTG[2:0] bits on the Extended page 2 of the register map control the number of power stages. See Table 37 for the
programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting,
SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage
of power stages that are enabled.
Table 37. Programmable current configuration
Regulators
Control bits
% of power stages enabled
Rated current (A)
SW1AB_PWRSTG[2:0]
ISW1ABMAX
1.0
0
0
1
1
1
1
40%
80%
SW1AB
0
1
1
1
2.0
0
60%
1.5
1
100%
2.5
SW2_PWRSTG[2:0]
ISW2MAX
0.55
0
0
1
1
0
1
1
1
1
38%
75%
SW2
1
1.125
0.95
0
63%
1
100%
1.5
SW3A_PWRSTG[2:0]
ISW3AMAX
0.5
0
0
1
1
0
1
0
1
1
1
1
1
40%
80%
SW3A
1.0
60%
0.75
100%
1.25
PF0200
NXP Semiconductors
35
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 37. Programmable current configuration (continued)
Regulators
Control bits
% of power stages enabled
Rated current (A)
SW3B_PWRSTG[2:0]
ISW3BMAX
0.5
0
0
1
1
0
1
0
1
1
1
1
1
40%
80%
SW3B
1.0
60%
0.75
100%
1.25
6.4.4.3
SW1A/B
SW1A/B is a 2.5 A single phase regulator. The SW1ALX and SW1BLX pins should be connected together on the board.
SW1_CONFIG[1:0] = 01 is the only configuration supported.
The single phase configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Extended page 1, as shown
in Table 38.
.
Table 38. SW1 configuration
SW1_CONFIG[1:0]
Description
00
01
10
11
Reserved
A/B Single Phase
Reserved
Reserved
SW1A/B single phase
In this configuration, SW1A/B is connected as a single phase with a single inductor. This configuration allows reduced component count
by using only one inductor for SW1A/B. Figure 11 shows the physical connection for SW1A/B in single phase.
VIN
SW1AIN
SW1ALX
SW1AMODE
ISENSE
CINSW1A
Controller
SW1A/B
Driver
LSW1A
COSW1A
SW1AFAULT
Internal
I2C
Compensation
Z2
I2C
Interface
SW1FB
Z1
EA
VREF
DAC
VIN
SW1BIN
SW1BMODE
ISENSE
CINSW1B
Controller
SW1BLX
Driver
SW1BFAULT
EP
Figure 11. SW1A/B single phase block diagram
Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register.
PF0200
36
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1A/B setup and control registers
SW1A/B output voltage is programmable from 0.300 to 1.875 V in steps of 25 mV. The output voltage set point is independently
programmed for Normal, Standby, and Sleep mode by setting the SW1AB[5:0], SW1ABSTBY[5:0], and SW1ABOFF[5:0] bits respectively.
Table 39 shows the output voltage coding for SW1A/B. Note: Output voltages of 0.6 V and below are not supported.
Table 39. SW1A/B output voltage configuration
SW1AB[5:0]
SW1ABSTBY[5:0]
SW1ABOFF[5:0]
SW1AB[5:0]
SW1ABSTBY[5:0]
SW1ABOFF[5:0]
Set point
SW1AB output (V)
Set point
SW1AB output (V)
0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
0.3000
0.3250
0.3500
0.3750
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 40 provides a list of registers used to configure and operate SW1A/B and a detailed description on each one of these register is
provided in Table 41 through Table 45.
PF0200
NXP Semiconductors
37
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 40. SW1A/B register summary
Register
SW1ABVOLT
Address
Output
0x20
0x21
0x22
0x23
0x24
SW1AB Output voltage set point in normal operation
SW1AB Output voltage set point on Standby
SW1AB Output voltage set point on Sleep
SW1ABSTBY
SW1ABOFF
SW1ABMODE
SW1ABCONF
SW1AB Switching Mode selector register
SW1AB DVS, Phase, Frequency and ILIM configuration
Table 41. Register SW1ABVOLT - ADDR 0x20
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during normal
operation mode. See Table 39 for all possible
configurations.
SW1AB
5:0
7:6
R/W
–
0x00
0x00
UNUSED
UNUSED
Table 42. Register SW1ABSTBY - ADDR 0x21
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during Standby
mode. See Table 39 for all possible
configurations.
SW1ABSTBY
UNUSED
5:0
7:6
R/W
–
0x00
0x00
UNUSED
Table 43. Register SW1ABOFF - ADDR 0x22
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during Sleep
mode. See Table 39 for all possible
configurations.
SW1ABOFF
5:0
7:6
R/W
–
0x00
0x00
UNUSED
UNUSED
Table 44. Register SW1ABMODE - ADDR 0x23
Name
Bit #
R/W Default
Description
Sets the SW1AB switching operation mode.
See Table 29 for all possible configurations.
SW1ABMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
UNUSED
Set status of SW1AB when in Sleep mode
SW1ABOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
PF0200
38
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 45. Register SW1ABCONF - ADDR 0x24
Name
Bit #
R/W Default
Description
SW1AB current limit level selection
SW1ABILIM
0
R/W
0x00
0 = High level current limit
1 = Low level current limit
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW1A/B switching frequency selector
See Table 36.
SW1ABFREQ
3:2
SW1A/B Phase clock selection
See Table 34.
SW1ABPHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW1A/B DVS speed selection
See Table 32.
SW1ABDVSSPEED
SW1A/B external components
Table 46. SW1A/B external component recommendations
Mode
Components
Description
A/B Single Phase
(39)
CINSW1A
SW1A Input capacitor
4.7 μF
0.1 μF
(39)
(39)
CIN1AHF
SW1A Decoupling input capacitor
SW1B Input capacitor
CINSW1B
4.7 μF
(39)
CIN1BHF
SW1B Decoupling input capacitor
SW1A/B Output capacitor
0.1 μF
(39)
COSW1AB
4 x 22 μF
1.0 μH
DCR = 12 mΩ
ISAT = 4.5 A
LSW1A
SW1A/B Inductor
Notes
39.
Use X5R or X7R capacitors.
PF0200
NXP Semiconductors
39
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1A/B specifications
Table 47. SW1A/B electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW1x = 3.6 V, VSW1AB
= 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted.
Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1AV = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], and 25 °C,
unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SW1A/B (single phase)
VINSW1A
Operating Input Voltage
2.8
–
–
4.5
–
V
V
VINSW1B
VSW1AB
Nominal Output Voltage
Output Voltage Accuracy
Table 39
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A
0.625 V ≤ VSW1AB ≤ 1.450 V
1.475 V ≤ VSW1AB ≤ 1.875 V
-25
-3.0%
-
-
25
3.0%
mV
%
(40)
VSW1ABACC
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA
-65
-45
-3.0%
–
–
–
65
45
3.0%
0.625 V < VSW1AB < 0.675 V
0.7 V < VSW1AB < 0.85 V
0.875 V < VSW1AB < 1.875 V
Rated Output Load Current,
(41)
(41)
ISW1AB
–
–
2500
mA
A
2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V
Current Limiter Peak Current Detection
•
SW1A/B Single Phase (current through inductor)
SW1ABILIM = 0
ISW1ABLIM
4.5
3.3
6.5
4.9
8.5
6.4
SW1ABILIM = 1
Start-up Overshoot
VSW1ABOSH
ISW1AB = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
–
–
–
–
66
mV
µs
Turn-on Time
Enable to 90% of end value
ISW1AB = 0.0 mA
tONSW1AB
500
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
Switching Frequency
SW1ABFREQ[1:0] = 00
SW1ABFREQ[1:0] = 01
SW1ABFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW1AB
MHz
Efficiency (Single Phase)
•
VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH
–
–
–
–
–
–
82
84
86
87
82
71
–
–
–
–
–
–
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 500 mA
APS, PWM, 1.2 V, 750 mA
APS, PWM, 1.2 V, 1250 mA
APS, PWM, 1.2 V, 2500 mA
ηSW1AB
%
ΔVSW1AB
VSW1ABLIR
VSW1ABLOR
Output Ripple
–
–
–
10
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient load = 0 to 1.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW1ABLOTR
mV
–
–
–
–
50
50
PF0200
40
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 47. SW1A/B electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW1x = 3.6 V, VSW1AB
= 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted.
Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1AV = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], and 25 °C,
unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SW1A/B (single phase) (continued)
Quiescent Current
ISW1ABQ
PFM Mode
APS Mode
–
–
18
235
–
–
µA
SW1A P-MOSFET RDSON
VINSW1A = 3.3 V
RONSW1AP
RONSW1AN
ISW1APQ
–
–
–
–
–
–
–
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW1A N-MOSFET RDSON
VINSW1A = 3.3 V
SW1A P-MOSFET Leakage Current
VINSW1A = 4.5 V
SW1A N-MOSFET Leakage Current
VINSW1A = 4.5 V
ISW1ANQ
–
2.5
µA
SW1B P-MOSFET RDSON
VINSW1B = 3.3 V
RONSW1BP
RONSW1BN
ISW1BPQ
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW1B N-MOSFET RDSON
VINSW1B = 3.3 V
SW1B P-MOSFET Leakage Current
VINSW1B = 4.5 V
SW1B N-MOSFET Leakage Current
VINSW1B = 4.5 V
ISW1BNQ
–
–
–
2.5
–
µA
RSW1ABDIS
Discharge Resistance
600
Ω
Notes
40.
Accuracy specification is inclusive of load and line regulation.
41.
Current rating of SW1AB supports the Power Virus mode of operation of the i.MX6X processor.
SW1AB single phase
Figure 12. SW1AB efficiency waveforms
PF0200
NXP Semiconductors
41
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4
SW2
SW2 is a single phase, 1.5 A rated buck regulator. Table 28 describes the modes, and Table 29 show the options for the SWxMODE[3:0]
bits. Figure 13 shows the block diagram and the external component connections for SW2 regulator.
VIN
SW2IN
SW2MODE
ISENSE
CINSW2
Controller
SW2
SW2LX
EP
Driver
LSW2
COSW2
SW2FAULT
I2C
Interface
Internal
I2C
Compensation
Z2
SW2FB
Z1
VREF
EA
DAC
Figure 13. SW2 block diagram
SW2 setup and control registers
SW2 output voltage is programmable from 0.400 to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is
set to “0”, the output will be limited to the lower output voltages from 0.400 to 1.975 V with 25 mV increments, as determined by bits
SW2[5:0]. Likewise, once bit SW2[6] is set to “1”, the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V
with 50 mV increments, as determined by bits SW2[5:0].
In order to optimize the performance of the regulator, it is recommended that only voltages from 2.000 to 3.300 V be used in the high
range, and the lower range be used for voltages from 0.400 to 1.975 V.
The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW2[5:0], SW2STBY[5:0]
and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] will be copied into bits SW2STBY[6], and SW2OFF[6] bits.
Therefore, the output voltage range will remain the same in all three operating modes. Table 48 shows the output voltage coding valid for
SW2. Note: Output voltages of 0.6 V and below are not supported.
Table 48. SW2 output voltage configuration
Low output voltage range(42)
High output voltage range
SW2[6:0]
SW2[6:0]
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
0
1
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
64
65
66
67
68
69
70
71
72
73
74
75
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
2
3
4
5
6
7
8
9
10
11
PF0200
42
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 48. SW2 output voltage configuration (continued)
Low output voltage range(42)
High output voltage range
SW2[6:0]
SW2[6:0]
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
76
77
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
2.5500
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
PF0200
NXP Semiconductors
43
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 48. SW2 output voltage configuration (continued)
Low output voltage range(42)
High output voltage range
SW2[6:0]
SW2[6:0]
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
Set point
SW2STBY[6:0]
SW2OFF[6:0]
SW2 output
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
3.2500
3.3000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
42.
For voltages less than 2.0 V, only use set points 0 to 63
Setup and control of SW2 is done through I2C registers listed in Table 49, and a detailed description of each one of the registers is
provided in Tables 50 to Table 54.
Table 49. SW2 register summary
Register
SW2VOLT
Address
Description
0x35
0x36
0x37
0x38
0x39
Output voltage set point on normal operation
Output voltage set point on Standby
Output voltage set point on Sleep
SW2STBY
SW2OFF
SW2MODE
SW2CONF
Switching Mode selector register
DVS, Phase, Frequency, and ILIM configuration
Table 50. Register SW2VOLT - ADDR 0x35
Name
Bit #
R/W Default
Description
Sets the SW2 output voltage during normal operation
mode. See Table 48 for all possible configurations.
SW2
SW2
5:0
R/W
0x00
Sets the operating output voltage range for SW2. Set
during OTP or TBB configuration only. See Table 48
for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
UNUSED
PF0200
44
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 51. Register SW2STBY - ADDR 0x36
Name
SW2STBY
Bit #
R/W Default
Description
Sets the SW2 output voltage during Standby mode.
See Table 48 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
Standby mode. This bit inherits the value configured
on bit SW2[6] during OTP or TBB configuration. See
Table 48 for all possible configurations.
SW2STBY
UNUSED
6
7
R
–
0x00
0x00
UNUSED
Table 52. Register SW2OFF - ADDR 0x37
Name
SW2OFF
Bit #
R/W Default
Description
Sets the SW2 output voltage during Sleep mode. See
Table 48 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
Sleep mode. This bit inherits the value configured on
bit SW2[6] during OTP or TBB configuration. See
Table 48 for all possible configurations.
SW2OFF
UNUSED
6
7
R
–
0x00
0x00
UNUSED
Table 53. Register SW2MODE - ADDR 0x38
Name
SW2MODE
Bit #
R/W
Default
Description
Sets the SW2 switching operation mode.
See Table 28 for all possible configurations.
3:0
4
R/W
–
0x80
0x00
UNUSED
UNUSED
Set status of SW2 when in Sleep mode
SW2OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
Table 54. Register SW2CONF - ADDR 0x39
Name
Bit #
R/W
Default
Description
SW2 current limit level selection
0 = High level current limit
1 = Low level current limit
SW2ILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW2 switching frequency selector.
See Table 36.
SW2FREQ
3:2
SW2 Phase clock selection.
See Table 34.
SW2PHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW2 DVS speed selection.
See Table 33.
SW2DVSSPEED
PF0200
NXP Semiconductors
45
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW2 external components
Table 55. SW2 external component recommendations
Components
Description
SW2 Input capacitor
Values
(43)
CINSW2
4.7 μF
0.1 μF
(43)
CIN2HF
COSW2
SW2 Decoupling input capacitor
SW2 Output capacitor
(43)
2 x 22 μF
1.0 μH
DCR = 50 mΩ
ISAT = 2.65 A
LSW2
SW2 Inductor
Notes
43.
Use X5R or X7R capacitors.
SW2 specifications
Table 56. SW2 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW2 = 3.6 V, VSW2
=
3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW2
(44)
VINSW2
VSW2
Operating Input Voltage
2.8
–
–
4.5
–
V
V
Nominal Output Voltage
Table 48
Output Voltage Accuracy
•
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 1.5 A
0.625 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
-25
-3.0%
-6.0%
–
–
–
25
3.0%
6.0%
mV
%
(45)
VSW2ACC
PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA
-65
-45
-3.0%
-3.0%
–
–
–
–
65
45
3.0%
3.0%
0.625 V < VSW2 < 0.675 V
0.7 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
Rated Output Load Current
(46)
ISW2
–
–
1500
mA
A
2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
Current Limiter Peak Current Detection
•
Current through Inductor
SW2ILIM = 0
SW2ILIM = 1
ISW2LIM
2.1
1.57
3.0
2.25
3.9
2.93
Start-up Overshoot
VSW2OSH
ISW2 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V
–
–
–
–
66
mV
µs
Turn-on Time
Enable to 90% of end value
ISW2 = 0.0 mA
tONSW2
550
DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V
Switching Frequency
SW2FREQ[1:0] = 00
SW2FREQ[1:0] = 01
SW2FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW2
MHz
PF0200
46
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 56. SW2 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW2 = 3.6 V, VSW2
=
3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Efficiency
•
VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
–
–
–
–
–
–
94
95
96
94
92
89
–
–
–
–
–
–
PFM, 3.15 V, 1.0 mA
PFM, 3.15 V, 50 mA
APS, PWM, 3.15 V, 400 mA
APS, PWM, 3.15 V, 600 mA
APS, PWM, 3.15 V, 1000 mA
APS, PWM, 3.15 V, 1500 mA
ηSW2
%
Switch mode supply SW2 (continued)
ΔVSW2
VSW2LIR
VSW2LOR
Output Ripple
–
–
–
10
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW2LOTR
mV
µA
–
–
–
–
50
50
Quiescent Current
PFM Mode
APS Mode (Low output voltage settings)
APS Mode (High output voltage settings)
–
–
–
23
145
305
–
–
–
ISW2Q
SW2 P-MOSFET RDSON
at VIN = VINSW2 = 3.3 V
RONSW2P
RONSW2N
ISW2PQ
–
–
–
190
212
–
209
255
12
mΩ
mΩ
µA
SW2 N-MOSFET RDSON
at VIN = VINSW2 = 3.3 V
SW2 P-MOSFET Leakage Current
VIN = VINSW2 = 4.5 V
SW2 N-MOSFET Leakage Current
VIN = VINSW2 = 4.5 V
ISW2NQ
–
–
–
4.0
–
µA
RSW2DIS
Discharge Resistance
600
Ω
Notes
44.
When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
Accuracy specification is inclusive of load and line regulation.
45.
46.
The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
PF0200
NXP Semiconductors
47
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 14. SW2 efficiency waveforms
6.4.4.5
SW3A/B
SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 28 describes the available switching modes and
Table 29 show the actual configuration options for the SW3xMODE[3:0] bits.
SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following
configurations are available:
• A single phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 57 shows the options for the SW3CFG[1:0]
bits.
Table 57. SW3 Configuration
SW3_CONFIG[1:0]
Description
00
01
10
11
A/B Single Phase
A/B Single Phase
Reserved
A/B Independent
SW3A/B single phase
In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 15. This configuration
reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control
is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.
PF0200
48
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
SW3AIN
SW3ALX
SW3AMODE
ISENSE
CINSW3A
Controller
SW3
Driver
LSW3A
COSW3A
SW3AFAULT
Internal
I2C
Compensation
Z2
SW3AFB
SW3BIN
I2C
Interface
Z1
VREF
EA
DAC
VIN
SW3BMODE
ISENSE
CINSW3B
Controller
SW3BLX
Driver
SW3BFAULT
I2C
EP
Internal
Compensation
Z2
VREF
SW3BFB
Z1
DAC
EA
Figure 15. SW3A/B single phase block diagram
PF0200
NXP Semiconductors
49
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW3A - SW3B independent outputs
SW3A and SW3B can be configured as independent outputs as shown in Figure 16, providing flexibility for applications requiring more
voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown
in Table 59.
VIN
SW3AIN
SW3ALX
SW3AMODE
ISENSE
CINSW3A
Controller
SW3A
Driver
LSW3A
COSW3A
SW3AFAULT
Internal
I2C
Compensation
Z2
SW3AFB
SW3BIN
Z1
VREF
EA
DAC
VIN
I2C
Interface
SW3BMODE
ISENSE
CINSW3B
Controller
SW3B
SW3BLX
EP
Driver
LSW3B
COSW3B
SW3BFAULT
Internal
I2C
Compensation
Z2
SW3BFB
Z1
VREF
EA
DAC
Figure 16. SW3A/B independent output block diagram
SW3A/B setup and control registers
SW3A/B output voltage is programmable from 0.400 to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6]
is set to “0”, the output will be limited to the lower output voltages from 0.40 to 1.975 V with 25 mV increments, as determined by bits
SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to
3.300 V with 50 mV increments, as determined by bits SW3x[5:0].
In order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 V be used in the high range
and that that the lower range be used for voltages from 0.400 to 1.975 V.
The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW3x[5:0],
SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit will be copied into the SW3xSTBY[6]
and SW3xOFF[6] bits. Therefore, the output voltage range will remain the same on all three operating modes. Table 58 shows the output
voltage coding valid for SW3x. Note: Output voltages of 0.6 V and below are not supported.
PF0200
50
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 58. SW3A/B output voltage configuration
Low output voltage range(47)
High output voltage range
SW3x[6:0]
SW3x[6:0]
Set point
SW3xSTBY[6:0]
SW3xOFF[6:0]
SW3x output
Set Point
SW3xSTBY[6:0]
SW3xOFF[6:0]
sw3xoutput
0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
2.5500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PF0200
NXP Semiconductors
51
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 58. SW3A/B output voltage configuration (continued)
Low output voltage range(47)
High output voltage range
SW3x[6:0]
SW3x[6:0]
Set point
SW3xSTBY[6:0]
SW3xOFF[6:0]
SW3x output
Set Point
SW3xSTBY[6:0]
SW3xOFF[6:0]
sw3xoutput
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
47.
For voltages less than 2.0 V, only use set points 0 to 63.
PF0200
52
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 59 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided
on Tables 60 through Table 69.
Table 59. SW3AB register summary
Register
SW3AVOLT
Address
Output
0x3C
0x3D
0x3E
0x3F
0x40
0x43
0x44
0x45
0x46
0x47
SW3A Output voltage set point on normal operation
SW3A Output voltage set point on Standby
SW3A Output voltage set point on Sleep
SW3ASTBY
SW3AOFF
SW3AMODE
SW3ACONF
SW3BVOLT
SW3BSTBY
SW3BOFF
SW3A Switching mode selector register
SW3A DVS, phase, frequency and ILIM configuration
SW3B Output voltage set point on normal operation
SW3B Output voltage set point on Standby
SW3B Output voltage set point on Sleep
SW3BMODE
SW3BCONF
SW3B Switching mode selector register
SW3B DVS, phase, frequency and ILIM configuration
Table 60. Register SW3AVOLT - ADDR 0x3C
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (Independent) or
SW3A/B output voltage (Single phase), during
normal operation mode. See Table 58 for all
possible configurations.
SW3A
SW3A
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(Independent) or SW3A/B (Single phase). Set
during OTP or TBB configuration only. See
Table 58 for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
UNUSED
Table 61. Register SW3ASTBY - ADDR 0x3D
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (Independent) or
SW3A/B output voltage (Single phase), during
Standby mode. See Table 58 for all possible
configurations.
SW3ASTBY
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(Independent) or SW3A/B (Single phase) on
Standby mode. This bit inherits the value
configured on bit SW3A[6] during OTP or TBB
configuration. See Table 58 for all possible
configurations.
SW3ASTBY
UNUSED
6
7
R
–
0x00
0x00
UNUSED
PF0200
NXP Semiconductors
53
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 62. Register SW3AOFF - ADDR 0x3E
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (Independent) or
SW3A/B output voltage (Single phase), during
Sleep mode. See Table 58 for all possible
configurations.
SW3AOFF
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(Independent) or SW3A/B (Single phase) on
Sleep mode. This bit inherits the value configured
on bit SW3A[6] during OTP or TBB configuration.
See Table 58 for all possible configurations.
SW3AOFF
UNUSED
6
7
R
–
0x00
0x00
UNUSED
Table 63. Register SW3AMODE - ADDR 0x3F
Name
Bit #
R/W Default
Description
Sets the SW3A (Independent) or SW3A/B (Single
phase) switching operation mode.
See Table 28 for all possible configurations.
SW3AMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
UNUSED
Set status of SW3A (Independent) or SW3A/B
(Single phase) when in Sleep mode.
SW3AOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
Table 64. Register SW3ACONF - ADDR 0x40
Name
Bit #
R/W Default
Description
SW3A current limit level selection
0 = High level current limit
1 = Low level current limit
SW3AILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW3A switching frequency selector. See
Table 36.
SW3AFREQ
3:2
SW3APHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW3A Phase clock selection. See Table 34.
SW3A DVS speed selection. See Table 33.
SW3ADVSSPEED
Table 65. Register SW3BVOLT - ADDR 0x43
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (Independent)
during normal operation mode. See Table 58 for
all possible configurations.
SW3B
SW3B
5:0
R/W
0x00
Sets the operating output voltage range for SW3B
(Independent). Set during OTP or TBB
configuration only. See Table 58 for all possible
configurations.
6
7
R
–
0x00
0x00
UNUSED
UNUSED
PF0200
54
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 66. Register SW3BSTBY - ADDR 0x44
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (Independent)
SW3BSTBY
5:0
R/W
0x00
during Standby mode. See Table 58 for all
possible configurations.
Sets the operating output voltage range for SW3B
(Independent) on Standby mode. This bit inherits
the value configured on bit SW3B[6] during OTP
or TBB configuration. See Table 58 for all
possible configurations.
SW3BSTBY
UNUSED
6
7
R
–
0x00
0x00
UNUSED
Table 67. Register SW3BOFF - ADDR 0x45
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (Independent)
during Sleep mode. See Table 58 for all possible
configurations.
SW3BOFF
5:0
R/W
0x00
Sets the operating output voltage range for SW3B
(Independent) on Sleep mode. This bit inherits
the value configured on bit SW3B[6] during OTP
or TBB configuration. See Table 58 for all
possible configurations.
SW3BOFF
UNUSED
6
7
R
–
0x00
0x00
UNUSED
Table 68. Register SW3BMODE - ADDR 0x46
Name
Bit #
R/W Default
Description
Sets the SW3B (Independent) switching
operation mode. See Table 28 for all possible
configurations.
SW3BMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
UNUSED
Set status of SW3B (Independent) when in Sleep
mode.
SW3BOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
UNUSED
Table 69. Register SW3BCONF - ADDR 0x47
Name
Bit #
R/W Default
Description
SW3B current limit level selection
0 = High level Current limit
1 = Low level Current limit
SW3BILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
Unused
SW3BFREQ
SW3BPHASE
SW3BDVSSPEED
3:2
5:4
7:6
SW3B switching frequency selector. See Table 36.
SW3B Phase clock selection. See Table 34.
SW3B DVS speed selection. See Table 33.
PF0200
NXP Semiconductors
55
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW3A/B external components
Table 70. SW3A/B external component requirements
Mode
SW3A independent
SW3A/B single
phase
Components
Description
SW3B independent
(48)
CINSW3A
SW3A Input capacitor
4.7 μF
0.1 μF
4.7 μF
0.1 μF
4 x 22 μF
–
4.7 μF
0.1 μF
(48)
CIN3AHF
SW3A Decoupling input capacitor
SW3B Input capacitor
(48)
CINSW3B
4.7 μF
(48)
CIN3BHF
SW3B Decoupling input capacitor
SW3A Output capacitor
0.1 μF
(48)
COSW3A
2 x 22 μF
2 x 22 μF
(48)
COSW3B
SW3B Output capacitor
1.0 μH
DCR = 50 mΩ
ISAT = 3.9 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
LSW3A
SW3A Inductor
SW3B Inductor
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
LSW3B
Notes
–
48.
Use X5R or X7R capacitors.
SW3A/B specifications
Table 71. SW3A/B electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V,
VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and
independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3a/B
VINSW3x
VSW3x
Operating Input Voltage(49)
2.8
-
–
4.5
-
V
V
Nominal Output Voltage
Output Voltage Accuracy
Table 58
•
PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX
0.625 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
-25
-3.0%
-6.0%
–
–
–
25
3.0%
6.0%
mV
%
(50)
VSW3xACC
•
PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA)
-65
-45
-3.0%
-3.0%
–
–
–
–
65
45
3.0%
3.0%
0.625 V < VSW3x < 0.675 V
0.7 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
Rated Output Load Current (51)
•
2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V
ISW3x
mA
–
–
–
–
2500
1250
PWM, APS mode single phase
PWM, APS mode independent (per phase)
PF0200
56
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 71. SW3A/B electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V,
VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and
independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3a/B (continued)
Current Limiter Peak Current Detection
•
Single phase (Current through inductor)
SW3xILIM = 0
SW3xILIM = 1
3.5
2.7
5.0
3.8
6.5
4.9
ISW3xLIM
A
•
Independent mode (Current through inductor per phase)
SW3xILIM = 0
SW3xILIM = 1
1.8
1.3
2.5
1.9
3.3
2.5
Start-up Overshoot
VSW3xOSH
ISW3x = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
–
–
–
–
66
mV
µs
Turn-on Time
Enable to 90% of end value
ISW3x = 0 mA
tONSW3x
500
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
Switching Frequency
SW3xFREQ[1:0] = 00
SW3xFREQ[1:0] = 01
SW3xFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW3x
MHz
Efficiency (Single Phase)
•
fSW3 = 2.0 MHz, LSW3x 1.0 μH
–
–
–
–
–
–
84
85
85
84
80
74
–
–
–
–
–
–
PFM, 1.5 V, 1.0 mA
PFM, 1.5 V, 50 mA
APS, PWM 1.5 V, 500 mA
APS, PWM 1.5 V, 750 mA
APS, PWM 1.5 V, 1250 mA
APS, PWM 1.5 V, 2500 mA
ηSW3AB
%
ΔVSW3x
VSW3xLIR
VSW3xLOR
Output Ripple
–
–
–
10
–
–
mV
mV
mV
Line Regulation (APS, PWM)
DC Load Regulation (APS, PWM)
Transient Load Regulation
20
20
–
•
Transient Load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW3xLOTR
mV
–
–
–
–
50
50
Quiescent Current
PFM Mode (Single Phase)
APS Mode (Single Phase)
PFM Mode (Independent mode)
APS Mode (SW3A Independent mode)
APS Mode (SW3B Independent mode)
–
–
–
–
–
22
300
50
250
150
–
–
–
–
–
ISW3xQ
µA
SW3A P-MOSFET RDSON
at VIN = VINSW3A = 3.3 V
RONSW3AP
RONSW3AN
ISW3APQ
–
–
–
mΩ
mΩ
µA
215
245
SW3A N-MOSFET RDSON
at VIN = VINSW3A = 3.3 V
258
–
326
7.5
SW3A P-MOSFET Leakage Current
VIN = VINSW3A = 4.5 V
PF0200
NXP Semiconductors
57
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 71. SW3A/B electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V,
VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and
independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3a/B (continued)
SW3A N-MOSFET Leakage Current
ISW3ANQ
RONSW3BP
RONSW3BN
ISW3BPQ
–
–
–
–
–
2.5
µA
mΩ
mΩ
µA
VIN = VINSW3A = 4.5 V
SW3B P-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V
215
245
SW3B N-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V
258
–
326
7.5
SW3B P-MOSFET Leakage Current
VIN = VINSW3B = 4.5 V
SW3B N-MOSFET Leakage Current
ISW3BPQ
–
–
–
2.5
–
µA
V
IN = VINSW3B = 4.5 V
RSW3xDIS
Discharge Resistance
600
Ω
Notes
49. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
50. Accuracy specification is inclusive of load and line regulation.
51. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance).
Figure 17. SW3AB single phase efficiency waveforms
6.4.5 Boost regulator
SWBST is a boost regulator with a programmable output from 5.0 to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY in
OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator will cause the SWBSTOUT and
SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is
integrated on-chip. Figure 18 shows the block diagram and component connection for the boost regulator.
PF0200
58
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
CINBST
SWBSTIN
SWBSTLX
LBST
DBST
SWBSTMODE
VOBST
Driver
I2C
Interface
OC
SWBSTFAULT
Controller
RSENSE
EP
VREFSC
VREFUV
SC
UV
SWBSTFB
Internal
Compensation
COSWBST
Z2
Z1
EA
VREF
Figure 18. Boost regulator architecture
6.4.5.1
SWBST setup and control
Boost regulator control is done through a single register SWBSTCTL described in Table 72. SWBST is included in the power-up sequence
if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.
Table 72. Register SWBSTCTL - ADDR 0x66
Name
Bit #
R/W
Default
Description
Set the output voltage for SWBST
00 = 5.000 V
SWBST1VOLT
1:0
R/W
0x00
01 = 5.050 V
10 = 5.100 V
11 = 5.150 V
Set the Switching mode on Normal operation
00 = OFF
SWBST1MODE
UNUSED
3:2
4
R
–
0x02
0x00
0x02
0x00
01 = PFM
10 = Auto (Default)(52)
11 = APS
UNUSED
Set the Switching mode on Standby
00 = OFF
SWBST1STBYMODE
6:5
7
R/W
–
01 = PFM
10 = Auto (Default)(52)
11 = APS
UNUSED
Notes
UNUSED
52.
In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the Auto mode, if SWBST is part of the startup sequence.
PF0200
NXP Semiconductors
59
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.2
SWBST external components
Table 73. SWBST external component requirements
Components
Description
Values
(53)
CINBST
SWBST input capacitor
SWBST decoupling input capacitor
SWBST output capacitor
SWBST inductor
10 μF
0.1 μF
(53)
CINBSTHF
(53)
COBST
LSBST
DBST
2 x 22 μF
2.2 μH
SWBST boost diode
1.0 A, 20 V Schottky
Notes
53.
Use X5R or X7R capacitors.
6.4.5.3
SWBST specifications
Table 74. SWBST electrical specifications
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSWBST = 3.6 V,
VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are
characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
Switch mode supply SWBST
VINSWBST
VSWBST
Input Voltage Range
2.8
–
–
4.5
–
V
V
Nominal Output Voltage
Table 72
Output Voltage Accuracy
VSWBSTACC
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX
-4.0
–
–
–
3.0
%
Output Ripple
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky
ΔVSWBST
120
mV Vp-p
diode
DC Load Regulation
VSWBSTLOR
–
–
0.5
50
–
–
mV/mA
mV
0 < ISWBST < ISWBSTMAX
DC Line Regulation
VSWBSTLIR
2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX
Continuous Load Current
2.8 V ≤ VIN ≤ 3.0 V
ISWBST
–
–
–
–
500
600
mA
3.0 V ≤ VIN ≤ 4.5 V
Quiescent Current
AUTO
ISWBSTQ
–
222
289
μA
RDSONBST
ISWBSTLIM
MOSFET on Resistance
Peak Current Limit
–
206
306
mΩ
(54)
1400
2200
3200
mA
Start-up Overshoot
ISWBST = 0.0 mA
VSWBSTOSH
–
–
–
–
500
300
mV
mV
Transient Load Response
VSWBSTTR
ISWBST from 1.0 to 100 mA in 1.0 µs
Maximum transient Amplitude
Transient Load Response
VSWBSTTR
ISWBST from 100 to 1.0 mA in 1.0 µs
Maximum transient Amplitude
–
–
300
mV
PF0200
60
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 74. SWBST electrical specifications (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSWBST = 3.6 V,
VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are
characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
Switch mode supply SWBST (continued)
Transient Load Response
tSWBSTTR
ISWBST from 1.0 to 100 mA in 1.0 µs
Time to settle 80% of transient
–
–
500
µs
Transient Load Response
tSWBSTTR
ISWBST from 100 to 1.0 mA in 1.0 µs
Time to settle 80% of transient
–
–
–
20
ms
µA
NMOS Off Leakage
ISWBSTHSQ
1.0
5.0
SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00
Turn-on Time
tONSWBST
fSWBST
–
–
–
–
2.0
–
ms
MHz
%
Enable to 90% of VSWBST, ISWBST = 0.0 mA
Switching Frequency
2.0
86
Efficiency
ηSWBST
–
ISWBST = ISWBSTMAX
Notes
54.
Only in Auto mode.
6.4.6 LDO regulators description
This section describes the LDO regulators provided by the PF0200. All regulators use the main bandgap as reference. Refer to Bias and
references block description section for further information on the internal reference voltages.
A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.
When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when RESETBMCU
is low.
VINx
VINx
VREF
_
+
VGENxEN
VGENxLPWR
VGENx
VGENx
I2C
Interface
CGENx
VGENx
Discharge
Figure 19. General LDO block diagram
PF0200
NXP Semiconductors
61
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.1
Transient response waveforms
Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 20. Note that the transient
line and load response refers to the overshoot, or undershoot only, excluding the DC shift.
IMAX
ILOAD
IMAX/10
1.0 us
1.0 us
Transient Load Stimulus
IL = IMAX/10
IL = IMAX
Overshoot
VOUT
Undershoot
VOUT Transient Load Response
VINx_INITIAL
VINx
VINx_FINAL
10 us
10 us
Transient Line Stimulus
VINx_FINAL
VINx_INITIAL
Overshoot
VOUT
Undershoot
VOUT Transient Line Response
Figure 20. Transient waveforms
PF0200
62
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.2
Short-circuit protection
All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault
condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VGENxEN bit, while at the same time, an interrupt
VGENxFAULTI will be generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the
VGENxFAULTM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a
short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is
not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI,
will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 75 for SCP behavior configuration.
Table 75. Short-circuit behavior
REGSCPEN[0]
Short-circuit behavior
0
1
Current limit
Shutdown
6.4.6.3
LDO regulator control
Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage
according to Table 76 for VGEN1 and VGEN2; and uses the voltage set point on Table 77 for VGEN3 through VGEN6.
Table 76. VGEN1, VGEN2 output voltage configuration
Set point
VGENx[3:0]
VGENx output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.800
0.850
0.900
0.950
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PF0200
NXP Semiconductors
63
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 77. VGEN3/ 4/ 5/ 6 output voltage configuration
Set point
VGENx[3:0]
VGENx output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as
programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 78
presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.
Table 78. LDO control
VGENxEN
VGENxLPWR
VGENxSTBY STANDBY(55)
VGENxOUT
0
1
1
1
1
1
X
0
1
X
0
1
X
0
0
1
1
1
X
X
X
0
Off
On
Low Power
On
1
Off
1
Low Power
Notes
55.
STANDBY refers to a Standby event as described earlier.
For more detail information, Table 79 through Table 84 provide a description of all registers necessary to operate all six general purpose
LDO regulators.
PF0200
64
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 79. Register VGEN1CTL - ADDR 0x6C
Name
Bit #
R/W Default
Description
Sets VGEN1 output voltage.
See Table 76 for all possible configurations.
VGEN1
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN1 output
VGEN1EN
4
5
0 = OFF
1 = ON
Set VGEN1 output state when in Standby. Refer
to Table 78.
VGEN1STBY
R/W
Enable Low Power mode for VGEN1. Refer to
Table 78.
VGEN1LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
Table 80. Register VGEN2CTL - ADDR 0x6D
Name
Bit #
R/W Default
Description
Sets VGEN2 output voltage.
See Table 76 for all possible configurations.
VGEN2
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN2 output
VGEN2EN
4
5
0 = OFF
1 = ON
Set VGEN2 output state when in Standby. Refer
to Table 78.
VGEN2STBY
R/W
Enable Low Power Mode for VGEN2. Refer to
Table 78.
VGEN2LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
Table 81. Register VGEN3CTL - ADDR 0x6E
Name
Bit #
R/W Default
Description
Sets VGEN3 output voltage.
See Table 77 for all possible configurations.
VGEN3
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN3 output
VGEN3EN
4
5
0 = OFF
1 = ON
Set VGEN3 output state when in Standby. Refer
to Table 78.
VGEN3STBY
R/W
Enable Low Power mode for VGEN3. Refer to
Table 78.
VGEN3LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
PF0200
NXP Semiconductors
65
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 82. Register VGEN4CTL - ADDR 0x6F
Name
Bit #
R/W Default
Description
Sets VGEN4 output voltage.
See Table 77 for all possible configurations.
VGEN4
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN4 output
VGEN4EN
4
5
0 = OFF
1 = ON
Set VGEN4 output state when in Standby. Refer
to Table 78.
VGEN4STBY
R/W
Enable Low Power mode for VGEN4. Refer to
Table 78.
VGEN4LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
Table 83. Register VGEN5CTL - ADDR 0x70
Name
Bit #
R/W Default
Description
Sets VGEN5 output voltage.
See Table 77 for all possible configurations.
VGEN5
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN5 output
VGEN5EN
4
5
0 = OFF
1 = ON
Set VGEN5 output state when in Standby. Refer
to Table 78.
VGEN5STBY
R/W
Enable Low Power mode for VGEN5. Refer to
Table 78.
VGEN5LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
Table 84. Register VGEN6CTL - ADDR 0x71
Name
Bit #
R/W Default
Description
Sets VGEN6 output voltage.
See Table 77 for all possible configurations.
VGEN6
3:0
R/W
–
0x80
0x00
0x00
Enables or Disables VGEN6 output
VGEN6EN
4
5
0 = OFF
1 = ON
Set VGEN6 output state when in Standby. Refer
to Table 78.
VGEN6STBY
R/W
Enable Low Power mode for VGEN6. Refer to
Table 78.
VGEN6LPWR
UNUSED
6
7
R/W
–
0x00
0x00
UNUSED
PF0200
66
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.4
External components
Table 85 lists the typical component values for the general purpose LDO regulators.
Table 85. LDO external components
Regulator
Output capacitor (μF)(56)
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
2.2
4.7
2.2
4.7
2.2
2.2
Notes
56. Use X5R/X7R ceramic capacitors.
6.4.6.5
VGEN1
LDO specifications
Table 86. VGEN1 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN
3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
=
Symbol
VGEN1
Parameter
Min.
Typ.
Max.
Unit
Notes
VIN1
VGEN1NOM
IGEN1
Operating Input Voltage
Nominal Output Voltage
Operating Load Current
1.75
–
–
Table 76
–
3.40
–
V
V
0.0
100
mA
VGEN1 DC
Output Voltage Tolerance
1.75 V < VIN1 < 3.4 V
VGEN1TOL
-3.0
–
–
3.0
–
%
0.0 mA < IGEN1 < 100 mA
VGEN1[3:0] = 0000 to 1111
Load Regulation
VGEN1LOR
(VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
0.15
mV/mA
Line Regulation
VGEN1LIR
IGEN1LIM
IGEN1OCP
(VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN1 < 100 mA
–
0.30
167
–
–
mV/mA
mA
Current Limit
122
115
200
200
IGEN1 when VGEN1 is forced to VGEN1NOM/2
Overcurrent Protection Threshold
IGEN1 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
Quiescent Current
IGEN1Q
No load, Change in IVIN and IVIN1
When VGEN1 enabled
–
14
–
μA
PF0200
NXP Semiconductors
67
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 86. VGEN1 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN
3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
=
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN1 AC and transient
PSRR
•
IGEN1 = 75 mA, 20 Hz to 20 kHz
VGEN1[3:0] = 0000 - 1101
VGEN1[3:0] = 1110, 1111
(57)
PSRRVGEN1
dB
50
37
60
45
–
–
Output Noise Density
VIN1 = 1.75 V, IGEN1 = 75 mA
100 Hz – <1.0 kHz
NOISEVGEN1
–
–
–
-108
-118
-124
-100
-108
-112
dBV/ √Hz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on Slew Rate
•
10% to 90% of end value
•
1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA
VGEN1[3:0] = 0000 to 0111
VGEN1[3:0] = 1000 to 1111
SLWRVGEN1
mV/μs
μs
–
–
–
–
12.5
16.5
Turn-On Time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
IGEN1 = 0.0 mA
GEN1tON
60
–
500
Turn-Off Time
GEN1tOFF
GEN1OSHT
Disable to 10% of initial value, VIN1 = 1.75 V
IGEN1 = 0.0 mA
–
–
–
10
ms
%
Start-Up Overshoot
1.0
2.0
VIN1 = 1.75 V, 3.4 V, IGEN1 = 0.0 mA
Transient Load Response
•
VIN1 = 1.75 V, 3.4 V
VGEN1LOTR
–
–
–
3.0
8.0
%
I
GEN1 = 10 to 100 mA in 1.0 μs. Peak of overshoot or undershoot of
VGEN1 with respect to final value
Refer to Figure 20
•
Transient Line Response
•
IGEN1 = 75 mA
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN1[3:0] = 0000 to 1101
VGEN1LITR
5.0
mV
VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for
VGEN1[3:0] = 1110, 1111
•
Refer to Figure 20
Notes
57.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
PF0200
68
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN2
Table 87. VGEN2 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN
3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
=
Symbol
VGEN2
Parameter
Min.
Typ.
Max.
Unit
Notes
VIN1
VGEN2NOM
IGEN2
Operating Input Voltage
Nominal Output Voltage
Operating Load Current
1.75
–
–
Table 76
–
3.40
–
V
V
0.0
250
mA
VGEN2 active mode - DC
Output VoltageTolerance
1.75 V < VIN1 < 3.4 V
0.0 mA < IGEN2 < 250 mA
VGEN2[3:0] = 0000 to 1111
VGEN2TOL
-3.0
–
–
3.0
–
%
Load Regulation
VGEN2LOR
(VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
0.05
mV/mA
Line Regulation
VGEN2LIR
IGEN2LIM
IGEN2OCP
(VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN2 < 250 mA
–
0.50
417
–
–
mV/mA
mA
Current Limit
305
290
510
500
IGEN2 when VGEN2 is forced to VGEN2NOM/2
Over-current Protection Threshold
IGEN2 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
Quiescent Current
IGEN2Q
No load, Change in IVIN and IVIN1
When VGEN2 enabled
–
16
–
μA
VGEN2 AC and transient
PSRR
•
IGEN2 = 187.5 mA, 20 Hz to 20 kHz
(58)
PSRRVGEN2
dB
50
37
60
45
–
–
VGEN2[3:0] = 0000 - 1101
VGEN2[3:0] = 1110, 1111
Output Noise Density
IN1 = 1.75 V, IGEN2 = 187.5 mA
•
V
NOISEVGEN2
–
–
–
-108
-118
-124
-100
-108
-112
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
1.75 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA
SLWRVGEN2
mV/μs
–
–
–
–
12.5
16.5
VGEN2[3:0] = 0000 to 0111
VGEN2[3:0] = 1000 to 1111
Turn-On Time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
IGEN2 = 0.0 mA
GEN2tON
GEN2tOFF
60
–
–
–
500
10
μs
Turn-Off Time
Disable to 10% of initial value, VIN1 = 1.75 V
IGEN2 = 0.0 mA
ms
PF0200
NXP Semiconductors
69
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 87. VGEN2 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN
3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
=
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN2 AC and transient (continued)
Start-up Overshoot
GEN2OSHT
–
1.0
2.0
%
VIN1 = 1.75 V, 3.4 V, IGEN2 = 0.0 mA
Transient Load Response
VIN1 = 1.75 V, 3.4 V
IGEN2 = 25 to 250 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN2 with respect to final
value
Refer to Figure 20
VGEN2LOTR
–
–
–
3.0
8.0
%
Transient Line Response
IGEN2 = 187.5 mA
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN2[3:0] = 0000 to 1101
VGEN2LITR
5.0
mV
VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for
VGEN2[3:0] = 1110, 1111
Refer to Figure 20
Notes
58.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
PF0200
70
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN3
Table 88. VGEN3 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN3
Parameter
Min.
Typ.
Max.
Unit
Operating Input Voltage
2.8
VGEN3NO
M+ 0.250
(59)
VIN2
1.8 V ≤ VGEN3NOM ≤ 2.5 V
2.6 V ≤ VGEN3NOM ≤ 3.3 V
–
–
3.6
3.6
V
VGEN3NOM
IGEN3
Nominal Output Voltage
Operating Load Current
–
Table 77
–
–
V
0.0
100
mA
VGEN3 DC
Output Voltage Tolerance
VIN2MIN < VIN2 < 3.6 V
VGEN3TOL
-3.0
–
–
3.0
–
%
0.0 mA < IGEN3 < 100 mA
VGEN3[3:0] = 0000 to 1111
Load Regulation
VGEN3LOR
(VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA)
For any VIN2MIN < VIN2 < 3.6 V
0.07
mV/mA
Line Regulation
VGEN3LIR
IGEN3LIM
IGEN3OCP
(VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN
For any 0.0 mA < IGEN3 < 100 mA
)
–
0.8
167
–
–
mV/mA
mA
Current Limit
127
120
200
200
IGEN3 when VGEN3 is forced to VGEN3NOM/2
Overcurrent Protection Threshold
IGEN3 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
Quiescent Current
IGEN3Q
No load, Change in IVIN and IVIN2
When VGEN3 enabled
–
13
–
μA
VGEN3 AC and transient
PSRR
•
IGEN3 = 75 mA, 20 Hz to 20 kHz
(60)
PSRRVGEN3
dB
35
55
40
60
–
–
VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V
Output Noise Density
•
VIN2 = VIN2MIN, IGEN3 = 75 mA
NOISEVGEN3
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on Slew Rate
•
10% to 90% of end value
•
VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA
SLWRVGEN3
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN3[3:0] = 0000 to 0011
VGEN3[3:0] = 0100 to 0111
VGEN3[3:0] = 1000 to 1011
VGEN3[3:0] = 1100 to 1111
Turn-on Time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
IGEN3 = 0.0 mA
GEN3tON
60
–
500
μs
PF0200
NXP Semiconductors
71
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 88. VGEN3 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VGEN3 AC and transient (continued)
Turn-off Time
GEN3tOFF
GEN3OSHT
Disable to 10% of initial value, VIN2 = VIN2MIN
IGEN3 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
1.0
2.0
VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA
Transient Load Response
VIN2 = VIN2MIN, 3.6 V
VGEN3LOTR
IGEN3 = 10 to 100 mA in 1.0μs
Peak of overshoot or undershoot of VGEN3 with respect to final
value. Refer to Figure 20
–
–
3.0
8.0
%
Transient Line Response
IGEN3 = 75 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
GEN3[3:0] = 0000 to 0111
VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for
VGEN3[3:0] = 1000 to 1010
VGEN3LITR
–
5.0
mV
VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for
VGEN3[3:0] = 1011 to 1111
Refer to Figure 20
Notes
59.
When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
60.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
VGEN4
Table 89. VGEN4 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN4
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
2.8
VGEN4NO
M+ 0.250
(61)
VIN2
1.8 V ≤ VGEN4NOM ≤ 2.5 V
2.6 V ≤ VGEN4NOM ≤ 3.3 V
–
–
3.6
3.6
V
VGEN4NOM
IGEN4
Nominal Output Voltage
Operating Load Current
–
Table 77
–
–
V
0.0
350
mA
VGEN4 DC
Output Voltage Tolerance
VIN2MIN < VIN2 < 3.6 V
VGEN4TOL
-3.0
–
–
3.0
–
%
0.0 mA < IGEN4 < 350 mA
VGEN4[3:0] = 0000 to 1111
Load Regulation
VGEN4LOR
(VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA )
For any VIN2MIN < VIN2 < 3.6 V
0.07
mV/mA
PF0200
72
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 89. VGEN4 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN4 DC (continued)
Line Regulation
VGEN4LIR
(VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN
For any 0.0 mA < IGEN4 < 350 mA
)
–
0.80
584.5
–
–
mV/mA
mA
Current Limit
IGEN4LIM
435
420
700
700
IGEN4 when VGEN4 is forced to VGEN4NOM/2
Overcurrent Protection Threshold
IGEN4OCP
IGEN4 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
Quiescent Current
IGEN4Q
No load, Change in IVIN and IVIN2
When VGEN4 enabled
–
13
–
μA
VGEN4 AC and transient
PSRR
•
IGEN4 = 262.5 mA, 20 Hz to 20 kHz
(62)
PSRRVGEN4
dB
35
55
40
60
–
–
VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V
Output Noise Density
•
VIN2 = VIN2MIN, IGEN4 = 262.5 mA
NOISEVGEN4
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on Slew Rate
•
10% to 90% of end value
•
VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA
SLWRVGEN4
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN4[3:0] = 0000 to 0011
VGEN4[3:0] = 0100 to 0111
VGEN4[3:0] = 1000 to 1011
VGEN4[3:0] = 1100 to 1111
Turn-on Time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
IGEN4 = 0.0 mA
GEN4tON
60
–
500
μs
Turn-off Time
GEN4tOFF
GEN4OSHT
Disable to 10% of initial value, VIN2 = VIN2MIN
IGEN4 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
1.0
2.0
VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA
Transient Load Response
VIN2 = VIN2MIN, 3.6 V
VGEN4LOTR
IGEN4 = 35 to 350 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN4 with respect to final
value. Refer to Figure 20
–
–
3.0
%
PF0200
NXP Semiconductors
73
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 89. VGEN4 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN4 AC and transient (continued)
Transient Line Response
IGEN4 = 262.5 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
VGEN4[3:0] = 0000 to 0111
VGEN4LITR
VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for
VGEN4[3:0] = 1000 to 1010
–
5.0
8.0
mV
VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for
VGEN4[3:0] = 1011 to 1111
Refer to Figure 20
Notes
61.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
62.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
VGEN5
Table 90. VGEN5 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN5
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
2.8
VGEN5NO
M+ 0.250
–
–
4.5
4.5
(63)
VIN3
1.8 V ≤ VGEN5NOM ≤ 2.5 V
2.6 V ≤ VGEN5NOM ≤ 3.3 V
V
VGEN5NOM
IGEN5
Nominal Output Voltage
Operating Load Current
–
Table 77
–
–
V
0.0
100
mA
VGEN5 active mode – DC
Output Voltage Tolerance
VIN3MIN < VIN3 < 4.5 V
0.0 mA < IGEN5 < 100 mA
VGEN5[3:0] = 0000 to 1111
VGEN5TOL
-3.0
–
–
3.0
–
%
Load Regulation
VGEN5LOR
(VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 mV
0.10
mV/mA
Line Regulation
VGEN5LIR
IGEN5LIM
IGEN5OCP
(VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN
For any 0.0 mA < IGEN5 < 100 mA
)
–
0.50
167
–
–
mV/mA
mA
Current Limit
GEN5 when VGEN5 is forced to VGEN5NOM/2
122
120
200
200
I
Overcurrent Protection threshold
IGEN5 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
PF0200
74
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 90. VGEN5 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN5 active mode – DC (continued)
Quiescent Current
IGEN5Q
No load, Change in IVIN and IVIN3
When VGEN5 enabled
–
13
–
μA
VGEN5 AC and transient
PSRR
•
IGEN5 = 75 mA, 20 Hz to 20 kHz
(64)
PSRRVGEN5
dB
35
52
40
60
–
–
VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V
Output Noise Density
•
VIN3 = VIN3MIN, IGEN5 = 75 mA
NOISEVGEN5
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on Slew Rate
•
10% to 90% of end value
•
VIN3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
SLWRVGEN5
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN5[3:0] = 0000 to 0011
VGEN5[3:0] = 0100 to 0111
VGEN5[3:0] = 1000 to 1011
VGEN5[3:0] = 1100 to 1111
Turn-on Time
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
IGEN5 = 0.0 mA
GEN5tON
60
–
500
μs
Turn-off Time
GEN5tOFF
GEN5OSHT
Disable to 10% of initial value, VIN3 = VIN3MIN
IGEN5 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
1.0
2.0
VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA
Transient Load Response
VIN3 = VIN3MIN, 4.5 V
IGEN5 = 10 to 100 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN5 with respect to final
value.
VGEN5LOTR
–
–
3.0
8.0
%
Refer to Figure 20
Transient Line Response
IGEN5 = 75 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for
VGEN5[3:0] = 0000 to 0111
VGEN5LITR
-
5.0
mV
VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for
VGEN5[3:0] = 1000 to 1111
Refer to Figure 20
Notes
63.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
64.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
PF0200
NXP Semiconductors
75
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN6
Table 91. VGEN6 electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN6
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
2.8
VGEN6NO
M+ 0.250
–
–
4.5
4.5
(65)
VIN3
1.8 V ≤ VGEN6NOM ≤ 2.5 V
2.6 V ≤ VGEN6NOM ≤ 3.3 V
V
VGEN6NOM
IGEN6
Nominal Output Voltage
Operating Load Current
–
Table 77
–
–
V
0.0
200
mA
VGEN6 DC
Output Voltage Tolerance
VIN3MIN < VIN3 < 4.5 V
VGEN6TOL
-3.0
–
–
3.0
–
%
0.0 mA < IGEN6 < 200 mA
VGEN6[3:0] = 0000 to 1111
Load Regulation
VGEN6LOR
(VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 V
0.10
mV/mA
Line Regulation
VGEN6LIR
IGEN6LIM
IGEN6OCP
(VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN
For any 0.0 mA < IGEN6 < 200 mA
)
–
0.50
333
–
–
mV/mA
mA
Current Limit
232
220
475
475
IGEN6 when VGEN6 is forced to VGEN6NOM/2
Overcurrent Protection Threshold
IGEN6 required to cause the SCP function to disable LDO when
REGSCPEN = 1
mA
Quiescent Current
IGEN6Q
No load, Change in IVIN and IVIN3
When VGEN6 enabled
–
13
–
μA
VGEN6 AC and transient
PSRR
•
IGEN6 = 150 mA, 20 Hz to 20 kHz
(66)
PSRRVGEN6
dB
35
52
40
60
–
–
VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V
Output Noise Density
•
VIN3 = VIN3MIN, IGEN6 = 150 mA
NOISEVGEN6
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-On Slew Rate
•
10% to 90% of end value
•
VIN3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA
SLWRVGEN6
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN6[3:0] = 0000 to 0011
VGEN6[3:0] = 0100 to 0111
VGEN6[3:0] = 1000 to 1011
VGEN6[3:0] = 1100 to 1111
Turn-on Time
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
IGEN6 = 0.0 mA
GEN6tON
60
–
500
μs
PF0200
76
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 91. VGEN6 electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN6 AC and transient (continued)
Turn-off Time
GEN6tOFF
GEN6OSHT
Disable to 10% of initial value, VIN3 = VIN3MIN
IGEN6 = 0.0 mA
–
–
–
10
ms
%
Start-up Overshoot
1.0
2.0
VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA
Transient Load Response
VIN3 = VIN3MIN, 4.5 V
VGEN6LOTR
IGEN6 = 20 to 200 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN6 with respect to final
value. Refer to Figure 20
–
–
–
3.0
8.0
%
Transient Line Response
IGEN6 = 150 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for
VGEN6[3:0] = 0000 to 0111
VGEN6LITR
5.0
mV
VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for
VGEN6[3:0] = 1000 to 1111
Refer to Figure 20
Notes
65.
When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
66.
The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
6.4.7 VSNVS LDO/switch
VSNVS powers the low power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be
disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,
VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register
VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2,
1.1, or 1.0 V as shown in Table 92. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a switch,
whose maximum resistance is 100 Ω. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across the
switch, which is 40 mV at a rated maximum load current of 400 μA.
The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied
for the very first time, VSNVS will output 1.0 V. Only when VIN is applied thereafter will VSNVS transition to its default, or programmed
value if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS will change configuration from an LDO to a switch
for the “110” setting, and will remain as an LDO for the other settings, continuing to output the same voltages as when VIN is applied,
providing certain conditions are met as described in Table 92.
PF0200
NXP Semiconductors
77
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
PF0200
VIN
2.25 V (VTL0) -
4.5 V
LDO/SWITCH
Input
LICELL
Charger
VREF
Sense/
Selector
_
+
VSNVS
Z
Coin Cell
1.8 - 3.3 V
I2C Interface
Figure 21. VSNVS supply switch architecture
Table 92 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system.
Table 92. VSNVS modes of operation
VSNVSVOLT[2:0]
110
VIN
MODE
> VTH1
< VTL1
> VTH0
< VTL0
VIN LDO 3.0 V
Coin cell switch
VIN LDO
110
000 – 101
000 – 101
Coin cell LDO
VSNVS control
The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 93.
Table 93. Register VSNVSCTL - ADDR 0x6B
Name
Bit #
R/W Default
Description
Configures VSNVS output voltage.(67)
000 = 1.0 V
001 = 1.1 V
010 = 1.2 V
VSNVSVOLT
2:0
7:3
R/W
0x80
0x00
011 = 1.3 V
100 = 1.5 V
101 = 1.8 V
110 = 3.0 V
111 = RSVD
UNUSED
Notes
–
UNUSED
67.
Only valid when a valid input voltage is present.
VSNVS external components
Table 94. VSNVS External Components
Capacitor
Value (μF)
VSNVS
0.47
PF0200
78
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VSNVS specifications
Table 95. VSNVS electrical characteristics
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS
3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
=
Symbol
VSNVS
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating Input Voltage
Valid Coin Cell range
Valid VIN
VINSNVS
1.8
2.25
–
–
3.3
4.5
V
Operating Load Current
ISNVS
5.0
–
400
μA
V
INMIN < VIN < VINMAX
VSNVS DC, LDO
Output Voltage
•
•
•
5.0 μA < ISNVS < 400 μA (OFF)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
-5.0%
-8.0%
3.0
1.0 - 1.8
7.0%
7.0%
5.0 μA < ISNVS < 400 μA (ON)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
VSNVS
V
-5.0%
-4.0%
3.0
1.0 - 1.8
5.0%
4.0%
5.0 μA < ISNVS < 400 μA (Coin Cell mode)
2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110
1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101]
VCOIN-0.04
-8.0%
–
VCOIN
7.0%
1.0 - 1.8
Dropout Voltage
VSNVSDROP
ISNVSLIM
–
–
50
mV
VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 μA
Current Limit
VIN > VTH1, VSNVSVOLT[2:0] = 110
VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101
VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101
1100
500
480
–
–
–
6750
6750
4500
μA
VIN Threshold (Coin Cell Powered to VIN Powered) VIN going high with
valid coin cell
V
V
VTH0
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101
2.25
2.40
2.55
VIN Threshold (VIN Powered to Coin Cell Powered) VIN going low with
valid coin cell
VTL0
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101
2.20
5.0
2.35
–
2.50
–
VHYST1
VHYST0
VIN Threshold Hysteresis for VTH1-VTL1
VIN Threshold Hysteresis for VTH0-VTL0
mV
mV
5.0
–
–
Output Voltage During Crossover
VSNVSVOLT[2:0] = 110
(68)
VSNVSCROSS
VCOIN > 2.9 V
2.70
–
–
V
Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA
LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA
Notes
68.
During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the
specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6’s RTC
continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching
back to the external crystal oscillator.
PF0200
NXP Semiconductors
79
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 95. VSNVS electrical characteristics (continued)
All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS
3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
=
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VSNVS AC and transient
Turn-on Time (Load capacitor, 0.47 μF)
VIN > UVDET to 90% of VSNVS
VCOIN = 0.0 V, ISNVS = 5.0 μA
–
–
24
(70),(71)
tONSNVS
ms
VSNVSVOLT[2:0] = 000 to 110
Start-up Overshoot
VSNVSVOLT[2:0] = 000 to 110
ISNVS = 5.0 μA
dVIN/dt = 50 mV/μs
VSNVSOSH
–
40
70
mV
mV
V
Transient Line Response ISNVS = 75% of ISNVSMAX
3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
–
–
32
22
–
–
VSNVSLITR
2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
Transient Load Response
VSNVSVOLT[2:0] = 110
3.1 V (UVDETL)< VIN ≤ 4.5 V
ISNVS = 75 to 750 μA
2.8
–
–
–
VSNVSLOTR
VSNVSVOLT[2:0] = 000 to 101
2.45 V < VIN ≤ 4.5 V
VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V
ISNVS = 40 to 400 μA
1.0
2.0
%
Refer to Figure 20
VSNVS DC, switch
VINSNVS
Operating Input voltage
Valid Coin Cell range
1.8
5.0
–
–
–
–
3.3
400
100
V
μA
Ω
ISNVS
Operating Load Current
Internal Switch RDS(on)
VCOIN = 2.6 V
RDSONSNVS
V
IN Threshold (VIN Powered to Coin Cell Powered)
VSNVSVOLT[2:0] = 110
(72)
VTL1
2.725
2.775
2.90
2.95
3.00
3.1
V
V
VIN Threshold (Coin Cell Powered to VIN Powered)
VSNVSVOLT[2:0] = 110
VTH1
Notes
69.
70.
For 1.8 V ISNVS limited to 100 μA for VCOIN < 2.1 V
The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tR1 time.
From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms.
71.
72.
During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the
specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6’s RTC
continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching
back to the external crystal oscillator.
6.4.7.1
Coin cell battery backup
The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN
threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic will be powered by the voltage applied to LICELL.
The supply for internal logic and the VSNVS rail will switch over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the
absence of a voltage at the LICELL pin, resulting in clearing of memory and turning off of VSNVS. When system operation below VTL1
is required, for systems not utilizing a coin cell, connect the LICELL pin to any system voltage between 1.8 and 3.0 V. A small capacitor
should be placed from LICELL to ground under all circumstances.
PF0200
80
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Coin cell charger control
The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for
rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit while the coin cell voltage is programmable
through the VCOIN[2:0] bits on register COINCTL on Table 97. The coin cell charger voltage is programmable. In the ON state, the
charger current is fixed at ICOINHI. In Sleep and Standby modes, the charger current is reduced to a typical 10 μA. In the OFF state,
coin cell charging is not available as the main battery could be depleted unnecessarily. The coin cell charging will be stopped when VIN
is below UVDET.
Table 96. Coin cell charger voltage
VCOIN[2:0]
VCOIN (V)(73)
000
001
010
011
100
101
110
111
2.50
2.70
2.80
2.90
3.00
3.10
3.20
3.30
Notes
73.
Coin cell voltages selected based on the type of LICELL used on the system.
Table 97. Register COINCTL - ADDR 0x1A
Name
Bit #
R/W Default
Description
Coin cell charger output voltage selection.
See Table 96 for all options selectable through
these bits.
VCOIN
2:0
R/W
0x00
COINCHEN
UNUSED
3
R/W
–
0x00
0x00
Enable or disable the Coin cell charger
UNUSED
7:4
External components
Table 98. Coin cell charger external components
Component
Value
Units
LICELL Bypass Capacitor
100
nF
Coin cell specifications
Table 99. Coin cell charger specifications
Parameter
Typ
Unit
Voltage Accuracy
100
60
mV
μA
%
Coin Cell Charge Current in On mode ICOINHI
Current Accuracy
30
PF0200
NXP Semiconductors
81
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
2
6.5
Control interface I C block description
The PF0200 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL
and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be
accomplished by reducing the drive strength of the I2C master via software. The i.MX6 I2C driver defaults to a 40 ohm drive strength. It
is recommended to use a drive strength of 80 ohm or higher to increase the edge times. Alternatively, this can be accomplished by using
small capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors
of 4.8 kohm. PWRON must be logic high for I2C communication to work robustly.
2
6.5.1 I C device ID
I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus
conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to One time
programmability (OTP) for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general call
addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave
address; these bits take affect right away.
6.5.2 I2C operation
The I2C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing diagrams, electrical
specifications, and further details can be found in the I2C specification, which is available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
will be sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The
host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet
contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to
transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
Host can
also drive
another
Start instead
Packet
Type
Device
Master Driven Data
byte 0 )
Register Address
Address
(
of Stop
7
0
7
0
0
7
0
START
STOP
Host SDA
R / W
A
C
K
A
C
K
A
C
K
Slave SDA
Figure 22. I2C write example
Host can also
Packet
Type
Device
Address
Register Address
Device Address
PMIC Driven Data
drive another
Start instead of
Stop
23
16
0
15
8
7
0
NA
CK
Host SDA
START
START
1
STOP
R/W
R/W
7
0
A
C
K
A
C
K
A
C
K
Slave SDA
Figure 23. I2C read example
PF0200
82
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.3 Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt
can be cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this will also cause the INTB pin to go high. If there
are multiple interrupt bits set the INTB pin will remain low until all are either masked or cleared. If a new interrupt occurs while the processor
clears an existing interrupt bit, the INTB pin will remain low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin will not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for
status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts
are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin
will go low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable.
Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before
an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 100 . Due to the
asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.5.4 Interrupt bit summary
Table 100 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer
to the related chapters.
Table 100. Interrupt, mask and sense bits
Interrupt
LOWVINI
Mask
LOWVINM
Sense
LOWVINS
Purpose
Trigger
Debounce time (ms)
Low Input Voltage Detect
Sense is 1 if below 2.80 V threshold
H to L
3.9(74)
Power on button event
H to L
L to H
31.25(74)
31.25
PWRONI
PWRONM
PWRONS
Sense is 1 if PWRON is high.
Thermal 110 °C threshold
Sense is 1 if above threshold
THERM110
THERM110M
THERM120M
THERM125M
THERM130M
SW1AFAULTM
SW1BFAULTM
SW2FAULTM
SW3AFAULTM
SW3BFAULTM
SWBSTFAULTM
VGEN1FAULTM
THERM110S
THERM120S
THERM125S
THERM130S
SW1AFAULTS
SW1BFAULTS
SW2FAULTS
SW3AFAULTS
SW3BFAULTS
SWBSTFAULTS
VGEN1FAULTS
Dual
Dual
3.9
3.9
3.9
3.9
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Thermal 120 °C threshold
Sense is 1 if above threshold
THERM120
Thermal 125 °C threshold
Sense is 1 if above threshold
THERM125
Dual
Thermal 130 °C threshold
Sense is 1 if above threshold
THERM130
Dual
Regulator 1A overcurrent limit
Sense is 1 if above current limit
SW1AFAULTI
SW1BFAULTI
SW2FAULTI
SW3AFAULTI
SW3BFAULTI
SWBSTFAULTI
VGEN1FAULTI
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Regulator 1B overcurrent limit
Sense is 1 if above current limit
Regulator 2 overcurrent limit
Sense is 1 if above current limit
Regulator 3A overcurrent limit
Sense is 1 if above current limit
Regulator 3B overcurrent limit
Sense is 1 if above current limit
SWBST overcurrent limit
Sense is 1 if above current limit
VGEN1 overcurrent limit
Sense is 1 if above current limit
PF0200
NXP Semiconductors
83
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 100. Interrupt, mask and sense bits (continued)
Interrupt
Mask
Sense
Purpose
VGEN2 overcurrent limit
Trigger
Debounce time (ms)
VGEN2FAULTI
VGEN2FAULTM
VGEN2FAULTS
L to H
8.0
Sense is 1 if above current limit
VGEN3 overcurrent limit
Sense is 1 if above current limit
VGEN3FAULTI
VGEN4FAULTI
VGEN5FAULTI
VGEN6FAULTI
VGEN3FAULTM
VGEN4FAULTM
VGEN5FAULTM
VGEN6FAULTM
OTP_ECCM
VGEN3FAULTS
VGEN4FAULTS
VGEN1FAULTS
VGEN6FAULTS
OTP_ECCS
L to H
L to H
L to H
L to H
L to H
8.0
8.0
8.0
8.0
8.0
VGEN4 overcurrent limit
Sense is 1 if above current limit
VGEN5 overcurrent limit
Sense is 1 if above current limit
VGEN6 overcurrent limit
Sense is 1 if above current limit
1 or 2 bit error detected in OTP registers
Sense is 1 if error detected
OTP_ECCI
Notes
74.
Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Tables 101 to 112.
Table 101. Register INTSTAT0 - ADDR 0x05
Name
PWRONI
Bit #
R/W
Default
Description
Power on interrupt bit
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
LOWVINI
Low-voltage interrupt bit
110 °C Thermal interrupt bit
120 °C Thermal interrupt bit
125 °C Thermal interrupt bit
130 °C Thermal interrupt bit
Unused
THERM110I
THERM120I
THERM125I
THERM130I
UNUSED
2
0
3
0
4
0
5
0
7:6
00
Table 102. Register INTMASK0 - ADDR 0x06
Name
PWRONM
Bit #
R/W
Default
Description
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
1
1
Power on interrupt mask bit
Low-voltage interrupt mask bit
110 °C Thermal interrupt mask bit
120 °C Thermal interrupt mask bit
125 °C Thermal interrupt mask bit
130 °C Thermal interrupt mask bit
Unused
LOWVINM
THERM110M
THERM120M
THERM125M
THERM130M
UNUSED
2
1
3
1
4
1
5
1
7:6
00
PF0200
84
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 103. Register INTSENSE0 - ADDR 0x07
Name
Bit #
R/W
Default
Description
Power on sense bit
PWRONS
0
R
0
0 = PWRON low
1 = PWRON high
Low-voltage sense bit
0 = VIN > 2.8 V
LOWVINS
1
2
3
4
R
R
R
R
0
0
0
0
1 = VIN ≤ 2.8 V
110 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
THERM110S
THERM120S
THERM125S
120 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
125 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
130 °C Thermal sense bit
0 = Below threshold
1 = Above threshold
THERM130S
UNUSED
5
6
7
R
–
0
0
Unused
Additional VDDOTP voltage sense pin
0 = VDDOTP grounded
VDDOTPS
R
00
1 = VDDOTP to VCOREDIG or greater
Table 104. Register INTSTAT1 - ADDR 0x08
Name
Bit #
R/W
Default
Description
SW1AFAULTI
SW1BFAULTI
RSVD
0
1
2
3
4
5
6
7
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
0
0
0
0
0
0
SW1A Overcurrent interrupt bit
SW1B Overcurrent interrupt bit
Reserved
SW2FAULTI
SW3AFAULTI
SW3BFAULTI
RSVD
SW2 Overcurrent interrupt bit
SW3A Overcurrent interrupt bit
SW3B Overcurrent interrupt bit
Reserved
UNUSED
Unused
Table 105. Register INTMASK1 - ADDR 0x09
Name
Bit #
R/W
Default
Description
SW1AFAULTM
SW1BFAULTM
RSVD
0
1
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
1
1
1
1
1
1
1
0
SW1A Overcurrent interrupt mask bit
SW1B Overcurrent interrupt mask bit
Reserved
SW2FAULTM
SW3AFAULTM
SW3BFAULTM
RSVD
SW2 Overcurrent interrupt mask bit
SW3A Overcurrent interrupt mask bit
SW3B Overcurrent interrupt mask bit
Reserved
UNUSED
Unused
PF0200
NXP Semiconductors
85
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 106. Register INTSENSE1 - ADDR 0x0A
Name
Bit #
R/W
Default
Description
SW1A Overcurrent sense bit
0 = Normal operation
SW1AFAULTS
0
R
0
1 = Above current limit
SW1B Overcurrent sense bit
0 = Normal operation
SW1BFAULTS
RSVD
1
2
3
R
R
R
0
0
0
1 = Above current limit
Reserved
SW2 Overcurrent sense bit
0 = Normal operation
SW2FAULTS
1 = Above current limit
SW3A Overcurrent sense bit
0 = Normal operation
SW3AFAULTS
SW3BFAULTS
4
5
R
R
0
0
1 = Above current limit
SW3B Overcurrent sense bit
0 = Normal operation
1 = Above current limit
RSVD
6
7
R
–
0
0
Reserved
Unused
UNUSED
Table 107. Register INTSTAT3 - ADDR 0x0E
Name
Bit #
R/W
Default
Description
SWBSTFAULTI
UNUSED
0
6:1
7
R/W1C
–
0
0x00
0
SWBST overcurrent limit interrupt bit
Unused
OTP_ECCI
R/W1C
OTP error interrupt bit
Table 108. Register INTMASK3 - ADDR 0x0F
Name
Bit #
R/W
Default
Description
SWBSTFAULTM
UNUSED
0
6:1
7
R/W
–
1
0x00
1
SWBST overcurrent limit interrupt mask bit
Unused
OTP_ECCM
R/W
OTP error interrupt mask bit
Table 109. Register INTSENSE3 - ADDR 0x10
Name
Bit #
R/W
Default
Description
SWBST overcurrent limit sense bit
0 = Normal operation
SWBSTFAULTS
UNUSED
0
6:1
7
R
–
0
0x00
0
1 = Above current limit
Unused
OTP error sense bit
0 = No error detected
1 = OTP error detected
OTP_ECCS
R
PF0200
86
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 110. Register INTSTAT4 - ADDR 0x11
Name
Bit #
R/W
Default
Description
VGEN1FAULTI
VGEN2FAULTI
VGEN3FAULTI
VGEN4FAULTI
VGEN5FAULTI
VGEN6FAULTI
UNUSED
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
VGEN1 Overcurrent interrupt bit
VGEN2 Overcurrent interrupt bit
VGEN3 Overcurrent interrupt bit
VGEN4 Overcurrent interrupt bit
VGEN5 Overcurrent interrupt bit
VGEN6 Overcurrent interrupt bit
Unused
2
0
3
0
4
0
5
0
7:6
00
Table 111. Register INTMASK4 - ADDR 0x12
Name
Bit #
R/W
Default
Description
VGEN1FAULTM
VGEN2FAULTM
VGEN3FAULTM
VGEN4FAULTM
VGEN5FAULTM
VGEN6FAULTM
UNUSED
0
1
R/W
R/W
R/W
R/W
R/W
R/W
–
1
1
VGEN1 Overcurrent interrupt mask bit
VGEN2 Overcurrent interrupt mask bit
VGEN3 Overcurrent interrupt mask bit
VGEN4 Overcurrent interrupt mask bit
VGEN5 Overcurrent interrupt mask bit
VGEN6 Overcurrent interrupt mask bit
Unused
2
1
3
1
4
1
5
1
7:6
00
Table 112. Register INTSENSE4 - ADDR 0x13
Name
Bit #
R/W
Default
Description
VGEN1 Overcurrent sense bit
0 = Normal operation
VGEN1FAULTS
0
R
0
1 = Above current limit
VGEN2 Overcurrent sense bit
0 = Normal operation
VGEN2FAULTS
VGEN3FAULTS
VGEN4FAULTS
VGEN5FAULTS
1
2
3
4
R
R
R
R
0
0
0
0
1 = Above current limit
VGEN3 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN4 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN5 Overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN6 Overcurrent sense bit
0 = Normal operation
VGEN6FAULTS
UNUSED
5
R
–
0
1 = Above current limit
7:6
00
Unused
PF0200
NXP Semiconductors
87
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.5 Specific registers
6.5.5.1
ic and Version Identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 113 to 115.
Table 113. Register DEVICEID - ADDR 0x00
Name
DEVICEID
UNUSED
Bit #
R/W
Default
Description
Die version.
0001 = PF0200
3:0
7:4
R
–
0x01
0x01
Unused
Table 114. Register SILICON REV- ADDR 0x03
Name
Bit #
R/W
Default
Description
Represents the metal mask revision
Pass 0.0 = 0000
METAL_LAYER_REV
3:0
R
XX
.
.
Pass 0.15 = 1111
Represents the full mask revision
Pass 1.0 = 0001
FULL_LAYER_REV
Notes
7:4
R
XX
.
.
Pass 15.0 = 1111
75.
Default value depends on the silicon revision.
Table 115. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
Allows for characterizing different options within
the same reticule
FIN
1:0
R
0x00
FAB
3:2
7:0
R
R
0x00
0x00
Represents the wafer manufacturing facility
Unused
Unused
6.5.5.2
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 116. Register MEMA ADDR 0x1C
Name
Bit #
R/W
Default
Description
MEMA
7:0
R/W
0
Memory bank A
Memory bank B
Table 117. Register MEMB ADDR 0x1D
Name
Bit #
R/W
Default
Description
MEMB
7:0
R/W
0
PF0200
88
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 118. Register MEMC ADDR 0x1E
Name
Bit #
R/W
Default
Description
MEMC
7:0
R/W
0
Memory bank C
Table 119. Register MEMD ADDR 0x1F
Name
Bit #
R/W
Default
Description
MEMD
7:0
R/W
0
Memory bank D
6.5.6 Register bitmap
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers on Extended page 1, one must first
write 0x01 to the page register at address 0x7F, and to access registers Extended page 2, one must first write 0x02 to the page register
at address 0x7F. To access the Functional page from one of the extended pages, no write to the page register is necessary.
Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have no effect.
The contents of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit.
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the Default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V.
Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that may have other
dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense
bits for the interrupts.
PF0200
NXP Semiconductors
89
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.6.1
Register map
Table 120. Functional page
BITS[7:0]
Add Register name R/W
Default
7
–
0
6
–
0
5
–
0
4
–
1
3
2
1
0
DEVICE ID [3:0]
00
DeviceID
R
8'b0001_0001
0
0
0
1
FULL_LAYER_REV[3:0]
METAL_LAYER_REV[3:0]
03
04
05
06
07
08
09
0A
SILICONREVID
FABID
R
R
8'b0001_0000
8'b0000_0000
X
X
X
X
–
0
X
0
X
X
X
–
–
–
FAB[1:0]
FIN[1:0]
0
0
0
0
0
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
INTSTAT0
INTMASK0
INTSENSE0
INTSTAT1
INTMASK1
INTSENSE1
RW1C 8'b0000_0000
0
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
R/W
R
8'b0011_1111
8'b00xx_xxxx
0
0
RSVD
0
1
1
1
1
1
1
VDDOTPS
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
x
0
–
0
–
0
–
0
x
x
x
x
RSVD
0
x
RSVD
0
SW3BFAULTI
0
SW3AFAULTI
0
SW2FAULTI
SW1BFAULTI
SW1AFAULTI
RW1C 8'b0000_0000
0
0
0
RSVD
1
SW3BFAULTM SW3AFAULTM
SW2FAULTM
RSVD
1
SW1BFAULTM
SW1AFAULTM
R/W
R
8'b0111_1111
8'b0xxx_xxxx
1
1
1
1
1
RSVD
x
SW3BFAULTS
x
SW3AFAULTS
x
SW2FAULTS
x
RSVD
x
SW1BFAULTS
x
SW1AFAULTS
x
OTP_ECCI
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SWBSTFAULTI
0E
0F
10
11
INTSTAT3
INTMASK3
INTSENSE3
INTSTAT4
RW1C 8'b0000_0000
0
0
OTP_ECCM
SWBSTFAULTM
R/W
R
8'b1000_0001
8'b0000_000x
1
1
OTP_ECCS
SWBSTFAULTS
0
–
0
x
VGEN6FAULTI VGEN5FAULTI VGEN4FAULTI VGEN3FAULTI VGEN2FAULTI
VGEN1FAULTI
0
RW1C 8'b0000_0000
0
0
0
0
0
VGEN6
FAULTM
VGEN5
FAULTM
VGEN4
FAULTM
VGEN3
FAULTM
VGEN2
FAULTM
VGEN1
FAULTM
–
0
–
0
–
0
–
0
12
13
INTMASK4
R/W
R
8'b0011_1111
8'b00xx_xxxx
1
1
1
1
1
1
VGEN6
FAULTS
VGEN5
FAULTS
VGEN4
FAULTS
VGEN3
FAULTS
VGEN2
FAULTS
VGEN1
FAULTS
INTSENSE4
x
x
x
x
x
x
–
0
–
0
–
0
–
0
COINCHEN
0
VCOIN[2:0]
0
1A
COINCTL
R/W
8'b0000_0000
0
0
PF0200
90
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 120. Functional page (continued)
BITS[7:0]
Add Register name R/W
Default
7
6
5
0
0
0
0
0
x
x
x
4
1
0
0
0
0
x
3
2
1
0
REGSCPEN
0
STANDBYINV
0
STBYDLY[1:0]
PWRONBDBNC[1:0]
PWRONRSTEN
0
RESTARTEN
0
1B
1C
1D
1E
1F
20
21
22
23
24
PWRCTL
MEMA
R/W
R/W
R/W
R/W
R/W
8'b0001_0000
0
0
0
0
0
x
x
x
1
0
0
0
0
0
x
MEMA[7:0]
MEMB[7:0]
MEMC[7:0]
MEMD[7:0]
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0
0
x
x
x
MEMB
MEMC
MEMD
0
–
0
–
0
–
0
–
0
0
–
0
–
0
–
0
–
0
SW1AB[5:0]
SW1ABVOLT
SW1ABSTBY
SW1ABOFF
SW1ABMODE
SW1ABCONF
R/W/M 8'b00xx_xxxx
SW1ABSTBY[5:0]
R/W
R/W
R/W
R/W
8'b00xx_xxxx
8'b00xx_xxxx
8'b0000_1000
8'bxx00_xx00
x
x
SW1ABOFF[5:0]
x
x
–
0
SW1ABOMODE
0
SW1ABMODE[3:0]
0
0
0
SW1ABDVSSPEED[1:0]
SW1BAPHASE[1:0]
SW1ABFREQ[1:0]
–
SW1ABILIM
0
x
x
0
0
x
x
0
–
0
–
0
–
0
–
0
SW2[6:0]
35
36
37
38
39
SW2VOLT
SW2STBY
SW2OFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx01_xx00
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SW2STBY[6:0]
x
SW2OFF[6:0]
x
x
–
0
x
x
–
0
SW2OMODE
0
SW2MODE[3:0]
SW2MODE
SW2CONF
1
0
0
SW2ILIM
0
SW2DVSSPEED[1:0]
SW2PHASE[1:0]
SW2FREQ[1:0]
–
x
x
0
1
x
0
–
0
–
0
–
0
SW3A[6:0]
3C
3D
3E
SW3AVOLT
SW3ASTBY
SW3AOFF
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SW3ASTBY[6:0]
x
SW3AOFF[6:0]
x
PF0200
NXP Semiconductors
91
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 120. Functional page (continued)
BITS[7:0]
Add Register name R/W
Default
7
6
5
4
–
0
3
2
0
x
1
0
SW3AOMODE
0
SW3AMODE[3:0]
3F
40
SW3AMODE
SW3ACONF
R/W
R/W
8'b0000_1000
0
0
1
0
–
0
0
SW3AILIM
0
SW3ADVSSPEED[1:0]
SW3APHASE[1:0]
SW3AFREQ[1:0]
8'bxx10_xx00
x
x
1
0
x
–
0
–
0
–
0
–
0
SW3B[6:0]
43
44
45
46
47
SW3BVOLT
SW3BSTBY
SW3BOFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx10_xx00
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
SW3BSTBY[6:0]
x
SW3BOFF[6:0]
x
x
–
0
x
x
–
0
x
SW3BOMODE
0
SW3BMODE[3:0]
SW3BMODE
SW3BCONF
1
x
0
–
0
0
SW3BILIM
0
SW3BDVSSPEED[1:0]
SW3BPHASE[1:0]
SW3BFREQ[1:0]
x
x
1
0
x
–
0
SWBST1STBYMODE[1:0]
–
0
SWBST1MODE[1:0]
SWBST1VOLT[1:0]
66
SWBSTCTL
R/W
8'b0xx0_10xx
x
x
1
0
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
–
VREFDDREN
–
0
–
0
–
0
–
0
–
0
6A
6B
6C
6D
6E
6F
70
71
VREFDDRCTL
VSNVSCTL
VGEN1CTL
VGEN2CTL
VGEN3CTL
VGEN4CTL
VGEN5CTL
VGEN6CTL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b000x_0000
8'b0000_0xxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
0
0
x
–
–
–
VSNVSVOLT[2:0]
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
VGEN1LPWR
VGEN1STBY
VGEN1EN
VGEN1[3:0]
VGEN2[3:0]
VGEN3[3:0]
VGEN4[3:0]
VGEN5[3:0]
VGEN6[3:0]
0
0
x
x
x
x
x
x
x
VGEN2LPWR
VGEN2STBY
VGEN2EN
0
0
x
VGEN3LPWR
VGEN3STBY
VGEN3EN
0
0
x
VGEN4LPWR
VGEN4STBY
VGEN4EN
0
0
x
VGEN5LPWR
VGEN5STBY
VGEN5EN
0
0
x
VGEN6LPWR
0
VGEN6STBY
0
VGEN6EN
x
–
0
–
0
–
0
PAGE[4:0]
0
7F
Page Register
R/W
8'b0000_0000
0
0
0
0
PF0200
92
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Extended page 1
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
6
–
0
5
–
0
4
–
x
3
–
x
2
–
x
1
–
x
0
OTP FUSE
READ EN
OTP FUSE READ
80
84
R/W
R/W
8'b000x_xxx0
EN
0
RL TRIM
FUSE
START
0
RL PWBRTN FORCE PWRCTL RL PWRCTL
RL OTP
0
RL OTP ECC RL OTP FUSE
OTP LOAD MASK
8'b0000_0000
0
0
0
0
0
0
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
ECC5_SE
ECC4_SE
ECC3_SE
ECC2_SE
ECC1_SE
8A
8B
8C
8D
OTP ECC SE1
OTP ECC SE2
OTP ECC DE1
OTP ECC DE2
R
R
R
R
8'bxxx0_0000
8'bxxx0_0000
8'bxxx0_0000
8'bxxx0_0000
0
0
0
0
0
ECC10_SE
ECC9_SE
ECC8_SE
ECC7_SE
ECC6_SE
0
0
0
0
0
ECC5_DE
ECC4_DE
ECC3_DE
ECC2_DE
ECC1_DE
0
0
ECC9_DE
0
0
ECC8_DE
0
0
ECC7_DE
0
0
ECC6_DE
0
ECC10_DE
0
–
0
–
0
–
0
–
0
SW1AB_VOLT[5:0]
x
A0
A1
A2
OTP SW1AB VOLT
OTP SW1AB SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxXx
8'b0000_xxxx
x
x
x
x
X
x
x
x
SW1AB_SEQ[4:0]
x
0
–
0
0
–
0
x
–
0
x
SW1_CONFIG[1:0]
SW1AB_FREQ[1:0]
OTP SW1AB
CONFIG
x
x
x
–
0
–
0
–
0
SW2_VOLT[5:0]
x
AC
AD
AE
OTP SW2 VOLT
OTP SW2 SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
–
0
–
0
x
x
x
x
x
x
x
x
SW2_SEQ[4:0]
0
–
0
x
–
0
x
–
0
x
–
0
SW2_FREQ[1:0]
OTP SW2 CONFIG
x
–
0
–
0
–
0
SW3A_VOLT[6:0]
x
B0
B1
B2
OTP SW3A VOLT
OTP SW3A SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_xxxx
x
–
0
–
0
x
x
x
x
x
x
x
SW3A_SEQ[4:0]
x
0
–
0
x
–
0
x
SW3_CONFIG[1:0]
SW3A_FREQ[1:0]
OTP SW3A
CONFIG
x
x
x
x
PF0200
NXP Semiconductors
93
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
–
0
6
5
4
3
2
1
x
x
0
x
x
SW3B_VOLT[6:0]
x
B4
B5
B6
OTP SW3B VOLT
OTP SW3B SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
–
0
–
0
x
x
x
SW3B_SEQ[4:0]
0
–
0
x
–
0
x
–
0
x
–
0
SW3B_CONFIG[1:0]
OTP SW3B
CONFIG
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
SWBST_VOLT[1:0]
BC
BD
OTP SWBST VOLT
OTP SWBST SEQ
R/W
R/W
8'b0000_00xx
8'b0000_xxxx
0
x
x
SWBST_SEQ[4:0]
x
0
x
x
x
–
0
–
0
–
0
–
0
–
0
VSNVS_VOLT[2:0]
x
C0
C4
OTP VSNVS VOLT
R/W
R/W
8'b0000_0xxx
8'b000x_x0xx
0
x
x
–
0
–
0
–
0
VREFDDR_SEQ[4:0]
0
OTP VREFDDR
SEQ
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN1_VOLT[3:0]
C8
C9
OTP VGEN1 VOLT
OTP VGEN1 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN1_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN2_VOLT[3:0]
CC
CD
OTP VGEN2 VOLT
OTP VGEN2 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN2_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN3_VOLT[3:0]
D0
D1
OTP VGEN3 VOLT
OTP VGEN3 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN3_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN4_VOLT[3:0]
D4
D5
OTP VGEN4 VOLT
OTP VGEN4 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN4_SEQ[4:0]
x
x
x
PF0200
94
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
6
–
0
–
0
5
–
0
–
0
4
–
0
3
x
x
2
1
0
x
x
VGEN5_VOLT[3:0]
D8
D9
OTP VGEN5 VOLT
OTP VGEN5 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
VGEN5_SEQ[4:0]
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN6_VOLT[3:0]
DC
DD
OTP VGEN6 VOLT
OTP VGEN6 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN6_SEQ[4:0]
x
x
x
PWRON_
CFG1
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SWDVS_CLK1[1:0]
SEQ_CLK_SPEED1[1:0]
E0
E1
E2
OTP PU CONFIG1
OTP PU CONFIG2
OTP PU CONFIG3
R/W
R/W
R/W
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
x
x
x
x
x
PWRON_
CFG2
SWDVS_CLK2[1:0]
SEQ_CLK_SPEED2[1:0]
x
x
x
x
x
PWRON_
CFG3
SWDVS_CLK3[1:0]
SEQ_CLK_SPEED3[1:0]
x
x
x
x
x
PWRON_CFG
_XOR
–
–
0
–
SWDVS_CLK3_XOR
SEQ_CLK_SPEED_XOR
OTP PU CONFIG
XOR
E3
R
8'b000x_xxxx
8'b0000_00x0
0
0
–
x
x
x
x
x
SOFT_FUSE_
POR
TBB_POR
–
–
–
FUSE_POR1
–
(76)
E4
OTP FUSE POR1
R/W
0
RSVD
0
0
RSVD
0
0
–
0
–
0
0
–
0
–
0
0
–
0
–
0
0
–
0
–
0
x
0
–
0
–
0
FUSE_POR2
(76)
E5
E6
OTP FUSE POR1
OTP FUSE POR1
R/W
R/W
8'b0000_00x0
8'b0000_00x0
x
RSVD
0
RSVD
0
FUSE_POR3
x
(76)
FUSE_POR_X
OR
RSVD
RSVD
–
–
–
–
–
OTP FUSE POR
XOR
E7
R
8'b0000_00x0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
x
–
x
0
OTP_PG_EN
0
E8
OTP PWRGD EN
R/W/M 8'b0000_000x
EN_ECC_
BANK5
EN_ECC_
BANK4
EN_ECC_
BANK3
EN_ECC_
BANK2
EN_ECC_
BANK1
–
0
–
0
–
0
–
0
–
0
–
0
F0
F1
OTP EN ECCO
OTP EN ECC1
R/W
R/W
8'b000x_xxxx
8'b000x_xxxx
x
x
x
x
x
EN_ECC_
BANK10
EN_ECC_
BANK9
EN_ECC_
BANK8
EN_ECC_
BANK7
EN_ECC_
BANK6
x
x
x
x
x
PF0200
NXP Semiconductors
95
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
–
0
–
0
6
–
0
–
0
–
0
–
0
5
–
0
–
0
–
0
–
0
4
–
0
–
0
–
0
–
0
3
2
1
0
x
x
RSVD
F4
F5
F6
F7
OTP SPARE2_4
OTP SPARE4_3
OTP SPARE6_2
OTP SPARE7_1
R/W
R/W
R/W
R/W
8'b0000_xxxx
8'b0000_0xxx
8'b0000_00xx
8'b0000_0xxx
x
–
0
–
0
–
0
x
x
RSVD
x
x
–
0
–
x
RSVD
x
–
x
x
RSVD
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
OTP_DONE
x
FE
FF
OTP DONE
R/W
R/W
8'b0000_000x
8'b0000_0xxx
I2C_SLV
ADDR[3]
–
0
–
0
–
0
–
0
I2C_SLV ADDR[2:0]
x
OTP I2C ADDR
1
x
x
Notes
76.
In PF0200 It is required to set all of the FUSE_PORx bits to be able to load the fuses.
Table 122. Extended page 2
BITS[7:0]
Address
Register Name
TYPE
Default
7
6
5
4
3
2
1
0
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW1AB_PWRSTG[2:0]
1
81
SW1AB PWRSTG
R/W
8'b1111_1111
1
1
RSVD
RSVD
RSVD
RSVD
RSVD
SW2_PWRSTG[2:0]
84
85
86
SW2 PWRSTG
SW3A PWRSTG
SW3B PWRSTG
R
R
R
8'b1111_1111
8'b1111_1111
8'b1111_1111
1
RSVD
1
1
RSVD
1
1
RSVD
1
1
RSVD
1
1
RSVD
1
1
1
1
1
1
1
1
SW3A_PWRSTG[2:0]
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW3B_PWRSTG[2:0]
1
FSLEXT_
THERM_
DISABLE
PWRGD_
SHDWN_
DISABLE
RSVD
RSVD
RSVD
RSVD
87
88
PWRCTRL
R
R
8'b0111_1111
8'b0000_0001
0
–
0
0
–
0
1
–
0
1
–
0
1
–
0
1
–
0
1
1
OTP_
SHDWN_EN
PWRGD_EN
PWRCTRL OTP
CTRL
0
0
1
I2C_WRITE_ADDRESS_TRAP[7:0]
I2C WRITE
ADDRESS TRAP
8D
R/W
8'b0000_0000
0
0
0
0
0
0
0
PF0200
96
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 122. Extended page 2 (continued)
BITS[7:0]
Address
Register Name
I2C TRAP PAGE
I2C TRAP CNTR
IO DRV
TYPE
R/W
Default
7
6
RSVD
0
5
RSVD
0
4
3
2
1
0
0
0
0
0
LET_IT_ ROLL
0
I2C_TRAP_PAGE[4:0]
0
8E
8F
90
8'b0000_0000
8'b0000_0000
8'b00xx_xxxx
0
0
I2C_WRITE_ADDRESS_COUNTER[7:0]
R/W
0
0
0
0
0
x
0
x
0
x
SDA_DRV[1:0]
SDWNB_DRV[1:0]
INTB_DRV[1:0]
RESETBMCU_DRV[1:0]
R/W
0
x
x
x
AUTO_ECC
_BANK5
AUTO_ECC AUTO_ECC_B AUTO_ECC AUTO_ECC_B
–
0
–
0
–
0
–
0
–
0
–
0
_BANK4
ANK3
_BANK2
ANK1
DO
D1
OTP AUTO ECC0
OTP AUTO ECC1
R/W
R/W
8'b0000_0000
8'b0000_0000
0
0
0
0
0
AUTO_ECC_B AUTO_ECC AUTO_ECC_B AUTO_ECCBA AUTO_ECC_B
ANK10
_BANK9
ANK8
NK7
ANK6
0
0
0
0
0
RSVD
RSVD
(77)
D8
Reserved
Reserved
–
–
8'b0000_0000
8'b0000_0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(77)
D9
ECC1_EN_
TBB
ECC1_CALC_
CIN
ECC1_CIN_TBB[5:0]
E1
E2
E3
E4
E5
E6
E7
E8
OTP ECC CTRL1
OTP ECC CTRL2
OTP ECC CTRL3
OTP ECC CTRL4
OTP ECC CTRL5
OTP ECC CTRL6
OTP ECC CTRL7
OTP ECC CTRL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ECC2_EN_
TBB
ECC2_CALC_
CIN
ECC2_CIN_TBB[5:0]
0
0
0
0
ECC3_EN_
TBB
ECC3_CALC_
CIN
ECC3_CIN_TBB[5:0]
0
0
0
0
ECC4_EN_
TBB
ECC4_CALC_
CIN
ECC4_CIN_TBB[5:0]
0
0
0
0
ECC5_EN_
TBB
ECC5_CALC_
CIN
ECC5_CIN_TBB[5:0]
0
0
0
0
ECC6_EN_
TBB
ECC6_CALC_
CIN
ECC6_CIN_TBB[5:0]
0
0
0
0
ECC7_EN_
TBB
ECC7_CALC_
CIN
ECC7_CIN_TBB[5:0]
0
0
0
0
ECC8_EN_
TBB
ECC8_CALC_
CIN
ECC8_CIN_TBB[5:0]
0
0
0
0
PF0200
NXP Semiconductors
97
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 122. Extended page 2 (continued)
BITS[7:0]
Address
Register Name
TYPE
Default
7
6
5
0
0
4
0
0
3
2
1
0
0
0
0
0
ECC9_EN_
TBB
ECC9_CALC_
CIN
ECC9_CIN_TBB[5:0]
E9
OTP ECC CTRL9
R/W
8'b0000_0000
0
0
0
0
ECC10_EN_T ECC10_CALC
ECC10_CIN_TBB[5:0]
BB
_CIN
EA
OTP ECC CTRL10
R/W
8'b0000_0000
0
0
0
0
ANTIFUSE1_E ANTIFUSE1_L ANTIFUSE1_R
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
BYPASS1
N
OAD
W
F1
F2
F3
F4
F5
F6
F7
F8
F9
OTP FUSE CTRL1
OTP FUSE CTRL2
OTP FUSE CTRL3
OTP FUSE CTRL4
OTP FUSE CTRL5
OTP FUSE CTRL6
OTP FUSE CTRL7
OTP FUSE CTRL8
OTP FUSE CTRL9
OTP FUSE CTRL10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
ANTIFUSE2_E ANTIFUSE2_L ANTIFUSE2_R
BYPASS2
N
OAD
W
0
0
0
0
ANTIFUSE3_E ANTIFUSE3_L ANTIFUSE3_R
BYPASS3
N
OAD
W
0
0
0
0
ANTIFUSE4_E ANTIFUSE4_L ANTIFUSE4_R
BYPASS4
N
OAD
W
0
0
0
0
ANTIFUSE5_E ANTIFUSE5_L ANTIFUSE5_R
BYPASS5
N
OAD
W
0
0
0
0
ANTIFUSE6_E ANTIFUSE6_L ANTIFUSE6_R
BYPASS6
N
OAD
W
0
0
0
0
ANTIFUSE7_E ANTIFUSE7_L ANTIFUSE7_R
BYPASS7
N
OAD
W
0
0
0
0
ANTIFUSE8_E ANTIFUSE8_L ANTIFUSE8_R
BYPASS8
N
OAD
W
0
0
0
0
ANTIFUSE9_E ANTIFUSE99_ ANTIFUSE9_R
BYPASS9
N
LOAD
W
0
0
0
0
ANTIFUSE10_ ANTIFUSE10_ ANTIFUSE10_
BYPASS10
0
EN
LOAD
RW
FA
0
0
0
Notes
77.
Do not write in reserved registers.
PF0200
98
NXP Semiconductors
TYPICAL APPLICATIONS
7
Typical applications
7.1
Introduction
Figure 24 provides a typical application diagram of the PF0200 PMIC together with its functional components. For details on component
references and additional components such as filters, refer to the individual sections.
7.1.1 Application diagram
SW1AB
output
VIN1
SW1FB
1.0uF
2.2uF
4.7uF
VIN1
VGEN1
VGEN2
Vin
4.7uF
PF0200
VGEN1
100mA
SW1AIN
SW1ALX
O/P
Drive
1.0uH
SW1A/B
Single
2500 mA
Buck
VGEN2
250mA
4 x 22uF
SW1BLX
SW1BIN
O/P
Drive
VIN2
1.0uF
2.2uF
VIN2
4.7uF
Vin
VGEN3
100mA
SW1VSSSNS
VGEN3
VGEN4
350mA
SW2
output
4.7uF
VGEN4
VIN3
VIN3
1.0uH
SW2LX
SW2IN
Core Control logic
1.0uF
2.2uF
O/P
Drive
SW2
1500 mA
Buck
VGEN5
100mA
SW2IN
2 x 22uF
4.7uF
Vin
SW2FB
GNDREF1
VGEN5
VGEN6
Initialization State Machine
VGEN6
200mA
2.2uF
SW3A
output
SW3AFB
OTP
Supplies
Control
Vin
4.7uF
SW3AIN
SW3ALX
VDDOTP
VDDIO
2 x 22uF
O/P
Drive
VDDOTP
VDDIO
1.0uH
1.0uH
SW3A/B
Single Phase
2500 mA
Buck
CONTROL
SW3BLX
SW3BIN
I2C
Interface
0.1uF
O/P
Drive
2 x 22uF
SCL
SDA
To
MCU
4.7uF
Vin
SW3BFB
SW3B
Output
DVS CONTROL
SW3VSSSNS
DVS Control
Vin
10uF
I2C
Register
map
2.2uH
1uF
Trim-In-Package
VCOREDIG
VCOREREF
SWBSTLX
SWBSTIN
SWBSTFB
SWBST
Output
SWBST
600 mA
Boost
220nF
1uF
O/P
Drive
Vin
Reference
Generation
Clocks and
resets
2 x 22uF
VCORE
GNDREF
1uF
VREFDDR
SW3A
VINREFDDR
100nF
100nF
Vin
Clocks
32kHz and 16MHz
Package Pin Legend
VHALF
Output Pin
Input Pin
Bi-directional Pin
VIN
Best
of
Supply
Li Cell
Charger
LICELL
+
-
100nF
VSNVS
Coin Cell
Battery
SW2
SW2
SW2
0.47uF
To/From
AP
Figure 24. PF0200 typical application schematic
PF0200
NXP Semiconductors
99
TYPICAL APPLICATIONS
7.1.2 Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the PF0200 Device. Critical
components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may
be used.
Table 123. Bill of materials (78)
Value
PMIC
Qty
Description
Part#
Manufacturer
Component/pin
1
Power management IC
PF0200
NXP
Buck, SW1AB - (0.300-1.875 V), 2.5 A
4 x 4 x 2.1
1.0 μH
1.0 μH
1
–
XFL4020-102MEB
LPS5015_102ML
Coilcraft
Coilcraft
Output Inductor
ISAT = 4.5 A for 10% drop, DCRMAX = 11.9 mΩ
5 x 5 x 1.5
Output Inductor
(Alternate)
ISAT = 3.6 A for 10% drop, DCRMAX = 50 mΩ
4 x 4 x 1.2
ISAT = 6.2 A, DCR = 37 mΩ
Output inductor
(Alternate)
1.0 μH
–
FDSD0412-H-1R0M
Toko
Output Inductor
(Alternate)
0.1 μF
22 μF
22 μF
–
4
2
3 x 3 x 1.5, ISAT = 4.5 A, DCR = 39 mΩ
10 V X5R 0805
74438335010
Wurth Elektronik
Taiyo Yuden
Murata
LMK212BJ226MG-T
GRM21BR61A226ME44L
Output capacitance
Output capacitance
(alternate)
10V, X5R 0805
4.7 μF
2
10 V X5R 0603
LMK107BJ475KA-T
Taiyo Yuden
Input capacitance
Input capacitance
(alternate)
4.7 μF
0.1 μF
1
1
10V X5R 0603
10 V X5R 0402
GRM155R61A104KA01D
C0402C104K8PAC
Murata
Kemet
Input capacitance
Buck, SW2- (0.400-3.300 V), 1.5 A
4 x 4 x 1.2
1.0 μH
1.0 μH
1
–
LPS4012-102NL
XFL3012-102ML
Coilcraft
Coilcraft
Output Inductor
ISAT = 2.8 A for 10% drop, DCRMAX = 60 mΩ
3x 3 1.2
Output Inductor
(Alternate)
ISAT = 2.5 A for 10% drop, DCRMAX = 42 mΩ
4 x 4 x 1.2
ISAT = 6.2 A, DCR = 37 mΩ
Output inductor
(Alternate)
1.0 μH
0.1 μF
–
–
FDSD0412-H-1R0M
74438335010
Toko
Output Inductor
(Alternate)
3 x 3 x 1.5, ISAT = 4.5 A, DCR = 39 mΩ
Wurth Elektronik
22 μF
4.7 μF
0.1 μF
2
1
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
Buck, SW3AB - (0.400-3.300 V), 2.5 A
4 x 4 x 2.1
1.0 μH
1.0 μH
1
–
XFL4020-102MEB
LPS5015_102ML
Coilcraft
Coilcraft
Output Inductor
ISAT = 4.5 A for 10% drop, DCRMAX = 11.9 mΩ
5 x 5 x 1.5
Output Inductor
(Alternate)
ISAT = 3.6 A for 10% drop, DCRMAX = 50 mΩ
PF0200
100
NXP Semiconductors
TYPICAL APPLICATIONS
Table 123. Bill of materials (78) (continued)
Value
Qty
Description
Part#
Manufacturer
Component/pin
4 x 4 x 1.2
ISAT = 6.2 A, DCR = 37 mΩ
Output inductor
(Alternate)
1.0 μH
–
FDSD0412-H-1R0M
Toko
Output Inductor
(Alternate)
0.1 μF
–
3 x 3 x 1.5, ISAT = 4.5 A, DCR = 39 mΩ
74438335010
Wurth Elektronik
22 μF
4.7 μF
0.1 μF
4
2
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
BOOST, SWBST - 5.0 V, 600 mA
3 x 3 x 1.5
2.2 μH
1
LPS3015-222ML
Coilcraft
Output Inductor
ISAT = 2.0 A for 10% drop, DCRMAX = 110 mΩ
3 x 3 x 1.2
ISAT = 3.1 A, DCR = 105 mΩ
Output inductor
(Alternate)
2.2 μH
2.2 μH
–
–
FDSD0312-H-2R2M
74438335022
Toko
Output Inductor
(Alternate)
3 x 3 x 1.5, ISAT = 3.5 A, DCR = 94 mΩ
Wurth Elektronik
22 μF
10 μF
2.2 μF
0.1 μF
1.0 A
2
1
1
1
1
10 V X5R 0805
10 V X5R 0805
6.3 V X5R 0402
10 V X5R 0402
20 V SOD-123FL
LMK212BJ226MG-T
C2012X5R1A106MT
C0402C225M9PACTU
C0402C104K8PAC
MBR120VLSFT1G
Taiyo Yuden
TDK
Output capacitance
Input capacitance
Input capacitance
Input capacitance
Schottky Diode
Kemet
Kemet
ON Semiconductor
LDO, VGEN1 - (0.80-1.55), 100 mA
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN2 - (0.80-1.55), 250 mA
4.7 μF 6.3 V X5R 0402
LDO, VGEN3 - (1.80-3.30), 100 mA
1
C0402X5R6R3-475MNP
Venkel
Output capacitance
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN4 - (1.80-3.30), 350 mA
4.7 μF 6.3 V X5R 0402
LDO, VGEN5 - (1.80-3.30), 150 mA
1
C0402X5R6R3-475MNP
Venkel
Output capacitance
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN6 - (1.80-3.30), 200 mA
2.2 μF 6.3 V X5R 0402
LDO/Switch VSNVS - (1.1-3.3), 200 mA
0.47 μF 6.3 V X5R 0402
Reference, VREFDDR - (0.20-1.65V), 10 mA
1
C0402C225M9PACTU
C1005X5R0J474K
Kemet
TDK
Output capacitance
Output capacitance
Output capacitance
1
1.0 μF
0.1 μF
1
2
10 V X5R 0402
10 V X5R 0402
CC0402KRX5R6BB105
C0402C104K8PAC
Yageo America
Kemet
VHALF,
VINREFDDR
PF0200
NXP Semiconductors
101
TYPICAL APPLICATIONS
Table 123. Bill of materials (78) (continued)
Value
Qty
Description
Part#
Manufacturer
Component/pin
Internal references, VCOREDIG, VCOREREF, VCORE
1.0 μF
1.0 μF
1
1
1
10 V X5R 0402
10 V X5R 0402
10 V X5R 0402
CC0402KRX5R6BB105
CC0402KRX5R6BB105
GRM155R61A224KE19D
Yageo America
VCOREDIG
VCORE
Yageo America
Murata
0.22 μF
VCOREREF
Coin cell
0.1 μF
1
10 V X5R 0402
C0402C104K8PAC
Kemet
LICELL
Miscellaneous
0.1 μF
1.0 μF
1
1
1
1
1
1
10 V X5R 0402
10 V X5R 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
C0402C104K8PAC
CC0402KRX5R6BB105
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
Kemet
VDDIO
VIN
Yageo America
KOA SPEER
KOA SPEER
KOA SPEER
KOA SPEER
100 kΩ
100 kΩ
100 kΩ
100 kΩ
Notes
PWRON
RESETBMCU
SDWN
INTB
78.
NXP does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables.
While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
7.2
PF0200 layout guidelines
7.2.1 General board recommendations
1. It is recommended to use an eight layer board stack-up arranged as follows:
• High current signal
• GND
• Signal
• Power
• Power
• Signal
• GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high-current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
7.2.2 Component placement
It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output
capacitors.
7.2.3 General routing requirements
1. Some recommended things to keep in mind for manufacturability:
•
•
•
•
Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
Minimum allowed spacing between line and hole pad is 3.5 mils
Minimum allowed spacing between line and line is 3.0 mils
PF0200
102
NXP Semiconductors
TYPICAL APPLICATIONS
2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power,
clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be
also shielded.
3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power
planes shield these traces).
4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node
(i.e. SW1ALX, SW1BLX, SW2LX, SW3ALX, SW3BLX, and SWBSTLX).
5. Make sure that all components related to a specific block are referenced to the corresponding ground.
7.2.4 Parallel routing requirements
1. I2C signal routing
•
CLK is the fastest signal of the system, so it must be given special care.
•
To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to
shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole
signal trace length.
Figure 25. Recommended shielding for critical signals
•
•
These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good
practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
7.2.5 Switching regulator layout recommendations
1. Per design, the switching regulators in PF0200 are designed to operate with only one input bulk capacitor. However, it is
recommended to add a high-frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor
should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low-inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
PF0200
NXP Semiconductors
103
TYPICAL APPLICATIONS
VIN
SWxIN
CIN_HF
CIN
SWx
SWxLX
Driver Controller
L
COUT
SWxFB
Compensation
Figure 26. Generic buck regulator architecture
Figure 27. Recommended layout for buck regulators
7.3
Thermal information
7.3.1 Rating data
The thermal rating data of the packages has been simulated with the results listed in Table 4.
Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for
junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) will be used for
both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and
2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org.
PF0200
104
NXP Semiconductors
TYPICAL APPLICATIONS
7.3.2 Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD)
with:
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four
layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See Functional block requirements and behaviors for more details on thermal management.
PF0200
NXP Semiconductors
105
PACKAGING
8
Packaging
8.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number. See the Thermal characteristics section for specific thermal characteristics
for each package.
Table 124. Package drawing information
Package
Suffix
Package outline drawing number
56 QFN 8x8 mm - 0.5 mm pitch. E-Type (full lead)
EP
ES
98ASA00405D
98ASA00589D
56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank)
PF0200
106
NXP Semiconductors
PACKAGING
PF0200
NXP Semiconductors
107
PACKAGING
PF0200
108
NXP Semiconductors
PACKAGING
PF0200
NXP Semiconductors
109
PACKAGING
PF0200
110
NXP Semiconductors
PACKAGING
PF0200
NXP Semiconductors
111
PACKAGING
PF0200
112
NXP Semiconductors
REVISION HISTORY
9
Revision History
Revision
Date
Description of changes
•
Initial release
3.0
2/2014
•
•
•
•
•
•
Corrected VDDOTP maximum rating
Corrected SWBSTFB maximum rating
Added note to clarify SWBST default operation in Auto mode
Changed VSNVS current limit
Noted that voltage settings 0.6 V and below are not supported
VSNVS Turn On Delay (tD1) spec corrected from 15 ms to 5.0 ms
4.0
5/2014
•
•
Updated VTL1, VTH1 and VSNVSCROSS threshold specifications
Updated per GPCN 16369
5.0
6.0
7.0
7/2014
•
•
Added new part number MMPF0200F6AEP to the Orderable Parts table
Added alternative capacitors in Bill of Materials
3/2015
8/2016
7/2019
•
Updated to NXP document form and style
•
•
Updated 98ASA00405D drawing as per PCN 201906034F01
Changed document status from Advance Information to Technical Data
PF0200
NXP Semiconductors
113
Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
Home Page:
NXP.com
Web Support:
http://www.nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
following address:
http://www.nxp.com/terms-of-use.html.
NXP, the NXP logo, Freescale, the Freescale logo, and SMARTMOS, are trademarks of NXP B.V. All other product
or service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2019.
Document Number: MMPF0200
Rev. 7
7/2019
相关型号：
©2020 ICPDF网 联系我们和版权申明