935311522574 [NXP]
Buffer/Inverter Based Peripheral Driver;
| 型号： | 935311522574 |
| 厂家： | 
NXP |
| 描述： | Buffer/Inverter Based Peripheral Driver 驱动 接口集成电路 |
| 文件： | 总30页 (文件大小：1442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33882
Rev. 11.0, 11/2014
escale Semiconductor
Technical Data
Six Output Low-side Switch with
SPI and Parallel Input Control
33882
The 33882 is a smart 6 output low-side switch able to control system
loads up to 1.0 A. The six outputs can be controlled via both serial
peripheral interface (SPI) and parallel input control, making the device
attractive for fault tolerant system applications. There are two
additional 30 mA low-side switches with SPI diagnostic reporting
(parallel input control only).
SIX OUTPUT LOW-SIDE SWITCH
The 33882 is designed to interface directly with industry standard
microcontrollers via SPI to control both inductive and incandescent
loads. Outputs are configured as open drain power MOSFETs
incorporating internal dynamic clamping and current limiting. The
device has multiple monitoring and protection features, including low
standby current, fault status reporting, internal 52 V clamp on each
output, output specific diagnostics, and protective shutdown.
Additionally, it has a mode select pin affording a dual means of input
control.
EK SUFFIX
(PB-FREE)
98ARL10543D
32-PIN SOICW
EP SUFFIX
(PB-FREE)
98ASA00706D
32-PIN QFN
VW SUFFIX
(PB-FREE)
98ASH70693A
30-PIN HSOP
ORDERING INFORMATION
Features
Device
• Outputs clamped for switching inductive loads
• Very low operational bias currents (< 2.0 mA)
• CMOS input logic compatible with 5.0 V logic levels
• Robust load dump (60 V transient at VPWR on OUT0–OUT5)
• Daisy chain operation of multiple devices possible
• Switch outputs can be paralleled for higher currents
• RDS(ON) of 0.4 per output (25 °C) at 13 V VPWR
• SPI operation guaranteed to 2.0 MHz
(For Tape and
Reel, add an R2
Suffix)
Temperature
Range (T )
A
Package
MC33882PVW
MC33882PEP
MC33882PEK
30 HSOP
32 QFN
-40 °C to 125 °C
32 SOICW-EP
VDD
VPWR
33882
VPWR
VDD
CS
OUT0
OUT1
OUT2
High Power
Outputs
SCLK
SI
OUT3
MCU
OUT4
OUT5
OUT6
OUT7
SO
Low Power
LED
Outputs
IN0
IN1
IN2
IN0 & IN1
IN2 & IN3
IN4 & IN5
MODE
IN3
Optional Parallel
Control of
Outputs 0 through 7
Optional Control
of Paired Outputs
IN4
IN5
IN6
IN7
GND
Figure 1. 33882 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2006 - 2014. All rights reserved.
RNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
1 (VPWR
)
16 (VDD
)
12 (SI)
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
Over-voltage
Shutdown
Under-voltage Internal
V
DD
Shutdown
Bias
On Open
Detect
Logic
3 (MODE
)
OUT6
Gate 7
and OUT7
Unclamped
Low
18 (IN7)
29 (IN6)
27 (IN5)
17 (OUT7)
30 (OUT6)
Gate 6
Power
Gate 5
Gate 4
26 (OUT5)
23 (OUT4)
20 (OUT3)
OUT1
to OUT5
High
24 (IN4)
28 (IN4 & IN5)
21 (IN3)
Gate 3
Gate 2
Gate 0
Power
10 (OUT2)
7 (OUT1)
5 (OUT0)
9 (IN2)
52 V
19 (IN2 & IN3)
6 (IN1)
Gate 0
V
REF
4 (IN0)
Output 0 Status
I
LIM
Output Status
1 through 7
2 (IN0 & IN1)
GND (Heat Sink)
0
1
2
3
4
5
6
7
Serial In
SO Fault Latch/Shift Register
Serial Out
OFF/ON
Open
Load
Detect
13 (SCLK)
14 (CS)
V
DD
V
OF (th)
Shift
Enable
3.0 A
3.0 V
Tri-state
Load
Short
Detect
I
15 (SO)
O(OFF)
40 A
Note Pin numbers shown in this figure are applicable only to the 30-lead HSOP package.
Figure 2. 33882 Simplified Internal Block Diagram
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
CONNECTIONS
PIN CONNECTIONS
TRANSPARENT TOP VIEW
TRANSPARENT TOP VIEW
VPWR
IN0&IN1
MODE
IN0
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT6
2
IN6
3
IN4&IN5
IN5
4
GND
1
2
3
4
5
6
7
8
IN4&IN5
IN6
24
23
22
21
20
19
18
17
OUT7
VDD
GND
GND
GND
GND
SO
OUT0
IN1
5
OUT5
NC
6
OUT1
NC
7
IN4
8
OUT4
NC
HEATSINK
OUT6
GND
IN2
9
OUT2
NC
10
11
12
13
14
15
IN3
OUT3
IN2&IN3
IN7
SI
HEATSINK
GND
SCLK
CS
OUT7
VDD
VPWR
IN0&IN1
MODE
SO
CS
30 PIN HSOP
TRANSPARENT TOP VIEW
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
NC
VDD
GND
NC
SO
CS
SCLK
SI
OUT2
IN2
OUT1
IN1
OUT0
IN0
MODE
IN0&IN1
VPWR
GND
32 PIN QFN
OUT7
IN7
IN2&IN3
OUT3
IN3
OUT4
IN4
OUT5
IN5
IN4&IN5
IN6
OUT6
GND
HEATSINK
9
10
11
12
13
14
15
16
32 PIN SOIC
Figure 3. HSOP, QFN, and SOIC Pin Connections
Table 1. HSOP Pin Function Description
30 Pin
HSOP
32 Pin 32 Pin
Pin Name
Formal Name
Definition
QFN
SOIC
This pin is connected to battery voltage. A decoupling cap is required from
VPWR to ground.
1
6
18
VPWR
Load Supply Voltage
These input pins control two output channels each when the MODE pin is
pulled high. These pins may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE pin is high. The states of these pins
are ignored during normal operation (MODE pin low), and override the
normal inputs (serial or parallel) when the MODE pin is high. These pins
have internal active 25 A pull-downs.
2
19
28
7
26
1
19
6
13
IN0 & IN1
IN2 & IN3
IN4 & IN5
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
The MODE pin is connected to the MODE pin of the control IC. This pin has
3
8
20
MODE
Mode Select
an internal active 25 A pull-up.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
3
Freescale Semiconductor
CONNECTIONS
Table 1. HSOP Pin Function Description (continued)
30 Pin
HSOP
32 Pin 32 Pin
Pin Name
Formal Name
Definition
QFN
SOIC
These are parallel control input pins. These pins have internal 25 A active
pull-downs.
4
6
9
18
21
24
27
29
9
21
23
25
5
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
Input 0–Input7
11
13
25
28
30
32
2
8
10
12
14
Each pin is one channel's drain, sinking current for the respective load.
5
7
10
12
14
24
27
29
31
3
22
24
26
4
7
9
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
Output 0–Output7
10
17
20
23
26
30
11
15
Not connected.
8, 11, 22,
25
2,31
NC
No Connect
Serial Input
The Serial Input pin is connected to the SPI Serial Data Output pin of the
control IC from where it receives output command data. This input has an
internal active 25 A pull-down and requires CMOS logic levels.
12
15
16
27
SI
The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It
transitions one time per bit transferred when in operation. It is idle between
command transfers. It is 50% duty cycle, and has CMOS levels.
13
28
SCLK
Serial Clock
This pin is connected to a chip select output of the control IC. This input has
an internal active 25 A pull-up and requires CMOS logic levels.
14
15
17
18
29
30
CS
SO
Chip Select
This pin is connected to the SPI Serial Data Input pin of the control IC or to
the SI pin of the next device in a daisy chain. This output will remain tri-
stated unless the device is selected by a low CS pin or the MODE pin goes
low. The output signal generated will have CMOS logic levels and the output
data will transition on the falling edges of SCLK. The serial output data
provides fault information for each output and is returned MSB first when the
device is addressed.
Serial Output
This pin is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from VDD to ground.
16
23
3
VDD
GND
Logic Supply Voltage
Ground
Ground continuity is required for the outputs to turn on. The heat sink must
be electrically connected to GND.
Heat
Sink
4,5,19- 1,16,17,
22 32
(exposed
pad)(1)
Notes
1. The exposed pad on this package provides the circuit ground connection for the IC.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Limit
ELECTRICAL RATINGS
Load Supply Voltage
V
V
25
Normal Operation (Steady-state)
PWR(SS)
V
-1.5 to 60
Transient Survival (2)
Logic Supply Voltage (3)
Input Pin Voltage (4)
PWR(T)
V
-0.3 to 7.0
V
V
V
DD
V
-0.3 to VDD + 0.3
IN
Output Clamp Voltage (OUT0 to OUT5) (5)
20 mA = IO = 0.2 A
V
O(OFF)
48 to 64
Output Self-limit Current
OUT0 to OUT5
I
A
V
O(LIM)
3.0 to 6.0
OUT6 and OUT7
0.05 to 0.15
ESD Voltage (HSOP, QFN, and SOIC)
Human Body Model (6)
V
V
±2000
±200
ESD1
ESD2
Machine Model (7)
Output Clamp Energy (8)
E
mJ
CLAMP
OUT0 to OUT5: Single Pulse at 1.5 A, TJ = 150C
OUT6 and OUT7: Single Pulse at 0.45 A, TJ = 150C
100
50
Maximum Operating Frequency (SPI) SO (9)
THERMAL RATINGS
f
3.2
MHz
OF
Storage Temperature
T
-55 to 150
-40 to 150
Note 11
C
STG
Operating Junction Temperature
T
C
J
Peak Package Reflow Temperature During Reflow (10)
,
TPPRT
(11)
°C
Notes
2. Transient capability with external 100 resistor in series with the VPWR pin and supply.
3. Exceeding these voltages may cause a malfunction or permanent damage to the device.
4. Exceeding the limits on any parallel inputs or SPI pins may cause permanent damage to the device.
5. With output OFF.
6. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 ).
ZAP
ZAP
7. ESD2 testing is performed in accordance with the Machine Model (C
=200 pF, R
=0 ).
ZAP
ZAP
8. Maximum output clamp energy capability at indicated junction temperature using a single pulse method.
9. Serial Frequency Specifications assume the IC is driving 8 tri-stated devices (20 pF each).
10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Limit
(13)
THERMAL RESISTANCE (12)
,
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (14)
R
C/W
JA
41
85
72
HSOP
QFN
SOIC
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (15)
R
C/W
C/W
C/W
JMA
18
27
TBD
HSOP
QFN
SOIC(17)
Junction-to-Board (Bottom)
R
JB
HSOP
QFN
SOIC(17)
3.0
10
TBD
Junction-to-Case (Top) (16)
R
JC
HSOP
QFN
SOIC
0.2
1.2
1.0
Notes
12. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
14. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
15. Per JEDEC JESD51-6 with the board horizontal.
16. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC
883, Method 1012.1) with the cold plate temperature used for the case temperature.
17. This value will be included when available.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 17 V, -40 C TA 125 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Ranges
V
V
V
Functional Threshold (18)
Full Operation
PWR
PWR
4.5
8.0
4.5
5.5
–
8.0
25
VDD
Logic Supply Voltage
5.0
5.5
V
Supply Current (All Outputs ON) (19)
I
mA
PWR
PWR(ON)
IO = 1.0 A Each
–
–
7.5
Over-voltage Shutdown (20)
V
30
0.4
2.5
–
–
–
40
1.5
3.5
V
V
PWR(OV)
Over-voltage Shutdown Hysteresis (21)
V
PWR(OV)HYS
(22)
Power-ON Reset Threshold, VDD
V
V
POR
Logic Supply Current (All Outputs ON)
VDD = 5.5 V
I
mA
DD
–
–
5.0
POWER OUTPUT
Output Drain-to-Source ON Resistance
R
A
DS(ON)
DS(ON)
O(LIM)
OUT0 to OUT5: TJ = 150°C, V
PWR
= 13.0 V, IO = 1.0 A
–
–
0.6
0.4
0.8
0.6
Output Drain-to-Source ON Resistance
R
I
OUT0 to OUT5: TJ = 25°C, V
Output Self-limiting Current
= 13.0 V, IO = 1.0 A
PWR
V
= 13.0 V, VDD = 4.5 V, VIN = 5.0 V
3.0
2.5
–
–
6.0
3.5
PWR
Open Load OFF Detection (Outputs Programmed OFF)
V
I
V
OFF(TH)
O(OFF)
Output OFF (Open Load Detect) Drain Current (Output Pins
Programmed OFF) (23)
A
OUT0 to OUT5
20
20
–
–
120
80
OUT6 and OUT7
Output ON (Open Load Detect) Drain Current (Output Pins Programmed
ON) (24)
–
mA
V
20
48
–
200
64
Output Clamp Voltage
V
I
OK
OUT0 to OUT5: IO = 20 mA, tCLAMP = 100 s
52
Output Leakage Current
A
OLK
VDD = VPWR = 0.5 V, VOUT = 24 V
–
1.0
10
Drain-to-Source Diode Forward Voltage
ISD = 1.0 mA @ 25 °C
V
V
SD
–
–
–
–
1.4
0.9
ISD = 1.0 mA @ 125 °C
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 17 V, -40 C TA 125 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
SI Logic High
SIV
SIV
4.0
–
–
–
–
–
–
–
–
2.0
–
V
V
IH
IL
SI Logic Low
CS and SCLK Logic High
CS and SCLK Logic Low
Input Logic High
CSV
CSV
3.0
–
V
IH
IL
3.0
–
V
V
V
3.15
–
V
IH
IL
Input Logic Low
1.35
V
Input Pull-down Current (25)
VIN = 1.5 V
I
I
A
IN(PD)
5.0
-25
3.5
0
–
–
–
–
25
-5.0
–
Input Pull-up Current (26)
VIN = 3.5 V
A
V
IN(PU)
SO and High-state Output Voltage
IOH = -1.0 mA
V
V
I
SOH
SOL
SO and Low-state Output Voltage
IOL = 1.0 mA
V
0.4
SO and Tri-state Leakage Current
CS = 0.7 VDD, VSO = 0.3 VDD
CS = 0.7 VDD, VSO = 0.7 VDD
A
SOT
-10
–
–
–
–
10
Input Capacitance (27)
0 = VIN = 5.5 V
C
pF
pF
IN
–
–
–
–
12
20
SO and Tri-state Capacitance (28)
0 = VIN = 5.5 V
C
SOT
Notes
18. Outputs of device functionally turn-on (RDS(ON) = 0.95 @125 °C). SPI/parallel inputs and power outputs are operational. Fault
detection and reporting may not be fully operational within this range.
19. Value reflects all outputs ON and equally conducting 1.0 A each. V
= 5.5 V, CS = 5.0 V.
PWR
20. An over-voltage condition will cause any enabled outputs to latch OFF (disabled).
21. This parameter is guaranteed by design; however, it is not production tested.
22. For VDD less than the Power-ON Reset voltage, all outputs are disabled and the serial fault register is reset to all 0s.
23. Drain current per output with VPWR = 24 V and VLOAD = 9.0 V.
24. Drain current per output with V
= 13 V, VLOAD = 9.0 V.
PWR
25. Inputs SI, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7 incorporate active internal pull-down current sinks for noise immunity
enhancement.
26. The MODE and CS inputs incorporate active internal pull-up current sources for noise immunity enhancement.
27. This parameter applies to inputs SI, CS, SCLK, MODE, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7. It is guaranteed by design;
however, it is not production tested.
28. This parameter applies to the OFF state (tri-stated) condition of SO and is guaranteed by design; however, it is not production tested.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 17 V, -40 C TA 125C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (29)
Output Fall Time (29)
t
1.0
1.0
1.0
1.0
–
–
–
–
10
10
10
10
s
s
s
s
s
R
t
F
Output Turn-ON Delay Time (30)
Output Turn-OFF Delay Time (31)
Output Short Fault Sense Time (32)
t
DLY(ON)
t
DLY(OFF)
t
SS
R
= < 1.0 V
25
–
100
LOAD
Output Short Fault Refresh Time (33)
= < 1.0 V
t
ms
REF
R
3.0
4.5
6.0
LOAD
Output OFF Open Load Sense Time (34)
Output ON Open Load Sense Time (35)
Output Short Fault ON Duty Cycle (36)
t
25
3.0
60
–
100
12
s
ms
%
OS(OFF)
t
OS(ON)
SC
0.42
–
3.22
DC
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) (37)
SCLK Clock Low Time (SCLK = 3.2 MHz) (37)
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time (37)
t
–
–
–
–
141
141
ns
ns
ns
SCLKH
SCLKL
t
t
LEAD
–
–
140
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time (37)
t
ns
LAG
–
–
50
SI, CS, SCLK Incoming Signal Rise Time (37)
SI, CS, SCLK Incoming Signal Fall Time (37)
t
–
–
–
–
50
50
ns
ns
RSI
FSI
t
Notes
29. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 resistive load to a V
BAT
of 15 V, V
= 15 V.
PWR
30. Output Turn-ON Delay Time measured from rising edge (3.0 V) V (CS for serial) to 90% V using a 15 load to a V of 15 V,
BAT
IN
O
V
= 15 V.
PWR
31. Output Turn-OFF Delay Time measured from falling edge (1.0 V) V (3.0 V rising edge of CS for serial) to 10% V using a 15 load
IN
O
to a V
of 15 V, V
= 15 V.
BAT
PWR
32. The shorted output is turned ON during t to retry and check if the short has cleared. The shorted output is in current limit during t
.
SS
SS
The t is measured from the start of current limit to the end of current limit.
SS
33. The Short Fault Refresh Time is the waiting period between t retry signals. The shorted output is disabled during this refresh time.
SS
The t
is measured from the end of current limit to the start of current limit.
REF
34. The t
is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
OS(OFF)
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 s after the faulted output is off.
35. The t is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault
OS(ON)
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
36. Percent Output Short Fault ON Duty Cycle is defined as (t ) (t ) x 100. This specification item is provided FYI and is not tested.
SS
REF
37. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 17 V, -40 C TA 125C, unless otherwise
noted.
Characteristic
Symbol
Min
–
Typ
–
Max
45
–
Unit
SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
Required Setup Time (38)
t
ns
SISU
SO Setup to SCLK Rising (2.0 V)/Falling (0.8 V) Edge
Required Setup Time (38)
t
ns
ns
ns
ns
ns
SOSU
90
–
–
SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
Required Hold Time (38)
t
SIHOLD
–
45
–
SO Hold After SCLK Rising (2.0 V)/Falling (0.8 V) Edge
Required Hold Time (38)
t
SOHOLD
90
–
SO Rise Time
CL = 200 pF
t
t
RSO
FSO
–
–
–
50
50
SO Fall Time
CL = 200 pF
–
Falling Edge of CS (0.8 V) to SO Low-impedance (39)
Rising Edge of CS (2.0 V) to SO High-impedance (40)
Falling Edge of SCLK (0.8 V) to SO Data Valid
CL = 200 pF at 3.2 MHz (41)
t
–
–
–
–
110
110
ns
ns
ns
SOEN
t
SODIS
t
SOVALID
–
–
65
–
80
CS Rising Edge to Next Falling Edge (38)
Xfer DELAY
1.0
s
Notes
38. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
39. Enable time required for SO. Pull-up resistor = 10 k.
40. Disable time required for SO. Pull-up resistor = 10 k.
41. Time required to obtain valid data out of SO following the falling edge of SCLK.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
5.0 V
0 V
Input X
ON
Gate X
G
OFF
Normal
Operation
IO(LIM)
ILOAD
I
X
OUT
0 A
Fault Bit X
F
Shorted Load/Short-to-VPWR
5.0V
I
Input X
0 V
ON
OFF
Gate X
T
tSSA
tSSD
tSSD
IO(LIM)
0A
ILOAD
I
X
Shorted
Operation
OUT
tREF
tREF
tREF
tREF
Fault Bit X
Fault
Fault
F
C
CB
Gate X = Command Signal at the Gate of Driver X
Fault Bit X = Internal Fault Register Bit State
tREF X = First Refresh Time may be less than tREF
ILOAD = 1.0 A
Figure 4. Short Occurring While On, Ending During Refresh (ILOAD = 1.0 A)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CTRICAL CHARACTERISTICS
TIMING DIAGRAMS
5.0 V
Input X
0 V
ON
Gate X
OFF
Normal
Operation
IO(LIM)
ILOAD
X
I
OUT
0 A
Fault Bit X
Shorted Load/Short-to-VPWR
0V
5.0 V
Input X
ON
Gate X
OFF
T
tSSD
tSSA
tSSD
IO(LIM)
Shorted
Operation
I
X
ILOAD
OUT
tREF
tREF
tREF
tREF
0 A
Fault Bit X
Fault
Fault
CB
Gate X = Command Signal at the Gate of Driver X
Fault Bit X = Internal Fault Register Bit State
tREF X = First Refresh Time may be less than tREF
ILOAD = 1.0 A
Figure 5. Short Occurring While On, Ending During Retry (ILOAD = 1.0 A)
0V
5.0 V
Input X
ON
Gate X
Normal
Operation
OFF
IO(LIM)
ILOAD
I X
OUT
0 A
Fault Bit X
ShortedLoad/Short-to-VPWR
5.0 V
0 V
Input X
ON
Gate X
OFF
TSSD
tSSD
tSSA
IO(LIM)
I
X
ILOAD
OUT
tREF
tREF
tREF
tREF
Shorted
Operation
0 A
Fault Bit X
Fault
Fault
CB
Gate X = Command Signal at the Gate of Driver X
Fault Bit X = Internal Fault Register Bit State
tREF X = First Refresh Time may be less than tREF
ILOAD = 20 mA
Figure 6. Short Occurring While On, Ending During Refresh (ILOAD = 20 mA)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
5.0 V
Input X
0 V
ON
Gate X
OFF
Normal
Operation
IO(LIM)
ILOAD
I X
OUT
0A
Fault Bit X
Shorted Load/Short-to-VPWR
5.0 V
0 V
Input X
ON
Gate X
OFF
tTSSSASA
T
tSSD
tSSD
IO(LIM)
ILOAD
Shorted
Operation
I
X
OUT
tREF
tREF
tREF
tREF
0 A
Fault Bit X
Fault
Fault
CB
Gate X = Command Signal at the Gate of Driver X
Fault Bit X = Internal Fault Register Bit State
tREF X = First Refresh Time may be less than tREF
ILOAD = 20 mA
Figure 7. Short Occurring While On, Ending During Retry (ILOAD = 20 mA)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
R
DS(ON)
0.43
0.42
0.41
0.4
VCLAMP
55.0
54.8
54.6
54.4
0.39
0.38
0.37
0.36
0.35
54.2
54.0
53.8
53.6
25
40
55
70
85
100
115
130
53.4
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (
C)
RDS(ON)
Figure 8. Output RDS(ON) Versus Temperature
Figure 9. Output Clamp Voltage Versus Temperature
Table 5. Logic Table
Status
Status
Command
Sent
Input Pins
5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0
Gates
Outputs
Mode of Operation
Transmitted Transmitted Mode Pin IN0&IN1 IN4&IN5
SO
Next SO
Normal Operation
00111111
00000000
00111111
001Y1010
000101Y1
00YYY000
L
L
L
L
X
X
X
X
X
X
X
X
X X X X X X H H H H H H L L L L L L
X H X L X L H H H L H L L L L H L H
L X L X H X L H L H H H H L H L L L
H H H L L L H H H L L L L L L H H H
001X1010 00000000
000101X1 00000000
00XXX000 00000000
Default Mode
00XXXXXX 11111111
00XXXXXX 11111111
00XXXXXX 11111111
00XXXXXX 11111111
11111111
11111111
11111111
11111111
H
H
H
H
H
H
L
H
L
X X H L X X H H H L H H L L L H L L
X X L H X X H H L H L L L L H L H H
X X H L X X L L H L H H H H L H L L
X X L H X X L L L H L L H H H L H H
H
L
L
Over-voltage Shutdown
00XXXXXX 00XXXXXX 00XXXXXX
X
X
X
X X X X X X L L L L L L H H H H H H
Short-to-Battery/
Short-circuit Output 0
00XXXXX0 00000000
00XXXXX1 00000001
00YYYYY0
00YYYYY0
L
L
X
X
X
X
X X X X X L Y Y Y Y Y L Y Y Y Y Y H
X X X X X X Y Y Y Y Y H Y Y Y Y Y H
Open Load/
Short-to-Ground Output 0
00XXXXX0 00000001
00XXXXX1 00000000
00YYYYY1
00YYYYY1
L
L
X
X
X
X
X X X X X L Y Y Y Y Y L Y Y Y Y Y L
X X X X X X Y Y Y Y Y H Y Y Y Y Y L
Legend
0011XXYY = Serial (SPI) commands and status bytes (8-bit operation mode) MSB to LSB.
0 = Off command, SO OK status.
1 = On command, SO FAULT status.
X = Don’t care.
Y = Defined by state of X.
H = High-voltage level: Active state for inputs/gates, inactive state for outputs.
L = Low-voltage level: Inactive state for inputs/gates, active state for outputs.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33882 incorporates six 1.0 A low-side switches using
both Serial Peripheral Interface (SPI) I/O as well as optional
parallel input control to each output. There are also two low-
power (30 mA) low-side switches with SPI diagnostic
feedback, but parallel-only input control. The 33882
bipolar/MOS analog circuitry, and DMOS power MOSFETs.
Designed to interface directly with a microcontroller, it
controls inductive or incandescent loads. Each output is
configured as an open drain transistor with dynamic
clamping.
incorporates SMARTMOS technology with CMOS logic,
FUNCTIONAL PIN DESCRIPTION
corresponding SPI control bit to control each output channel.
These pins have internal 25 A active pull-downs.
VPWR PIN
The VPWR pin is connected to battery voltage. This supply
is provided for over-voltage shutdown protection and for
added gate drive capabilities. A decoupling capacitor is
required from VPWR to ground.
OUT0 TO OUT7 PINS
Each pin is one channel's low-side switch output. OUT0 to
OUT5 are actively clamped to handle inductive loads.
IN0 & IN1, IN2 & IN3, AND IN4 & IN5 PINS
SI PIN
These input pins control two output channels each when
the MODE pin is pulled high: IN0 & IN1 controls OUT0 and
OUT1, IN2 & IN3 controls OUT2 and OUT3, while IN4 & IN5
controls OUT4 and OUT5. These pins may be connected to
PWM outputs of the control IC and pulled high or pulled low
to control output channel states while the MODE pin is high.
The states of these pins are ignored during normal operation
(MODE pin low) and override the normal inputs (serial or
parallel) when the MODE pin is high. These pins have internal
active 25 A pull-downs.
The Serial Input pin is connected to the SPI Serial Data
Output pin of the control IC from where it receives output
command data. This input has an internal active 25 A pull-
down and requires CMOS logic levels. The serial data
transmitted on this line is an 8- or 16-bit control command
sent MSB first, controlling the six output channels. Bits A5
through A0 control channels 5 through 0, respectively. Bits
A6 and A7 enable ON open load fault detection on channels
5 through 0. The control IC will ensure that data is available
on the rising edge of SCLK. Each channel has its serial
control bit high with its parallel input to determine its state.
MODE PIN
The MODE pin is connected to the MODE pin of the control
IC. This pin has an internal active 25 A pull-up. When pulled
high, the MODE pin does the following:
SCLK PIN
The SCLK pin of the control IC is a bit (shift) clock for the
SPI port. It transitions one time per bit transferred when in
operation. It is idle between command transfers. It is 50%
duty cycle and has CMOS levels. This signal is used to shift
data to and from the device. For proper fault reporting
operation, the SCLK input must be low when CS transitions
from high to low.
• Disables all serial control of the outputs while still reading
any serial input commands.
• Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5
control of the outputs.
• Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input pins for
control of OUT0 and OUT1, OUT2 and OUT3, OUT4 and
OUT5, respectively.
CS PIN
• Turns off OUT6 and OUT7.
The CS pin is connected to a chip select output of the
control IC. The control IC controls which device is addressed
by pulling the CS pin of the desired device low, enabling the
SPI communication with the device, while other devices on
the serial link keep their serial outputs tri-stated. This input
has an internal active 25 A pull-up and requires CMOS logic
levels.
• Tri-states the SO pin.
IN0 TO IN7 PINS
These are parallel input pins connected to output pins of
the control IC. Each parallel input is logic high with the
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
CTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
representing no faults. If a fault is present, a 1 is returned for
the appropriate bit. In 16-bit SPI mode, sending a double
command byte will provide a command verification byte
following the fault status byte returned from the SO pin (non-
daisy chained). With the MODE pin high, the serial output pin
tri-states. If nothing is connected to the SO pin except an
external 10 k pull-up resistor, data is read as all [1]s by the
control IC.
SO PIN
The Serial Output pin is connected to the SPI Serial Data
Input pin of the control IC or to the SI pin of the next device in
a daisy chain. This output will remain tri-stated unless the
device is selected by a low CS pin or the MODE pin goes low.
The output signal generated will have CMOS logic levels and
the output data will transition on the falling edges of SCLK.
The serial output data provides fault information for each
output and is returned MSB first when the device is
addressed. Fault bit assignments for return data are as
follows: MSB-0 through MSB-7 are output fault bits for OUT7
to OUT0, respectively. In 8-bit SPI mode, under normal
conditions, the SO pin (not daisy chained) returns all 0s,
VDD PIN
This pin is connected to the 5.0 V power supply of the
system. A decoupling capacitor is required from VDD to
ground.
PERFORMANCE FEATURES
NORMAL OPERATION
SERIAL STATUS OUTPUT
OUT0 to OUT7 are independent during normal operation.
OUT0 to OUT5 may be driven serially or by their parallel input
pins. OUT6 and OUT7 can only be controlled by their parallel
input pins. Device operation is considered normal only if the
following conditions apply:
Serial output information sent on the SPI port is a check on
the fault status of each output channel as well as a check for
MODE initiation. Serial command verification is also possible.
SO PIN OPERATION
• VPWR of 5.5 V to 24 V, and VDD voltage of 4.75 V to 5.25 V.
• Junction temperatures less than 150 C.
The SO pin provides SPI status, allowing daisy chaining.
The status bits returned to the IC are the fault register bits
with logic [1]s indicating a fault on the designated output or
MODE if all bits return logic [1] (with a 10 k pull-up resistor
on the SO pin). A command verification is possible if the SPI
mode is switched to 16 bits. The first byte (8 bits) returned
would be the fault status, while the second byte returned
would be the first byte sent feeding through the 33882 IC.
• For each output, drain voltage exceeds the Open Load
OFF Detection Voltage, specified in the specification table,
while the output is OFF. For open load detection, an open
condition existing for less than the Open Load Detection
time, specified in the specification table, is not considered
a fault nor is it reported to the fault status register.
• The MODE pin is held at the logic low level, keeping the
serial channel/parallel input pins in control of the eight
outputs.
The second command byte sent would be latched into the
33882 IC. The CS pin switching low indicates the device is
selected for serial communication with the IC. Once CS
switches low, the fault status register cannot receive new
fault information and serial communication begins. As the
control bits are clocked from the IC MSB first, they are
received on rising SCLK edges at the SI pin.
SERIAL/PARALLEL INPUT CONTROL
Input control is accomplished by the serial control byte
sent via the SPI port from the control IC or by the parallel
control pins for each channel. For channels 0 to 5 with serial
and parallel control the output state is determined by the OR
of the serial bit and the parallel input pin state. Serial
communication is initiated by a low state on the CS pin and
timed by the SCLK signal. After CS switches low, the IC
initiates eight or 16 clock pulses with the control bits being
available on the SI pin at the rising edge of SCLK.
The fault status bits transition on the SO pin on falling
SCLK edges and are sampled on rising SCLK edges at the
input pin of the IC SPI device. When the command bit
transmissions for serial communication are complete, the CS
pin is switched high. This terminates communication with the
device. The SO pin tri-states, the fault status register is
opened to accept new fault information, and the transmitted
command data is loaded to the outputs. At the same time, the
IC can read the status byte it received.
The bits are transferred in descending bit-significant
order. Any fault or MODE indications on bits returned are logic
[1]s. The last six bits are the command signals to the six
outputs. Upon completion of the serial communication the CS
pin will switch high. This terminates the communication with
the slave device and loads the control bits just received to the
output channels. Upon device power-up, the serial register is
cleared.
DAISY CHAIN OPERATION (ONLY POSSIBLE WITH
SO PIN)
Daisy chain configurations can be used with the SO pin to
save CS outputs on the IC. Clocking and pin operations are
as defined in the SO Pin Operation paragraph. For daisy
chaining two 8-bit devices, a 16-bit SPI command is sent, the
first command byte for the second daisy chain device and the
second command byte for the first daisy chain device. A
command verification is possible if the SPI mode is switched
In the application for non-daisy chain configurations, the
number of SPI devices available to be driven by the SO pin is
limited to eight devices.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
to 32 bits. The first word sent is command verification data
fed through the two 33882 ICs. Data returned in the 32 bits is
the two fault status bytes, followed by the first word sent. Bits
sent out are sampled on rising SCLK edges at the input pin
of the next IC in the daisy chain.
normal condition. When the CS pin is pulled low for serial
communication, the fault bits in the internal fault register
latch, preventing erroneous status transmissions and the
forthcoming communication reports this latched fault status.
The SO pin serial output data for 8-bit SPI mode are the fault
status register bits.
Note Because SO pins of the 33882 ICs are tri-stated,
any device receiving its SPI data from a previous 33882 IC
SO pin in a daisy chain will not receive data if the MODE pin
is low. This prohibits setting SPI-controlled channels ON with
a SPI command while the MODE pin is low. Therefore, all
channels remain OFF when the MODE pin changes from low
to high at vehicle power-up.
For 16-bit SPI mode and SO pin (non-daisy chained) use,
a transmitted double command provides the fault byte
followed by the first byte of the double command, becoming
a command verification. The status is sent back to the IC for
fault monitoring. Diagnostic interpretation of the following
fault types can be accomplished using the procedure
described in the paragraph entitled Extensive Fault
Diagnostics:
MODE OPERATION
• Communication error
• Open load/short-to-ground
• Short-to-battery or short-circuit
During normal operation output channels are controlled by
either the Serial Input control bits or the parallel input pins. If
the MODE pin is pulled high:
• Serial input control is disabled.
• Parallel input pins IN0 to IN5 are ignored.
• The SO pin is tri-stated.
When serial communication is ended, the CS pin returns
high, opening the fault status register to new fault information
and tri-stating the SO pin.
Two fault conditions initiate protective action by the device:
OUT0 and OUT1, OUT2 and OUT3, and OUT4 and OUT5
are controlled by the IN0 & IN1, IN2 & IN3, and IN4 & IN5
pins, respectively. When a 10 kpull-up resistor is used, a
logic high on the MODE pin or an open serial output pin is
flagged by the SPI when all bits are returned as logic [1]s.
• A short-circuit or short-to-battery on a particular output will
cause that output to go into a low duty cycle operation until
the fault condition is removed or the input to that channel
turns OFF.
• A short-circuit condition causes all channels to shut down,
ignoring serial and parallel inputs to the device.
Although a logic high on the MODE pin disables serial
control of outputs, data can still be clocked into the serial
input register. This allows programming of a desired state for
the outputs taking effect only when the MODE pin returns to a
logic low. For applications using the SO pin, daisy chaining is
permitted, but if the MODE pin is high, writing to other than the
first IC in a daisy chain is not possible because the serial
outputs are tri-stated.
To be detected and reported as a fault, a fault condition
must last a specified time (fault sense time or fault mask
time). This prevents any normal switching transients from
causing inadvertent fault status indications.
Fault status information should be ignored for VBAT levels
outside the 9.0 V to 17 V range. The fault reporting may
appear to function properly but may not be 100 percent
reliable.
OUTPUT DRIVERS
The high power OUT0 to OUT5 outputs are active
clamped, low-side switches driving 1.0 A typical or less loads.
The low-power OUT6 and OUT7 outputs are unclamped low-
side switches driving 30 mA typical or less loads. All outputs
are individually protected from short circuit or short-to-battery
conditions and transient voltages. The outputs are also
protected by short-circuit device shutdown. Each output
individually detects and reports open load/short-to-ground
and short-circuit/short-to-battery faults.
SHORT-CIRCUIT/SHORT-TO-BATTERY SENSING
AND PROTECTION
When an output is turned ON, if the drain current limit is
reached, the current remains at the limit until the short-circuit
sense time, tSS, has elapsed. At this time, the affected output
will shut down and its fault status bit switches to a logic [1].
The output goes into a low duty cycle operation as long as the
short-circuit condition exists and the input to that channel is
ON.
FAULT SENSE/PROTECTION CIRCUITRY
This duty cycle is defined by the sense and refresh times.
If a short occurs after the output is ON, the fault sense time
indicates the fault and enters the low duty cycle mode at
much less than tSS. The duty cycle is low enough to keep the
driver from exceeding its thermal capabilities. When the short
is removed, the driver resumes normal operation at the next
retry, but the fault status bit does not return to a normal
logic [0] state until it is read from the SPI. When the CS pin of
this device is pulled low, the fault status bits are latched, after
which any new fault information is not a part of this serial
communication event.
Each output channel individually detects shorted loads/
short-to-battery while the output is ON and open load/short-
to-ground while the output is OFF. OUT0 to OUT5 may also
be programmed via SPI bits 6 and 7 to detect open loads and
shorts-to-ground while the output is ON. Whenever a short or
open fault condition is present on a particular output channel,
its fault bit in the internal fault register indicates the fault with
a logic [1].
When a fault ends, its fault bit remains set until the SPI
register is read, then it returns to a logic [0], indicating a
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
CTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
The low duty cycle operation for a short-circuit condition is
required to protect the output. It is possible to override this
duty cycle if the input signal (parallel or SPI) turns the channel
ON and OFF faster than 10 kHz. For this reason control
signals should not exceed this frequency.
all logic [1]s are again returned, there is an open SO line, an
open MODE line, or the SPI is not functioning.
If the fault does not verify on the command resend, normal
operation is resumed. The error could be a communication
mistake, a momentary output fault, or a fault condition no
longer sensed due to switching the state of the output. For the
first two cases, normal operation is resumed and the software
continues its normal functions. However in the third case,
additional commands are required for extensive diagnosis of
the fault type, if this information is mandatory.
OPEN LOAD/SHORT-TO-GROUND WHILE OFF
SENSING
If the drain voltage falls below the Open Load OFF
Detection Voltage at turn OFF for a period of time exceeding
the Open Load Sense Time, the fault status bit for this output
switches to a logic [1].
EXTENSIVE FAULT DIAGNOSTICS
More extensive diagnosis may be required under the
following conditions:
If a drain voltage falls below the Open Load OFF Detection
Voltage threshold when the output has been OFF, a fault is
indicated with a delay much less than the Open Load Sense
Time. When the fault is removed, normal operation resumes
and the fault status bit will return to a normal logic [0] state.
When the CS pin of this device is pulled low, the fault status
bits are latched, after which any new fault information is not
part of this serial communication event.
• When the fault type of a confirmed fault is desired, the
following scenarios are possible:
–
If MSB-2 to MSB-7 indicates a fault, it is an open
load/short-to-ground fault if the output is OFF when
the fault is reported because only open load/short-
to-ground sensing remains operable while an output
is OFF.
OVER-VOLTAGE SENSING AND PROTECTION
–
If the output is ON when the fault is reported, the
fault is a short-circuit/short-to-battery if ON open
load detection is not enabled via SPI. If ON open
load detection is enabled, it must be disabled and
the fault status reread. If the fault remains, it is a
short-circuit/short-to-battery or it is an open load/
short-to-ground.
When VPWR exceeds the Over-voltage Shutdown
Threshold, all channels are shut down. Serial input data and
parallel inputs are ignored. The device resumes normal
operation when the VPWR voltage drops below the Over-
voltage Shutdown Hysteresis voltage. During over-voltage
shutdown, some faults may appear to report accurately;
however, fault sensing operation is only guaranteed for
battery voltage levels from 9.0 V to 17 V.
–
–
If MSB-0 to MSB-2 indicates a fault, it is an open
load/short-to-ground fault if the output is OFF when
the fault is reported because only open load/short-
to-ground sensing remains operable while an output
is OFF.
FAULT STATUS MONITORING REQUIREMENTS
FOR SERIALLY CONTROLLED OUTPUTS, SO PIN
Fault monitoring over the serial channel by the IC requires
a minimal amount of overhead for normal operation. Each
status byte received consists of all logic [0]s when faults are
not present. If any logic [1]s are returned, a communication
error occurred, an output fault occurred, or the MODE pin has
been set low. Upon receiving any logic [1] bits, the IC must
resend the last command, verifying the returned logic [1]s, or
correct any communication error.
If the output is ON when the fault is reported, the
fault is a short-circuit/short-to-battery.
• When a fault did not confirm on resend, the fault could
either be an short-circuit/short-to-battery fault, not sensed
when turned OFF; an open load/short-to-ground fault, not
sensed when turned ON; or a corrected communication
error.
To determine if it is an output fault condition, the faulted
output must be turned back to its previous state with a new
command. This command should be sent twice to read the
status after the output is latched in this state, thus
confirming the fault and reporting it again.
A 16-bit SPI transmission with a double command byte to
this 8-bit device allows verification of the command (second
byte returned) in addition to the fault byte (first byte returned).
The command (second) byte returned should mirror the bits
sent unless a communication error occurred, in which case
the command resent should accomplish the correction.
Parallel control of outputs is a mode of control, potentially
requiring extensive diagnostics if a fault is reported. This is
because parallel control signals are completely
asynchronous to the serial commands. Status reports for
parallel controlled outputs could require additional
information exchange in software to:
If the returned logic [1] validates, it may indicate a MODE
pin high or a confirmed output fault. If it was a confirmed
output fault, extensive diagnostics could be performed,
determining the fault type, especially if vehicle service is
being performed. If all bits return high and verify such, the IC
must verify sending a logic low to the MODE pin. It should
then resend the command, verifying the MODE pin is at a
logic low level, allowing resumption of a normal operation. If
• Avoid status reads when outputs are transitioned, thereby
avoiding fault masking times.
• Obtain the state of a faulted output for determining fault
type (if required).
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
SYSTEM ACTUATOR ELECTRICAL
POWER-UP
CHARACTERISTICS (AT ROOM TEMPERATURE)
The device is insensitive to power sequencing for VPWR
and VDD, as well as intolerant to latch-up on all I/O pins.
Upon power-up, an internal power-ON reset clears the serial
registers, allowing all outputs to power up in the off-state
when parallel control pins are also low. Although the serial
register is cleared by this power-ON reset, software must still
initialize the outputs with an SPI command prior to changing
the MODE pin from a high to a low state. This assures known
output states when MODE is low.
All drains should have a 0.01 F filter capacitor connected
to ground. Any unused output pin should not be energized. A
20 resistor to the battery is required to prevent false open
load reporting. There must also be a maximum of 100 of
resistance from VPWR to ground, keeping battery-powered
loads OFF when the IC is powered down. However, all loads
should be powered by VPWR to protect the device from full
transient voltages on the battery voltage.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
KAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. Dimensions
shown are provided for reference ONLY.
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
KAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
KAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
KAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
KAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
REVISION HISTORY
PACKAGE DIMENSIONS (CONTINUED)
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Implemented Revision History page
• Added Thermal Addendum
9/2005
3.0
• Converted to Freescale format
5/2006
• Updated ordering information block on page 1
• Updated data sheet format
4.0
5.0
10/2006
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Ratings on page 5. Added note with instructions to obtain this information
from www.freescale.com.
6/2009
3/2011
• Changed Supply Voltage in Static Electrical Characteristics, Table 4, on page 9
6.0
7.0
• New Fab transfer devices added. No electrical parameter changes.
• Removed Part Numbers MC33882FC/R2, MC33882EK/R2, MC33882VW, and
MC33882EP, and replaced with part numbers MC33882PVW, MC33882PEP.
• Added EK package to the ordering information and supporting data
• Removed all DH suffix information.
• Corrected HSOP 98A reference number and associated information
• Update the Packaging section 98A drawings
• In 33882 Simplified Application Diagram on page 1, added OUT2, changed the direction
of arrow for the SI pin and connected the SO pin to MCU
5/2012
8.0
• In Table 3, Static Electrical Characteristics on page 7, changed VDD Supply Current (All
Outputs ON) to VPWR Supply Current (All Outputs ON)
• Updated Freescale form and style
6/2012
6/2013
11/2014
• Updated part number PC33882EK to MC33882EK in the Ordering Information Table.
• Updated part number MC33882EK to MC33882PEK in the Ordering Information Table.
• Updated the QFN package from 98ARH99032A to 98ASA00706D as per PCN 16521
9.0
10.0
11.0
MC33882 Data Sheet, Rev. 11.0, 11/2014
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
Information in this document is provided solely to enable system and software implementers to use Freescale products.
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2014 Freescale Semiconductor, Inc.
Document Number: MC33882
Rev. 11.0
11/2014
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