935313028518 [NXP]
RISC Microcontroller;
| 型号： | 935313028518 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总133页 (文件大小：1493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: KL82P121M72SF0
Rev. 4, 12/2016
Kinetis KL82 Microcontroller
MKL82Z128Vxx7(R)
72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB
SRAM
The KL82 MCU family's high performance, encryption features
and ultra-low power capabilities extend its reach beyond
traditional mPOS pin pads and terminals into more power-
restricted payment applications, such as smartphone and tablet
attach readers, as well as those embedded in wearable
technology.
100 & 80 & 64 LQFP
(LL&LK&LH)
14x14 x1.7 mm Pitch
121 & 64 MAPBGA
(MC&MP)
8x8x1.43 mm Pitch 0.5mm 12x12x1.6 mm
0.65 mm 5x5x1.23 mm
Pitch 0.5 mm
Pitch 0.5 mm
10x10x1.6 mm Pitch
0.5 mm
The product offers:
• Hardware asymmetric cryptography – high-speed, code-
and power-efficient data authentication with support for
latest encryption protocols
• EMV®-compatible with ISO7816-3 SIM interfaces – architected for EMV compliance and supported by
an EMV Level 1 software stack
• QSPI interface to expand program memory
• Sleep mode power consumption from 2.5 µA with the SRAM content retained and RTC enabled
• Crystal-less USB OTG controller, 16-bit ADC and multiple serial communication interfaces can all
function autonomously in low-power modes with minimal CPU intervention
• FlexIO to support any standard and customized serial peripheral emulation
Core Processor
Peripherals
• USB full-speed 2.0 OTG controller supporting
• 72 MHz ARM® Cortex®-M0+ core ( up to 96 MHz for high-
speed run)
crystal-less operation and keeping connection
alive under ultra-low power
Memories
• Three low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules supporting up to 1 Mbps
• Two 16-bit SPI modules supporting up to
24Mbps
• 128 KB program flash memory
• 96 KB SRAM
• 32 KB ROM with built-in boot loader
• 32 B backup register
• QSPI to expand program code in external high-speed serial
NOR flash memory
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, I2S, PWM and
other serial modules, etc. up to 32 channels
• One 16-bit ADC module with high accurate
internal voltage reference and up to 16
channels
System
• 8-channel asynchronous enhanced DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin serial wire debug (SWD) programming and
debugging interface
• Micro trace buffer
• Bit manipulation engine
• Interrupt controller
• High-speed analog comparator containing a 6-
bit DAC for programmable reference input
• One 12-bit DAC module
• Two EMVSIM modules supporting EMV L1
compatible interface
• Touch sensing interface up to 16 channels
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Memory protection unit
• SRAM bit-banding
I/O
• Up to 85 General-purpose input/output pins
(GPIO)
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference clock Operating Characteristics
for high-speed run
• Voltage range: 1.71 to 3.6 V
• 4 MHz high accuracy (up to 2%) internal reference clock for
low-speed run
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
• 32 kHz internal reference clock
• 1 kHz internal reference clock
• 32–40 kHz and 3–32 MHz crystal oscillator
• PLL/FLL
Low Power
• Down to 125 µA/MHz in Run mode
• Down to 272 nA in Stop mode (RAM and RTC
retained)
Timers
• Six flexible static modes
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• Two low-power timers
• 4-channel periodic interrupt timer
• Independent real time clock
Packages
• 121 MAPBGA 8mm x 8mm, 0.65mm pitch,
1.43mm max thickness
• 80 LQFP 12mm x 12mm, 0.5mm pitch, 1.6mm
max thickness
Security
• 100 LQFP 14mm x 14mm, 0.5mm pitch,
1.7mm max thickness (Package Your Way)
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch,
1.23mm max thickness (Package Your Way)
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
max thickness (Package Your Way)
• 128-bit unique identification number per chip
• Advanced flash security and access control
• Hardware CRC module
• Low-power trusted crypto engine supporting AES128/256,
DES, 3DES, SHA256, RSA and ECC, with hardware DPA
• True random number generator
NOTE
The 100-, 64-pin LQFP and 64-pin MAPBGA packages supporting
MKL82Z128VLL7, MKL82Z128VLH7 and MKL82Z128VMP7 part numbers for this
product are not yet available. However, these packages are included in Package Your
Way program for Kinetis MCUs. Visit nxp.com/KPYW for more details.
Related resources
Type
Description
Resource
Solution Advisor
Selector Guide The NXP Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Reference
Manual
The Reference Manual contains a comprehensive description of the KL82P121M72SF0RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL82P121M72SF01
Chip Errata
The chip mask set Errata provides additional or corrective information xN51R2
for a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
MAPBGA 121-pin: 98ASA00423D
MAPBGA 64-pin: 98ASA00420D
LQFP 100-pin: 98ASS23308W
LQFP 80-pin: 98ASS23174W
LQFP 64-pin: 98ASS23234W
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the "x" replaced
by the revision of the device you are using.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
3
NXP Semiconductors
Table of Contents
1 Ordering information............................................................... 5
4.3.7
4.3.8
Communication interfaces.................................48
Human-machine interfaces (HMI)..................... 51
2 Overview................................................................................. 5
2.1 System features...............................................................7
4.4 KL82 Pinouts................................................................... 51
4.5 Package dimensions....................................................... 57
5 Electrical characteristics..........................................................64
5.1 Terminology and guidelines.............................................64
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
ARM Cortex-M0+ core...................................... 7
NVIC..................................................................7
AWIC.................................................................7
Memory............................................................. 8
Reset and boot..................................................9
Clock options.....................................................11
Security............................................................. 14
Power management..........................................15
LLWU................................................................ 16
5.1.1
5.1.2
5.1.3
5.1.4
Definitions......................................................... 65
Examples.......................................................... 65
Typical-value conditions....................................66
Relationship between ratings and operating
requirements..................................................... 66
Guidelines for ratings and operating
5.1.5
2.1.10 Debug controller................................................18
2.1.11 INTMUX............................................................ 18
2.1.12 Watch dog.........................................................18
2.2 Peripheral features.......................................................... 19
requirements..................................................... 67
5.2 Ratings............................................................................ 67
5.2.1
5.2.2
5.2.3
5.2.4
Thermal handling ratings...................................67
Moisture handling ratings..................................68
ESD handling ratings........................................ 68
Voltage and current operating ratings...............68
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
BME.................................................................. 19
eDMA and DMAMUX........................................ 19
TPM...................................................................20
ADC...................................................................21
VREF.................................................................21
CMP.................................................................. 22
RTC...................................................................22
PIT.....................................................................23
LPTMR..............................................................23
5.3 General............................................................................69
5.3.1
5.3.2
5.3.3
5.3.4
AC electrical characteristics..............................69
Nonswitching electrical specifications...............69
Switching specifications.................................... 83
Thermal specifications...................................... 84
5.4 Peripheral operating requirements and behaviors...........86
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Core modules....................................................86
Clock modules...................................................88
Memories and memory interfaces.....................95
Security and integrity modules..........................101
Analog...............................................................101
Timers............................................................... 112
Communication interfaces.................................112
Human-machine interfaces (HMI)..................... 123
2.2.10 CRC.................................................................. 24
2.2.11 LPUART............................................................24
2.2.12 SPI.................................................................... 25
2.2.13 I2C.....................................................................25
2.2.14 USB...................................................................26
2.2.15 FlexIO................................................................27
2.2.16 DAC...................................................................27
2.2.17 EMV-SIM...........................................................28
2.2.18 LTC................................................................... 29
2.2.19 TRNG................................................................29
2.2.20 TSI.....................................................................29
2.2.21 QuadSPI............................................................30
3 Memory map........................................................................... 30
4 Pinouts.................................................................................... 32
4.1 KL82 signal multiplexing and pin assignments................32
4.2 Pin properties.................................................................. 37
4.3 Module signal description tables..................................... 42
6 Design considerations.............................................................124
6.1 Hardware design considerations..................................... 124
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations.............124
Power delivery system...................................... 124
Analog design................................................... 125
Digital design.....................................................126
Crystal oscillator................................................128
6.2 Software considerations.................................................. 130
6.3 Soldering temperature..................................................... 131
7 Part identification.....................................................................131
7.1 Description.......................................................................131
7.2 Format............................................................................. 131
7.3 Fields............................................................................... 131
7.4 Example...........................................................................132
8 Revision history.......................................................................132
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Core Modules....................................................42
System modules................................................42
Clock Modules...................................................44
Memories and memory interfaces.....................44
Analog...............................................................45
Timer Modules.................................................. 46
4
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Part number
Memory
Package
IO and ADC channel
Marking
Flash
SRAM
(KB)
Pin Package GPIOs
count
GPIOs
(INT/
ADC
channels
(SE/DP)
(KB)
(Line1/Line2)
HD)1
MKL82Z128VMC7(R)
MKL82
128
96
121
MAPBGA
85
85/0
16/2
Z128VMC7
MKL82Z128VLL7(R)
MKL82Z128VLK7(R)
MKL82Z128VL
L7
128
128
96
96
100
80
LQFP
LQFP
66
56
66/0
56/0
14/1
12/1
MKL82Z128
VLK7
MKL82Z128VMP7(R)
MKL82Z128VLH7(R)
M82N7V
MKL82Z128V
LH7
128
128
96
96
64
64
MAPBGA
LQFP
41
41
41/0
41/0
11/1
11/1
1. INT: interrupt pin numbers; HD: high drive pin numbers
NOTE
The 100-, 64-pin LQFP and 64-pin MAPBGA packages supporting
MKL82Z128VLL7, MKL82Z128VLH7 and MKL82Z128VMP7 part
numbers for this product are not yet available. However, these packages
are included in Package Your Way program for Kinetis MCUs. Visit
nxp.com/KPYW for more details.
2 Overview
The following figure shows the system diagram of this device
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
5
NXP Semiconductors
Overview
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
128 KB
Flash
FMC
Slave
Master
Cortex M0+
TSI0
S0
S1
ADC0(16-bit 16-ch)
CMP0
IOPORT
32 KB ROM
M0
1.2V Voltage reference
Debug
(SWD)
CM0+ core
TPM0(6-channel)
TPM1(2-channel)
TPM2(2-channel)
LPTMR0
96 KB
RAM
Bit
Band
NVIC
S3
LPTMR1
QSPI0
2 KB
PIT0
M2
RTC
DMA
MUX
DMA
S2a
LPUART0
LPUART1
LPUART2
SPI0
USB SRAM
M3
S2b
SPI1
USB FS/LS
BME
I2C0
I2C1
FlexIO0
EMVSIM0
EMVSIM1
MCG
VBAT Register File(128B)
LP Trusted Cryptographic 0
TRNG0
IRC 4MHz
IRC 32kHz
PLL
Watchdog
EWM
IRC 48M
OSC
Register File(32 Bytes)
CRC
RTC OSC
FLL
LLWU
RCM
SMC
PMC
INTMUX0
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
6
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
2.1 System features
The following sections describe the high-level system features.
2.1.1 ARM Cortex-M0+ core
The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors
targeting microcontroller cores focused on very cost sensitive, low power
applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC
component. It also has hardware debug functionality including support for simple
program trace capability. The processor supports the ARMv6-M instruction set
(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus
seven 32-bit instructions. It is upward compatible with other Cortex-M profile
processors.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to
15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait
and VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect
asynchronous wake-up events in Stop mode and signal to clock control logic to
resume system clocking. After clock restarts, the NVIC observes the pending interrupt
and performs the normal interrupt or event processing. The AWIC can be used to
wake MCU core from Stop and VLPS modes.
Wake-up sources are listed as below:
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
7
NXP Semiconductors
Overview
Table 2. AWIC Partial Stop, Stop and VLPS wake-up sources
Wake-up source
Description
RESET_b pin and WDOG when LPO is its clock source, and Debug
Power mode controller
Available system resets
Low-voltage detect
Low-voltage warning
Pin interrupts
Power mode controller
Port control module - any enabled pin interrupt is capable of waking the system
The ADC is functional when using internal clock source
ADC0
CMPx
Since no system clocks are available, functionality is limited, trigger mode provides wakeup
functionality with periodic sampling
I2Cx
Address match wakeup
LPUARTx
Functional when using clock source which is active in Stop and VLPS modes
USB FS/LS Controller
Wakeup
FlexIO0
LPTMR
RTC
Functional when using clock source which is active in Stop and VLPS modes
Functional when using clock source which is active in Stop, VLPS and LLS/VLLS modes
Functional in Stop/VLPS modes
TPM
Functional when using clock source which is active in Stop and VLPS modes
Wakeup
TSI0
NMI
Non-maskable interrupt
2.1.4 Memory
This device has the following features:
• 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into two arrays
• 128 KB of embedded program memory
• 32 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI
interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program flash
is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents from
debug port.
• System register file
8
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the
footnote, is reset by the corresponding Reset source. N
means the specific module is not reset by the corresponding
Reset source.
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC SIM SMC RCM LLWU Reset
RTC1 LPTMR Other
s
pin is
negated
POR reset
Power-on reset (POR)
Y
N
Y
Y2
Y
N
Y
Y
Y
N
Y
Y3
N
N
Y
N
Y
Y
System reset Low leakage wakeup
(LLWU) reset
External pin reset (RESET)
Y
Y
Y2
Y2
Y4
Y4
Y
Y5
Y
Y
Y
Y
N
N
N
N
Y
Y
Computer operating
properly (COP) watchdog
reset
Stop mode acknowledge
error (SACKERR)
Y
Y2
Y4
Y5
Y
Y
N
N
Y
Software reset (SW)
Lockup reset (LOCKUP)
Y
Y
Y
Y
Y2
Y2
Y2
Y2
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
MDM DAP system reset
Debug reset Debug reset
1. The VBAT POR asserts on a VBAT POR reset source. It affects only the modules withinthe VBAT power domain: RTC
and VBAT Register File. These modules are notaffected by the other reset types.
2. Except SIM_SOPT1
3. Only if RESET is used to wake from VLLS mode.
4. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
5. Except RCM_RPFC, RCM_RPFW, RCM_FM
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
9
NXP Semiconductors
Overview
The CM0+ core adds support for a programmable Vector Table Offset Register
(VTOR) to relocate the exception vector table after reset. This device supports booting
from:
• internal flash
• ROM
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains read-
only bits that are loaded from the NVM's option byte in the flash configuration field.
Below is boot flow chart for this device.
POWER ON
Power On Reset(POR)
Reset to Processor
FOPT [BOOTSRC_SEL]:
BOOTPIN_OPT=0?
No
00 = Internal Flash
01 = Reserved
10 = ROM -> QSPI Yes
11 = ROM -> QSPI No
Yes
[BOOTSRC_SEL] = 0x
Configure and boot
from internal flash.
Boot from On-
Chip Flash?
BOOTCFG
Pin assert?
No
Yes
[BOOTSRC_SEL] =1x
RESET module
BOOT ROM module
Load BCA
(Boot Configuration Area)
No
[BOOTSRC_SEL] =11
Configure
QSPI ?
Yes
[BOOTSRC_SEL] =10
No
Peripheral
detect mode or boot pin
No
QSPI
present?
asserted?
Yes
Yes
Config Failure
Image Download with timeout
Configure QSPI
Jump to PC in vector table
Figure 2. Boot Flow For Devices with QSPI
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
10
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
If booting from ROM, the device executes in boot loader mode or proceeds with a
secondary boot to a QSPI device connected to QSPI0.
2.1.6 Clock options
This chip provides a wide range of sources to generate the internal clocks. These
sources include internal resistor capacitor (IRC) oscillators, external oscillators,
external clock sources, ceramic resonators, phase-locked loop (PLL) and frequency-
locked loop (FLL). These sources can be configured to provide the required
performance and optimize the power consumption.
The IRC oscillators include the 48 MHz internal resister capacitor (IRC48M)
oscillator, the 4 MHz internal resister capacitor (4 MHz IRC) oscillator, the 32 kHz
internal resister capacitor (32 kHz IRC) oscillator, and the low power oscillator
(LPO).
The 48 MHz internal resister capacitor (IRC48M) oscillator generates a 48 MHz clock
and synchronizes with the USB clock in full speed mode to achieve the required
accuracy.
The 4 MHz internal resister capacitor (4 MHz IRC) oscillator generates a 4 MHz
clock. It can serve as the low power, low speed system clock under very low power
run (VLPR) mode or very low power wait (VLPW) mode. It can also be provided as
clock source for other on-chip modules. The 4 MHz IRC cannot be used in any VLLS
modes.
The 32 kHz internal resister capacitor (32 kHz IRC) oscillator generates a 32 kHz
clock. It can be used as FLL internal reference clock or can be provided as low power
clock source to other on-chip modules. The 32 kHz IRC cannot be used in any VLLS
modes.
The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode.
The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high
frequency crystals (1 MHz to 32 MHz), and ceramic resonators (1 MHz to 32 MHz).
An external clock source, DC to 48 MHz, can be used as the system clock through the
EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768
kHz) on the RTC_CLKIN pin for use with the RTC.
The frequency-locked loop (FLL) can generate clock up to four programmable
different frequency ranges (20–25 MHz, 40–50 MHz, 60–75 MHz or 80–100 MHz)
with low speed (31.25–39.0625 kHz) internal or external reference clock. The FLL
can be used as the system clock or clock source for other on-chip modules.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
11
NXP Semiconductors
Overview
The phase-locked loop (PLL) can generate up to 144 MHz high speed, low jitter clock
with 8–16 MHz internal or external reference clock. The PLL can be used as the system
clock or clock source for other on-chip modules.
For more details on the clock operations and configurations, see Reference Manual.
MCG
SIM
FCRDIV
4 MHz IRC
32 kHz IRC
Clock options for
some peripherals
(see note)
MCGIRCLK
MCGFFCLK
CG
FLL
OUTDIV1
CG
CG
CG
CG
Core / system clocks
Bus clock
OUTDIV2
OUTDIV4
OUTDIV5
MCGOUTCLK
Flash clock
PLL
QSPI bus interface clock
MCGFLLCLK
MCGPLLCLK
FRDIV
MCGPLLCLK/
MCGFLLCLK/
PRDIV
IRC48MCLK/
System oscillator
EXTAL0
XTAL0
OSCCLK
DIV_OSCERCLK
DIV
XTAL_CLK
OSCERCLK
CG
OSC
logic
OSC32KCLK
ERCLK32K
PMC
RTC oscillator
LPO
32.768 kHz
1Hz
EXTAL32
XTAL32
PMC logic
OSC logic
RTC_CLKOUT
IRC48M
IRC48MCLK
IRC48M logic
IRC48MCLK
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.
Figure 3. Clocking diagram
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
12
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
The following table summarizes the clocks associated with each module.
Table 4. Module clocks
Module
Bus interface clock
Internal clocks
I/O interface clocks
Core modules
ARM Cortex-M0+ core
System clock
System clock
System clock
Core clock
—
—
NVIC
DAP
—
—
SWD_CLK
System modules
DMA
System clock
Bus clock
—
—
—
—
—
—
—
—
DMAMUX
Port control
Bus clock
LPO
—
Crossbar Switch
Peripheral bridges
System clock
System clock
Bus clock
Bus clock
LPO
LLWU, PMC, SIM,
RCM
Mode controller
INTMUX
Bus clock
Bus clock
—
—
—
—
—
—
—
MCM
System clock
Bus clock
—
EWM
LPO
LPO
Watchdog timer
Bus clock
Clocks
MCG
Flash clock
MCGOUTCLK,
—
MCGPLLCLK, MCGFLLCLK,
MCGIRCLK, OSCERCLK
OSC
Bus clock
—
OSCERCLK
IRC48MCLK
—
—
IRC48M
Memory and memory interfaces
Flash controller
Flash memory
QSPI controller
System clock
Flash clock
Flash clock
—
—
—
QSPI bus interface clock
QSPI clock
QSPIx_SCK
Security
CRC
TRNG
Bus clock
Bus clock
—
—
—
—
—
—
LTC Encryption Engine
System clock
Analog
ADC
CMP
DAC
Bus clock
Bus clock
Bus clock
Flash clock
OSCERCLK, IRC48MCLK
—
—
—
—
—
—
—
VREF
Timers
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
13
NXP Semiconductors
Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
Bus clock
Internal clocks
I/O interface clocks
TPM
PDB
TPM clock
TPM_CLKIN0, TPM_CLKIN1
Bus clock
—
—
—
—
—
PIT
Bus clock
LPTMR
Bus clock
LPO, OSCERCLK,
MCGIRCLK, ERCLK32K
RTC
Bus clock
EXTAL32
—
Communication interfaces
USB FS OTG
USB DCD
SPI
System clock
Bus clock
USB FS clock
—
—
—
—
DSPI_SCK
I2C_SCL
—
System clock
Bus clock
I2C
—
LPUART
EMVSIM
FlexIO
Bus clock
LPUART clock
EMVSIM clock
FlexIO clock
Bus clock
—
Bus clock
—
Human-machine interfaces
GPIO
TSI
Platform clock
Bus clock
—
—
—
LPO, ERCLK32K,
MCGIRCLK
2.1.7 Security
Security state can be enabled via programming flash configuration field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU, and ROM boot loader is also limited to access flash and not allowed to read out
flash information via ROM boot loader commands.
Access interface
Secure state
Unsecure operation
SWD port
Cannot access memory source by SWD The debugger can write to the Flash
interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
ROM boot loader Interface
(UART/I2C/SPI/USB)
Limit access to the flash, cannot read
out flash content
Send “FlashEraseAllUnsecureh"
command or attempt to unlock flash
security using the backdoor key
This device features 128-bit unique identification number, which is programmed in
factory and loaded to SIM register after power-on reset.
14
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
2.1.8 Power management
The Power Management Controller (PMC) expands upon ARM’s operational modes
of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes
can be used to optimize current consumption for a wide range of applications. The
WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on ARM’s operational modes, See the ARM®
Cortex User Guide.
The PMC provides High Speed Run (HSRUN), Run (Run), and Very Low Power Run
(VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core
is active and can access all peripherals. The difference between the modes is the
maximum clock frequency of the system and therefore the power consumption. The
configuration that matches the power versus performance requirements of the
application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core
from LLS and VLLSx modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, or the LLWU, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
15
NXP Semiconductors
Overview
Table 6. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
High Speed Run
In HSRun mode, MCU is able to operate at a faster frequency, all device
modules are operational.
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Deep sleep
Wait
In Wait mode, all peripheral modules are operational. The MCU core is placed
into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU
core is placed into Sleep mode.
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static state.
Stop mode retains all registers and SRAMs while maintaining Low Voltage
Detection protection. In Stop mode, the ADC, DAC, CMP, LPTimer, RTC,
TPM, LPUART, TSI and pin interrupts are operational. The NVIC is disabled,
but the AWIC can be used to wake up from an interrupt.
Very Low Power Stop
Low Leakage Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low speed),
ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, USB, TSI and DMA are
operational, LVD and NVIC are disabled, AWIC is used to wake up from
interrupt.
In LLS mode, the contents of the SRAM and the 32-byte system register file
are retained. The CMP (low speed), LLWU, LPTMR, and RTC are operational.
The ADC, CRC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC, PIT, SPI, TPM,
UART, USB, and WDOGCOP are static, but retain their programming. The
DAC, GPIO, and VREF are static, retain their programming, and continue to
drive their previous values.
Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation
from their reset state when the device wakes up. The LLWU, LPTMR, and
RTC are operational in all VLLS modes.
In VLLS3, the contents of the SRAM and the 32-byte system register file are
retained. The CMP (low speed), and PMC are operational. The DAC, GPIO,
and VREF are not operational but continue driving.
In VLLS1, the contents of the 32-byte system register file are retained. The
CMP (low speed), and PMC are operational. The DAC, GPIO, and VREF are
not operational but continue driving.
In VLLS0, the contents of the 32-byte system register file are retained. The
PMC is operational. The GPIO is not operational but continues driving. The
POR detection circuit can be enabled or disabled.
2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
16
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
This device uses 25 external wakeup pin inputs and five internal modules as wakeup
sources to the LLWU module.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
Table 7. Wakeup sources for LLWU inputs
LLWU pins
LLWU_P0
LLWU_P1
LLWU_P2
LLWU_P3
LLWU_P4
LLWU_P5
LLWU_P6
LLWU_P7
LLWU_P8
LLWU_P9
LLWU_P10
LLWU_P11
LLWU_P12
LLWU_P13
LLWU_P14
LLWU_P15
LLWU_P16
LLWU_P17
LLWU_P18
LLWU_P19
LLWU_P20
LLWU_P21
LLWU_P22
LLWU_P23
LLWU_P24
LLWU_P25
LLWU_P26
LLWU_P27
LLWU_P28
LLWU_P29
LLWU_P30
LLWU_P31
LLWU_M0IF
Module sources or pin names
PTE1
PTE2
PTE4
PTA4
PTA13
PTB0
PTC1
PTC3
PTC4
PTC5
PTC6
PTC11
PTD0
PTD2
PTD4
PTD6
PTE6
PTE9
PTE10
Reserved
Reserved
Reserved
PTA10
PTA11
PTD8
PTD11
Reserved
USB0_DP
USB0_DM1
Reserved
Reserved
Reserved
LPTMR0 or LPTMR12
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
17
NXP Semiconductors
Overview
Table 7. Wakeup sources for LLWU inputs (continued)
LLWU pins
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
Module sources or pin names
CMP0
Reserved
Reserved
TSI02
RTC alarm
Reserved
RTC second
1. A wakeup source of LLWU, USB0_DP or USB0_DM is available only when the chip is in USB host mode.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU_ME[WUMEn] (n=0-7) bit enables the
internal module flag a wakeup inputs. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
2.1.10 Debug controller
This device supports standard ARM 2-pin SWD debug port. It provides register and
memory accessibility from the external debugger interface, basic run/halt control plus 2
breakpoints and 2 watchpoints.
It also supports trace function with the Micro Trace Buffer (MTB), which provides a
simple execution trace capability for the Cortex-M0+ processor.
2.1.11 INTMUX
The Interrupt Multiplexer (INTMUX) routes the interrupt sources to the interrupt
outputs. It provides interrupt status registers to monitor interrupt pending status and
vector numbers and implements the ability to logical AND or OR enabled interrupts on
a given channel.
The INTMUX has the following features:
• Supports 4 multiplex channels
• Each channel receives 32 interrupt sources and has one interrupt output
• Each interrupt source can be enabled or disabled
• Each channel supports logic AND or logic OR of all enabled interrupt sources
18
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
2.1.12 Watch dog
The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it
in case of its failure.
The WDOG has the following features:
• Clock source input independent from CPU/bus clock. Choice between low-power
oscillator (LPO) and external system clock.
• Unlock sequence for allowing updates to write-once WDOG control/configuration
bits.
• All WDOG control/configuration bits are writable once only within 256 bus clock
cycles of being unlocked.
• Programmable time-out period specified in terms of number of WDOG clock
cycles.
• Ability to test WDOG timer and reset with a flag indicating watchdog test.
• Windowed refresh option.
• Robust refresh mechanism.
• Count of WDOG resets as they occur.
• Configurable interrupt on time-out to provide debug breadcrumbs. This is
followed by a reset after 256 bus clock cycles.
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 BME
The Bit Manipulation Engine (BME) provides hardware support for atomic read-
modify-write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for
bit-oriented operations to peripheral registers.
The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit,
bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized
data type.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
19
NXP Semiconductors
Overview
2.2.2 eDMA and DMAMUX
The eDMA controller module enables fast transfers of data, which provides an efficient
way to move blocks of data with minimal processor interaction. The eDMA controller
in this device implements eight channels which can be routed from up to 63 DMA
request sources through DMA MUX module. Some of the peripheral request sources
have asynchronous eDMA capability which can be used to wake MCU from Stop
mode. The peripherals which have such capability include FlexIO, LPUART0,
LPUART1, LPUART2, TPM0, TPM1, TPM2, PORTA-PORTE, ADC0, and CMP0.
The DMA channel 0 t0 3 can be periodically triggered by PIT via DMA MUX.
Main features are listed below:
• Dual-address transfers via 32-bit master connection to the system bus and data
transfers in 8-, 16-, or 32-bit blocks
• 8-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• Provide the selectable channel activation methods.
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
2.2.3 TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input or internal clock source,
HIRC48M clock, external crystal input clock, MCGIRCLK, MCGPLLCLK, or
MCGFLLCLK.
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare, edge-
aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
20
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.4 ADC
this device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16-
bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-Calibration mode
2.2.5 VREF
The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically)
trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage
to external devices or used internally as a reference to analog peripherals such as the
ADC, DAC or CMP.
The VREF supports the following programmable buffer modes:
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
21
NXP Semiconductors
Overview
• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled
A 100 nF capacitor must always be connected between VERF output (VREFO) pin and
VSSA if the VREF is used. This capacitor must be as close to VREFO pin as possible.
2.2.6 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The window and filter functions are not available in Stop, VLPS, LLS, or VLLSx
modes
• Integrated 6-bit DAC with selectable supply reference source and can be power
down to conserve power
• Two 8-to-1 channel mux
22
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
2.2.7 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers. During chip power-down, RTC is powered from the backup power
supply (VBAT), electrically isolated from the rest of the chip, continues to increment
the time counter (if enabled) and retain the state of the RTC registers. The RTC
registers are not accessible.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
• 64-bit monotonic counter with roll-over protection
2.2.8 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has four independent channels and each channel has a 32-bit counter. Two channels
can be chained together to form a 64-bit counter.
The PIT module can trigger a DMA transfer on the first four DMA channels. and also
can be selected as ADC, TPM, and DAC trigger source.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
23
NXP Semiconductors
Overview
2.2.9 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.10 CRC
This device contains one cyclic redundancy check (CRC) module which can generate
16/32-bit CRC code for error detection.
The CRC module provides a programmable polynomial, WAS, and other parameters
required to implement a 16-bit or 32-bit CRC standard.
The CRC module has the following features:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift
register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
2.2.11 LPUART
This product contains three Low-Power UART modules, both of their clock sources are
selectable fromIRC48M, MCGFLLCLK, MCGPLLCLK, MCGIRCCLK or external
crystal clock, and can work in Stop and VLPS modes. They also support 4x to 32x data
oversampling rate to meet different applications.
The LPUART module has the following features:
• Full-duplex, standard non-return-to-zero (NRZ) format
24
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods: idle line wakeup, address mark wakeup, receive
data match
• Automatic address matching to reduce ISR overhead
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS)
signals
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable
pulse width
2.2.12 SPI
This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.
FIFO function is available only on SPI1 module.
The SPI modules have the following features:
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
25
NXP Semiconductors
Overview
2.2.13 I2C
This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer
features, and address match to wake MCU from the low power mode.
I2C modules support DMA transfer, and the interrupt condition can trigger DMA
request when DMA function is enabled.
The I2C modules have the following features:
• Support for system management bus (SMBus) Specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate
2.2.14 USB
This device contains one USB module which implements a USB2.0 full-speed
compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements
keep-alive feature to avoid re-enumerating when exiting from low power modes and
enables HIRC48M to allow crystal-less USB operation.
The USBFS has the following features:
• USB 1.1 and 2.0 compatible FS device controller
• 16 bidirectional endpoints
• DMA or FIFO data stream interfaces
• Low-power consumption
26
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
• IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is
used for USB device-only implementation.
• Keep-alive feature is supported to power down system bus and CPU. USB can
respond to IN with NAK and wake up for SETUP/OUT.
2.2.15 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to LPUART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/
Waveform generation. The module supports programmable baud rates independent of
bus clock frequency, with automatic start/stop bit generation. It also supports to work
in VLPR, VLPW, Stop, and VLPS modes when clock source remains enabled.
The FlexIO module has the following features:
• Array of 32-bit shift registers with transmit, receive and data match modes
• Double buffered shifter operation for continuous data transfer
• Shifter concatenation to support large transfer sizes
• Automatic start/stop bit generation
• 1, 2, 4, 8, 16 or 32 multi-bit shift widths for parallel interface support
• Interrupt, DMA or polled transmit/receive operation
• Programmable baud rates independent of bus clock frequency, with support for
asynchronous operation during stop modes
• Highly flexible 16-bit timers with support for a variety of internal or external
trigger, reset, enable and disable conditions
• Programmable logic mode for integrating external digital logic functions on-chip
or combining pin/shifter/timer functions to generate complex outputs
• Programmable state machine for offloading basic system control functions from
CPU with support for up to 8 states, 8 outputs and 3 selectable inputs per state
2.2.16 DAC
The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, OPAMPS or ADC.
DAC module has the following features:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
27
NXP Semiconductors
Overview
• Vin can be selected from two reference sources
• Static operation in Normal Stop mode
• 16-word data buffer supported with configurable watermark and multiple operation
modes
• DMA support
2.2.17 EMV-SIM
The EMV_SIM (Euro/Mastercard/Visa/SIM Serial Interface Module) is designed to
facilitate communication to Smart Cards compatible to the EMV ver4.3 standard (Book
1) and Smart Cards compatible with ISO/IEC 7816-3 Standard.
EMV-SIM module has the following features:
• Supports Smart Cards based on the EMV Standard v4.3 and ISO 7816-3 standard
• Independent clock for SIM logic (transmitter + receiver) and independent clock for
register read-write interface
• 16 byte deep FIFO for transmitter and receiver
• Automatic NACK generation on parity error and receiver FIFO overflow error
• Support for both Inverse and Direct conventions
• Re-transmission of byte upon Smart Card NACK request with programmable
threshold of re-transmissions
• Auto detection of Initial Character in receiver and setting of data format (inverse or
direct)
• NACK detection in receiver
• Independent timers to measure character wait time, block wait time and block guard
time
• Two general purpose counters available for use by software application with
programmable clock selection for the counters
• DMA support available to transfer data to/from FIFOs. Programmable option
available to select interrupt or DMA feature
• Programmable Prescaler to generate the desired frequency for Card Clock and Baud
Rate Divisor to generate the internal ETU clocks for transmitter and receiver for
any F/D ratio
• Deep sleep wake-up via Smart Card presence detect interrupt
• Manual control of all Smart Card interface signals
28
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Overview
• Automatic power down of port logic on Smart Card presence detect
• Support for 8-bit LRC and 16-bit CRC generation for bytes sent out from
transmitter and checking incoming message checksum for receiver
2.2.18 LTC
LP Trusted Cryptography (LTC) is a hardware accelerate module dedicate for the
popular encryption algorithm.
LTC module has the following features:
• Cryptographic authentication
• Authenticated encryption algorithms
• AES-CCM (counter with CBC-MAC)
• AES-GCM (Galois counter mode)
• Symmetric key block ciphers
• Public key cryptography
• Secure Scan
2.2.19 TRNG
The Standalone True Random Number Generator (SA-TRNG) is hardware accelerator
module that generates a 512-bit entropy as needed by an entropy consuming module
or by other post processing functions.
2.2.20 TSI
The touch sensing input (TSI) module provides capacitive touch sensing detection
with high sensitivity and enhanced robustness.
TSI module has the following features:
• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
• Internal reference oscillator for high-accuracy measurement
• Configurable software or hardware scan trigger
• Fully support NXP touch sensing software (TSS) library, see www.nxp.com/
touchsensing.
• Capability to wake MCU from low power modes
• Compensate for temperature and supply voltage variations
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
29
NXP Semiconductors
Memory map
• High sensitivity change with 16-bit resolution register
• Configurable up to 4096 scan times.
• Support DMA data transfer
2.2.21 QuadSPI
The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to one single
or two external serial flash devices, each with up to eight bidirectional data lines. This
device contains one QSPI module, which supports singles, dual, quad or octal data lines
in single (SDR) or double (DDR) data rate configurations. The QuadSPI clock
frequencies support up to 96 MHz in SDR mode and up to 72 MHz in DDR mode.
The QuadSPI has the following features:
• Flexible sequence engine to support various flash vendor devices.
• Single, dual, quad and octal modes of operation.
• DDR/DTR mode wherein the data is generated on every edge of the serial flash
clock.
• Support for flash data strobe signal for data sampling in DDR and SDR mode.
• Support for parallel writes via register mapped interface in single I/O mode.
• Two identical serial flash devices can be connected and accessed in parallel for data
read operations, forming one (virtual) flash memory with doubled readout
bandwidth.
• DMA support to read RX Buffer data via AMBA AHB bus (64-bit width interface)
or IP registers space (32-bit access) and DMA support to fill TX Buffer via IPS
register space (32-bit access).
• Multimaster accesses with priority
• Multiple interrupt conditions
• Memory mapped read access to connected flash devices.
• Programmable sequence engine to cater to future command/protocol changes and
able to support all existing vendor commands and operations.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. The following figure shows the system memory and
peripheral locations
30
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Memory map
0x4000_0000
Reserved
0x4000_8000
0x4000_9000
DMA controller
DMA TCD
0x4000_A000
Reserved
0x4000_D000
0x4000_E000
System MPU
Reserved
GPIO controller(alias to 0x400F_F00)
Reserved
0x4000_F000
0x4001_0000
0x4002_0000
0x4002_1000
Flash memory unit
DMAMUX
Reserved
INTMUX0
TRNG
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
Reserved
SPI0
0x4002_C000
0x4002_D000
0x4002_E000
0x4003_2000
SPI1
Reserved
CRC
Reserved
0x0000_0000
0x4003_3000
0x4003_7000
0x4003_8000
0x4003_9000
Flash
ROM
PIT
TPM0
0x0000_0000
0x03FF_FFFF
0x1C00_0000
TPM1
0x4003_A000
Code space
Reserved
TPM2
ADC0
0x4003_B000
0x4003_C000
0x4003_D000
0x4003_E000
0x4003_F000
0x0400_0000
0x1C00_0000
Reserved
RTC
Boot ROM
Reserved
VBAT Register File
0x1C00_7FFF
0x1FFF_A000
DAC0
0x1C00_8000
0x1FFF_A000
0x4004_0000
0x4004_1000
LPTMR0
System register file
Reserved
0x4004_2000
0x4004_4000
0x4004_5000
0x4004_6000
0x4004_7000
SRAM_L
SRAM_U
Data Space
Reserved
LPTMR1
TSI0
Reserved
0x2000_0000
0x2001_FFFF
0x4000_0000
0x2002_0000
0x4000_0000
SIM low power logic
SIM
0x4004_8000
0x4004_9000
0x4004_A000
Public
peripheral
PORT A
AIPS
peripherals
PORT B
PORT C
PORT D
0x4004_B000
0x4004_C000
0x400F_F000
0x4400_0000
Reserved
BME
0x4007_FFFF
0x400F_F000
0x4004_D000
0x4004_E000
PORT E
EMVSIM0
EMVSIM1
Reserved
LTC
GPIO
0x4004_F000
0x4010_0000
0x4010_07FF
0x6000_0000
0x6700_0000
0x7000_0000
0xE000_0000
USB RAM
Reserved
QSPI
0x4005_0000
0x4005_1000
0x4005_2000
0x4005_3000
WDOG
Reserved
0xE000_0000
0xE000_E000
Reserved
Reserved
0x4005_4000
0x4005_5000
LPUART0
LPUART1
LPUART2
Reserved
QSPI0
System
control
space
0x4005_6000
0x4005_7000
Private
peripheral
0xE000_F000
0xE00F_F000
Reserved
0x4005_A000
0x4005_B000
0x4005_F000
0x4006_0000
Reserved
FlexIO0
Core
ROM table
0xE010_0000
0xF000_0000
0xE00F_FFFF
0xF000_0000
Reserved
Reserved
EWM
MTB
0x4006_1000
0x4006_2000
0xF000_1000
0xF000_2000
0xF000_3000
Reserved
MCG
MTBDWT
0x4006_4000
0x4006_5000
OSC
I2C0
ROM Table
MCM
0x4006_6000
0x4006_7000
Private
peripheral
bus
I2C1
Reserved
USB FS
CMP0
0x4006_8000
0x4007_2000
0x4007_3000
0xF000_4000
0xF800_0000
Reserved
IOPORT
0xFFFF_FFFF
0x4007_4000
0x4007_5000
VREF
Reserved
LLWU
PMC
0xFFFF_FFFF
0x4007_C000
0x4007_D000
0x4007_E000
0x4007_F000
SMC
RCM
0x400F_F000
eGPIO
Kinetis KL82 Microcontroller, Rev. 4, 12/2016Figure 4. Memory map
31
NXP Semiconductors
Pinouts
4 Pinouts
4.1 KL82 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
BGA
B1
1
2
3
4
1
2
3
4
A1
1
2
3
4
PTE0
DISABLED
DISABLED
DISABLED
DISABLED
PTE0
SPI1_PCS1
SPI1_SCK
LPUART1_
TX
QSPI0A_
DATA3
I2C1_SDA
I2C1_SCL
RTC_
CLKOUT
C2
C1
D2
B1
C5
D2
PTE1/
LLWU_P0
PTE1/
LLWU_P0
LPUART1_
RX
QSPI0A_
SCLK
SPI1_SIN
PTE2/
LLWU_P1
PTE2/
LLWU_P1
SPI1_SOUT LPUART1_
CTS_b
QSPI0A_
DATA0
SPI1_SCK
PTE3
PTE3
SPI1_PCS2
LPUART1_
RTS_b
QSPI0A_
DATA2
SPI1_SOUT
F7
E5
D1
5
6
7
5
6
7
C4
D3
E2
5
6
7
VSS
VSS
VSS
VDDIO_E
VDDIO_E
DISABLED
VDDIO_E
PTE4/
LLWU_P2
PTE4/
LLWU_P2
SPI1_SIN
QSPI0A_
DATA1
E2
E1
F3
F2
F1
G2
G1
8
8
D1
—
—
—
—
—
—
8
PTE5
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTE5
SPI1_PCS0
SPI1_PCS3
QSPI0A_
SS0_B
USB0_
SOF_OUT
9
—
9
—
—
—
—
—
—
PTE6/
LLWU_P16
PTE6/
LLWU_P16
QSPI0B_
DATA3
10
11
12
13
14
PTE7
PTE8
PTE7
PTE8
QSPI0B_
SCLK
QSPI0A_
SS1_B
10
—
—
11
QSPI0B_
DATA0
PTE9/
LLWU_P17
PTE9/
LLWU_P17
QSPI0B_
DATA2
PTE10/
LLWU_P18
PTE10/
LLWU_P18
QSPI0B_
DATA1
PTE11
PTE11
QSPI0B_
SS0_B
QSPI0A_
DQS
—
—
15
16
—
17
18
12
13
—
14
15
—
—
—
9
VDDIO_E
VSS
VDDIO_E
VSS
VDDIO_E
VSS
H3
H2
H1
F3
E1
F1
—
10
11
VSS
VSS
VSS
USB0_DP
USB0_DM
USB0_DP
USB0_DM
USB0_DP
USB0_DM
32
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
J1
BGA
F2
—
19
20
21
—
—
22
23
24
25
26
27
28
16
—
—
—
—
17
18
19
20
21
22
23
12
—
—
—
—
13
14
15
16
17
18
19
USB_VDD
NC
USB_VDD
NC
USB_VDD
NC
J2
—
—
NC
K2
K1
F5
G5
G6
F6
L2
—
ADC0_DP0
ADC0_DM0
VDDA
ADC0_DP0
ADC0_DM0
VDDA
ADC0_DP0
ADC0_DM0
VDDA
—
G2
H3
H2
G1
H1
G3
F4
VREFH
VREFL
VREFH
VREFH
VREFL
VREFL
VSSA
VSSA
VSSA
ADC0_DP1
ADC0_DM1
ADC0_DP1
ADC0_DM1
ADC0_DP1
ADC0_DM1
L1
L3
VREF_OUT/ VREF_OUT/ VREF_OUT/
CMP0_IN5/ CMP0_IN5/ CMP0_IN5/
ADC0_SE22 ADC0_SE22 ADC0_SE22
K4
29
24
G4
20
DAC0_OUT/ DAC0_OUT/ DAC0_OUT/
ADC0_SE23 ADC0_SE23 ADC0_SE23
H6
K5
—
—
—
—
NC
NC
NC
30
25
F5
21
RTC_
RTC_
RTC_
WAKEUP_B WAKEUP_B WAKEUP_B
L4
L5
K6
—
31
32
33
34
35
36
26
27
28
—
—
29
H4
H5
G5
—
22
23
24
—
—
25
XTAL32
EXTAL32
VBAT
VDD
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
VDD
VDD
—
—
VSS
VSS
VSS
L7
D4
PTA0
SWD_CLK
TSI0_CH1
PTA0
LPUART0_
CTS_b
TPM0_CH5
FXIO0_D10
FXIO0_D11
FXIO0_D12
FXIO0_D13
FXIO0_D14
FXIO0_D15
EMVSIM0_
CLK
SWD_CLK
H8
J7
37
38
39
40
41
30
31
32
33
—
D5
E5
H6
G6
—
26
27
28
29
—
PTA1
PTA2
PTA3
TSI0_CH2
TSI0_CH3
SWD_DIO
NMI_b
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
PTA1
PTA2
PTA3
LPUART0_
RX
EMVSIM0_
IO
LPUART0_
TX
EMVSIM0_
PD
H9
J8
LPUART0_
RTS_b
TPM0_CH0
TPM0_CH1
TPM0_CH2
EMVSIM0_
RST
SWD_DIO
NMI_b
PTA4/
LLWU_P3
PTA4/
LLWU_P3
EMVSIM0_
VCCEN
K7
PTA5
DISABLED
PTA5
USB0_
CLKIN
L10
K10
J9
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
VDD
VDD
VSS
VSS
PTA10/
LLWU_P22
DISABLED
PTA10/
LLWU_P22
TPM2_CH0
TPM2_CH1
EMVSIM1_
VCCEN
FXIO0_D16
FXIO0_D17
H7
—
—
—
—
PTA11/
DISABLED
PTA11/
LLWU_P23
LLWU_P23
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
33
NXP Semiconductors
Pinouts
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
K8
BGA
—
42
43
—
—
—
—
PTA12
DISABLED
DISABLED
PTA12
TPM1_CH0
TPM1_CH1
FXIO0_D18
FXIO0_D19
L8
—
PTA13/
PTA13/
LLWU_P4
LLWU_P4
K9
L9
44
45
46
47
34
35
36
37
—
—
—
—
—
—
—
—
PTA14
PTA15
PTA16
PTA17
DISABLED
DISABLED
DISABLED
DISABLED
PTA14
PTA15
PTA16
PTA17
SPI0_PCS0
SPI0_SCK
LPUART0_
TX
FXIO0_D20
FXIO0_D21
FXIO0_D22
FXIO0_D23
LPUART0_
RX
J10
H10
SPI0_SOUT LPUART0_
CTS_b
SPI0_SIN
LPUART0_
RTS_b
E6
G7
48
49
50
38
39
40
H7
G7
H8
30
31
32
VDD
VDD
VDD
VSS
VSS
VSS
L11
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
TPM_
CLKIN0
K11
51
41
G8
33
PTA19
XTAL0
XTAL0
TPM_
CLKIN1
LPTMR0_
ALT1/
LPTMR1_
ALT1
J11
H11
G11
52
—
53
42
—
43
F8
—
34
—
35
RESET_b
PTA29
RESET_b
RESET_b
DISABLED
PTA29
E6
PTB0/
LLWU_P5
ADC0_SE8/ ADC0_SE8/ PTB0/
TSI0_CH0 TSI0_CH0 LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
TPM1_CH0
TPM1_CH1
FXIO0_D0
FXIO0_D1
FXIO0_D2
G10
G9
54
55
44
—
—
—
—
—
PTB1
ADC0_SE9/ ADC0_SE9/ PTB1
TSI0_CH6
TSI0_CH6
PTB2
ADC0_
SE12/
TSI0_CH7
ADC0_
SE12/
TSI0_CH7
PTB2
PTB3
LPUART0_
RTS_b
G8
56
—
—
—
PTB3
ADC0_
SE13/
ADC0_
SE13/
I2C0_SDA
LPUART0_
CTS_b
FXIO0_D3
TSI0_CH8
TSI0_CH8
B11
C11
F11
E11
D11
—
—
—
—
—
45
46
47
48
49
F7
F6
E7
E8
D7
36
37
38
39
40
PTB4
PTB5
PTB6
PTB7
PTB8
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTB4
PTB5
PTB6
PTB7
PTB8
EMVSIM1_
IO
EMVSIM1_
CLK
EMVSIM1_
VCCEN
EMVSIM1_
PD
EMVSIM1_
RST
E10
D10
C10
L6
57
58
59
60
—
—
50
—
—
—
—
—
—
—
—
—
PTB9
PTB10
PTB11
VSS
DISABLED
DISABLED
DISABLED
VSS
PTB9
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
PTB10
PTB11
FXIO0_D4
FXIO0_D5
VSS
34
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
E7
BGA
—
61
62
—
—
—
VDD
VDD
VDD
B10
51
—
PTB16
TSI0_CH9
TSI0_CH9
PTB16
SPI1_SOUT LPUART0_
RX
TPM_
CLKIN0
EWM_IN
E9
63
52
—
—
PTB17
TSI0_CH10
TSI0_CH10
PTB17
SPI1_SIN
LPUART0_
TX
TPM_
CLKIN1
EWM_OUT_
b
D9
C9
F10
F9
64
65
66
67
68
69
70
53
54
—
—
—
—
55
D6
C7
—
41
42
—
—
—
—
43
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
TSI0_CH11
TSI0_CH12
DISABLED
DISABLED
DISABLED
DISABLED
TSI0_CH11
TSI0_CH12
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
TPM2_CH0
TPM2_CH1
FXIO0_D6
FXIO0_D7
CMP0_OUT FXIO0_D8
FXIO0_D9
—
F8
—
FXIO0_D10
E8
B9
—
SPI0_PCS5
EXTRG_IN
FXIO0_D11
D8
ADC0_
SE14/
TSI0_CH13
ADC0_
SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
USB0_
SOF_OUT
FXIO0_D12
D8
C8
B8
71
72
73
56
57
58
C6
B7
C8
44
45
46
PTC1/
LLWU_P6
ADC0_
SE15/
TSI0_CH14
ADC0_
SE15/
TSI0_CH14
PTC1/
LLWU_P6
LPUART1_
RTS_b
TPM0_CH0
TPM0_CH1
TPM0_CH2
FXIO0_D13
PTC2
ADC0_
SE4b/
TSI0_CH15
ADC0_
SE4b/
TSI0_CH15
PTC2
LPUART1_
CTS_b
PTC3/
LLWU_P7
DISABLED
PTC3/
LLWU_P7
LPUART1_
RX
CLKOUT
—
—
74
75
76
59
60
61
E3
E4
B8
47
48
49
VSS
VDD
VSS
VSS
VDD
VDD
A8
PTC4/
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
LPUART1_
TX
TPM0_CH3
LLWU_P8
D7
77
62
A8
50
PTC5/
DISABLED
PTC5/
LLWU_P9
LPTMR0_
ALT2/
CMP0_OUT TPM0_CH2
LLWU_P9
LPTMR1_
ALT2
C7
B7
78
79
63
64
A7
B6
51
52
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
SPI0_SOUT EXTRG_IN
FXIO0_D14
FXIO0_D15
PTC7
PTC7
SPI0_SIN
USB0_
SOF_OUT
A7
D6
C6
C5
80
81
82
83
65
66
67
68
A6
B5
B4
A5
53
54
55
56
PTC8
PTC9
PTC10
CMP0_IN2
CMP0_IN3
DISABLED
DISABLED
CMP0_IN2
CMP0_IN3
PTC8
PTC9
PTC10
FXIO0_D16
FXIO0_D17
FXIO0_D18
FXIO0_D19
I2C1_SCL
I2C1_SDA
PTC11/
PTC11/
LLWU_P11
LLWU_P11
B6
A6
A5
84
85
86
69
70
—
—
—
—
—
—
—
PTC12
PTC13
PTC14
DISABLED
DISABLED
DISABLED
PTC12
PTC13
PTC14
TPM_
CLKIN0
TPM_
CLKIN1
FXIO0_D20
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
35
NXP Semiconductors
Pinouts
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
B5
—
BGA
—
87
88
89
—
90
—
—
91
—
—
—
71
72
—
—
73
—
—
—
—
—
—
—
57
PTC15
VSS
DISABLED
VSS
PTC15
FXIO0_D21
—
VSS
VDD
—
—
VDD
VDD
D5
C4
B4
A4
D4
—
PTC16
PTC17
PTC18
PTC19
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTC16
PTC17
PTC18
PTC19
—
—
—
C3
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
LPUART2_
RTS_b
FXIO0_D22
FXIO0_D23
I2C0_SCL
I2C0_SDA
SPI1_PCS0
D3
C3
B3
A3
A2
B2
92
93
94
95
96
97
74
75
76
77
78
79
A4
C2
B3
A3
C1
B2
58
59
60
61
62
63
PTD1
ADC0_SE5b ADC0_SE5b PTD1
LPUART2_
CTS_b
PTD2/
LLWU_P13
DISABLED
DISABLED
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT LPUART2_
RX
PTD3
PTD3
SPI0_SIN
LPUART2_
TX
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
SPI0_PCS2
SPI0_PCS3
LPUART0_
RTS_b
TPM0_CH4
TPM0_CH5
EWM_IN
PTD5
ADC0_SE6b ADC0_SE6b PTD5
LPUART0_
CTS_b
EWM_OUT_ SPI1_SCK
b
PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LPUART0_
RX
SPI1_SOUT
LLWU_P15
PTD7
—
—
98
99
—
—
80
—
—
—
—
64
VSS
VSS
VSS
VDD
VDD
PTD7
VDD
A1
100
A2
DISABLED
LPUART0_
TX
SPI1_SIN
A10
—
—
—
—
PTD8/
LLWU_P24
DISABLED
PTD8/
LLWU_P24
I2C0_SCL
I2C0_SDA
FXIO0_D24
A9
E4
E3
—
—
—
—
—
—
—
—
—
—
—
—
PTD9
DISABLED
DISABLED
DISABLED
PTD9
FXIO0_D25
FXIO0_D26
FXIO0_D27
PTD10
PTD10
PTD11/
PTD11/
LLWU_P25
LLWU_P25
F4
G3
G4
H4
A11
J6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTD12
PTD13
PTD14
PTD15
NC
DISABLED
DISABLED
DISABLED
DISABLED
NC
PTD12
PTD13
PTD14
PTD15
FXIO0_D28
FXIO0_D29
FXIO0_D30
FXIO0_D31
NC
NC
NC
NC
NC
NC
NC
NC
NC
J4
NC
NC
H5
J3
NC
NC
NC
NC
J5
NC
NC
K3
NC
NC
36
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
121
100
80
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP LQFP MAP LQFP
BGA
BGA
121
100
80
64
64
4.2 Pin properties
The following table lists the pin properties.
B1
C2
C1
D2
F7
E5
D1
E2
E1
F3
F2
F1
G2
G1
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A1
B1
C5
D2
C4
D3
E2
D1
PTE0
ND
ND
ND
ND
—
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FS
FS
FS
FS
—
N
N
Y
2
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
Hi-Z
Hi-Z
Hi-Z
—
N
N
Y
3
N
N
Y
4
N
N
Y
5
VFS
—
—
N
—
—
N
—
—
Y
6
VDDIO_E
PTE4/LLWU_P2
PTE5
—
—
—
7
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
FS
FS
FS
FS
FS
FS
FS
FS
—
8
N
N
Y
9
PTE6/LLWU_P16 ND
N
N
Y
10
11
12
13
14
15
16
9
PTE7
PTE8
ND
ND
N
N
Y
10
N
N
Y
PTE9/LLWU_P17 ND
PTE10/LLWU_P18 ND
N
N
Y
N
N
Y
11
12
13
PTE11
ND
—
—
—
—
—
—
N
N
Y
VDDIO_E
VFS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
—
—
H3
H2
H1
J1
F3
E1
F1
F2
VFS
—
—
17
18
19
14
15
16
10
11
12
USB0_DP
USB0_DM
USB_VDD
—
—
—
—
—
—
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
37
NXP Semiconductors
Pinouts
J2
20
21
NC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
—
—
N
—
—
—
—
—
—
—
—
—
—
—
NC
—
—
—
K2
K1
F5
G5
G6
F6
L2
L1
L3
ADC0_DP0
ADC0_DM0
VDDA
ND
ND
—
Hi-Z
Hi-Z
—
FS
FS
—
N
N
22
23
24
25
26
27
28
17
18
19
20
21
22
23
13
14
15
16
17
18
19
G2
H3
H2
G1
H1
G3
F4
—
—
—
—
N
—
—
—
—
N
VREFH
VREFL
—
—
—
—
—
—
VFSA
—
—
—
ADC0_DP1
ADC0_DM1
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
FS
FS
FS
N
N
VREF_OUT/
CMP0_IN5/
ADC0_SE22
N
N
K4
29
24
20
G4
DAC0_OUT/
ADC0_SE23
ND
—
Hi-Z
—
FS
N
N
—
H6
K5
L4
L5
K6
NC
—
Hi-Z
Hi-Z
Hi-Z
—
—
—
L
—
—
—
N
—
Y
—
—
Y
30
31
32
33
34
35
36
37
38
39
40
41
25
26
27
28
21
22
23
24
F5
H4
H5
G5
RTC_WAKEUP_B ND
—
FS
FS
FS
—
XTAL32
EXTAL32
VBAT
ND
ND
—
—
N
N
—
N
N
Y
—
—
—
—
N
—
—
—
N
—
—
—
Y
VDD
—
—
—
VFS
—
—
—
L7
29
30
31
32
33
25
26
27
28
29
D4
D5
E5
H6
G6
PTA0
ND
ND
ND
ND
ND
ND
—
PU
PU
PU
PU
PU
PU
—
FS
FS
FS
FS
FS
FS
—
H8
J7
PTA1
H
N
N
Y
PTA2
H
N
N
Y
H9
J8
PTA3
H
N
N
Y
PTA4/LLWU_P3
PTA5
H
Y
N
Y
K7
L10
K10
H
N
N
Y
VDD
—
—
—
—
—
—
—
—
VFS
—
—
—
Table continues on the next page...
38
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
J9
PTA10/LLWU_P22 ND
PTA11/LLWU_P23 ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
PU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FS
FS
FS
FS
FS
FS
FS
FS
—
N
N
N
N
N
N
N
N
—
—
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
N
N
N
N
N
N
N
—
—
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
Y
H7
K8
42
43
44
45
46
47
48
49
50
51
52
PTA12
ND
L8
PTA13/LLWU_P4 ND
K9
34
35
36
37
38
39
40
41
42
PTA14
PTA15
PTA16
PTA17
VDD
ND
ND
ND
ND
—
L9
J10
H10
E6
30
31
32
33
34
H7
G7
H8
G8
F8
G7
VFS
—
—
—
L11
K11
J11
H11
G11
G10
G9
PTA18
PTA19
RESET_b
PTA29
PTB0/LLWU_P5
PTB1
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
—
Hi-Z
Hi-Z
H
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
—
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
N
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
53
54
55
56
43
44
35
E6
PTB2
G8
PTB3
B11
C11
F11
E11
D11
E10
D10
C10
L6
45
46
47
48
49
36
37
38
39
40
F7
F6
E7
E8
D7
PTB4
PTB5
PTB6
PTB7
PTB8
57
58
59
60
61
62
PTB9
PTB10
PTB11
VFS
50
51
E7
VDD
—
—
—
B10
PTB16
ND
Hi-Z
FS
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
39
NXP Semiconductors
Pinouts
E9
D9
C9
F10
F9
F8
E8
B9
D8
C8
B8
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
52
53
54
PTB17
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
—
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
—
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
Y
Y
41
42
D6
C7
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
43
44
45
46
47
48
49
50
51
52
53
54
55
56
D8
C6
B7
C8
E3
E4
B8
A8
A7
B6
A6
B5
B4
A5
PTC0
PTC1/LLWU_P6
PTC2
PTC3/LLWU_P7
VFS
VDD
—
—
—
A8
D7
C7
B7
A7
D6
C6
C5
B6
A6
A5
B5
PTC4/LLWU_P8
PTC5/LLWU_P9
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
—
PTC6/LLWU_P10 ND
PTC7
PTC8
PTC9
PTC10
ND
ND
ND
ND
PTC11/LLWU_P11 ND
PTC12
PTC13
PTC14
PTC15
VFS
ND
ND
ND
ND
—
VDD
—
—
—
D5
C4
71
72
PTC16
PTC17
ND
ND
Hi-Z
Hi-Z
FS
FS
90
Table continues on the next page...
40
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
B4
A4
D4
D3
C3
B3
A3
A2
B2
PTC18
PTC19
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FS
FS
FS
FS
FS
FS
FS
FS
FS
—
N
N
Y
N
N
Y
91
92
93
94
95
96
97
98
99
100
73
74
75
76
77
78
79
57
58
59
60
61
62
63
C3
A4
C2
B3
A3
C1
B2
PTD0/LLWU_P12 ND
PTD1 ND
PTD2/LLWU_P13 ND
PTD3 ND
PTD4/LLWU_P14 ND
PTD5 ND
PTD6/LLWU_P15 ND
N
N
Y
N
N
Y
N
N
Y
N
N
Y
N
N
Y
N
N
Y
N
N
Y
VFS
—
—
—
N
—
—
N
—
—
Y
VDD
PTD7
—
—
—
A1
A10
A9
E4
E3
F4
G3
G4
H4
A11
J6
80
64
A2
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
FS
FS
FS
FS
FS
FS
FS
FS
FS
—
PTD8/LLWU_P24 ND
N
N
Y
PTD9
ND
ND
N
N
Y
PTD10
N
N
Y
PTD11/LLWU_P25 ND
N
N
Y
PTD12
PTD13
PTD14
PTD15
NC
ND
ND
ND
ND
—
N
N
Y
N
N
Y
N
N
Y
N
N
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NC
—
—
—
J4
NC
—
—
—
H5
J3
NC
—
—
—
NC
—
—
—
J5
NC
—
—
—
K3
NC
—
—
—
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
41
NXP Semiconductors
Pinouts
Properties
Abbreviation
Descriptions
Normal drive
High drive
High impendence
High level
Low level
Driver strength
ND
HD
Hi-Z
H
Default status after POR
L
Pullup/ pulldown setting
after POR
PD
PU
FS
SS
N
Pulldown
Pullup
Slew rate after POR
Fast slew rate
Slow slew rate
Disabled
Passive Pin Filter after
POR
Y
Enabled
Open drain
N
Disabled1
Enabled2
Y
Pin interrupt
Y
Yes
1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain configurable.
2. PTA20 is a true open drain pin that must never be pulled above VDD.
4.3 Module signal description tables
The following sections correlate the chip-level signal name with the signal name used in
the module's chapter. They also briefly describe the signal function and direction.
4.3.1 Core Modules
Table 9. SWD Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
SWD_DIO
SWD_CLK
SWD_DIO
SWD_CLK
Serial Wire Data
Serial Wire Clock
I/O
I
42
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
4.3.2 System modules
Table 10. System signal descriptions
Chip signal name
Module signal
name
Description
I/O
NMI_b
—
Non-maskable interrupt
I
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
RESET_b
VDD
—
—
Reset bi-directional signal
MCU power
I/O
I
I
I
I
I
I
VDDIO_E
VDDA
PTE
—
MCU power for IOs on PTE
MCU analog power
VSS
—
MCU ground
VREFH
VREFL
—
MCU analog voltage reference-high
MCU analog voltage reference--low
—
Table 11. EWM signal descriptions
Chip signal name
Module signal
Description
I/O
name
EWM_IN
EWM_in
EWM input for safety status of external safety circuits. The
polarity of EWM_in is programmable using the
I
EWM_CTRL[ASSIN] bit. The default polarity is active-low.
EWM_OUT_ b
EWM_out
EWM reset out signal
O
Table 12. LLWU signal descriptions
Chip signal name
Module signal
Description
I/O
name
LLWU_Pn
LLWU_Pn
Wakeup inputs
I
Table 13. EMVSIM0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
EMVSIM0_CLK
EMVSIM0_IO
EMVSIM0_PD
EMVSIM_SCLK
EMVSIM_IO
EMVSIM_PD
Card Clock. Clock to Smart Card.
O
I/O
I
Card Data Line. Bi-directional data line.
Card Presence Detect. Signal indicating presence or removal of
card
EMVSIM0_RST
EMVSIM_SRST
Card Reset. Reset signal to Smart Card
O
O
EMVSIM0_VCCEN EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart
Card
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
43
NXP Semiconductors
Pinouts
Table 14. EMVSIM1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
EMVSIM1_CLK
EMVSIM1_IO
EMVSIM1_PD
EMVSIM_SCLK
EMVSIM_IO
EMVSIM_PD
Card Clock. Clock to Smart Card.
O
I/O
I
Card Data Line. Bi-directional data line.
Card Presence Detect. Signal indicating presence or removal of
card
EMVSIM1_RST
EMVSIM_SRST
Card Reset. Reset signal to Smart Card
O
O
EMVSIM1_VCCEN EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card
4.3.3 Clock Modules
Table 15. OSC signal descriptions
Chip signal name
Module signal
name
Description
I/O
EXTAL0
XTAL0
EXTAL
XTAL
External clock/Oscillator input
Oscillator output
I
O
Table 16. RTC OSC signal descriptions
Chip signal name
Module signal
Description
I/O
name
EXTAL32
XTAL32
EXTAL32
XTAL32
Analog input of the RTC oscillator
I
Analog output of the RTC oscillator module
O
4.3.4 Memories and memory interfaces
Table 17. QSPI signal description
Chip signal name
Module signal
Description
I/O
Name
QSPI0A_SS0_B
PCSFA1
Peripheral Chip Select Flash A1. This
signal is the chip select for the serial
flash device A1. A1 represents the
first device in a dual-die package flash
A or the first of the two flash devices
that share IOFA.
O
QSPI0A_SS1_B
PCSFA2
Peripheral Chip Select Flash A2. This
signal is the chip select for the serial
flash device A2. A2 represents the
O
Table continues on the next page...
44
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
Table 17. QSPI signal description (continued)
Chip signal name
Module signal
Name
Description
I/O
second device in a dual-die package
flash A or the second of the two flash
devices that share IOFA.
QSPI0B_SS0_B
PCSFB1
Peripheral Chip Select Flash B1. This
signal is the chip select for the serial
flash device B1. B1 represents the
first device in a dual-die package flash
B or the first of the two flash devices
that share IOFB.
O
QSPI0A_SCLK
QSPI0B_SCLK
SCKFA
SCKFB
Serial Clock Flash A. This signal is the
serial clock output to the serial flash
device A.
O
O
Serial Clock Flash B. This signal is the
serial clock output to the serial flash
device B.
QSPI0B_DATA3
QSPI0B_DATA2
QSPI0B_DATA1
QSPI0B_DATA0
QSPI0A_DATA3
QSPI0A_DATA2
QSPI0A_DATA1
QSPI0A_DATA0
QSPI0B_DATA3
QSPI0B_DATA2
QSPI0B_DATA1
QSPI0B_DATA0
IOFA[7:0]
Serial I/O Flash A. These signals are
the data I/O lines to/from the serial
flash device A. Note that the signal
pins of the serial flash device may
change their function according to the
SFM Command executed, leaving
them as control inputs when Single
and Dual Instructions are executed.
The module supports driving these
inputs to dedicated values.
I/O
IOFB[3:0]
Serial I/O Flash B. These signals are
the data I/O lines to/from the serial
flash device B. Note that the signal
pins of the serial flash device may
change their function according to the
SFM Command executed, leaving
them as control inputs when Single
and Dual Instructions are executed.
The module supports driving these
inputs to dedicated values.
I/O
QSPI0A_DQS
DQSFA
Data Strobe signal Flash A. Data
strobe signal for port A. Some flash
vendors provide the DQS signal to
which the read data is aligned in DDR
mode.
I
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
45
NXP Semiconductors
Pinouts
4.3.5 Analog
Chip signal name
Table 18. ADC0 Signal Descriptions
Module signal
Description
I/O
name
ADC0_DP[1:0]
ADC0_DM[1:0]
ADC0_SEn
VREFH
DADP1–DADP0
Differential analog channel inputs
I
I
I
I
I
I
I
DADM1–DADM0 Differential Analog Channel Inputs
ADn
VREFSH
VREFSL
VDDA
Single-Ended Analog Channel Inputs1
Voltage Reference Select High
Voltage Reference Select Low
Analog power supply
VREFL
VDDA
VSSA
VSSA
Analog ground
1. See ADC channel assignment for the n.
Table 19. CMP0 Signal Descriptions
Chip signal name
CMP0_INn, n=[5,3:0]
CMP0_OUT
Module signal
Description
I/O
I
name
INn, n=[5,3:0]
Analog voltage inputs, see CMP input connection for more details
about the n.
CMPO
Comparator output
O
NOTE
There is no CMP0_IN[4] coming from pad.
Table 20. DAC0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
DAC0_OUT
—
DAC output
O
Table 21. VREF Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
VREF_OUT
VREF_OUT
Internally-generated Voltage Reference output
O
46
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
4.3.6 Timer Modules
Table 22. LPTMR0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
LPTMR0_ALT[2:1]
LPTMR_ALTn
Pulse Counter Input
I
Table 23. LPTMR1 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR1_ALT[2:1]
LPTMR_ALTn
Pulse Counter Input
I
Table 24. RTC Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
VBAT
EXTAL32
—
Backup battery supply for RTC and VBAT register file
32.768 kHz oscillator input
I
I
EXTAL32
XTAL32
XTAL32
32.768 kHz oscillator output
O
O
I/O
RTC_CLKOUT
RTC_WAKEUP_B
RTC_CLKOUT
RTC_WAKEUP
1 Hz square-wave output or OSCERCLK
Wakeup for external device
Table 25. TPM0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM0_CH[5:0]
TPM_CHn
A TPM channel pin is configured as output when configured in an
output compare or PWM mode and the TPM counter is enabled,
otherwise the TPM channel pin is an input.
I/O
Table 26. TPM1 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM1_CH[1:0]
TPM_CHn
A TPM channel pin is configured as output when configured in an
output compare or PWM mode and the TPM counter is enabled,
otherwise the TPM channel pin is an input.
I/O
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
47
NXP Semiconductors
Pinouts
Table 27. TPM2 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM1_CH[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM_CHn
A TPM channel pin is configured as output when configured in an
output compare or PWM mode and the TPM counter is enabled,
otherwise the TPM channel pin is an input.
I/O
4.3.7 Communication interfaces
Table 28. USB FS OTG signal descriptions
Chip signal name
Module signal
Description
I/O
name
usb_dm
usb_dp
—
USB0_DM
USB0_DP
USB D- analog data signal on the USB bus.
USB D+ analog data signal on the USB bus.
Alternate USB clock input
I/O
I/O
I
USB0_CLKIN
USB_VDD
—
USB domain power supply, 3.3 V.
I
USB0_SOF_OUT
—
USB start of frame signal. Can be used to make the USB start of
frame available for external synchronization.
O
Table 29. SPI0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
SPI0_PCS0
PCS0/SS
Peripheral Chip Select 0 (O) in the master mode and Slave Select
(I) in the slave mode
I/O
SPI0_PCS[1:3]
SPI0_PCS4
SPI0_PCS5
PCS[1:3]
PCS4
Peripheral Chip Selects 1–3 in the master mode
Peripheral Chip Select 4 in the master mode
O
O
O
PCS5
Peripheral Chip Select 5 /Peripheral Chip Select Strobe in the
master mode
SPI0_SIN
SPI0_SOUT
SPI0_SCK
SIN
SOUT
SCK
Serial Data In
I
Serial Data Out
O
Serial Clock (O) in the master mode and Serial Clock (I) in the
slave mode
I/O
48
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
Table 30. SPI1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
SPI1_PCS0
PCS0/SS
Peripheral Chip Select 0 (O) in the master mode and Slave
Select (I) in the slave mode
I/O
SPI1_PCS[1:3]
SPI1_SIN
PCS[1:3]
SIN
Peripheral Chip Selects 1–3 in the master mode
Serial Data In
O
I
SPI1_SOUT
SPI1_SCK
SOUT
SCK
Serial Data Out
O
Serial Clock (O) in the master mode and Serial Clock (I) in the
slave mode
I/O
Table 31. I2C0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C0_SCL
I2C0_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 32. I2C1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C1_SCL
I2C1_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 33. LPUART0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART0_CTS_b
LPUART0_RTS_b
LPUART0_TX
LPUART_CTS
LPUART_RTS
LPUART_TX
Clear to Send
I
Request to send
O
Transmit data. This pin is normally an output, but is an input
(tristated) in single wire mode whenever the transmitter is
disabled or transmit direction is configured for receive data.
I/O
LPUART0_RX
LPUART_RX
Receive Data
I
Table 34. LPUART1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART1_CTS_b
LPUART1_RTS_b
LPUART_CTS
LPUART_RTS
Clear to Send
I
Request to send
O
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
49
NXP Semiconductors
Pinouts
Table 34. LPUART1 signal descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
LPUART1_TX
LPUART_TX
Transmit data. This pin is normally an output, but is an input
(tristated) in single wire mode whenever the transmitter is
disabled or transmit direction is configured for receive data.
I/O
LPUART1_RX
LPUART_RX
Receive Data
I
Table 35. LPUART2 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART2_CTS_b
LPUART2_RTS_b
LPUART2_TX
LPUART_CTS
LPUART_RTS
LPUART_TX
Clear to Send
I
Request to send
O
Transmit data. This pin is normally an output, but is an input
(tristated) in single wire mode whenever the transmitter is disabled
or transmit direction is configured for receive data.
I/O
LPUART2_RX
LPUART_RX
Receive Data
I
Table 36. FlexIO signal descriptions
Chip signal name
Module signal
name
Description
I/O
FXIO0_Dn(n=0-31) FXIO_Dn (n=0...31) Bidirectional FlexIO Shifter and Timer pin inputs/outputs
I/O
Table 37. EMVSIM0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
EMVSIM0_ CLK
EMVSIM0_ IO
EMVSIM0_ PD
EMVSIM_SCLK
EMVSIM_IO
Card Clock. Clock to Smart Card.
O
I/O
I
Card Data Line. Bi-directional data line.
EMVSIM_PD
Card Presence Detect. Signal indicating presence or removal of
card
EMVSIM0_ RST
EMVSIM_SRST
Card Reset. Reset signal to Smart Card
O
O
EMVSIM0_ VCCEN EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card
Table 38. EMVSIM1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
EMVSIM1_ CLK
EMVSIM1_ IO
EMVSIM_SCLK
EMVSIM_IO
Card Clock. Clock to Smart Card.
O
Card Data Line. Bi-directional data line.
I/O
Table continues on the next page...
50
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
Table 38. EMVSIM1 signal descriptions (continued)
Chip signal name
EMVSIM1_ PD
Module signal
name
Description
I/O
EMVSIM_PD
Card Presence Detect. Signal indicating presence or removal of
card
I
EMVSIM1_ RST
EMVSIM_SRST
Card Reset. Reset signal to Smart Card
O
O
EMVSIM1_ VCCEN EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card
4.3.8 Human-machine interfaces (HMI)
Table 39. GPIO signal descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[31:0]1
PTB[31:0]1
PTC[31:0]1
PTD[31:0]1
PTE[31:0]1
PORTA31–PORTA0 General-purpose input/output
PORTB31–PORTB0 General-purpose input/output
PORTC31–PORTC0 General-purpose input/output
PORTD31–PORTD0 General-purpose input/output
PORTE31–PORTE0 General-purpose input/output
I/O
I/O
I/O
I/O
I/O
1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO
signals are available.
Table 40. TSI0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TSI0_CH[15:0]
TSI[15:0]
TSI capacitive pins. Switches driver that connects directly to the
electrode pins TSI[15:0] can operate as GPIO pins.
I/O
4.4 KL82 Pinouts
The below figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
51
NXP Semiconductors
Pinouts
1
2
3
4
5
6
7
8
9
10
11
PTD4/
LLWU_P14
PTC4/
LLWU_P8
PTD8/
LLWU_P24
A
B
C
D
E
F
G
H
J
PTD7
PTD5
PTC19
PTC14
PTC13
PTC8
PTD9
NC
A
B
C
D
E
F
G
H
J
PTD6/
LLWU_P15
PTC3/
LLWU_P7
PTE0
PTD3
PTC18
PTC17
PTC15
PTC12
PTC10
PTC9
VDD
PTC7
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTB16
PTB11
PTB10
PTB9
PTB4
PTB5
PTB8
PTB7
PTB6
PTE2/
PTE1/
PTD2/
PTC11/
LLWU_P11
PTC6/
LLWU_P10
PTC2
LLWU_P1 LLWU_P0 LLWU_P13
PTE4/
LLWU_P2
PTD0/
LLWU_P12
PTC5/
PTC1/
LLWU_P9 LLWU_P6
PTE3
PTE5
PTE8
PTD1
PTC16
PTE6/
LLWU_P16
PTD11/
LLWU_P25
VDDIO_E
PTD10
PTD12
PTD14
PTD15
NC
VDD
VSS
VSS
PTB23
PTB22
PTB3
PTE9/
LLWU_P17
PTE7
PTD13
VSS
VDDA
VREFH
NC
VSSA
VREFL
NC
PTB20
PTB1
PTE10/
LLWU_P18
PTB0/
LLWU_P5
PTE11
PTA11/
LLWU_P23
USB0_DM USB0_DP
PTA1
PTA3
PTA17
PTA16
VSS
PTA29
PTA4/
LLWU_P3 LLWU_P22
PTA10/
USB_VDD
RESET_b
NC
NC
NC
NC
PTA2
PTA5
DAC0_OUT/ RTC_WAK
ADC0_SE23 EUP_B
ADC0_DM0 ADC0_DP0
K
L
NC
VBAT
PTA12
PTA14
PTA19
K
L
VREF_OUT/
ADC0_DM1 ADC0_DP1 CMP0_IN5/
ADC0_SE22
PTA13/
LLWU_P4
XTAL32
4
EXTAL32
5
VSS
6
PTA0
7
PTA15
9
VDD
10
PTA18
11
1
2
3
8
Figure 5. KL82 121-pin MAPBGA pinout diagram
52
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Pinouts
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VDD
VSS
2
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
VSS
6
VDDIO_E
PTE4/LLWU_P2
PTE5
7
PTB23
8
PTB22
9
PTB21
PTE6/LLWU_P16
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTB20
PTB19
PTE8
PTB18
PTE9/LLWU_P17
PTE10/LLWU_P18
PTE11
PTB17
PTB16
VDD
VDDIO_E
VSS
VSS
PTB11
USB0_DP
USB0_DM
USB_VDD
NC
PTB10
PTB9
PTB3
PTB2
NC
PTB1
VDDA
PTB0/LLWU_P5
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 6. KL82 100-pin LQFP pinout diagram
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
53
NXP Semiconductors
Pinouts
1
PTE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
2
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VSS
3
PTC3/LLWU_P7
PTC2
4
5
VSS
PTC1/LLWU_P6
PTC0
6
VDDIO_E
PTE4/LLWU_P2
PTE5
7
PTB19
8
PTB18
9
PTE7
PTB17
10
11
12
13
14
15
16
17
18
19
20
PTE8
PTB16
PTE11
PTB11
VDDIO_E
VSS
PTB8
PTB7
USB0_DP
USB0_DM
USB_VDD
VDDA
PTB6
PTB5
PTB4
PTB1
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 7. KL82 80-pin LQFP pinout diagram
54
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
1
2
3
4
5
6
7
8
PTD4/
LLWU_P14
PTC11/
LLWU_P11
PTC6/
LLWU_P10 LLWU_P9
PTC5/
A
B
C
D
E
F
PTE0
PTD7
PTD1
PTC8
A
B
C
D
E
F
PTE1/
LLWU_P0 LLWU_P15
PTD6/
PTC4/
LLWU_P8
PTD3
PTC10
VSS
PTC9
PTE2/
PTC7
PTC2
PTD2/
PTD5
PTD0/
LLWU_P13 LLWU_P12
PTC1/
PTC3/
LLWU_P7
PTB19
LLWU_P1 LLWU_P6
VDDIO_E
PTE5
PTE3
PTA0
VDD
PTA1
PTA2
PTB18
PTB8
PTB6
PTB4
VSS
PTC0
PTB7
PTE4/
LLWU_P2
PTB0/
LLWU_P5
USB0_DP
VSS
VSS
VREF_OUT/
CMP0_IN5/
ADC0_SE22
RTC_WAK
EUP_B
USB0_DM USB_VDD
RESET_b
PTA19
PTB5
DAC0_OUT/
ADC0_SE23
PTA4/
LLWU_P3
ADC0_DM1
G
H
VSSA
VDDA
VBAT
G
H
ADC0_DP1
1
VREFL
2
VREFH
3
XTAL32
4
EXTAL32
5
PTA3
6
VDD
7
PTA18
8
Figure 8. KL82 64-pin MAPBGA pinout diagram
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
55
NXP Semiconductors
Pinouts
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
4
VSS
5
PTC1/LLWU_P6
PTC0
VDDIO_E
PTE4/LLWU_P2
PTE5
6
7
PTB19
8
PTB18
VSS
9
PTB8
USB0_DP
USB0_DM
USB_VDD
VDDA
10
11
12
13
14
15
16
PTB7
PTB6
PTB5
PTB4
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 9. KL82 64-pin LQFP pinout diagram
NOTE
The 100-, 64-pin LQFP and 64-pin MAPBGA packages for
this product are not yet available, however they are included
in a Package Your Way program for KL MCUs. Please visit
nxp.com/KPYW for more details.
56
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
4.5 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
Figure 10. 64-pin LQFP package dimensions 1
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
57
NXP Semiconductors
Pinouts
Figure 11. 64-pin LQFP package dimensions 2
58
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
Figure 12. 64-pin MAPBGA package dimension
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
59
NXP Semiconductors
Pinouts
Figure 13. 80-pin LQFP package dimension 1
60
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
Figure 14. 80-pin LQFP package dimension 2
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
61
NXP Semiconductors
Pinouts
Figure 15. 100-pin LQFP package dimension 1
62
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Pinouts
Figure 16. 100-pin LQFP package dimension 2
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
63
NXP Semiconductors
Electrical characteristics
Figure 17. 121-pin MAPBGA package dimension
5 Electrical characteristics
64
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.1 Terminology and guidelines
5.1.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
65
NXP Semiconductors
Electrical characteristics
5.1.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
5.1.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
66
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.1.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
67
NXP Semiconductors
Electrical characteristics
5.2.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
Max.
3.8
Unit
V
Digital supply voltage 1
VDDIO
IDD
VDDIO is an independent voltage supply for PORTE 2
–0.3
3.8
V
Digital supply current
—
300
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog3, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–0.3
VDD + 0.3
VDD + 0.3
25
VAIO
–0.3
V
ID
–25
mA
V
VDDA
VUSB0_DP
VUSB0_DM
VBAT
VDD – 0.3
–0.3
VDD + 0.3
3.63
USB0_DP input voltage
V
USB0_DM input voltage
–0.3
3.63
V
RTC battery supply voltage
–0.3
3.8
V
1. It applies for all port pins.
2. VDDIO is independent of VDD domain and can operate at a voltage independent of VDD. However, it is required that VDD
domain be powered up first prior to VDDIO. VDDIO must never be higher than VDD during power ramp up, or power down.
VDD and VDDIO may ramp together if tied to the same power supply.
68
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5.3 General
5.3.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 18. Input signal measurement reference
5.3.2 Nonswitching electrical specifications
5.3.2.1 Voltage and current operating requirements
Table 41. Voltage and current operating requirements
Symbol
Description
Min.
1.71
Max.
3.6
3.6
3.6
3.6
0.1
0.1
3.6
—
Unit
V
Notes
VDD
Supply voltage
USB_VDD Supply voltage
3.0
V
1
VDDIO_E
VDDA
Supply voltage
VDD
V
Analog supply voltage
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
1.71
V
0.7 × VDD
0.75 × VDD
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
VIL
Input low voltage
—
0.35 × VDD
V
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
69
NXP Semiconductors
Electrical characteristics
Table 41. Voltage and current operating requirements (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V
Min.
Max.
Unit
Notes
—
0.3 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
Input hysteresis
0.06 × VDD
—
V
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
1. The ripple limit for USB_VDD is 100 mV.
5.3.2.2 LVD and POR operating requirements
Table 42. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
40
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
70
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 43. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
5.3.2.3 Voltage and current operating behaviors
Table 44. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Not
es
VOH
Output high voltage 3.3 V, Iload = -5 mA
VDD – 0.5
VDD – 0.5
—
—
—
V
V
1
— Standard IO
1.71 V, Iload = -2.5 mA
IOHT
Output high current total for all ports
100
—
mA
V
VOH_RTC_WAKEUP Output high voltage 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA
VBAT – 0.5
VBAT – 0.5
— normal drive pad
1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5
—
V
mA
IOH_RTC_WAKEUP Output high current total for RTC_WAKEUP pins
—
100
0.5
0.5
0.5
0.5
100
0.5
0.5
—
mA
V
VOL
VOL
IOLT
Output low voltage
— Standard IO
3.3 V, Iload = 5 mA
1.71 V, Iload = 2.5 mA
3.3 V, Iload = 5 mA
1.71 V, Iload = 2.5 mA
—
1
1
—
Output low voltage
— RESET_b
—
V
—
Output low current total for all ports
—
mA
V
VOL_RTC_WAKEUP Output low voltage— 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 5 mA
—
normal drive pad
1.71 V ≤ VBAT ≤ 2.7 V, IOL = 2.5 mA
—
VOH
Output high voltage 3.3 V, Iload = 15 mA
VDD – 0.5
V
V
2
2
— Standard fast IO
1.71V, Iload = 7.5 mA
VDD – 0.5
—
VOL
Output high voltage 3.3 V, Iload = 15 mA
—
—
—
—
—
—
—
20
20
0.5
0.5
100
0.5
0.002
0.25
0.25
50
— Standard fast IO
1.71 V, Iload =7.5 mA
IOL_RTC_WAKEUP Output low current total for RTC_WAKEUP pins
mA
µA
µA
µA
µA
kΩ
kΩ
IIN
IIN
Input leakage current (per pin) for full temperature range
Input leakage current (per pin) at 25 °C
3
3
IOZ
Hi-Z (off-state) leakage current (per pin)
IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per RTC_WAKEUP pin)
RPU
RPD
Internal pullup resistors
4
5
Internal pulldown resistors
50
1. This is applicanble for all GPIO pins except PTE
2. This is applicable for PTE pins only.
3. Measured at VDD=3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
71
NXP Semiconductors
Electrical characteristics
5.3.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 24 MHz
• Flash clock = 24 MHz
• MCG mode=FEI
Table 45. Power mode transition operating behaviors
Symbol Description
Min.
Max.
Unit
Notes
tPOR After a POR event, amount of time VDD slew rate ≥ 5.7
—
300
µs
1
from the point VDD reaches 1.71 V kV/s
to execution of the first instruction
across the operating temperature
range of the chip.
VDD slew rate < 5.7
kV/s
—
1.7 V/
(VDD slew
rate)
—
—
—
—
—
—
—
—
138
138
76
µs
µs
µs
µs
µs
µs
µs
µs
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
76
6.1
6.1
5.6
5.6
1. Normal boot (FTFA_FOPT[LPBOOT]=1)
Table 46. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1051
IIREFSTEN4MHz
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52
52
52
52
52
52
µA
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
72
NXP Semiconductors
Electrical characteristics
Table 46. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1051
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
206
228
237
245
251
258
µA
IEREFSTEN32KHz
External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with the
crystal enabled.
VLLS1
VLLS3
LLS2
440
440
490
490
510
510
22
490
490
490
490
560
560
22
540
540
540
540
560
560
22
560
560
560
560
560
560
22
570
570
570
570
610
610
22
580
580
680
680
680
680
22
nA
LLS3
VLPS
STOP
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
µA
nA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432
66
357
66
388
66
475
66
532
66
810
66
IUART
UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
µA
OSCERCLK
(4 MHz
external
crystal)
214
86
237
86
246
86
254
86
260
86
268
86
ITPM
TPM peripheral adder
MCGIRCLK
(4 MHz
internal
reference
clock)
µA
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and I/O
switching currents.
OSCERCLK
(4 MHz
external
crystal)
235
256
265
274
280
287
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
366
366
366
366
366
366
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
73
NXP Semiconductors
Electrical characteristics
Table 46. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
50 70
Unit
-40
25
85
1051
configured for low power mode using the
internal clock and continuous conversions.
1. Only LQFP and MAPBGA packages support the data in this column.
5.3.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The data at 105 °C is for MAPBGA and LQFP packages only.
Table 47. Power consumption operating behaviors
Symbol
IDDA
Description
Typ.
—
Max.
See note
17.32
Unit
mA
mA
Notes
Analog supply current
1
IDD_HSRUN
Running CoreMark in Flash in
Compute Operation mode, Core at
96 MHz, bus at 24 MHz, flash at 24
MHz, VDD = 3 V
25 °C
25 °C
25 °C
14.21
2, 3
IDD_HSRUN
IDD_HSRUN
IDD_RUN
Running CoreMark in Flash, all
peripheral clock disabled, Core at 96
MHz, bus at 24 MHz, flash at 24
MHz, VDD = 3 V
15.43
20.01
18.54
23.12
mA
mA
mA
mA
mA
mA
2, 3
2, 3
2, 4
2, 4
2, 5
2, 5
Running CoreMark in Flash, all
peripheral clock enabled, Core at 96
MHz, bus at 24 MHz, flash at 24
MHz, VDD = 3 V
Running CoreMark in Flash in
Compute Operation mode, Core at
72 MHz, bus at 24 MHz, flash at 24
MHz, VDD = 3 V
25 °C
8.99
9.43
10.59
10.88
105 °C
IDD_RUN
Running CoreMark in Flash all
peripheral clock disabled, Core at 72
MHz, bus at 24 MHz,flash at 24
MHz , VDD = 3 V
25 °C
10.1
11.70
12.00
105 °C
10.55
IDD_RUN
Running CoreMark in Flash all
peripheral clock disabled, Core at 48
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
9.1
10.70
10.99
105 °C
9.54
IDD_RUN
Running CoreMark in Flash all
peripheral clock disabled, Core at 24
MHz, bus at 12 MHz, flash at 12
MHz , VDD = 3 V
25 °C
5.57
6.02
7.17
7.47
105 °C
Table continues on the next page...
74
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
2.8
Max.
4.40
4.67
Unit
Notes
IDD_RUN
Running CoreMark in Flash all
peripheral clock disabled, Core at 12
MHz, bus at 6 MHz, flash at 6 MHz ,
VDD = 3 V
25 °C
mA
2, 5
105 °C
3.22
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
IDD_WAIT
IDD_WAIT
IDD_WAIT
Running CoreMark in Flash all
peripheral clock enabled, Core at 72
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
12.94
13.35
14.54
14.80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2, 4
4
105 °C
Running While(1) loop in Flash, all
peripheral clock disabled Core at 72
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
7.6
9.20
9.53
105 °C
8.08
Running While(1) loop in Flash, all
peripheral clock disabled Core at 48
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
6.3
7.90
8.24
5
105 °C
6.79
Running While(1) loop in Flash, all
peripheral clock disabled Core at 24
MHz, bus at 12 MHz, flash at 12
MHz , VDD = 3 V
25 °C
4.08
4.53
5.68
5.98
5
105 °C
Running While(1) loop in Flash, all
peripheral clock disabled Core at 12
MHz, bus at 6 MHz, flash at 6 MHz ,
VDD = 3 V
25 °C
3.03
3.46
4.63
4.91
5
105 °C
Running While(1) loop in Flash, all
peripheral clock enabled Core at 72
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
10.93
11.45
12.53
12.90
4
105 °C
Running CoreMark loop in SRAM all
peripheral clock disabled, Core at 72
MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
11.64
12.17
13.24
13.62
2, 4
2, 4
4
105 °C
Running CoreMark loop in SRAM in
Compute Operation mode, Core at
72 MHz, bus at 24 MHz, flash at 24
MHz , VDD = 3 V
25 °C
10.52
11.03
12.12
12.48
105 °C
Core disabled, system at 72 MHz,
bus at 24 MHz, flash disabled (flash
doze enabled), VDD = 3 V, all
peripheral clocks disabled
25 °C
25 °C
25 °C
5.11
4.33
2.76
6.47
5.69
4.12
Core disabled, system at 48 MHz,
bus at 24 MHz, flash disabled (flash
doze enabled), VDD = 3 V, all
peripheral clocks disabled
5
Core disabled, system at 24 MHz,
bus at 12 MHz, flash disabled (flash
doze enabled), VDD = 3 V, all
peripheral clocks disabled
5
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
75
NXP Semiconductors
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_WAIT
Core disabled, system at 12 MHz,
bus at 6 MHz, flash disabled (flash
doze enabled), VDD = 3 V, all
peripheral clocks disabled
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
1.98
3.34
mA
5
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPW
Very Low Power Run Core Mark in
Flash in Compute Operation mode:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
845
1033
898
328
460
256
34
936.88
1145.32
995.64
380.03
512.03
308.03
64.00
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
2, 6
2, 6
2, 6
6
Very Low Power Run Core Mark in
Flash all peripheral clock enabled:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
Very Low Power Run Core Mark in
Flash all peripheral clock disabled:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
Very Low Power Run While(1) loop
in Flash all peripheral clock disabled
mode: Core at 4 MHz, bus at 1 MHz,
flash at 1 MHz, VDD = 3 V
Very Low Power Run While(1) loop
in Flash all peripheral clock enabled:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
6
Very Low Power Run While(1) loop
in Flash all peripheral clock disabled
mode: Core at 2 MHz, bus at 0.5
MHz, flash at 0.5 MHz, VDD = 3 V
6
Very Low Power Run While(1) loop
in Flash all peripheral clock disabled
mode: Core at 125 kHz, bus at 31.25
kHz, flash at 31.25 kHz, VDD = 3 V
6
Very Low Power Run Core Mark in
SRAM in Compute Operation mode:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
591
777
643
297
655.26
861.48
712.91
349.03
2, 6
2, 6
2, 6
6
Very Low Power Run Core Mark in
SRAM all peripheral clock enable:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
Very Low Power Run Core Mark in
SRAM all peripheral clock disable:
Core at 4 MHz, bus at 1 MHz, flash
at 1 MHz, VDD = 3 V
Very Low Power Run Wait current,
core disabled, system at 4 MHz, bus
and flash at 1 MHz, all peripheral
clocks disabled, VDD = 3 V
Table continues on the next page...
76
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_VLPW
Very Low Power Run Wait current,
core disabled, system at 2 MHz, bus
and flash at 0.5 MHz, all peripheral
clocks disabled, VDD = 3 V
25 °C
225
277.03
μA
6
IDD_VLPW
Very Low Power Run Wait current,
core disabled, system at 125 kHz,
bus and flash at 31.25 kHz, all
peripheral clocks disabled, VDD = 3
V
25 °C
31
61.00
μA
6
7
IIDD_PSTOP2
Partial stop 2, core and system clock
disabled, bus and flash at 12 MHz,
VDD = 3 V
25 °C
2.9
4.26
mA
μA
IDD_STOP
Stop mode current at 3.0 V
VLPS current, VDD= 3 V
VLPS current, VDD= 1.8 V
25 °C and
below
273
304.31
50°C
85 °C
105 °C
306
440
625
5.82
384.47
589.29
925.33
15.42
IDD_VLPS
IDD_VLPS
IDD_LLS3
25 °C and
below
μA
μA
μA
50 °C
85 °C
105°C
14.41
56.47
121.54
5.61
29.41
99.67
223.54
15.21
25 °C and
below
50 °C
85 °C
14.01
55.8
29.01
99.00
222.14
7.88
105 °C
120.14
3.68
LLS3 current, all peripheral disabled, 25 °C and
VDD = 3 V
below
50 °C
70 °C
85 °C
105 °C
8.28
13.52
20.91
40.27
5.08
15.48
22.52
39.55
67.79
9.28
IDD_LLS3
LLS3 with RTC current, VDD = 3 V
25 °C and
below
μA
μA
50 °C
70 °C
85 °C
105 °C
10.31
15.76
22.8
17.51
24.76
41.44
71.02
9.22
43.5
IDD_LLS3
LLS3 with RTC current, VDD = 1.8 V 25 °C and
below
5.02
50 °C
10.06
17.26
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
77
NXP Semiconductors
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
15.15
21.88
41.82
3.37
Max.
24.15
40.52
69.34
6.67
Unit
Notes
70 °C
85 °C
105 °C
IDD_LLS2
LLS2 current, all peripheral disabled, 25 °C and
μA
VDD = 3 V
below
50 °C
70 °C
85 °C
105 °C
6.82
11.13
16.84
32.93
4.49
13.42
20.73
31.46
48.89
7.79
IDD_LLS2
IDD_LLS2
IDD_VLLS3
IDD_VLLS3
IDD_VLLS3
LLS2 with RTC current, VDD = 3 V
25 °C and
below
μA
μA
μA
μA
μA
50 °C
70 °C
85 °C
105 °C
9.07
12.98
17.88
35.98
4.47
16.27
22.58
32.50
51.94
7.77
LLS2 with RTC current, VDD = 1.8 V 25 °C and
below
50 °C
8.79
12.27
17.77
34.31
2
15.99
21.87
32.39
50.27
3.80
70 °C
85 °C
105 °C
VLLS3 current, all peripheral disable, 25 °C and
VDD = 3 V
below
50 °C
70 °C
85 °C
105 °C
3.76
7.19
7.36
12.82
21.10
42.33
4.63
12.62
27.61
2.83
VLLS3 with RTC current, VDD = 3 V 25 °C and
below
50 °C
4.62
8.38
8.22
14.01
21.54
44.53
4.39
70 °C
85 °C
105 °C
14.06
29.81
2.59
VLLS3 with RTC current, VDD = 1.8 25 °C and
V
below
50 °C
70 °C
85 °C
105 °C
4.28
7.89
7.88
13.52
20.81
43.06
13.33
28.34
Table continues on the next page...
78
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_VLLS2
VLLS2 current, all peripheral disable, 25 °C and
1.98
3.78
μA
VDD = 3 V
below
50 °C
70 °C
85 °C
105 °C
2.95
4.83
7.95
16.92
2.8
5.71
9.33
13.80
24.26
4.60
IDD_VLLS2
VLLS2 with RTC current, VDD = 3 V 25 °C and
below
μA
μA
μA
μA
μA
nA
50 °C
3.74
5.96
9.35
19.37
2.56
6.50
10.46
15.20
26.71
4.36
70 °C
85 °C
105 °C
IDD_VLLS2
VLLS2 with RTC current, VDD = 1.8 25 °C and
V
below
50 °C
70 °C
85 °C
105 °C
3.43
5.51
6.19
10.01
14.46
26.21
1.11
8.61
18.87
0.718
IDD_VLLS1
VLLS1 current, all peripheral disable, 25 °C and
VDD = 3 V
below
50 °C
70 °C
85 °C
105 °C
1.28
2.4
2.48
4.56
7.62
15.68
1.90
4.38
10.28
1.51
IDD_VLLS1
VLLS1 with RTC current, VDD = 3 V 25 °C and
below
50 °C
2.13
3.65
5.76
12.89
1.26
3.63
6.29
9.00
18.29
1.65
70 °C
85 °C
105 °C
IDD_VLLS1
VLLS1 with RTC current, VDD = 1.8 25 °C and
V
below
50 °C
70 °C
85 °C
105 °C
1.73
2.93
4.98
11.21
432
3.23
5.57
8.22
16.61
835
IDD_VLLS0
VLLS0 current, all peripheral
disabled,
25 °C and
below
(SMC_STOPCTRL[PORPO] = 0),
VDD = 3 V
50 °C
70 °C
986
1723
3270
2030
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
79
NXP Semiconductors
Electrical characteristics
Table 47. Power consumption operating behaviors (continued)
Symbol
Description
Typ.
4000
9760
272
Max.
5546
12709
520
Unit
Notes
85 °C
105 °C
IDD_VLLS0
VLLS0 current, all peripheral
disabled,
25 °C and
below
nA
(SMC_STOPCTRL[PORPO] = 1),
VDD = 3 V
50 °C
70 °C
85 °C
105 °C
743
1700
3650
9300
160
1398
2927
5177
12191
218.10
IDD_VBAT
IDD_VBAT
IDD_VBAT
IDD_VBAT
Average current with RTC and 32
kHz disabled at 3 V
25 °C and
below
nA
nA
nA
nA
50 °C
70 °C
85 °C
105 °C
269
483
366.96
714.32
1211.88
2715.16
195.10
851
1870
137
Average current with RTC and 32
kHz disabled at 1.8 V
25 °C and
below
50 °C
70 °C
85 °C
105 °C
230
422
327.96
653.32
1106.88
2505.16
784.00
746
1660
676
Average current when CPU is not
accessing RTC register at 3.0 V
including 32 kHz
25 °C and
below
50 °C
70 °C
85 °C
105 °C
809
1040
1420
2460
556
1013.00
1538.08
2022.17
3571.81
664.00
Average current when CPU is not
accessing RTC register at 1.8 V
including 32 kHz
25 °C and
below
50 °C
70 °C
85 °C
105 °C
674
880
878.00
1378.08
1822.17
3271.81
1220
2160
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. CoreMark benchmark compiled using IAR 7.40 with optimization level high, optimized for balanced.
3. MCG configured for PEE mode.
4. MCG configured for FEE mode.
5. MCG configured for PBE mode.
6. MCG configured for BLPE mode.
7. MCG configured for FEI mode.
80
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.3.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Temperature=25, VDD=3V
Cache-- CG
-- CoreFreq
--Core:Bus:Flash:QSPI
Figure 19. Run mode supply current vs. core frequency
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
81
NXP Semiconductors
Electrical characteristics
Temperature=25, VDD=3V
Cache-- CG
-- CoreFreq
--Core:Bus:Flash:QSPI
Figure 20. VLPR mode supply current vs. core frequency
5.3.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following applications notes, available on nxp.com for advice and guidance
specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
• KL-QRUG (Kinetis L-series Quick Reference).
82
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.3.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for "EMC design"
5.3.2.8 Capacitance attributes
Table 48. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3.3 Switching specifications
5.3.3.1 Device clock specifications
Table 49. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
System and core clock
—
96
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
fBUS
System and core clock
Bus clock
—
—
36
—
—
72
24
—
24
25
MHz
MHz
MHz
MHz
MHz
fFBUS
fFLASH
fLPTMR
Bus interface clock for QSPI
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
2
4
1
MHz
MHz
MHz
MHz
MHz
MHz
fFBUS
fFLASH
fERCLK
fLPTMR
Bus interface clock for QSPI
Flash clock
—
1
—
—
—
External reference clock
LPTMR clock
16
16
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
83
NXP Semiconductors
Electrical characteristics
5.3.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO,
LPUART, timers, and I2C signals.
Table 50. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter disabled, analog
filter enabled) — Asynchronous path
16 2
50
—
—
ns
3
3
GPIO pin interrupt pulse width (digital glitch filter disabled, analog
filter disabled) — Asynchronous path
ns
External reset pulse width (digital glitch filter disabled)
100
—
—
34
16
ns
ns
3
Port rise and fall time
(high drive) — slew
enabled
1.71 V < VDDIO_E < 2.7 V
2.7 V < VDDIO_E ≤ 3.6 V
4, 5
—
Port rise and fall time
(high drive) — slew
disabled
1.71 V < VDDIO_E < 2.7 V
2.7 V < VDDIO_E ≤ 3.6V
—
—
4.5
3
ns
4, 5
Port rise and fall time (low 1.71 V < VDDIO_E < 2.7 V
—
—
—
—
25
16
ns
ns
6, 5
6, 5
drive) — slew enabled
2.7 V < VDDIO_E ≤ 3.6 V
Port rise and fall time
(high drive) — slew
disabled
1.71 V < VDDIO_E < 2.7 V
2.7 V < VDDIO_E ≤ 3.6V
4.2
2.5
Port rise and fall time (low 1.71 < VDDIO_E < 2.7V
—
—
—
—
25
13
ns
ns
6, 7
6, 7
drive) — slew enabled
2.7 < VDDIO_E ≤ 3.6V
Port rise and fall time (low 1.71 < VDDIO_E < 2.7V
5.5
3.5
drive) — slew disabled
2.7 < VDDIO_E ≤ 3.6V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. This is applicable for Port E pins
6. 25 pF load
7. This is applicable for Ports A, B, C, and D.
5.3.4 Thermal specifications
84
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.3.4.1 Thermal operating requirements
Table 51. Thermal operating requirements
Symbol
Description
Min.
–40
–40
Max.
125
Unit
°C
TJ
Die junction temperature
Ambient temperature
1
TA
105
°C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + θJA x chip power dissipation
5.3.4.2 Thermal attributes
Board type
Symbol
Descriptio
n
121
MAPBGA
80 LQFP
64
MAPBGA
Unit
Notes
Single-layer RθJA
(1s)
Thermal
75.5
55
92.2
°C/W
1
1
1
1
resistance,
junction to
ambient
(natural
convection)
Four-layer
(2s2p)
RθJA
Thermal
43.5
60.0
38.3
40
44
34
45.4
72.9
40.1
°C/W
°C/W
°C/W
resistance,
junction to
ambient
(natural
convection)
Single-layer RθJMA
(1s)
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance,
junction to
board
23.1
8.2
24
12
2
20.4
19.4
0.7
°C/W
°C/W
°C/W
2
3
4
Thermal
resistance,
junction to
case
Thermal
characterizati
on
0.5
parameter,
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
85
NXP Semiconductors
Electrical characteristics
Board type
Symbol
Descriptio
n
121
MAPBGA
80 LQFP
64
MAPBGA
Unit
Notes
junction to
package top
outside
center
(natural
convection)
—
RθJB_CSB
Thermal
characterizati
on
14.6
—
19.5
°C/W
5
parameter,
junction to
package top
outside
center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
5.4 Peripheral operating requirements and behaviors
5.4.1 Core modules
5.4.1.1 Debug trace timing specifications
Table 52. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
1.5
1.0
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
ns
86
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
5.4.1.2 SWD electricals
Table 53. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 21. Serial wire clock input timing
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
87
NXP Semiconductors
Electrical characteristics
SWD_CLK
J9
J10
Input data valid
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J11
Output data valid
J12
J11
Output data valid
Figure 22. Serial wire data timing
5.4.2 Clock modules
5.4.2.1 MCG specifications
Table 54. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
—
—
20
32
0.3
—
µA
µs
tirefsts
[O: ] Internal reference (slow clock) startup time
—
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.6
%fdco
1
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
—
0.2
1
0.5
2
%fdco
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
Table continues on the next page...
88
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
Table 54. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
0.5
1
%fdco
1
fintf_ft
fintf_t
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
Iintf
Internal reference (fast clock) current
—
—
25
10
—
—
15
—
µA
µs
tirefsts
floc_low
[L: ] Internal reference startup time (fast clock)
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
ext clk freq: above (3/5)fint never reset
ext clk freq: between (2/5)fint and (3/5)fint maybe
reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
16.0
—
39.0625
26.66
kHz
fdco_ut
DCO output
Low range
23.04
MHz
2
frequency range
— untrimmed
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
32.0
48.0
64.0
18.3
36.6
46.08
69.12
92.16
26.35
52.70
53.32
79.99
106.65
30.50
60.99
(DRS=01, DMX32=0)
1280 × fints_ut
Mid-high range
(DRS=10, DMX32=0)
1920 × fints_ut
High range
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
89
NXP Semiconductors
Electrical characteristics
Symbol Description
Table 54. MCG specifications (continued)
Min.
Typ.
Max.
Unit
Notes
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
54.93
79.09
91.53
(DRS=10, DMX32=1)
2197 × fints_ut
High range
73.23
105.44
122.02
(DRS=11, DMX32=1)
2929 × fints_ut
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
40
60
80
—
—
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
25
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
3, 4
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fpll_ref
fvcoclk_2x VCO output frequency
fvcoclk PLL output frequency
fvcoclk_90 PLL quadrature output frequency
PLL reference frequency range
8
—
—
—
—
16
MHz
MHz
MHz
MHz
180
90
360
180
180
90
Ipll
PLL operating current
8
8
—
—
2.8
—
mA
• VCO at 184 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 23)
Ipll
PLL operating current
3.6
—
mA
• VCO at 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
90
NXP Semiconductors
Electrical characteristics
Table 54. MCG specifications (continued)
Symbol Description
Jcyc_pll PLL period jitter (RMS)
Min.
Typ.
Max.
Unit
Notes
9
• fvco = 180 MHz
• fvco = 360 MHz
—
—
120
75
—
—
ps
ps
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
9
—
—
1350
600
—
—
ps
ps
• fvco = 360 MHz
Dunl
Lock exit frequency tolerance
Lock detector detection time
4.47
—
—
—
5.97
150 × 10-6
+ 1075(1/
%
s
tpll_lock
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
5.4.2.2 IRC48M specifications
Table 55. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
520
48
μA
Internal reference frequency
—
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
• Regulator disable
—
—
0.5
0.5
1.5
1.5
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
—
0.5
1.5
%firc48m
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
91
NXP Semiconductors
Electrical characteristics
Table 55. IRC48M specifications (continued)
Symbol
Description
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Min.
Typ.
Max.
Unit
Notes
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
—
—
0.1
%fhost
1
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
2
1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
5.4.2.3 Oscillator electrical specifications
5.4.2.3.1 Oscillator DC electrical specifications
Table 56. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
600
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
7.5
500
650
2.5
3.25
4
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
Cx
Cy
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
2, 3
2, 3
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
92
NXP Semiconductors
Electrical characteristics
Table 56. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RF Feedback resistor — low-frequency, low-power
—
—
—
MΩ
2, 4
mode (HGO=0)
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
kΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
5.4.2.3.2 Oscillator frequency specifications
Table 57. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Table continues on the next page...
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
93
NXP Semiconductors
Electrical characteristics
Table 57. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
—
8
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
tdc_extal Input clock duty cycle (external clock mode)
40
—
50
60
—
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
1, 2
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
5.4.2.4 32 kHz oscillator electrical characteristics
5.4.2.4.1 32 kHz oscillator DC electrical specifications
Table 58. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
94
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.4.2.4.2 32 kHz oscillator frequency specifications
Table 59. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
5.4.3 Memories and memory interfaces
5.4.3.1 QuadSPI AC specifications
• All data is based on a negative edge data launch from the device and a positive
edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15pf (1.8V) and 35pf (3V) on output pins. Input
slew: 1ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the
reference manual for details).
The following table lists the QuadSPI delay chain read/write settings. Please see the
device reference manual for register and bit descriptions.
Table 60. QuadSPI delay chain read/write settings
Mode
QuadSPI registers
Notes
QuadSPI_MCR[DQ QuadSPI_SOCCR[ QuadSPI_MCR[SC QuadSPI_FLSHC
S_EN]
SOCCFG]
LKCFG]
R[TDH]
SDR
DDR
Yes
3Fh
5
No
Delay of 63
buffer and 64
mux
Yes
3Fh
0h
1
2
2
Delay of 63
buffer and 64
mux
Hyperflash
RDS driven from
Flash
No
Delay of 1 mux
SDR mode
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
95
NXP Semiconductors
Electrical characteristics
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tis
Tih
Data in
Figure 23. QuadSPI input timing (SDR mode) diagram
NOTE
• The below timing values are with default settings for
sampling registers like QuadSPI_SMPR.
• A negative time indicates the actual capture edge inside
the device is earlier than clock appearing at pad.
• The below timing are for a load of 15pf (1.8V) and 35pf
(3V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 61. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Tih
Setup time for incoming data
4
—
—
ns
ns
Hold time requirement for incoming data
1.5
96
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Toh
Tov
Data out
Figure 24. QuadSPI output timing (SDR mode) diagram
Table 62. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
—
-1.4
—
2
2.8
—
ns
Toh
Tck
ns
96
—
MHz
ns
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
-1
—
ns
NOTE
For any frequency setup and hold specifications of the
memory should be met.
DDR Mode
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tih
Tis
Data in
Figure 25. QuadSPI input timing (DDR mode) diagram
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
97
NXP Semiconductors
Electrical characteristics
NOTE
• Numbers are for a load of 15pf (1.8V) and 35pf (3V)
• The numbers are for setting of hold condition in register
QuadSPI_SMPR[DDRSNP]
Table 63. QuadSPI input timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Setup time for incoming data
4 (Without
learning)
—
—
—
ns
ns
1 (With
learning)
Tih
Hold time requirement for incoming data
1.5
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tov
Toh
Data out
Figure 26. QuadSPI output timing (DDR mode) diagram
Table 64. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Toh
Tck
Output Data Valid
Output Data Hold
SCK clock period
—
1.5
—
—
2
4.5
ns
—
ns
72 (with learning)
MHz
45 (without learning)
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
—
—
Clk(sck)
Clk(sck)
-1
Hyperflash mode
98
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
RDS
TsMIN
ThMIN
DI[7:0]
Figure 27. QuadSPI input timing (Hyperflash mode) diagram
Table 65. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TsMIN
ThMIN
Setup time for incoming data
2
2
—
—
ns
ns
Hold time requirement for incoming data
CK
CK 2
TclkSKMAX
TclkSKMIN
THO
TDVO
Output Invalid Data
Figure 28. QuadSPI output timing (Hyperflash mode) diagram
Table 66. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TdvMAX
Output Data Valid
—
4.3
ns
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
99
NXP Semiconductors
Electrical characteristics
Table 66. QuadSPI output timing (Hyperflash mode) specifications (continued)
Symbol
Parameter
Value
Unit
Min
Max
Tho
Output Data Hold
1.3
—
—
ns
TclkSKMAX
TclkSKMIN
Ck to Ck2 skew max
Ck to Ck2 skew min
T/4 + 0.5 ns
— ns
T/4 - 0.5
NOTE
Maximum clock frequency = 72 MHz.
5.4.3.2 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
5.4.3.2.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 67. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
13
113
904
ms
ms
thversall
Erase All high-voltage time
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
5.4.3.2.2 Flash timing specifications — commands
Table 68. Flash command timing specifications
Symbol Description
Min.
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec2k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
45
μs
—
—
30
μs
1
—
65
145
114
0.9
30
μs
—
2
tersscr
trd1all
—
14
ms
ms
μs
—
—
1
trdonce
—
—
1
tpgmonce Program Once execution time
tersall Erase All Blocks execution time
—
100
140
—
μs
—
2
—
1150
ms
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
100
NXP Semiconductors
Electrical characteristics
Table 68. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.3.2.3 Flash high voltage current behaviors
Table 69. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
5.4.3.2.4 Reliability specifications
Table 70. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.4.5 Analog
5.4.5.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 1 and Table 72 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
101
NXP Semiconductors
Electrical characteristics
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
5.4.5.1.1 16-bit ADC operating conditions
Table 71. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 ×
VREFH
—
—
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
ksps
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
102
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 29. ADC input impedance equivalency diagram
5.4.5.1.2 16-bit ADC electrical characteristics
Table 72. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
103
NXP Semiconductors
Electrical characteristics
Table 72. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
INL
Integral non-linearity
• 12-bit modes
—
1.0
–2.7 to
+1.9
LSB4
5
• <12-bit modes
—
0.5
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's
voltage and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
104
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 30. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 31. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
105
NXP Semiconductors
Electrical characteristics
5.4.5.2 CMP and 6-bit DAC electrical specifications
Table 73. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
106
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 32. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
107
NXP Semiconductors
Electrical characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 33. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
5.4.5.3 12-bit DAC electrical characteristics
5.4.5.3.1 12-bit DAC operating requirements
Table 74. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
108
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.4.5.3.2 12-bit DAC operating behaviors
Table 75. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
700
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
3.7
—
μV/C
%FSR/C
μV/yr
Ω
6
0.000421
—
—
100
250
Rop
SR
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
—
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
109
NXP Semiconductors
Electrical characteristics
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 34. Typical INL error vs. digital code
110
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Electrical characteristics
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 35. Offset at half scale vs. temperature
5.4.5.4 Voltage reference electrical specifications
Table 76. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
1.71
3.6
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
111
NXP Semiconductors
Electrical characteristics
Symbol Description
Table 77. VREF full-range operating behaviors
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 78. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 79. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
5.4.6 Timers
See General switching specifications.
5.4.7 Communication interfaces
112
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
5.4.7.1 EMV SIM specifications
Each EMV SIM module interface consists of a total of five pins.
The interface is designed to be used with synchronous Smart cards, meaning the EMV
SIM module provides the clock used by the Smart card. The clock frequency is
typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also
work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the
EMV SIM module provides to the Smart card is used by the Smart card to recover the
clock from the data in the same manner as standard UART data exchanges. All five
signals of the EMV SIM module are asynchronous with each other.
There are no required timing relationships between signals in normal mode. The smart
card is initiated by the interface device; the Smart card responds with Answer to
Reset. Although the EMV SIM interface has no defined requirements, the ISO/IEC
7816 defines reset and power-down sequences (for detailed information see ISO/IEC
7816).
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 36. EMV SIM Clock Timing Diagram
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
113
NXP Semiconductors
Electrical characteristics
The following table defines the general timing requirements for the EMV SIM
interface.
Table 80. Timing Specifications, High Drive Strength
ID
Parameter
Symbol
Min
Max
Unit
MHz
SI EMV SIM clock frequency (EMVSIMn_CLK)1
1
SI EMV SIM clock rise time (EMVSIMn_CLK)2
2
SI EMV SIM clock fall time (EMVSIMn_CLK)2
3
Sfreq
Srise
Sfall
0.01
25
—
0.09 × (1/Sfreq)
ns
ns
ns
ns
ns
—
0.09 × (1/Sfreq)
SI EMV SIM input transition time (EMVSIMn_IO,
4
Si EMV SIM I/O rise time / fall time (EMVSIMn_IO)3
5
Si EMV SIM RST rise time / fall time (EMVSIMn_RST)4
6
Stran
Tr/Tf
Tr/Tf
20
—
25
1
EMVSIMn_PD)
—
1
1. 50% duty cycle clock,
2. With C = 50 pF
3. With Cin = 30 pF, Cout = 30 pF,
4. With Cin = 30 pF,
5.4.7.1.1 EMV SIM Reset Sequences
Smart cards may have internal reset, or active low reset. The following subset describes
the reset sequences in these two cases.
5.4.7.1.1.1 Smart Cards with Internal Reset
Following figure shows the reset sequence for Smart cards with internal reset. The reset
sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between
400–40000 clock cycles after T0.
114
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
1
2
T0
Figure 37. Internal Reset Card Reset Sequence
The following table defines the general timing requirements for the SIM interface.
Table 81. Timing Specifications, Internal Reset Card Reset Sequence
Ref
Min
Max
Units
1
—
200
EMVSIMx_CLK
clock cycles
2
400
40,000
EMVSIMx_CLK
clock cycles
5.4.7.1.1.2 Smart Cards with Active Low Reset
Following figure shows the reset sequence for Smart cards with active low reset. The
reset sequence comprises the following steps::
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no
response is to be received on RX during those 40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1,
and a response must be received on EMVSIMn_IO between 400 and 40,000 clock
cycles after T1.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
115
NXP Semiconductors
Electrical characteristics
EMVSIMn_VCCEN
EMVSIMn_RST
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
2
1
3
3
T0
T1
Figure 38. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM
interface..
Table 82. Timing Specifications, Internal Reset Card Reset Sequence
Ref No
Min
—
Max
200
Units
1
2
3
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
400
40,000
—
40,000
5.4.7.1.2 EMVSIM Power-Down Sequence
Following figure shows the EMV SIM interface power-down AC timing diagram.Table
83 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.
The power-down sequence for the EMV SIM interface is as follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
Each of the above steps requires one RTC CLK period (usually 32 kHz). Power-down
may be initiated by a Smart card removal detection; or it may be launched by the
processor.
116
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
EMVSIMn_IO
SI8
SI9
EMVSIMn_VCCEN
Figure 39. Smart Card Interface Power Down AC Timing
Table 83. Timing Requirements for Power-down Sequence
Ref No
Parameter
Symbol
Min
Max
Units
SI7
EMVSIM reset to SIM clock stop Srst2clk
0.9 × 1/
Frtcclk
1.1 × 1/Frtcclk
ns
SI8
SI9
EMVSIM reset to SIM Tx data
low
Srst2dat
Srst2ven
Spd2rst
1.8 × 1/
Frtcclk
2.2 × 1/Frtcclk
3.3 × 1/Frtcclk
1.1 × 1/Frtcclk
ns
ns
ns
EMVSIM reset to SIM voltage
enable low
2.7 × 1/
Frtcclk
SI10
EMVSIM presence detect to
SIM reset low
0.9 × 1/
Frtcclk
NOTE
Same timing is also followed when auto power down is
initiated. See Reference Manual for reference.
5.4.7.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
117
NXP Semiconductors
Electrical characteristics
NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the USB
clock recovery mode is enabled. It does not meet the USB
signaling rate specifications for certification in Host mode
operation.
5.4.7.3 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 84. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
24
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
1
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
15.8
0
15.0
—
ns
ns
ns
ns
—
—
1. The SPI can run at a maximum frequency of 24 MHz serial clocks on PORTE interface, and up to 18 MHz on other
PORT interfaces
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
118
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 40. DSPI classic SPI timing — master mode
Table 85. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
—
15 1
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
23.0
—
ns
ns
2.7
7.0
—
—
—
ns
—
ns
13
13
ns
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of system clock, for
example, when system clock is 60MHz, SPI clock should not be greater than 10MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 41. DSPI classic SPI timing — slave mode
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
119
NXP Semiconductors
Electrical characteristics
5.4.7.4 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 86. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
19.1
0
16
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 42. DSPI classic SPI timing — master mode
120
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Electrical characteristics
Table 87. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
23.1
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.6
7.0
—
—
—
ns
—
ns
13.0
13.0
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 43. DSPI classic SPI timing — slave mode
5.4.7.5 Inter-Integrated Circuit Interface (I2C) timing
Table 88. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum
Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
4001
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
121
NXP Semiconductors
Electrical characteristics
Characteristic
Table 88. I2C timing (continued)
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum
Minimum Maximum
Data set-up time
tSU; DAT
2505
—
1000
300
—
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
—
300
300
—
ns
ns
ns
µs
µs
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
tr
tf
—
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 89. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
1
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tLOW
tHIGH
0.5
0.26
—
—
µs
µs
µs
µs
ns
ns
tSU; STA
tHD; DAT
tSU; DAT
tr
0.26
—
0
—
50
—
Rise time of SDA and SCL signals
20 +0.1Cb
120
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
122
NXP Semiconductors
Electrical characteristics
Table 89. I 2C 1Mbit/s timing (continued)
Characteristic
Symbol
tf
Minimum
Maximum
Unit
ns
1
Fall time of SDA and SCL signals
20 +0.1Cb
120
—
Set-up time for STOP condition
tSU; STO
tBUF
0.26
0.5
0
µs
Bus free time between STOP and START condition
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
50
ns
1. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 44. Timing definition for devices on the I2C bus
5.4.7.6 LPUART switching specifications
See General switching specifications.
5.4.8 Human-machine interfaces (HMI)
5.4.8.1 TSI electrical specifications
Table 90. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Typ.
100
—
Max.
—
Unit
Fixed power consumption in run mode
µA
µA
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
123
NXP Semiconductors
Design considerations
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital circuits
between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane
directly under LQFP packages; and solder the exposed pad (EP) to ground directly
under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential
segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• The USB_VDD voltage range is 3.0 V to 3.6 V. It is recommended to include a
filter circuit with one bulk capacitor (no less than 2.2 μF) and one 0.1 μF capacitor
at the USB_VDD pin to improve USB performance.
124
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Design considerations
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2 V typically) as the ADC
reference.
• VDDIO_E, which is dedicated to powering PORTE, must be powered after VDD
and must be greater than or equal to VDD voltage.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 45. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and
over-voltage protection as shown the following figure. The voltage divider formed by
R1 – R4 must yield a voltage less than or equal to VREFH. The current must be
limited to less than the injection current limit. Since the ADC pins do not have diodes
to VDD, external clamp diodes must be included to protect against transient over-
voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 46. High voltage measurement with an ADC input
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
125
NXP Semiconductors
Design considerations
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• RESET_b pin
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following figure.
The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended
capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to
reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 47. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. The
supervisor chip must have an active high, open-drain output.
126
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Design considerations
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 48. Reset signal connection to external reset chip
• NMI pin
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low
level on this pin will trigger non-maskable interrupt. When this pin is enabled as
the NMI function, an external pull-up resistor (10 kΩ) as shown in the following
figure is recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
VDD
MCU
10k
NMI_b
Figure 49. NMI pin biasing
• Debug interface
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required
(SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down),
external 10 kΩ pull resistors are recommended for system robustness. The
RESET_b pin recommendations mentioned above must also be considered.
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
127
NXP Semiconductors
Design considerations
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 50. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). See for pin selection.
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating. Connect USB_VDD to ground through a 10 kΩ resistor if the USB module
is not used.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators. An
external feedback is required when using high gain (HGO=1) mode.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode.
Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for the
crystal. Typically, values of 10pf to 16pF are sufficient for 32.768kHz crystals that have
a 12.5pF CL specification. The internal load capacitor selection must not be used for
high frequency crystals and resonators.
128
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Design considerations
Table 91. External crystal/resonator connections
Oscillator mode
Low frequency (32.768kHz), low power
Low frequency (32.768kHz), high gain
High frequency (3-32MHz), low power
High frequency (3-32MHz), high gain
Oscillator mode
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 51. Crystal connection – Diagram 1
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 52. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 53. Crystal connection – Diagram 3
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
129
NXP Semiconductors
Design considerations
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 54. Crystal connection – Diagram 4
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and
software enablement solutions, which can reduce development costs and time to market.
Featured software and tools are listed below. Visit http://www.nxp.com/kinetis/sw for
more information and supporting collateral.
Evaluation and Prototyping Hardware
• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.nxp.com/kds
• Partner IDEs: http://www.nxp.com/kide
Development Tools
• PEG Graphics Software: http://www.nxp.com/peg
• Processor Expert Software and Embedded Components: http://www.nxp.com/
processorexpert )
Run-time Software
• Kinetis SDK: http://www.nxp.com/ksdk
• Kinetis Bootloader: http://www.nxp.com/kboot
• ARM mbed Development Platform: http://www.nxp.com/mbed
• MQX RTOS: http://www.nxp.com/mqx
130
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
NXP Semiconductors
Part identification
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
6.3 Soldering temperature
Base on JEDEC/IPC J-STD-020 Industry Standard, refer to AN3298: Solder Joint
Temperature and Package Peak Temperature for soldering guideline of different
packages.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis KL family
Key attribute
• KL82
• Z = Cortex-M0+
• 128 = 128 KB
FFF
R
Program flash memory size
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LH = 64 LQFP (10 mm x 10 mm)
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
131
NXP Semiconductors
Revision history
Field
Description
Values
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 7 = 72 MHz
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKL82Z128VMC7
8 Revision history
The following table provides a revision history for this document.
Table 92. Revision history
Rev. No.
Date
Substantial Changes
2
3
11/2015
08/2016
Initial public release
• Updated the specification of frequency of operation in DSPI switching specifications
(limited voltage range).
• Updated USB electrical specifications
4
12/2016
• Updated the Pin properties.
• Added a note to the TA in the Thermal operating requirements
• Updated the description of RPU and RPD in the Voltage and current operating
behaviors
132
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 4, 12/2016
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, the Energy Efficient Solutions logo, and
Kinetis are trademarks of NXP B.V. All other product or service names are the
property of their respective owners. ARM, the ARM powered logo, and Cortex
are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or
elsewhere. All rights reserved.
© 2015 - 2016 NXP B.V.
Document Number KL82P121M72SF0
Revision 4, 12/2016
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明