935313111557 [NXP]
RISC Microcontroller;
| 型号： | 935313111557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 |
| 文件： | 总117页 (文件大小：1622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
KS22P100M120SF0
Rev. 3, 04/2016
KS22/KS20 Microcontroller
MKS22FN256Vxx12
120 MHz ARM® Cortex®-M4, with up to 256 KB Flash
MKS22FN128Vxx12
MKS20FN256Vxx12
MKS20FN128Vxx12
The KS2x product family is built on the ARM® Cortex®-M4
processor with lower power and higher memory densities in
multiple packages. This device offers 120 MHz performance with
an integrated single-precision floating point unit (FPU).
Embedded flash memory sizes range from 128 KB to 256KB.
This device also includes:
• USB FS OTG 2.0 with crystal-less functionality
• FlexCAN, supporting CAN protocol according to the ISO
11898-1 standard and CAN 2.0 B protocol specifications
• FlexIO, a highly configurable module providing a wide
range of protocols including, but not limited to UART,
LPI2C, SPI, I2S, and PWM/Waveform generation.
100 & 64 LQFP (LL &
LH)
14×14×1.7 mm Pitch 7×7×0.65 mm Pitch 0.5
48 QFN (FT)
0.5 mm; 10×10×1.6 mm
Pitch 0.5 mm
mm
Performance
• 120 MHz ARM Cortex-M4 core with DSP instructions
Analog modules
• One 16-bit ADC module with up to 17 single-end
channels and 4 differential channels, and up to 1.2
Msps at ≤ 13-bit mode
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• One 12-bit DAC module
• Up to 256 KB of embedded flash and 64 KB of SRAM
• Preprogrammed Kinetis Flashloader for one-time, in-
system factory programming
• One analog comparator (CMP) module
Communication interfaces
• USB full-speed 2.0 device controller
• One FlexIO module
• Three UART modules (one supporting ISO7816,
and the other two operating up to 1.5 Mbit/s)
• One LPUART module supporting asynchronous
operation in low-power modes
• Two LPI2C modules supporting up to 5 Mbit/s,
asynchronous operation in low-power modes
supported
• Two 16-bit SPI modules supporting up to 30 Mbit/s
• Two FlexCAN modules for KS22, One FlexCAN for
KS20
System peripherals
• Flexible low-power modes, multiple wake up sources
• 16-channel asynchronous DMA controller
• Independent external and software watchdog monitor
Clocks
• Two crystal oscillators: 32 kHz (RTC), and 32-40 kHz
or 3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator (MCG) with PLL and FLL
Security and integrity modules
• Hardware CRC module
• Two I2S modules
• 128-bit unique identification (UID) number per chip
• Hardware random-number generator
• Flash access control (FAC) to protect proprietary
software
Timers
• Three 16-bit low-power timer PWM modules (TPM)
• One low-power timer (LPTMR)
• Periodic interrupt timer (PIT)
• Real time clock (RTC), with independent power
domain
Human-machine interfaces
• Up to 66 general-purpose input/output pins (GPIO)
• Programmable delay block (PDB)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products. © 2015–2016 NXP B.V.
Operating characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105 °C
Related Resources
Type
Description
Resource
Selector Guide The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to KS22PB 1
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the KS22P100M120SF0RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document:
KS22P100M120SF01
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_K_0N87R 1
Package
drawing
Package dimensions are provided in package drawings.
LQFP 100-pin: 98ASS23308W
LQFP 64-pin: 98ASS23234W
QFN 48-pin: 98ASA00616D
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
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ARM® Cortex™-M4
Core
System
Memories and Memory Interfaces
Clocks
Phase-
locked loop
Program
RAM
eDMA (16ch)
flash
DMAMUX
Debug
Frequency-
locked loop
DSP
FPU
Flash cache
interfaces
Low-leakage
wake-up unit
Low/high
frequency
oscillators
Interrupt
controller
WDOG
EWM
Internal
reference
clocks
Security
and Integrity
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
I2S
x2
TPM
x1 (6ch)
x2 (2ch)
Up to
16-bit
ADC x1
LPI2C
x2
CRC
66 GPIOs
Comparator
Random-
number
generator
Programmable
delay block
UART
x3
USB full-
speed OTG
with 6-bit DAC
x1
12-bit DAC
x1
Flash access
control
LPUART
x1
PIT (4ch)
FlexIO
16-bit
low-power
timer
PMC
SPI
x2
FlexCAN *
Note:
for KS22, CAN x2;
for KS20, CAN x1.
Independent
real-time
clock
Figure 1. Functional block diagram
NOTE
DAC0 and I2S1 are NOT supported in the 48-QFN package. For more details, see
the "Signal Multiplexing and Pin Assignments" section.
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Table of Contents
1 Ordering information............................................................... 5
4.3.7
Human-Machine Interfaces (HMI).....................47
2 Overview................................................................................. 6
2.1 System features...............................................................7
4.4 Pinouts.............................................................................47
4.5 Package dimensions....................................................... 50
5 Electrical characteristics..........................................................56
5.1 Terminology and guidelines.............................................56
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
ARM Cortex-M4 core........................................ 7
NVIC..................................................................7
AWIC.................................................................7
Memory............................................................. 8
Reset and boot..................................................9
Clock options.....................................................10
Security............................................................. 13
Power management..........................................14
LLWU................................................................ 16
5.1.1
5.1.2
5.1.3
5.1.4
Definitions......................................................... 56
Examples.......................................................... 57
Typical-value conditions....................................58
Relationship between ratings and operating
requirements..................................................... 58
Guidelines for ratings and operating
5.1.5
requirements..................................................... 59
2.1.10 Debug controller................................................17
2.1.11 Computer operating properly (COP) watchdog
timer.................................................................. 17
5.2 Ratings............................................................................ 59
5.2.1
5.2.2
5.2.3
5.2.4
Thermal handling ratings...................................59
Moisture handling ratings..................................60
ESD handling ratings........................................ 60
Voltage and current operating ratings...............60
2.2 Peripheral features.......................................................... 17
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
eDMA and DMAMUX........................................ 18
TPM...................................................................18
ADC...................................................................19
DAC...................................................................19
CMP.................................................................. 20
RTC...................................................................21
PIT.....................................................................21
PDB...................................................................21
LPTMR..............................................................22
5.3 General............................................................................60
5.3.1
5.3.2
5.3.3
5.3.4
AC electrical characteristics..............................61
Nonswitching electrical specifications...............61
Switching specifications.................................... 72
Thermal specification........................................ 74
5.4 Peripheral operating requirements and behaviors...........75
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Debug modules.................................................75
System modules................................................80
Clock modules...................................................80
Memories and memory interfaces.....................86
Security and integrity modules..........................87
Analog...............................................................87
Timers............................................................... 97
Communication interfaces.................................97
2.2.10 CRC.................................................................. 22
2.2.11 UART................................................................ 23
2.2.12 LPUART............................................................23
2.2.13 SPI.................................................................... 24
2.2.14 FlexCAN............................................................24
2.2.15 LPI2C................................................................ 26
2.2.16 USB...................................................................26
2.2.17 I2S.....................................................................27
2.2.18 FlexIO................................................................27
2.2.19 Port control and GPIO.......................................28
3 Memory map........................................................................... 30
4 Pinouts.................................................................................... 31
4.1 Signal Multiplexing and Pin Assignments........................31
4.2 Pin properties.................................................................. 34
4.3 Module Signal Description Tables................................... 39
6 Design considerations.............................................................108
6.1 Hardware design considerations..................................... 108
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations.............108
Power delivery system...................................... 108
Analog design................................................... 109
Digital design.....................................................110
Crystal oscillator................................................112
6.2 Software considerations.................................................. 114
7 Part identification.....................................................................114
7.1 Description.......................................................................114
7.2 Format............................................................................. 115
7.3 Fields............................................................................... 115
7.4 Example...........................................................................115
8 Revision history.......................................................................116
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Core Modules....................................................39
System Modules................................................40
Clock Modules...................................................40
Analog...............................................................41
Timer Modules.................................................. 42
Communication Interfaces................................ 43
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Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
GPIOs ADC
Commu
nication
Part
number
Marking
(Line1/Line2)
Flash
SRAM
(KB)
Pin Package GPIOs
count
FlexCAN
(KB)
(INT/HD) channel
1
s
(SE/DP)
2
MKS22F MKS22FN256 /
256
256
256
128
128
128
256
256
256
128
128
128
64
64
64
64
64
64
64
64
64
64
64
64
100
64
LQFP
LQFP
QFN
66
40
35
66
40
35
66
40
35
66
40
35
66/8
40/8
35/8
66/8
40/8
35/8
66/8
40/8
35/8
66/8
40/8
35/8
17/4
14/2 3
13/—
17/4
2
2
2
2
2
2
1
1
1
1
1
1
N256VLL
12
VLL12
MKS22F MKS22FN256 /
N256VLH
12
VLH12
MKS22F MKS22FN256 /
48
N256VFT
12
VFT12
MKS22F MKS22FN128 /
100
64
LQFP
LQFP
QFN
N128VLL
12
VLL12
MKS22F MKS22FN128 /
14/2 3
13/—
17/4
N128VLH
12
VLH12
MKS22F MKS22FN128 /
48
N128VFT
12
VFT12
MKS20F MKS20FN256 /
100
64
LQFP
LQFP
QFN
N256VLL
12
VLL12
MKS20F MKS20FN256 /
14/2 3
13/—
17/4
N256VLH
12
VLH12
MKS20F MKS20FN256 /
48
N256VFT
12
VFT12
MKS20F MKS20FN128 /
100
64
LQFP
LQFP
QFN
N128VLL
12
VLL12
MKS20F MKS20FN128 /
14/2 3
13/—
N128VLH
12
VLH12
MKS20F MKS20FN128 /
48
N128VFT
12
VFT12
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NXP Semiconductors
Overview
1. INT: interrupt pin numbers; HD: high drive pin numbers
2. SE: single-ended; DP: differential pair
3. ADC0_DP1 is for single-ended (SE) mode only in 64-LQFP.
2 Overview
The following figure shows the system diagram of this device.
GPIOA
GPIOB
Slave
Master
GPIOC
Cortex M4
GPIOD
M0
GPIOE
IOPORT
ADC (16-bit)
code bus
CMP (with 6-bit DAC)
DAC (12-bit)
Flash
128-256 KB
Debug
(SWD/JTAG)
CM4 core
M1
PDB
TPM0 (6-channel)
TPM1 (2-channel)
TPM2 (2-channel)
S0
S1
NVIC
system bus
FMC
Low Power Timer
Periodic Interrupt Timer
RTC
SRAM_L and _U,
64 KB in total
M2
M4
CAN x2 (KS22), x1 (KS20)
UART x3
DMA
MUX
S2
S3
eDMA
LPUART
DSPI x2
MUX
LPI2C x2
FlexIO
USB FS
I2S x2
CRC
RNG
Clock Source
EWM
4 MHz IRC
FLL
Watchdog (COP)
Register File (32 Bytes)
32 kHz IRC
OSC
PLL
Low Leakage Wakeup Unit
Reset Control Module
IRC48M
System Mode Control
RTC
Oscillator
LPO
Power Management Control
Figure 2. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
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Overview
2.1 System features
The following sections describe the high-level system features.
2.1.1 ARM Cortex-M4 core
The ARM Cortex-M4 is the member of the Cortex M Series of processors targeting
microcontroller cores focused on very cost sensitive, deterministic, interrupt driven
environments. The Cortex M4 processor is based on the ARMv7 Architecture and
Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and
Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP
(ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with
SIMD (single instruction multiple data) DSP style multiply-accumulates and
saturating arithmetic.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 16 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains 4 bits. It
also differs in number of interrupt sources and supports 240 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency . It also
can be used to wake the MCU core from Wait and VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect
asynchronous wake-up events in Stop mode and signal to clock control logic to
resume system clocking. After clock restarts, the NVIC observes the pending interrupt
and performs the normal interrupt or event processing. The AWIC can be used to
wake MCU core from Partial Stop, Stop and VLPS modes.
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7
NXP Semiconductors
Overview
Wake-up sources for this SoC are listed as below:
Table 2. AWIC Partial Stop, Stop and VLPS Wake-up Sources
Wake-up source
Available system resets
Low voltage detect
Low voltage warning
High voltage detect
Pin interrupts
Description
RESET pin and WDOG when LPO is its clock source, and JTAG
Power Mode Controller
Power Mode Controller
Power Mode Controller
Port Control Module - Any enabled pin interrupt is capable of waking the system
The ADC is functional when using internal clock source
ADC
CMP
Since no system clocks are available, functionality is limited, trigger mode provides wakeup
functionality with periodic sampling
LPI2C
Functional when using clock source which is active in Stop and VLPS modes
Functional when using clock source which is active in Stop and VLPS modes
Functional when using clock source which is active in Stop and VLPS modes
Active edge on RXD
FlexIO
TPM
UART
LPUART
USB FS/LS Controller
LPTMR
RTC
Functional when using clock source which is active in Stop and VLPS modes
Wakeup
Functional when using clock source which is active in Stop and VLPS modes
Functional in Stop/VLPS modes
I2S (SAI)
TPM
Functional when using an external bit clock or external master clock
Functional when using clock source which is active in Stop and VLPS modes
Wakeup on edge (CANx_RX)
CAN
NMI
Non-maskable interrupt
2.1.4 Memory
This device has the following features:
• 64 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into
• 128/256 KB of embedded program memory
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program flash
is 2 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
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Overview
The security circuitry prevents unauthorized access to RAM or flash contents
from debug port.
• System register file
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the
footnote, is reset by the corresponding Reset source. N
means the specific module is not reset by the corresponding
Reset source.
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC SIM SMC RCM LLWU Reset
RTC LPTM Others
R
pin is
negated
POR reset
Power-on reset (POR)
Y
Y1
N
Y
Y
Y2
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y3
Y
N
N
Y
Y
N
Y
Y
Y
System resets Low-voltage detect (LVD)
Low leakage wakeup
(LLWU) reset
External pin reset
(RESET)
Y1
Y2
Y4
Y
Y
Y
N
N
Y
Watchdog (WDOG) reset
Y1
Y1
Y2
Y2
Y4
Y4
Y5
Y5
Y
Y
Y
Y
N
N
N
N
Y
Y
Multipurpose clock
generator loss of clock
(LOC) reset
Multipurpose clock
generator loss of lock
(LOL) reset
Y1
Y1
Y2
Y2
Y4
Y4
Y5
Y5
Y
Y
Y
Y
N
N
N
N
Y
Y
Stop mode acknowledge
error (SACKERR)
Software reset (SW)
Y1
Y1
Y2
Y2
Y4
Y4
Y5
Y5
Y
Y
Y
Y
N
N
N
N
Y
Y
Lockup reset (LOCKUP)
Table continues on the next page...
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Overview
Table 3. Reset source (continued)
Reset
Descriptions
Modules
sources
PMC SIM SMC RCM LLWU
Reset
pin is
RTC LPTM Others
R
negated
MDM DAP system reset
Y1
Y1
Y2
Y2
Y4
Y4
Y5
Y5
Y
Y
Y
Y
N
N
N
N
Y
Y
Debug reset Debug reset
1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SIM_SOPT1
3. Only if RESET is used to wake from VLLS mode.
4. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
5. Except RCM_RPFC, RCM_RPFW, RCM_FM
This device supports booting from:
• internal flash
2.1.6 Clock options
The MCG module controls which clock source is used to derive the system clocks. The
clock generation logic divides the selected clock source into a variety of clock domains,
including the clocks for the system bus masters, system bus slaves, and flash memory .
The clock generation logic also implements module-specific clock gating to allow
granular shutoff of modules.
The primary clocks for the system are generated from the MCGOUTCLK clock. The
clock generation circuitry provides several clock dividers that allow different portions
of the device to be clocked at different frequencies. This allows for trade-offs between
performance and power dissipation.
Various modules, such as the USB OTG Controller, have module-specific clocks that
can be generated from the IRC48MCLK or MCGPLLCLK or MCGFLLCLK clock. In
addition, there are various other module-specific clocks that have other alternate
sources. Clock selection for most modules is controlled by the SOPT registers in the
SIM module.
For more details on the clock operations and configurations, see the Clock Distribution
chapter in the Reference Manual.
The following figure is a high level block diagram of the clock generation.
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Overview
MCG
SIM
FCRDIV
4 MHz IRC
32 kHz IRC
Clock options for
some peripherals
(see note)
MCGIRCLK
MCGFFCLK
CG
FLL
OUTDIV1
CG
CG
Core / system clocks
Bus clock
OUTDIV2
MCGOUTCLK
PLL
OUTDIV4
Flash clock
CG
MCGFLLCLK
MCGPLLCLK
FRDIV
MCGPLLCLK/
MCGFLLCLK/
IRC48MCLK
PRDIV
System oscillator
IRC48MCLK
EXTAL0
XTAL0
OSCCLK
OSCERCLK_UNDIV
OSCERCLK
XTAL_CLK
OSC
logic
DIV
OSC32KCLK
ERCLK32K
PMC
RTC oscillator
32.768 kHz
LPO
EXTAL32
XTAL32
PMC logic
OSC logic
1 Hz
RTC_CLKOUT
IRC48M internal oscillator
IRC48MCLK
IRC48M logic
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.
Figure 3. Clock block diagram
In order to provide flexibility, many peripherals can select the clock source to use for
operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
The following table summarizes the clocks associated with each module.
Table 4. Module clocks
Module
Bus interface clock
Core modules
Internal clocks
I/O interface clocks
ARM Cortex-M4 core
System clock
System clock
System clock
Core clock
—
—
—
NVIC
DAP
—
—
Table continues on the next page...
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Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
System clock
—
Internal clocks
I/O interface clocks
ITM
—
—
—
cJTAG, JTAGC
JTAG_CLK
System modules
DMA
DMA Mux
System clock
Bus clock
—
—
—
—
—
—
—
—
—
—
—
—
Port control
Bus clock
LPO
Crossbar Switch
Peripheral bridges
LLWU, PMC, SIM, RCM
Mode controller
MCM
System clock
System clock
Flash clock
Flash clock
System clock
Bus clock
—
Bus clock, Flash clock
LPO
—
—
EWM
LPO
LPO
Watchdog timer
Bus clock
Clocks
MCG
Flash clock
MCGOUTCLK,
—
MCGPLLCLK, MCGFLLCLK,
MCGIRCLK, OSCCLK, RTC
OSC, IRC48MCLK
OSC
Bus clock
—
OSCERCLK, OSCCLK,
OSCERCLK_UNDIV,
OSC32KCLK
—
—
IRC48M
IRC48MCLK
Memory and memory interfaces
Flash Controller
Flash memory
System clock
Flash clock
Flash clock
—
—
—
Security
CRC
Bus clock
Bus clock
—
—
—
—
RNGA
Analog
ADC
CMP
DAC
Bus clock
Bus clock
Bus clock
OSCERCLK , IRC48MCLK
—
—
—
—
—
Timers
TPM
PDB
Bus clock
Bus clock
Bus clock
Flash clock
TPM clock
TPM_CLKIN0, TPM_CLKIN1
—
—
—
—
—
PIT
LPTMR
LPO, OSCERCLK,
MCGIRCLK, ERCLK32K
RTC
Flash clock
EXTAL32
—
Communication interfaces
Table continues on the next page...
12
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Overview
Table 4. Module clocks (continued)
Module
USB FS OTG
DSPI
Bus interface clock
System clock
Bus clock
Internal clocks
USB FS clock
—
I/O interface clocks
—
DSPI_SCK
I2C_SCL
—
LPI2C
Bus clock
LPI2C clock
—
UART0, UART1
UART2
System clock
Bus clock
—
—
LPUART0
I2S
Bus clock
LPUART0 clock
I2S master clock
—
Bus clock
I2S_TX_BCLK,
I2S_RX_BCLK
FlexCAN
FlexIO
Bus clock
Bus clock
FlexCAN clock
FlexIO clock
—
—
Human-machine interfaces
GPIO
Platform clock
—
—
2.1.7 Security
Security state can be enabled via programming flash configure field (0x40e). After
enabling device security, the SWD/JTAG port cannot access the memory resources of
the MCU.
External interface
SWD/JTAG port
Security
Unsecure
Can't access memory source by SWD/ the debugger can write to the Flash
JTAG interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
2.1.7.1 Flash Access Control (FAC)
The FAC is a native or third-party configurable memory protection scheme optimized
to allow end users to utilize software libraries while offering programmable
restrictions to these libraries. The flash memory is divided into equal size segments
that provide protection to proprietary software libraries. The protection of these
segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access
rights for each transaction routed to the on-chip flash memory. Configurability allows
an increasing number of protected segments while supporting two levels of vendors
adding their proprietary software to a device.
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2.1.8 Power management
The Power Management Controller (PMC) expands upon ARM’s operational modes of
Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can
be used to optimize current consumption for a wide range of applications. The WFI or
WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on ARM’s operational modes, See the ARM®
Cortex® User Guide.
The PMC provides High Speed Run (HSRUN), Normal Run (RUN), and Very Low
Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the
MCU core is active and can access all peripherals. The difference between the modes is
the maximum clock frequency of the system and therefore the power consumption. The
configuration that matches the power versus performance requirements of the
application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Battery Backup mode allows the VBAT voltage domain to operate while the rest of
the device is disabled to conserve power. All modules in the VBAT domain are
functional in this mode of operation.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core from
LLS and VLLSx modes.
For additional information regarding operational modes, power management, the NVIC,
AWIC, or the LLWU, please refer to the Reference Manual.
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The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 6. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
High Speed Run
In HSRun mode, MCU is able to operate at a faster frequency, and all device
modules are operational.
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Deep sleep
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, DAC, CMP, LPTMR,
RTC, and pin interrupts are operational. The NVIC is disabled, but the AWIC
can be used to wake up from an interrupt.
Very Low Power Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, LPI2C,USB, and
DMA are operational, LVD and NVIC are disabled, AWIC is used to wake up
from interrupt.
Low Leakage Stop
(LLS3/LLS2)
State retention power mode. Most peripherals are in state retention mode
(with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used.
NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt controller
to avoid a scenario where the system does not fully exit stop mode
on an LLS recovery.
In LLS3 mode, all SRAM is operating (content retained and I/O
states held). In LLS2 mode, a portion of SRAM_U remains powered
on (content retained and I/O states held).
Very Low Leakage Stop Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer,
(VLLSx)
RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up.
In VLLS3, SRAM_U and SRAM_L remain powered on (content retained and
I/O states held).
In VLLS2, SRAM_L is powered off. A portion of SRAM_U remains powered
on (content retained and I/O states held).
In VLLS1 and VLLS0, all of SRAM_U and SRAM_L are powered off. The 32-
byte system register file and 32-byte VBAT register file remain powered for
customer-critical data.
In VLLS0, The POR detect circuit can be optionally powered off.
Powered Off
Battery Backup
The RTC and 32-byte VBAT register file are powered from the VBAT domain
and is fully functional. The rest of the device is powered down.
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2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
Table 7. Wakeup sources for LLWU inputs
Input
Wakeup source
PTE1/LLWU_P0 pin
PTE2/LLWU_P1 pin
PTE4/LLWU_P2 pin
PTA4/LLWU_P3 pin1
PTA13/LLWU_P4 pin
PTB0/LLWU_P5 pin
PTC1/LLWU_P6 pin
PTC3/LLWU_P7 pin
PTC4/LLWU_P8 pin
PTC5/LLWU_P9 pin
PTC6/LLWU_P10 pin
PTC11/LLWU_P11 pin
PTD0/LLWU_P12 pin
PTD2/LLWU_P13 pin
PTD4/LLWU_P14 pin
PTD6/LLWU_P15 pin
Reserved
LLWU_P0
LLWU_P1
LLWU_P2
LLWU_P3
LLWU_P4
LLWU_P5
LLWU_P6
LLWU_P7
LLWU_P8
LLWU_P9
LLWU_P10
LLWU_P11
LLWU_P12
LLWU_P13
LLWU_P14
LLWU_P15
LLWU_P16
LLWU_P17
LLWU_P18
LLWU_P19
LLWU_P20
LLWU_P21
LLWU_P22
LLWU_P23
LLWU_P24
LLWU_P25
LLWU_P26
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USBVDD
Table continues on the next page...
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Table 7. Wakeup sources for LLWU inputs (continued)
Input
Wakeup source
USB0_DP
USB0_DM2
Reserved
Reserved
Reserved
LPTMR3
LLWU_P27
LLWU_P28
LLWU_P29
LLWU_P30
LLWU_P31
LLWU_M0IF
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
CMP0
Reserved
Reserved
Reserved
RTC Alarm3
Reserved
RTC Seconds3
1. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit from the low
power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit.
2. As a wakeup source of LLWU, USB0_DP and USB0_DM are only available when the chip is in USB host mode.
3. It requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal
module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
2.1.10 Debug controller
This device has extensive debug capabilities including run control and tracing
capabilities. The standard ARM debug port supports SWD/JTAG interface. Also the
cJTAG interface is supported on this device.
2.1.11 Computer operating properly (COP) watchdog timer
The computer operating properly (COP) watchdog timer (WDOG) monitors the
operation of the system by expecting periodic communication from the software. This
communication is generally known as servicing (or refreshing) the COP watchdog. If
this periodic refreshing does not occur, the watchdog issues a system reset.
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
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2.2.1 eDMA and DMAMUX
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications
where the data size to be transferred is statically known and not defined within the
transferred data itself. The DMA controller in this device implements 16 channels
which can be routed from up to 63 DMA request sources through DMA MUX module.
Main features of eDMA are listed below:
• All data movement via dual-address transfers: read from source, write to
destination
• 16-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• Channel activation via one of three methods
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
2.2.2 TPM
This device contains three low power Timer/PWM Modules (TPM), one with 6
channels and the other two with 2 channels. All TPM modules are functional in Stop/
VLPS mode if the clock source is enabled.
The TPM features are as follows:
• TPM clock mode is selectable (can increment on every edge of the asynchronous
counter clock, or only on on rising edge of an external clock input synchronized to
the asynchronous counter clock)
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• Include a 16-bit counter
• Include 6 or 2 channels (1×6ch, 2×2ch) that can be configured for input capture,
output compare, edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
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• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.3 ADC
This device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16-
bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to three
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32×
• Voltage reference: from external
• Self-calibration mode
2.2.3.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel
of AD26, see Table 66 for details of the linearity factor.
The sensor must be calibrated to gain good accuracy, so as to provide good linearity,
see also AN3031.
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2.2.4 DAC
The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, or ADC.
DAC module has the following features:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from the reference source VDDA
• Static operation in Normal Stop mode
• 16-word data buffer supported with multiple operation modes
• DMA support
2.2.5 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power
down to conserve power
• Two 8-to-1 channel mux
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2.2.6 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the RTC oscillator.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
2.2.7 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has four independent channels and each channel has a 32-bit counter. Both channels
can be chained together to form a 64-bit counter.
Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be
used to periodically trigger DMA channel 1. Either channel can be programmed as an
ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger
DAC.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
2.2.8 PDB
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise
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timing between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the
CMP block.
The PIT module has the following features:
• Up to 15 trigger input sources and one software trigger source
• Up to 8 configurable PDB channels for ADC hardware trigger
• Up to 8 pulse outputs (pulse-out's)
2.2.9 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.10 CRC
This device contains one cyclic redundancy check (CRC) module which can generate
16/32-bit CRC code for error detection.
The CRC module provides a programmable polynomial, WAS, and other parameters
required to implement a 16-bit or 32-bit CRC standard.
The CRC module has the following features:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift
register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
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2.2.11 UART
This device contains 3 basic universal asynchronous receiver/transmitter (UART)
modules with DMA function supported. Generally, this module is used in RS-232,
RS-485, and other communications. It also supports LIN slave operation and
ISO7816.
The UART module has the following features:
• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock
frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR
overhead
• Ability to select MSB or LSB to be the first bit on wire
• UART0 supporting ISO-7816 protocol to interface with SIM cards and smart
cards
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface
2.2.12 LPUART
This device contains one Low-Power UART module, and can work in Stop and VLPS
modes. The module also supports 4× to 32× data oversampling rate to meet different
applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
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• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.13 SPI
This device contains two SPI modules. The SPI module provides a synchronous serial
bus for communication between a chip and an external peripheral device.
The SPI modules have the following features:
• Full-duplex, three-wire synchronous transfers
• Master mode, or slave mode
• Data streaming operation in Slave mode with continuous slave selection
• Buffered transmit/receive operation using the transmit/receive first in first out
(TX/RX FIFO) with depth of 4 entries
• Programmable transfer attributes on a per-frame basis
• Multiple peripheral chip select (PCS) (6 PCS available for SPI0 and 4 PCS for
SPI1), expandable to 64 with external demultiplexer
• Deglitching support for up to 32 peripheral chip selects (PCSes) with external
demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO
• Global interrupt request line
• Modified SPI transfer formats for communication with slower peripheral devices
• Power-saving architectural features
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2.2.14 FlexCAN
For KS22, the device contains two FlexCAN modules. For KS20, it has only one
FlexCAN module. The FlexCAN module is a communication controller implementing
the CAN protocol according to the ISO 11898-1 standard and CAN 2.0 B protocol
specifications.
The FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.
The FlexCAN module has the following features:
• Flexible mailboxes of zero to eight bytes data length
• Each mailbox configurable as receive or transmit, all supporting standard and
extended messages
• Individual Rx Mask registers per mailbox
• Full-featured Rx FIFO with storage capacity for up to six frames and automatic
internal pointer handling with DMA support
• Transmission abort capability
• Programmable clock source to the CAN Protocol Interface, either peripheral clock
or oscillator clock
• RAM not used by reception or transmission structures can be used as general
purpose RAM space
• Listen-Only mode capability
• Programmable Loop-Back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independence from the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
• Remote request frames may be handled automatically or by software
• CAN bit time settings and configuration bits can only be written in Freeze mode
• Tx mailbox status (Lowest priority buffer or empty buffer)
• Identifier Acceptance Filter Hit Indicator (IDHIT) register for received frames
• SYNCH bit available in Error in Status 1 register to inform that the module is
synchronous with CAN bus
• CRC status for transmitted message
• Rx FIFO Global Mask register
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• Selectable priority between mailboxes and Rx FIFO during matching process
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either
128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual
masking capability
2.2.15 LPI2C
This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated
Circuit (I2C) module that supports an efficient interface to an I2C bus as a master
and/or a slave. The LPI2C can continue operating in stop modes provided an
appropriate clock is available and is designed for low CPU overhead with DMA
offloading of FIFO register accesses. The LPI2C implements logic support for standard-
mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module
also complies with the System Management Bus (SMBus) Specification, version 2.
The LPI2C modules have the following features:
• Standard, Fast, Fast+ and Ultra Fast modes are supported
• HS-mode supported in slave mode
• Multi-master support including synchronization and arbitration
• Clock stretching
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID require software support
• For master mode:
• command/transmit FIFO of 4 words
• receive FIFO of 4 words
• For slave mode:
• separate I2C slave registers to minimize software overhead due to master/slave
switching
• support for 7-bit or 10-bit addressing, address range, SMBus alert and general
call address
• transmit/receive data register supporting interrupt or DMA requests
2.2.16 USB
This device contains one USB module which implements a USB2.0 full-speed
compliant peripheral and interfaces to the on-chip USBFS transceiver. It enables
IRC48M to allow crystal-less USB operation.
The USBFS has the following features:
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• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is
used for USB device-only implementation.
2.2.17 I2S
The I2S module provides a synchronous audio interface (SAI), which can be clocked
by bus clock, PLL/FLL output clock or external oscillator clock. The module supports
asynchronous bit clocks (BCLKs) that can be generated internally from the audio
master clock or supplied externally. And also supports the option for synchronous
operation between the receiver and transmitter. And it can be functional in stop or
very low power mode.
I2S module has the following features:
• Transmitter with independent bit clock and frame sync supporting 1 data channel
• Receiver with independent bit clock and frame sync supporting 1 data channel
• Maximum frame size of 16 words
• Word size of between 8-bits and 32-bits
• Word size configured separately for first word and remaining words in frame
• Asynchronous 8 × 32-bit FIFO for each transmit and receive channels
• Supports graceful restart after FIFO error
• Supports automatic restart after FIFO error without software intervention
• Supports packing of 8-bit and 16-bit data into each 32-bit FIFO word
2.2.18 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, I2S, and PWM/Waveform generation.
The module supports programmable baud rates independent of bus clock frequency,
with automatic start/stop bit generation.
The FlexIO module has the following features:
• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using
remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match
modes, and continuous data transfer
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• The timing of the shifter's shift, load and store events are controlled by the highly
flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on
a variety of internal or external trigger conditions with programmable trigger
polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional
output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation
2.2.19 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions. The GPIO data direction and output data
registers control the direction and output data of each pin when the pin is configured for
the GPIO function. The GPIO input data register displays the logic value on each pin
when the pin is configured for any digital function, provided the corresponding Port
Control and Interrupt module for that pin is enabled.
The following figure shows the basic I/O pad structure. This diagram applies to all I/O
pins except RESET_b and those configured as pseudo open-drain outputs. RESET_b is
a true open-drain pin without p-channel output driver or diode to the ESD bus. Pseudo
open-drain pins have the p-channel output driver disabled when configured for open-
drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins,
are allowed to go above VDD.
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Digital input
IBE=1 whenever
MUX≠000
PFE
IBE
ESD
Bus
VDD
RPULL
PE
PS
Analog input
Digital output
DSE
SRE
Figure 4. I/O simplified block diagram
The PORT module has the following features:
• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
KS22/KS20 Microcontroller, Rev. 3, 04/2016
29
NXP Semiconductors
Memory map
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. For more details of the system memory and peripheral
locations, see the Memory Map chapter in the Reference Manual.
0x4000_0000
Reserved
0x4000_8000
DMA controller
0x4000_9000
DMA controller transfer control descriptors
0x4000_A000
Reserved
Flash memory controller (FMC)
Flash memory
DMA channel mutiplexer
Reserved
FlexCAN 0
FlexCAN 1 (only for KS22)
0x4001_F000
0x4002_0000
0x0000_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
Flash
0x0000_0000
0x0800_0000
0x1C00_0000
Reserved
Random Number Generator (RNGA)
0x4002_9000
0x4002_A000
0x4002_B000
0x4002_C000
0x07FF_FFFF
Code space
Reserved
note:
take 256 KB flash memory as an example
LPUART 0
Reserved
SPI 0
0x4002_D000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_6000
0x4003_7000
SPI 1
Reserved
I2S 0
I2S 1
Reserved
CRC
Reserved
0x1C00_0000
SRAM_L
SRAM_U
Data space
Reserved *
0x2000_0000
Programmable delay block (PDB)
Periodic interrupt timers (PIT)
TPM 0
0x2010_0000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_D000
TPM 1
TPM 2
ADC 0
0x200F_FFFF
note:
0x2200_0000–0x23FF_FFFF: Aliased to SRAM_U bitband
0x3000_0000–0x33FF_FFF: Program Flash and read only data
Reserved
Real-time clock (RTC)
VBAT register file
0x4003_E000
0x4003_F000
0x4004_0000
0x4004_1000
0x4004_2000
0x4004_7000
0x4000_0000
0x4010_0000
DAC 0
Low-power timer (LPTMR)
System register file
Reserved
SIM low-power logic
System integration module (SIM)
Port A multiplexing control
Port B multiplexing control
Port C multiplexing control
Port D multiplexing control
Port E multiplexing control
Public
peripherals
0x4000_0000
AIPS
peripherals
0x4007_FFFF
0x4008_0000
0x4004_8000
0x4004_9000
0x4004_A000
Reserved
0x400F_EFFF
0x4004_B000
0x4004_C000
Reserved *
note:
0x400F_F000
0x400F_FFFF
0x4200_0000–0x42FF_FFFF
: Aliased to peripheral bridge (AIPS-lite) bitband
0x43FE_0000–0x43FF_FFFF
GPIO
0x4004_D000
0x4004_E000
0x4005_2000
Reserved
Software watchdog
: Aliased to general purpose input/output(GPIO) bitband
0xE000_0000
0x4005_3000
0x4005_F000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_4000
0x4006_5000
0x4006_6000
0x4006_7000
0x4006_8000
0x4006_A000
0x4006_B000
0x4006_C000
0x4006_D000
0x4007_2000
0x4007_3000
0x4007_4000
0x4007_C000
Reserved
FlexIO
Reserved
note:
Private
Peripheral
Bus
0xE000_0000–0xE000_0FFF: Instrumentation Trace Macrocell (ITM)
0xE000_1000–0xE000_1FFF: Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF: Flash Patch and Breakpoint (FPB)
0xE000_3000–0xE000_DFFF: Reserved
0xE000_E000–0xE000_EFFF: System Control Space (SCS) (for NVIC and FPU)
0xE000_F000–0xE003_FFFF: Reserved
0xE004_0000–0xE004_0FFF: Trace Port Interface Unit (TPIU)
0xE004_1000–0xE004_1FFF: Reserved
0xE004_2000–0xE004_2FFF: Reserved
0xE004_3000–0xE004_3FFF: Reserved
0xE004_4000–0xE007_FFFF: Reserved
0xE008_0000–0xE008_0FFF: Miscellaneous Control Module (MCM)
0xE008_1000–0xE008_1FFF: Reserved
0xE008_2000–0xE00F_EFFF: Reserved
External watchdog
Reserved
Multi-purpose Clock Generator (MCG)
System oscillator (OSC)
LPI2C 0
(PPB) *
LPI2C 1
Reserved
UART 0
UART 1
UART 2
Reserved
0xFFFF_FFFF
USB Full Speed OTG Controller
0xE00F_F000–0xE00F_FFFF: ROM Table - allows auto-detection of debug components
0xE010_0000–0xFFFF_FFFF: Reserved
CMP (with 6-bit DAC)
Reserved
Low-leakage wakeup unit (LLWU)
Power management controller (PMC)
System Mode controller (SMC)
Reset Control Module (RCM)
0x4007_D000
0x4007_E000
0x4007_F000
0x4007_FFFF
Figure 5. Memory map
30
KS22/KS20 Microcontroller, Rev. 3, 04/2016
NXP Semiconductors
Pinouts
4 Pinouts
4.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
For KS20, only CAN0 exists. For KS22, there are two
instances of CAN module (CAN0 and CAN1).
100
64
48
Pin Name
Default
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
DISABLED
DISABLED
DISABLED
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
1
2
3
4
5
6
7
1
1
2
PTE0/
CLKOUT32K
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
PTE0/
CLKOUT32K
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
UART1_TX
UART1_RX
LPI2C1_SDA
LPI2C1_SCL
RTC_
CLKOUT
2
PTE1/
LLWU_P0
PTE1/
LLWU_P0
SPI1_SIN
—
—
—
—
—
3
PTE2/
LLWU_P1
PTE2/
LLWU_P1
UART1_
CTS_b
4
PTE3
PTE3
UART1_
RTS_b
SPI1_SOUT
LPI2C1_SDA
LPI2C1_SCL
5
PTE4/
LLWU_P2
PTE4/
LLWU_P2
SPI1_PCS0
SPI1_PCS2
SPI1_PCS3
LPUART0_
TX
6
PTE5
PTE5
LPUART0_
RX
—
PTE6
PTE6
LPUART0_
CTS_b
I2S0_MCLK
USB_SOF_
OUT
8
3
4
7
VDD
VDD
VDD
9
8
VSS
VSS
VSS
10
11
12
13
14
15
16
17
18
19
20
5
9
USB0_DP
USB0_DM
USBVDD
NC
USB0_DP
USB0_DM
USBVDD
NC
USB0_DP
USB0_DM
USBVDD
NC
6
10
11
—
—
—
—
—
—
—
—
7
—
8
ADC0_DP1
ADC0_DM1
ADC0_DP2
ADC0_DM2
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DP1
ADC0_DM1
ADC0_DP2
ADC0_DM2
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DP1
ADC0_DM1
ADC0_DP2
ADC0_DM2
ADC0_DP0
ADC0_DM0
ADC0_DP3
—
—
—
9
10
11
KS22/KS20 Microcontroller, Rev. 3, 04/2016
31
NXP Semiconductors
Pinouts
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
21
22
23
24
25
26
27
12
13
14
15
16
17
18
—
12
12
13
13
—
—
ADC0_DM3
VDDA
ADC0_DM3
VDDA
ADC0_DM3
VDDA
VREFH
VREFL
VREFH
VREFL
VREFH
VREFL
VSSA
VSSA
VSSA
CMP0_IN5
CMP0_IN5
CMP0_IN5
DAC0_OUT/
ADC0_SE23
DAC0_OUT/
ADC0_SE23
DAC0_OUT/
ADC0_SE23
28
29
30
31
32
19
20
21
—
—
14
15
16
—
—
XTAL32
EXTAL32
VBAT
XTAL32
XTAL32
EXTAL32
VBAT
EXTAL32
VBAT
PTE24
PTE25
ADC0_SE17
ADC0_SE18
ADC0_SE17
ADC0_SE18
PTE24
CAN1_TX
CAN1_RX
TPM0_CH0
TPM0_CH1
I2S1_TX_FS
LPI2C0_SCL
LPI2C0_SDA
EWM_OUT_b
EWM_IN
PTE25
I2S1_TX_
BCLK
33
34
35
36
—
22
23
24
—
17
18
19
PTE26/
CLKOUT32K
DISABLED
PTE26/
CLKOUT32K
I2S1_TXD0
RTC_
CLKOUT
USB_CLKIN
PTA0
PTA1
PTA2
JTAG_TCLK/
SWD_CLK
PTA0
PTA1
PTA2
UART0_
CTS_b
TPM0_CH5
EWM_IN
JTAG_TCLK/
SWD_CLK
JTAG_TDI
UART0_RX
CMP0_OUT
LPI2C1_
HREQ
TPM1_CH1
TPM1_CH0
JTAG_TDI
JTAG_TDO/
TRACE_
SWO
UART0_TX
JTAG_TDO/
TRACE_
SWO
37
38
39
25
26
27
20
21
—
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
TPM0_CH0
TPM0_CH1
TPM0_CH2
EWM_OUT_b
JTAG_TMS/
SWD_DIO
PTA4/
LLWU_P3
NMI_b
PTA4/
LLWU_P3
I2S0_MCLK
NMI_b
PTA5
DISABLED
PTA5
USB_CLKIN
I2S0_TX_
BCLK
JTAG_TRST_
b
40
41
42
43
—
—
28
29
—
—
—
—
VDD
VDD
VDD
VSS
VSS
VSS
PTA12
DISABLED
DISABLED
PTA12
CAN0_TX
CAN0_RX
TPM1_CH0
TPM1_CH1
I2S0_TXD0
PTA13/
PTA13/
I2S0_TX_FS
LLWU_P4
LLWU_P4
44
—
—
PTA14
DISABLED
PTA14
SPI0_PCS0
UART0_TX
UART0_RX
I2S0_RX_
BCLK
45
46
—
—
—
—
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD0
SPI0_SOUT
UART0_
CTS_b
I2S0_RX_FS
47
—
—
PTA17
DISABLED
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
48
49
50
30
31
32
22
23
24
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
TPM_CLKIN0
32
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Pinouts
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
51
33
25
PTA19
XTAL0
XTAL0
PTA19
TPM_CLKIN1
LPTMR0_
ALT1
52
53
34
35
26
27
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
PTB0/
LLWU_P5
LPI2C0_SCL
TPM1_CH0
TPM1_CH1
FXIO0_D4
UART0_RX
54
55
36
37
28
29
PTB1
PTB2
ADC0_SE9
ADC0_SE9
PTB1
PTB2
LPI2C0_SDA
LPI2C0_SCL
EWM_IN
FXIO0_D5
FXIO0_D6
UART0_TX
CAN1_RX
ADC0_SE12
ADC0_SE12
UART0_
RTS_b
56
57
58
59
38
—
—
—
30
—
—
—
PTB3
ADC0_SE13
DISABLED
DISABLED
DISABLED
ADC0_SE13
PTB3
LPI2C0_SDA
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
UART0_
CTS_b
FXIO0_D7
CAN1_TX
PTB9
PTB9
LPUART0_
CTS_b
PTB10
PTB11
PTB10
PTB11
LPUART0_
RX
I2S1_TX_
BCLK
LPUART0_
TX
I2S1_TX_FS
60
61
62
—
—
39
—
—
31
VSS
VSS
VSS
VDD
VDD
VDD
PTB16
DISABLED
PTB16
SPI1_SOUT
UART0_RX
TPM_CLKIN0
TPM_CLKIN1
EWM_IN
I2S1_TXD0
(Note:
100LQFP
only)
63
64
40
41
—
PTB17
PTB18
DISABLED
DISABLED
PTB17
PTB18
SPI1_SIN
CAN0_TX
UART0_TX
TPM2_CH0
EWM_OUT_b FXIO0_D0
FXIO0_D1
32
I2S0_TX_
BCLK
65
66
67
68
69
70
42
—
—
—
—
43
33
—
—
—
—
—
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
ADC0_SE14
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
CAN0_RX
TPM2_CH1
I2S0_TX_FS
FXIO0_D2
CMP0_OUT
FXIO0_D5
FXIO0_D6
FXIO0_D7
FXIO0_D3
FXIO0_D4
SPI0_PCS5
ADC0_SE14
ADC0_SE15
ADC0_SE4b
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
PDB0_
EXTRG
USB_SOF_
OUT
SPI0_PCS0
71
72
73
44
45
46
34
35
36
PTC1/
LLWU_P6
ADC0_SE15
ADC0_SE4b
DISABLED
PTC1/
LLWU_P6
UART1_
RTS_b
TPM0_CH0
TPM0_CH1
TPM0_CH2
I2S0_TXD0
LPUART0_
RTS_b
PTC2
PTC2
UART1_
CTS_b
I2S0_TX_FS
LPUART0_
CTS_b
PTC3/
LLWU_P7
PTC3/
LLWU_P7
UART1_RX
CLKOUT
I2S0_TX_
BCLK
LPUART0_
RX
74
75
76
47
48
49
—
—
37
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
UART1_TX
TPM0_CH3
I2S0_RXD0
LPI2C0_
HREQ
LPUART0_
TX
77
50
38
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
LPTMR0_
ALT2
CMP0_OUT
TPM0_CH2
KS22/KS20 Microcontroller, Rev. 3, 04/2016
33
NXP Semiconductors
Pinouts
100
64
48
Pin Name
Default
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
ALT0
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
ALT1
ALT2
SPI0_SOUT
SPI0_SIN
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
78
79
80
81
51
52
53
54
39
40
—
—
PTC6/
LLWU_P10
PTC6/
LLWU_P10
PDB0_
EXTRG
I2S0_RX_
BCLK
I2S0_MCLK
LPI2C0_SCL
LPI2C0_SDA
I2S1_RXD0
PTC7
PTC7
USB_SOF_
OUT
I2S0_RX_FS
PTC8
PTC9
PTC10
PTC8
PTC9
PTC10
LPI2C0_
SCLS
I2S0_MCLK
FXIO0_D0
FXIO0_D1
LPI2C0_
SDAS
I2S0_RX_
BCLK
I2S1_RX_
BCLK
82
83
55
56
—
—
DISABLED
DISABLED
LPI2C1_SCL
LPI2C1_SDA
I2S0_RX_FS
FXIO0_D2
FXIO0_D3
I2S1_RX_FS
I2S1_MCLK
PTC11/
PTC11/
LLWU_P11
LLWU_P11
84
85
86
87
—
—
—
—
—
—
—
—
PTC12
PTC13
PTC14
PTC15
DISABLED
DISABLED
DISABLED
DISABLED
PTC12
PTC13
PTC14
PTC15
LPI2C1_
SCLS
TPM_CLKIN0
TPM_CLKIN1
FXIO0_D0
FXIO0_D1
FXIO0_D2
FXIO0_D3
LPI2C1_
SDAS
LPUART0_
RTS_b
LPUART0_
CTS_b
88
89
90
—
—
—
—
—
—
VSS
VSS
VSS
VDD
VDD
VDD
PTC16
DISABLED
PTC16
PTC17
PTC18
CAN1_RX
CAN1_TX
LPUART0_
RX
FXIO0_D4
FXIO0_D5
91
92
93
94
95
96
97
98
99
100
—
—
57
58
59
60
61
62
63
64
—
—
41
42
43
44
45
46
47
48
PTC17
PTC18
DISABLED
DISABLED
DISABLED
ADC0_SE5b
DISABLED
DISABLED
DISABLED
ADC0_SE6b
ADC0_SE7b
DISABLED
LPUART0_
TX
LPUART0_
RTS_b
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_
RTS_b
LPUART0_
RTS_b
FXIO0_D6
PTD1
ADC0_SE5b
PTD1
UART2_
CTS_b
LPUART0_
CTS_b
FXIO0_D7
PTD2/
LLWU_P13
PTD2/
LLWU_P13
UART2_RX
LPUART0_
RX
LPI2C0_SCL
LPI2C0_SDA
SPI1_PCS0
PTD3
PTD3
UART2_TX
LPUART0_
TX
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
SPI0_PCS2
SPI0_PCS3
UART0_
RTS_b
TPM0_CH4
TPM0_CH5
EWM_IN
PTD5
ADC0_SE6b
ADC0_SE7b
PTD5
UART0_
CTS_b
EWM_OUT_b SPI1_SCK
SPI1_SOUT
PTD6/
LLWU_P15
PTD6/
LLWU_P15
UART0_RX
PTD7
PTD7
UART0_TX
SPI1_SIN
34
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Pinouts
4.2 Pin properties
The following table lists the pin properties.
100LQF 64LQFP 48QFN
P
Pin
Driver
Default Pull-up/
Slew
Rate
after
POR
Passive
Pin
Filter
after
Open
Drain
Pin
Interrupt
Name Strength Status
pull-
down
Setting
after
after
POR
POR
POR
1
2
3
1
2
1
2
3
PTE0/
CLKOUT
32K
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
-
-
-
FS
N
N
N
N
Y
PTE1/
LLWU_P
0
FS
FS
N
N
Y
Y
PTE2/
LLWU_P
1
4
5
4
5
PTE3
ND
ND
Hi-Z
Hi-Z
-
-
FS
FS
N
N
N
N
Y
Y
PTE4/
LLWU_P
2
6
6
PTE5
PTE6
VDD
VSS
ND
Hi-Z
-
-
-
-
-
-
FS
N
N
-
N
N
-
Y
Y
-
7
ND
Hi-Z
FS
8
3
4
4
5
7
-
-
-
-
-
-
-
-
-
9
8
-
-
-
-
9
9
VSS
-
-
-
-
10
10
USB0_D
P
Hi-Z
-
-
-
11
6
7
11
USB0_D
M
-
Hi-Z
-
-
-
-
-
12
13
14
USBVDD -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
-
-
8
ADC0_D
P1
Hi-Z
15
16
17
18
19
ADC0_D
M1
-
-
-
-
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC0_D
P2
ADC0_D
M2
9
ADC0_D
P0
10
ADC0_D
M0
Table continues on the next page...
KS22/KS20 Microcontroller, Rev. 3, 04/2016
35
NXP Semiconductors
Pinouts
100LQF 64LQFP 48QFN
P
Pin
Driver
Default Pull-up/
Slew
Rate
after
POR
Passive
Pin
Filter
after
Open
Drain
Pin
Interrupt
Name Strength Status
pull-
down
Setting
after
after
POR
POR
POR
20
21
11
12
ADC0_D
P3
-
-
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
ADC0_D
M3
-
22
23
24
25
26
13
14
15
16
17
12
12
13
13
VDDA
VREFH
VREFL
VSSA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CMP0_IN -
5
27
18
DAC0_O
UT/
-
Hi-Z
-
-
-
-
-
ADC0_S
E23
28
29
30
31
32
33
19
20
21
14
15
16
XTAL32
-
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXTAL32 -
-
-
VBAT
-
-
-
PTE24
PTE25
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
FS
FS
FS
N
N
N
N
N
N
Y
Y
Y
PTE26/
CLKOUT
32K
34
35
36
37
38
22
23
24
25
26
17
18
19
20
21
PTA0
PTA1
PTA2
PTA3
ND
ND
ND
ND
ND
L
PD
PU
PU
PU
PU
FS
FS
FS
FS
FS
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
H
H
H
H
PTA4/
LLWU_P
3
39
40
41
42
43
27
PTA5
VDD
ND
-
Hi-Z
-
-
-
-
-
-
FS
-
N
-
N
-
Y
-
VSS
-
-
-
-
-
-
28
29
PTA12
ND
ND
Hi-Z
Hi-Z
FS
FS
N
N
N
N
Y
Y
PTA13/
LLWU_P
4
44
45
46
PTA14
PTA15
PTA16
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
-
-
-
FS
FS
FS
N
N
N
N
N
N
Y
Y
Y
Table continues on the next page...
36
KS22/KS20 Microcontroller, Rev. 3, 04/2016
NXP Semiconductors
Pinouts
100LQF 64LQFP 48QFN
P
Pin
Driver
Default Pull-up/
Slew
Rate
after
POR
Passive
Pin
Filter
after
Open
Drain
Pin
Interrupt
Name Strength Status
pull-
down
Setting
after
after
POR
POR
POR
47
PTA17
VDD
ND
-
Hi-Z
-
-
-
-
-
-
FS
N
N
-
Y
48
49
50
51
52
30
31
32
33
34
22
23
24
25
26
-
-
-
VSS
-
-
-
-
-
-
PTA18
PTA19
ND
ND
-
Hi-Z
Hi-Z
H
FS
FS
-
N
N
Y
N
N
N
Y
Y
-
RESET_
b
PU
53
35
27
PTB0/
LLWU_P
5
HD
Hi-Z
-
FS
N
N
Y
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
36
37
38
28
29
30
PTB1
HD
ND
ND
ND
ND
ND
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FS
FS
FS
FS
FS
FS
-
N
N
N
N
N
N
-
N
N
N
N
N
N
-
Y
Y
Y
Y
Y
Y
-
PTB2
PTB3
PTB9
PTB10
PTB11
VSS
VDD
-
-
-
-
-
-
39
40
41
42
31
PTB16
PTB17
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
32
33
43
44
34
PTC1/
LLWU_P
6
72
73
45
46
35
36
PTC2
ND
HD
Hi-Z
Hi-Z
-
-
FS
FS
N
N
N
N
Y
Y
PTC3/
LLWU_P
7
74
75
47
48
VSS
VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table continues on the next page...
KS22/KS20 Microcontroller, Rev. 3, 04/2016
37
NXP Semiconductors
Pinouts
100LQF 64LQFP 48QFN
P
Pin
Driver
Default Pull-up/
Slew
Rate
after
POR
Passive
Pin
Filter
after
Open
Drain
Pin
Interrupt
Name Strength Status
pull-
down
Setting
after
after
POR
POR
POR
76
77
78
49
50
51
37
38
39
40
PTC4/
LLWU_P
8
HD
ND
ND
Hi-Z
Hi-Z
Hi-Z
-
-
-
FS
N
N
N
N
Y
PTC5/
LLWU_P
9
FS
FS
N
N
Y
Y
PTC6/
LLWU_P
10
79
80
81
82
83
52
53
54
55
56
PTC7
PTC8
PTC9
PTC10
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
FS
FS
FS
FS
FS
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
PTC11/
LLWU_P
11
84
85
86
87
88
89
90
91
92
93
PTC12
PTC13
PTC14
PTC15
VSS
ND
ND
ND
ND
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
FS
FS
FS
FS
-
N
N
N
N
-
N
N
N
N
-
Y
Y
Y
Y
-
VDD
-
-
-
-
-
-
PTC16
PTC17
PTC18
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FS
FS
FS
FS
N
N
N
N
N
N
N
N
Y
Y
Y
Y
57
41
PTD0/
LLWU_P
12
94
95
58
59
42
43
PTD1
ND
ND
Hi-Z
Hi-Z
-
-
FS
FS
N
N
N
N
Y
Y
PTD2/
LLWU_P
13
96
97
60
61
44
45
PTD3
ND
HD
Hi-Z
Hi-Z
-
-
FS
FS
N
N
N
N
Y
Y
PTD4/
LLWU_P
14
98
99
62
63
46
47
PTD5
HD
HD
Hi-Z
Hi-Z
-
-
FS
FS
N
N
N
N
Y
Y
PTD6/
LLWU_P
15
Table continues on the next page...
38
KS22/KS20 Microcontroller, Rev. 3, 04/2016
NXP Semiconductors
Pinouts
100LQF 64LQFP 48QFN
P
Pin
Driver
Default Pull-up/
Slew
Rate
after
POR
Passive
Pin
Filter
after
Open
Drain
Pin
Interrupt
Name Strength Status
pull-
down
Setting
after
after
POR
POR
POR
100
64
48
PTD7
HD
Hi-Z
-
FS
N
N
Y
Properties
Abbreviation Descriptions
Driver strength
ND
HD
Hi-Z
H
Normal drive
High drive
High impendence
High level
Low level
Pull-up
Default status after POR
L
Pull-up/pull-down setting
after POR
PU
PD
FS
SS
N
Pull-down
Fast slew rate
Slow slew rate
Disabled
Slew rate after POR
Passive Pin Filter after
POR
Y
Enabled
Open drain
N
Disabled1
Y
Enabled
Pin interrupt
Y
Yes
1. When UART or LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open
drain configurable.
4.3 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
4.3.1 Core Modules
Table 9. JTAG Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
JTAG_TMS
JTAG_TMS/
SWD_DIO
JTAG Test Mode Selection
I
Table continues on the next page...
KS22/KS20 Microcontroller, Rev. 3, 04/2016
39
NXP Semiconductors
Pinouts
Table 9. JTAG Signal Descriptions
(continued)
Chip signal name
Module signal
name
Description
I/O
JTAG_TCLK
JTAG_TCLK/
SWD_CLK
JTAG Test Clock
I
JTAG_TDI
JTAG_TDI
JTAG Test Data Input
JTAG Test Data Output
I
JTAG_TDO
JTAG_TDO/
O
TRACE_SWO
JTAG_TRST
JTAG_TRST_b
JTAG Reset
I
Table 10. SWD Signal Descriptions
Chip signal name
SWD_DIO
Module signal
Description
I/O
name
JTAG_TMS/
SWD_DIO
Serial Wire Data
Serial Wire Clock
I
I
SWD_CLK
JTAG_TCLK/
SWD_CLK
Table 11. TPIU Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TRACE_SWO
JTAG_TDO/
TRACE_SWO
Trace output data from the ARM CoreSight debug block over a
single pin
O
4.3.2 System Modules
Table 12. EWM Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
EWM_IN
EWM_in
EWM input for safety status of external safety circuits. The polarity
of EWM_in is programmable using the EWM_CTRL[ASSIN] bit.
The default polarity is active-low.
I
EWM_OUT
EWM_out
EWM reset out signal
O
40
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Pinouts
4.3.3 Clock Modules
Table 13. OSC Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
EXTAL0
XTAL0
EXTAL
XTAL
External clock/Oscillator input
Oscillator output
I
O
Table 14. RTC OSC Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
EXTAL32
XTAL32
EXTAL32
XTAL32
32.768 kHz oscillator input
32.768 kHz oscillator output
I
O
4.3.4 Analog
Table 15. ADC 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
ADC0_DP[3:0]
ADC0_DM[3:0]
ADC0_SEn
VREFH
DADP3–DADP0
Differential Analog Channel Inputs
I
I
I
I
I
I
I
DADM3–DADM0 Differential Analog Channel Inputs
ADn
VREFSH
VREFSL
VDDA
Single-Ended Analog Channel Inputs
Voltage Reference Select High
Voltage Reference Select Low
Analog Power Supply
VREFL
VDDA
VSSA
VSSA
Analog Ground
Table 16. CMP 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
IN[5:0]
CMPO
CMP0_IN[5:0]
CMP0_OUT
Analog voltage inputs
Comparator output
I
O
Table 17. DAC 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
DAC0_OUT
—
DAC output
O
KS22/KS20 Microcontroller, Rev. 3, 04/2016
41
NXP Semiconductors
Pinouts
4.3.5 Timer Modules
Table 18. PDB 0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PDB0_EXTRG
EXTRG
External Trigger Input Source
I
If the PDB is enabled and external trigger input source is selected,
a positive edge on the EXTRG signal resets and starts the
counter.
Table 19. LPTMR 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR0_ALT[2:1]
LPTMR0_ALTn
Pulse Counter Input pin
I
Table 20. RTC Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
VBAT
—
Backup battery supply for RTC and VBAT register file
1 Hz square-wave output or OSCERCLK
I
RTC_CLKOUT
RTC_CLKOUT
O
Table 21. TPM 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM0_CH[5:0]
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Table 22. TPM 1 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
Table continues on the next page...
42
NXP Semiconductors
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Pinouts
Table 22. TPM 1 Signal Descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
TPM1_CH[1:0]
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Table 23. TPM 2 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM2_CH[1:0]
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
4.3.6 Communication Interfaces
Table 24. USB FS OTG Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
usb_dm
usb_dp
—
USB0_DM
USB0_DP
USB D- analog data signal on the USB bus.
USB D+ analog data signal on the USB bus.
Alternate USB clock input
I/O
I/O
I
USB_CLKIN
USB_SOF_OUT
—
USB start of frame signal. Can be used to make the USB start of
frame available for external synchronization.
O
Table 25. CAN 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CAN Rx
CAN Tx
CAN0_RX
CAN0_TX
CAN Receive Pin
CAN Transmit Pin
Input
Output
KS22/KS20 Microcontroller, Rev. 3, 04/2016
43
NXP Semiconductors
Pinouts
Table 26. CAN 1 (for KS22 only) Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
CAN1_RX
CAN1_TX
CAN Rx
CAN Tx
CAN Receive Pin
CAN Transmit Pin
Input
Output
Table 27. SPI 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
PCS0/SS
PCS[1:3]
PCS4
SPI0_PCS0
SPI0_PCS[3:1]
SPI0_PCS4
SPI0_PCS5
SPI0_SIN
Peripheral Chip Select 0 (O)
Peripheral Chip Selects 1–3
Peripheral Chip Select 4
Peripheral Chip Select 5 /Peripheral Chip Select Strobe
Serial Data In
I/O
O
O
PCS5/ PCSS
SIN
O
I
SPI0_SOUT
SPI0_SCK
SOUT
Serial Data Out
O
SCK
Serial Clock (O)
I/O
Table 28. SPI 1 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
PCS0/SS
PCS[1:3]
SIN
SPI1_PCS0
SPI1_PCS[3:1]
SPI1_SIN
Peripheral Chip Select 0 (O)
Peripheral Chip Selects 1–3
Serial Data In
I/O
O
I
SPI1_SOUT
SPI1_SCK
SOUT
SCK
Serial Data Out
O
Serial Clock (O)
I/O
Table 29. LPI2C 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPI2C0_SCL
LPI2C0_SDA
LPI2C0_HREQ
SCL
LPI2C clock line.
LPI2C data line.
I/O
I/O
I
SDA
HREQ
Host request, can initiate an LPI2C master transfer if asserted and
the I2C bus is idle.
LPI2C0_SCLS
LPI2C0_SDAS
SCLS
SDAS
Secondary I2C clock line. If LPI2C master/slave are configured to
use separate pins, this the LPI2C slave SCL pin.
I/O
I/O
Secondary I2C data line. If LPI2C master/slave are configured to
use separate pins, this the LPI2C slave SDA pin.
44
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Pinouts
I/O
Table 30. LPI2C 1 Signal Descriptions
Chip signal name
Module signal
Description
name
LPI2C1_SCL
LPI2C1_SDA
LPI2C1_HREQ
SCL
LPI2C clock line.
LPI2C data line.
I/O
I/O
I
SDA
HREQ
Host request, can initiate an LPI2C master transfer if asserted
and the I2C bus is idle.
LPI2C1_SCLS
LPI2C1_SDAS
SCLS
SDAS
Secondary I2C clock line. If LPI2C master/slave are configured to
use separate pins, this the LPI2C slave SCL pin.
I/O
I/O
Secondary I2C data line. If LPI2C master/slave are configured to
use separate pins, this the LPI2C slave SDA pin.
Table 31. LPUART Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART0_TX
LPUART_TX
Transmit data. This pin is normally an output, but is an input
(tristated) in single wire mode whenever the transmitter is
disabled or transmit direction is configured for receive data.
O/I
LPUART0_RX
LPUART0_CTS
LPUART0_CTS
LPUART_RX
LPUART_CTS
LPUART_RTS
Receive data
Clear to send
Request to send
I
I
I
Table 32. UART 0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CTS
RTS
TXD
RXD
UART0_CTS
UART0_RTS
UART0_TX
UART0_RX
Clear to send
Request to send
Transmit data
Receive data
I
O
O
I
Table 33. UART 1 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CTS
RTS
TXD
RXD
UART1_CTS
UART1_RTS
UART1_TX
UART1_RX
Clear to send
Request to send
Transmit data
Receive data
I
O
O
I
KS22/KS20 Microcontroller, Rev. 3, 04/2016
45
NXP Semiconductors
Pinouts
Table 34. UART 2 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CTS
RTS
TXD
RXD
UART2_CTS
UART2_RTS
UART2_TX
UART2_RX
Clear to send
Request to send
Transmit data
Receive data
I
O
O
I
Table 35. I2S0 Signal Descriptions
Chip signal name
I2S0_MCLK
Module signal
name
Description
I/O
I/O
I/O
I/O
SAI_MCLK
Audio Master Clock. The master clock is an input when externally
generated and an output when internally generated.
I2S0_RX_BCLK
I2S0_RX_FS
SAI_RX_BCLK
SAI_RX_SYNC
Receive Bit Clock. The bit clock is an input when externally
generated and an output when internally generated.
Receive Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated.
I2S0_RXD
I2S0_TX_BCLK
I2S0_TX_FS
SAI_RX_DATA
SAI_TX_BCLK
SAI_TX_SYNC
Receive Data. The receive data is sampled synchronously by the
bit clock.
I
Transmit Bit Clock. The bit clock is an input when externally
generated and an output when internally generated.
I/O
I/O
Transmit Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated.
I2S0_TXD
SAI_TX_DATA
Transmit Data. The transmit data is generated synchronously by
the bit clock and is tristated whenever not transmitting a word.
O
Table 36. I2S1 Signal Descriptions
Chip signal name
I2S1_MCLK
Module signal
Description
I/O
I/O
I/O
I/O
name
SAI_MCLK
Audio Master Clock. The master clock is an input when externally
generated and an output when internally generated.
I2S1_RX_BCLK
I2S1_RX_FS
SAI_RX_BCLK
SAI_RX_SYNC
Receive Bit Clock. The bit clock is an input when externally
generated and an output when internally generated.
Receive Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated.
I2S1_RXD
SAI_RX_DATA
Receive Data. The receive data is sampled synchronously by the
bit clock.
I
Table continues on the next page...
46
NXP Semiconductors
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Pinouts
Table 36. I2S1 Signal Descriptions (continued)
Chip signal name
I2S1_TX_BCLK
I2S1_TX_FS
Module signal
name
Description
I/O
I/O
I/O
SAI_TX_BCLK
Transmit Bit Clock. The bit clock is an input when externally
generated and an output when internally generated.
SAI_TX_SYNC
Transmit Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated.
I2S1_TXD
SAI_TX_DATA
Transmit Data. The transmit data is generated synchronously by
the bit clock and is tristated whenever not transmitting a word.
O
Table 37. FlexIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
FXIO0_Dn
FXIO_Dn (n=0...7) Bidirectional FlexIO Shifter and Timer pin inputs/outputs
I/O
4.3.7 Human-Machine Interfaces (HMI)
Table 38. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[31:0]1
PTB[31:0]1
PTC[31:0]1
PTD[31:0]1
PTE[31:0]1
PORTA31–PORTA0 General-purpose input/output
PORTB31–PORTB0 General-purpose input/output
PORTC31–PORTC0 General-purpose input/output
PORTD31–PORTD0 General-purpose input/output
PORTE31–PORTE0 General-purpose input/output
I/O
I/O
I/O
I/O
I/O
1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO
signals are available.
4.4 Pinouts
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous "signal multiplexing and pin
assignments" section.
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Pinouts
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0/CLKOUT32K
VDD
2
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VSS
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
PTE4/LLWU_P2
PTE5
6
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE6
8
VDD
9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
USB0_DP
USB0_DM
USBVDD
NC
ADC0_DP1
ADC0_DM1
ADC0_DP2
ADC0_DM2
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
VSS
PTB11
PTB10
PTB9
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 6. 100 LQFP Pinout Diagram
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Pinouts
PTE0/CLKOUT32K
PTE1/LLWU_P0
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
VSS
4
USB0_DP
USB0_DM
USBVDD
ADC0_DP1
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
5
PTC1/LLWU_P6
PTC0
6
7
PTB19
8
PTB18
9
PTB17
10
11
12
13
14
15
16
PTB16
PTB3
PTB2
PTB1
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 7. 64 LQFP Pinout Diagram
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Pinouts
PTC3/LLWU_P7
PTC2
36
35
34
33
32
31
30
29
28
27
26
25
PTE0/CLKOUT32K
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
1
2
PTC1/LLWU_P6
PTB19
3
4
PTB18
PTE4/LLWU_P2
PTE5
5
PTB16
6
VDD
PTB3
7
VSS
PTB2
8
USB0_DP
USB0_DM
USBVDD
PTB1
9
PTB0/LLWU_P5
RESET_b
PTA19
10
11
12
VDDA VREFH
Figure 8. 48 QFN Pinout Diagram
4.5 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
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Figure 9. 100-pin LQFP package dimensions 1
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Figure 10. 100-pin LQFP package dimensions 2
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Figure 11. 64-pin LQFP package dimensions 1
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Figure 12. 64-pin LQFP package dimensions 2
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Figure 13. 48-pin QFN package dimension 1
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45°
0.25
(0.05)
0.95
1.13
DETAIL F
// 0.1 C
48X
0.65
0.50
0.08 C
4
0.05
0.00
(0.2)
C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.
Figure 14. 48-pin QFN package dimension 2
5 Electrical characteristics
5.1 Terminology and guidelines
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5.1.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
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5.1.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
5.1.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
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5.1.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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5.2.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
Table 39. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
VUSB_DP
VUSB_DM
VBAT
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
RTC battery supply voltage
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
–0.3
3.63
–0.3
3.8
5.3 General
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5.3.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 15. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
5.3.2 Nonswitching electrical specifications
5.3.2.1 Voltage and current operating requirements
Table 40. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
3.6
0.1
0.1
3.6
3.6
—
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VBAT
RTC battery supply voltage
1.71
V
USBVDD USB Transceiver supply voltage
3.0
V
1
VIH
Input high voltage
0.7 × VDD
0.75 × VDD
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
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Table 40. Voltage and current operating requirements (continued)
Symbol
Description
Min.
—
Max.
Unit
V
Notes
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
—
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
2
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
3
VDD voltage required to retain RAM
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. USB nominal operating voltage is 3.3 V.
2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or greater
than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VIO_MIN-VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD.
5.3.2.2 HVD, LVD and POR operating requirements
Table 41. VDD supply HVD, LVD and POR operating requirements
Symbol Description
Min.
—
Typ.
3.72
3.46
1.1
Max.
—
Unit
V
Notes
VHVDH
VHVDL
VPOR
High Voltage Detect (High Trip Point)
High Voltage Detect (Low Trip Point)
Falling VDD POR detect voltage
—
—
V
0.8
2.48
1.5
2.64
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.56
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
1
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Table 41. VDD supply HVD, LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW1L
VLVW2L
VLVW3L
VLVW4L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.84
1.94
2.04
1.90
2.00
2.10
1.96
2.06
2.16
V
V
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 42. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
5.3.2.3 Voltage and current operating behaviors
Table 43. Voltage and current operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VOH Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
1
VOH
Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
Output high current total for all ports
VDD – 0.5
VDD – 0.5
—
—
—
—
—
—
V
V
1
IOHT
VOL
100
mA
Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
—
—
0.5
0.5
V
V
1
1
VOL
Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
Output low voltage — RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
—
—
—
—
0.5
0.5
V
V
VOL
—
—
0.5
V
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Table 43. Voltage and current operating behaviors (continued)
Symbol Description
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Min.
—
Typ.
—
Max.
0.5
Unit
V
Notes
IOLT
IIN
Output low current total for all ports
—
—
100
mA
Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins
High drive port pins
—
—
—
0.002
0.004
—
0.5
0.5
1.0
μA
μA
μA
1, 2
2
IIN
Input leakage current (total all pins) for full
temperature range
RPU
RPD
Internal pullup resistors
20
20
—
—
50
50
kΩ
kΩ
3
4
Internal pulldown resistors
1. PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4 I/O have both high drive and normal drive capability selected
by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.3.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx → RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 80 MHz
• Bus clock = 40 MHz
• Flash clock = 20 MHz
• MCG mode: FEI
Table 44. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
—
—
—
—
—
—
—
—
140
140
80
μs
μs
μs
μs
80
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Table 44. Power mode transition operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• LLS2 → RUN
—
—
6
μs
• LLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
6
μs
—
—
5.7
5.7
μs
—
—
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=1)
5.3.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent the characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while(1) test is executed with flash cache enabled.
Table 45. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
@ 1.8V
@ 3.0V
—
—
24.17
24.20
26.215
26.292
mA
mA
2, 3, 4
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
20.97
20.97
23.015
23.062
mA
mA
2
5
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
27.77
27.79
30.028
30.083
mA
mA
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from
flash
@ 1.8V
@ 3.0V
—
—
15.58
16.19
16.790
17.457
mA
mA
3, 4, 6
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Table 45. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V
@ 3.0V
—
—
13.38
13.42
14.590
14.687
mA
mA
6
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
—
13.81
15.087
mA
7
8
9
@ 3.0V
• @ 25°C
—
—
—
—
—
13.87
13.72
14.03
14.12
14.31
15.158
15.050
15.267
15.347
15.529
mA
mA
mA
mA
mA
• @ -40°C
• @ 70°C
• @ 85°C
• @ 105°C
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
—
18.00
20.042
mA
@ 3.0V
• @ 25°C
—
—
—
—
—
18.08
17.88
18.27
18.35
18.55
20.145
20.022
20.229
20.321
20.544
mA
mA
mA
mA
mA
• @ -40°C
• @ 70°C
• @ 85°C
• @ 105°C
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V
—
12.68
13.763
mA
@ 3.0V
• @ 25°C
—
—
—
—
—
—
12.62
12.53
12.76
12.84
13.02
6.56
13.714
13.652
13.827
13.895
14.078
7.022
mA
mA
mA
mA
mA
mA
• @ -40°C
• @ 70°C
• @ 85°C
• @ 105°C
IDD_WAIT Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
7
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
3.80
4.118
mA
10
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Table 45. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V
@ 3.0V
—
—
967.09
973.06
1031.341
1040.294
μA
μA
3, 4, 11
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V
@ 3.0V
—
—
—
449.10
462.61
520.34
513.351
529.844
592.022
μA
μA
μA
11
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
12
13
14
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
845.46
240.81
1005.706
269.275
μA
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
@ 25°C
—
—
—
—
—
269.63
253.73
309.98
347.88
450.05
292.223
280.001
346.335
401.693
565.013
μA
μA
μA
μA
μA
@ -40°C
@ 70°C
@ 85°C
@ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ 25°C
—
—
—
—
—
3.48
2.47
6.005
3.740
µA
µA
µA
µA
µA
@ -40°C
@ 70°C
15.20
28.62
65.48
30.384
52.396
115.129
@ 85°C
@ 105°C
IDD_LLS3 Low leakage stop mode 3 current at 3.0 V
@ 25°C
—
—
—
—
—
2.78
2.14
3.778
2.881
µA
µA
µA
µA
µA
@ -40°C
@ 70°C
7.72
12.481
21.607
47.202
@ 85°C
13.30
29.50
@ 105°C
IDD_LLS2 Low leakage stop mode 2 current at 3.0 V
@ 25°C
—
—
—
—
—
2.56
2.10
3.293
2.802
µA
µA
µA
µA
µA
@ -40°C
@ 70°C
6.14
8.758
@ 85°C
10.34
22.68
15.242
33.393
@ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ 25°C
—
2.01
2.769
µA
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Table 45. Power consumption operating behaviors (continued)
Symbol Description
Min.
—
Typ.
1.55
Max.
2.485
Unit
µA
Notes
@ -40°C
@ 70°C
—
5.81
9.658
µA
@ 85°C
—
10.06
22.30
16.695
35.783
µA
@ 105°C
—
µA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ 25°C
—
—
—
—
—
1.76
1.51
3.73
6.12
13.22
2.298
1.963
5.221
8.624
18.408
µA
µA
µA
µA
µA
@ -40°C
@ 70°C
@ 85°C
@ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ 25°C
@ -40°C
@ 70°C
@ 85°C
@ 105°C
—
—
—
—
—
0.64
0.55
1.88
3.52
8.62
0.835
0.795
2.427
4.640
11.273
µA
µA
µA
µA
µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ 25°C
@ -40°C
@ 70°C
@ 85°C
@ 105°C
—
—
—
—
—
0.36
0.29
1.58
3.19
8.20
0.525
0.513
2.108
4.289
10.838
µA
µA
µA
µA
µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ 25°C
@ -40°C
@ 70°C
@ 85°C
@ 105°C
—
—
—
—
—
0.093
0.016
1.30
0.249
0.145
1.821
3.994
10.501
µA
µA
µA
µA
µA
2.91
7.92
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
VDD is off.
@ 25°C
@ -40°C
@ 70°C
@ 85°C
@ 105°C
—
—
—
—
—
0.21
0.14
1.15
2.44
6.49
0.245
0.163
1.498
3.596
9.557
µA
µA
µA
µA
µA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
VDD is off.
• @ 25°C
—
0.76
0.899
µA
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Table 45. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• @ -40°C
—
0.63
0.745
µA
• @ 70°C
• @ 85°C
• @ 105°C
—
—
—
1.80
3.11
7.24
2.346
4.575
µA
µA
µA
10.653
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All
peripheral clocks disabled.
3. Cache on and prefetch on, low compiler optimization.
4. Coremark benchmark compiled using IAR 7.2 with optimization level high.
5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All
peripheral clocks enabled.
6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode.
Compute operation.
7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute
operation.
10. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
11. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation.
Code executing from flash.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
5.3.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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Figure 16. Run mode supply current vs. core frequency
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Figure 17. VLPR mode supply current vs. core frequency
5.3.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
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• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
5.3.2.6.1 EMC radiated emissions operating behaviors
Table 46. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
Clocks
Frequency range
Level
(Typ.)
Unit
Notes
VEME
Device configuration, test FSYS = 120 MHz
150 kHz–50 MHz
50 MHz–150 MHz
150 MHz–500 MHz
500 MHz–1000 MHz
IEC level
14
23
23
9
dBuV
1, 2
conditions and EM
testing per standard IEC
FBUS = 60 MHz
External crystal = 8 MHz
61967-2.
Supply voltages:
• VDD = 3.3 V
L
3
Temp = 25°C
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
3. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
5.3.2.6.2 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.3.2.7 Capacitance attributes
Table 47. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3.3 Switching specifications
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5.3.3.1 Device clock specifications
Table 48. Device clock specifications
Symbol
Description
Min.
Max.
Unit
High Speed run mode
Normal run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
120
60
MHz
MHz
fSYS
fSYS_USB
fBUS
System and core clock
—
20
—
—
—
80
—
MHz
MHz
MHz
MHz
MHz
System and core clock when Full Speed USB in operation
Bus clock
50
fFLASH
fLPTMR
Flash clock
26.67
25
LPTMR clock
VLPR and VLPS modes1
System and core clock
Bus clock
fSYS
fBUS
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fERCLK
fLPTMR_pin
Flash clock
1
External reference clock
LPTMR clock
16
25
16
12.5
4
fLPTMR_ERCLK LPTMR external reference clock
fI2S_MCLK
fI2S_BCLK
fFlexIO
I2S master clock
I2S bit clock
FlexIO clock
LPI2C clock
16
16
4
fLPI2C
fFlexCAN
FlexCAN clock
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
5.3.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 49. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
3
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Table 49. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50
—
ns
4
Port rise and fall time
• Slew disabled
5
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
10
5
ns
ns
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
30
16
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
5.3.4 Thermal specification
5.3.4.1 Thermal operating requirements
Table 50. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
5.3.4.2 Thermal attributes
Table 51. Thermal attributes
Board type
Symbol
Description
100
64 LQFP 48 QFN
Unit
Notes
LQFP
Single-layer (1s)
RθJA
Thermal resistance, junction to
ambient (natural convection)
58
61 81
°C/W
1, 2, 3
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Table 51. Thermal attributes (continued)
Board type
Symbol
Description
100
LQFP
64 LQFP 48 QFN
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2, 3,4
1, 4, 5
1, 4, 5
6
Four-layer (2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
46
48
40
31
16
2
43
49
36
25
13
2
28
66
23
11
1.3
2
Single-layer (1s)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer (2s2p)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
Thermal resistance, junction to
case
7
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
8
—
ΨJB
Thermal characterization
-
-
-
°C/W
9
parameter, junction to package
bottom (natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
7. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
8. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
9. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
5.4 Peripheral operating requirements and behaviors
5.4.1 Debug modules
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5.4.1.1 SWD electricals
Table 52. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
SWD_CLK frequency of operation
• Serial wire debug
0
33
—
MHz
ns
S2
S3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/S1
15
—
ns
S4
S9
SWD_CLK rise and fall times
—
8
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
25
—
S10
S11
S12
1.4
—
5
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 18. Serial wire clock input timing
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Electrical characteristics
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
S9
S10
Input data valid
S11
Output data valid
S12
S11
Output data valid
Figure 19. Serial wire data timing
5.4.1.2 JTAG electricals
Table 53. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
TCLK frequency of operation
• Boundary Scan
2.7
3.6
J1
MHz
0
0
10
20
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
ns
ns
• JTAG and CJTAG
J4
J5
TCLK rise and fall times
—
20
1
3
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
—
—
25
25
—
—
J6
J7
—
—
8
J8
J9
J10
1
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Table 53. JTAG limited voltage range electricals (continued)
Symbol
J11
Description
Min.
—
Max.
19
Unit
ns
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
J12
—
19
ns
J13
100
8
—
ns
J14
TRST setup time (negation) to TCLK high
—
ns
Table 54. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
10
15
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
33
—
—
ns
ns
• JTAG and CJTAG
J4
J5
TCLK rise and fall times
—
20
1.4
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
27
27
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
26.2
26.2
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 20. Test clock input timing
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Electrical characteristics
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 21. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 22. Test Access Port timing
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TCLK
TRST
J14
J13
Figure 23. TRST timing
5.4.2 System modules
There are no specifications necessary for the device's system modules.
5.4.3 Clock modules
5.4.3.1 MCG specifications
Table 55. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Δfints_t
fints_t
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
31.25
—
+0.5/-0.7
—
2
39.0625
0.6
%
Internal reference frequency (slow clock) —
user trimmed
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
2
%fdco
%fdco
1, 2
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
—
4
—
5
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
5
MHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
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Table 55. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
20.97
MHz
3, 4
frequency range
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
180
150
—
—
—
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
120
—
MHz
µA
PLL operating current
8
8
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
=
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
9
9
—
—
120
75
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
—
—
1350
600
—
—
ps
ps
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Symbol Description
Table 55. MCG specifications (continued)
Min.
Typ.
Max.
Unit
Notes
• fvco = 48 MHz
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
5.4.3.2 IRC48M specifications
Table 56. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
400
48
500
—
μA
Internal reference frequency
—
MHz
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
—
high voltage (VDD=1.89V-3.6V) over 0°C to 70°C
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
—
—
—
0.2
0.4
0.4
0.5
1.0
1.0
%firc48m
%firc48m
%firc48m
1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full temperature
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
1
1
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at low
voltage (VDD=1.71V-1.89V) over full temperature
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
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Table 56. IRC48M specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Regulator enable
—
0.5
1.5
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency over
—
—
0.1
%fhost
2
3
voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean 3 sigma).
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.
It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1,
USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable
the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
5.4.3.3 Oscillator electrical specifications
5.4.3.3.1 Oscillator DC electrical specifications
Table 57. Oscillator DC electrical specifications
Symbol Description
VDD Supply voltage
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
IDDOSC Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
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Table 57. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 24 MHz
—
4
—
mA
• 32 MHz
Cx
Cy
RF
EXTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
XTAL load capacitance
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-
power mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
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5.4.3.3.2 Oscillator frequency specifications
Table 58. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
5.4.3.4 32 kHz oscillator electrical characteristics
5.4.3.4.1 32 kHz oscillator DC electrical specifications
Table 59. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
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5.4.3.4.2 32 kHz oscillator frequency specifications
Table 60. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
5.4.4 Memories and memory interfaces
5.4.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
5.4.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 61. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
13
113
904
ms
ms
thversall
Erase All high-voltage time
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
5.4.4.1.2 Flash timing specifications — commands
Table 62. Flash command timing specifications
Symbol Description
Min.
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec2k Read 1s Section execution time (flash sector)
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
—
—
45
μs
—
—
30
μs
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Table 62. Flash command timing specifications (continued)
Symbol Description
Min.
—
Typ.
65
Max.
145
114
1.8
Unit
μs
Notes
tpgm4
tersscr
trd1all
Program Longword execution time
—
2
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
14
ms
ms
μs
—
—
1
trdonce
—
—
30
1
tpgmonce Program Once execution time
—
100
175
—
—
μs
—
2
tersall
Erase All Blocks execution time
—
1300
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
—
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.4.1.3 Flash high voltage current behaviors
Table 63. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
5.4.4.1.4 Reliability specifications
Table 64. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.4.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
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5.4.6 Analog
5.4.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 65 and Table 66 are achievable on the
differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
5.4.6.1.1 16-bit ADC operating conditions
Table 65. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
Ground voltage Delta to VSS (VSS – VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20
37
—
—
1200
461
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
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Table 65. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 24. ADC input impedance equivalency diagram
5.4.6.1.2 16-bit ADC electrical characteristics
Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
2.4
3.9
MHz
tADACK = 1/
fADACK
fADACK
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Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
3.0
4.4
5.2
6.2
7.3
9.5
MHz
MHz
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
• <12-bit modes
—
—
1.0
0.5
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
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Table 66. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
EIL Input leakage error
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's
voltage and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 25. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 26. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
5.4.6.2 CMP and 6-bit DAC electrical specifications
Table 67. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
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2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 28. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
5.4.6.3 12-bit DAC electrical characteristics
5.4.6.3.1 12-bit DAC operating requirements
Table 68. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
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5.4.6.3.2 12-bit DAC operating behaviors
Table 69. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
330
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
1200
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
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8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 29. Typical INL error vs. digital code
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1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 30. Offset at half scale vs. temperature
5.4.7 Timers
See General switching specifications.
5.4.8 Communication interfaces
5.4.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
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NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter or signaling
rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the USB
clock recovery mode is enabled. It does not meet the USB
signaling rate specifications for certification in Host mode
operation.
5.4.8.2 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the SPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 70. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
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DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 31. DSPI classic SPI timing — master mode
Table 71. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
15
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
1
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
21.4
—
ns
ns
2.6
7
—
ns
—
ns
—
—
17
17
ns
ns
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus
clock is 60 MHz, the SPI clock must not be greater than 10 MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 32. DSPI classic SPI timing — slave mode
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5.4.8.3 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the SPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 72. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
24.6
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 33. DSPI classic SPI timing — master mode
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Table 73. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.5
—
ns
ns
3.2
7
—
ns
—
ns
—
—
25
25
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 34. DSPI classic SPI timing — slave mode
Table 74. LPI2C specifications
5.4.8.4 LPI2C
Symbol Description
Min.
Max.
100
Unit
Notes
1
fSCL
SCL clock frequency
Standard mode (Sm)
Fast mode (Fm)
0
0
0
0
0
kHz
400
1, 2
1, 3
1, 4
1, 5
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1. See General switching specifications, measured at room temperature.
2. Measured with the maximum bus loading of 400pF at 3.3V VDD with pull-up Rp = 220Ω , and at 1.8V VDD with Rp =
880Ω. For all other cases, select appropriate Rp per I2C Bus Specification and the pin drive capability.
3. Fm+ is only supported on high drive pin with high drive enabled. It is measured with the maximum bus loading of
400pF at 3.3V VDD with Rp = 220Ω. For all other cases, select appropriate Rp per I2C Bus Specification and the pin
drive capability.
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4. UFm is only supported on high drive pin with high drive enabled and push-pull output only mode. It is measured at 3.3V
VDD with the maximum bus loading of 400pF. For 1.8V VDD, the maximum speed is 4Mbps.
5. Hs-mode is only supported in slave mode and on the high drive pins with high drive enabled.
5.4.8.5 UART switching specifications
See General switching specifications.
5.4.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
5.4.8.6.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 75. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
18
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 35. I2S/SAI timing — master modes
Table 76. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
2.7
80
3.6
—
V
S11
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
20
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
4.5
2
—
—
25
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 36. I2S/SAI timing — slave modes
5.4.8.6.2 Normal Run, Wait and Stop mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 77. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
27
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 37. I2S/SAI timing — master modes
Table 78. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
80
3.6
—
V
S11
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
28.5
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
5.8
2
—
ns
ns
ns
—
—
26.3
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 38. I2S/SAI timing — slave modes
5.4.8.6.3 VLPR, VLPW, and VLPS mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 79. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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Electrical characteristics
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 39. I2S/SAI timing — master modes
Table 80. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
7
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
—
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
4
—
—
72
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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Design considerations
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 40. I2S/SAI timing — slave modes
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital circuits
between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane
directly under LQFP packages; and solder the exposed pad (EP) to ground directly
under QFN packages.
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Design considerations
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as
sequential segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• The USB_VDD voltage range is 3.0 V to 3.6 V. It is recommended to include a
filter circuit with one bulk capacitor (no less than 2.2 μF) and one 0.1 μF capacitor
at the USB_VDD pin to improve USB performance.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 41. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and
over-voltage protection as shown the following figure. The voltage divider formed by
R1 – R4 must yield a voltage less than or equal to VREFH. The current must be
limited to less than the injection current limit. Since the ADC pins do not have diodes
to VDD, external clamp diodes must be included to protect against transient over-
voltages.
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Design considerations
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 42. High voltage measurement with an ADC input
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• RESET_b pin
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following figure.
The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended
capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to
reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 43. Reset circuit
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Design considerations
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength.
The supervisor chip must have an active high, open-drain output.
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 44. Reset signal connection to external reset chip
• NMI pin
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low
level on this pin will trigger non-maskable interrupt. When this pin is enabled as
the NMI function, an external pull-up resistor (10 kΩ) as shown in the following
figure is recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
VDD
MCU
10k
NMI_b
Figure 45. NMI pin biasing
• Debug interface
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Design considerations
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
recommendations mentioned above must also be considered.
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 46. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection.
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating. Connect USB_VDD to ground through a 10 kΩ resistor if the USB module
is not used.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators. An
external feedback is required when using high gain (HGO=1) mode.
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NXP Semiconductors
Design considerations
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786 kHz)
mode. Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for
the crystal. Typically, values of 10pf to 16 pF are sufficient for 32.768 kHz crystals
that have a 12.5 pF CL specification. The internal load capacitor selection must not be
used for high frequency crystals and resonators.
Table 81. External crystal/resonator connections
Oscillator mode
Low frequency (32.768 kHz), low power
Low frequency (32.768 kHz), high gain
High frequency (3-32 MHz), low power
High frequency (3-32 MHz), high gain
Oscillator mode
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 47. Crystal connection – Diagram 1
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 48. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 49. Crystal connection – Diagram 3
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Part identification
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 50. Crystal connection – Diagram 4
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive Freescale and third-party hardware
and software enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below. Visit http://www.freescale.com/
kinetis/sw for more information and supporting collateral.
Evaluation and Prototyping Hardware
• MAPS Development Kit: http://www.freescale.com/KS
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.freescale.com/kds
• Partner IDEs: http://www.freescale.com/kide
Run-time Software
• Kinetis SDK: http://www.freescale.com/ksdk
• Kinetis Bootloader: http://www.freescale.com/kboot
• ARM mbed Development Platform: http://www.freescale.com/mbed
For all other partner-developed software and tools, visit http://www.freescale.com/
partners.
7 Part identification
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Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KS## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 82. Part number fields description
Field
Description
Values
Q
Qualification status
Kinetis family
• M = Fully qualified, general market flow
• P = Prequalification
KS##
• KS20
• KS22
A
Key attribute
• F = Cortex-M4 with DSP and FPU
FFF
Program flash memory size
• 128 = 128 KB
• 256 = 256 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FT = 48 QFN (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 12 = 120 MHz
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKS22FN256VLL12
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Revision history
8 Revision history
The following table provides a revision history for this document.
Table 83. Revision history
Rev. No.
Date
Substantial Changes
Initial public release.
2
3
12/2015
04/2016
Added 48-pin QFN package.
116
NXP Semiconductors
KS22/KS20 Microcontroller, Rev. 3, 04/2016
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, Freescale, the Freescale logo and Kinetis are trademarks of
NXP B.V.All other product or service names are the property of their respective
owners. ARM and Cortex are registered trademarks of ARM Limited (or its
subsidiaries) in the EU and/or elsewhere. All rights reserved.
©2016 NXP B.V.
Document Number KS22P100M120SF0
Revision 3, 04/2016
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