935314509574_技术文档

Document Number: MMA68xx

Rev. 9.0, 01/2017

NXP Semiconductors

Data sheet: Technical data

MMA68xx, Dual-axis SPI Inertial

Sensor

MMA68xx

MMA68xx, a SafeAssure solution, is a SPI-based, 2-axis, medium-g, over-

damped lateral accelerometer designed for use in automotive airbag systems.

Features

Bottom View

•

±20 g to ±120 g full-scale range, independently specified for each axis

3.3 V or 5 V single supply operation

SPI-compatible serial interface

10-bit digital signed or unsigned SPI data output

Independent programmable arming functions for each axis

Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz

Pb-free, 16-pin QFN

6 mm x 6 mm x 1.98 mm package

Optional offset cancellation with > 6 s averaging period and < 0.25 LSB/s

slew rate

•

Pb-free, 16-pin QFN, 6 mm x 6 mm x 1.98 mm package

Top View

Referenced Documents

• Qualified AEC-Q100, Revision G, Grade 1 (-40°C to +125°C)

(http://www.aecouncil.com/)

16 15 14 13

Ordering information

V

1

2

3

4

12 CS

REGA

17

X-axis

Range

Y-axis

Range

V

11 MOSI

10 SCLK

SS

Device

Package

Shipping

V

REG

MMA6811BKCW

MMA6813BKCW

MMA6821BKCW

MMA6823BKCW

MMA6825BKCW

MMA6826BKCW

MMA6827BKCW

MMA6811BKCWR2

MMA6813BKCWR2

MMA6821BKCWR2

MMA6823BKCWR2

MMA6825BKCWR2

MMA6826BKCWR2

MMA6827BKCWR2

±60 g

±50 g

±25 g

±50 g

±25 g

±60 g

±100 g

±60 g

±120 g

±25 g

±50 g

±25 g

±60 g

±100 g

±60 g

±120 g

98ASA00690D

Tubes

V

9 V

CC

SS

5

6

7

8

±120 g

±100 g

±60 g

Tubes

±120 g

±60 g

Tubes

Pin Connections

Tape & Reel

±50 g

±120 g

±100 g

±60 g

±120 g

1

General Description

1.1

Application Diagram

V_CC

CS_A

CS_D

SCLK2

MOSI2

MISO2

CS

SCLK

MOSI

V_REG

V_REGA

SCLK1

MOSI1

MISO1

SCLK

MOSI

MISO

C1

C2

C3

Main MCU

Deployment IC

MMA68xx

V_SSA

DEPLOY_EN1

DEPLOY_EN2

ARM_X

ARM_Y

V_SS

V_PP/TEST

Figure 1. Application Diagram

Table 1. External Component Recommendations

Ref Des

C1

Type

Description

Purpose

Ceramic

0.1 μF, 10 %, 10 V Minimum, X7R

1 μF, 10 %, 10 V Minimum, X7R

V_CCPower Supply Decoupling

C2

Voltage Regulator Output Capacitor (C_REG)

C3

Voltage Regulator Output Capacitor (C_REGA

)

1.2

Device Orientation and Part Marking

x x x x x x x

xxxxxxx

X: 0 g

Y: +1 g

X: –1 g

Y: 0 g

X: 0 g

Y: 0 g

X: 0 g

Y: 0 g

X: 0 g

Y: –1 g

X: +1 g

Y: 0 g

EARTH GROUND

Figure 2. Device Orientation Diagram

Data Code Legend:

A: Assembly Location

WL: Wafer Lot Number (g-cell Lot Number)

MMA68xx

BKCW

AWLYWWZ

TTT

Y: Year

WW: Work Week

Z: Assembly Lot Number

Figure 3. Part Marking

MMA68xx

Sensors

2

NXP Semiconductors

1.3

Internal Block Diagram

V_PP

V_CC

V_REG

V_SS

V_REGA

V_SSA

Offset

IIR

Linear

Interpolation

Low-Pass Filter

Cancellation

SINC Filter

ARM_Y

Compensation

Output

Scaling

Over-Damped

ARM_Y

Y-axis g-Cell

Offset

Monitor

Clock CRC

Generation

Y-axis

SPI

Mismatch

Verification

Y-axis Register

Array

ΣΔ

Converter

V_REGA

V_CC

V_REG

CS

Clock & bias

Generator

SPI

SCLK

MOSI

1 MHz

I/O

OTP

Array

8 MHz

Digital

Voltage

Monitoring

Memory

Self

Analog

Test

Regulator

1 MHz Oscillator

Regulator

V_REGA

MISO

V_REG

Clock & bias

Generator

ΣΔ

Converter

Over-Damped

X-axis g-Cell

X-axis Register

Array

X-axis

SPI

Clock CRC

Generation

Clock

Monitoring

Offset

Monitor

Output

Scaling

IIR

ARM_X

Offset

Cancellation

Linear

Interpolation

Low-Pass Filter

ARM_X

SINC Filter

Compensation

Figure 4. Block Diagram

MMA68xx

Sensors

NXP Semiconductors

3

2

Pin Connections

16 15 14 13

17

V_REGA

V_SS

1

2

3

4

12 CS

11 MOSI

10 SCLK

V_REG

V_SS

9

V_CC

5

6

7

8

Figure 5. 16-Pin QFN Package, Top View

Definition

Table 2. Pin Description

Formal Name

Name

1

V_REGA

Analog

Supply

This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be

connected between this pin and V_SSA. Reference Figure 1.

2

3

V_SS

Digital GND This pin is the power supply return node for the digital circuitry.

V_REG

Digital

This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be

connected between this pin and V_SS. Reference Figure 1.

Supply

4

5

V_SS

Digital GND This pin is the power supply return node for the digital circuitry.

Y-axis The function of this pin is configurable via the DEVCFG register as described in Section 4.1.6.5. When the

ARM_Y/

PCM_Y Arm Output / arming output is selected, ARM_Y can be configured as an open drain, active low output with a pullup current;

PCM Output or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital

output with PCM signal proportional to the Y-axis acceleration data. Reference Section 4.8.9 and Section

4.8.9.1. If unused, this pin must be left unconnected.

6

7

ARM_X/

X-axis

The function of this pin is configurable via the DEVCFG register as described in Section 4.1.6.5. When the

PCM_X Arm Output / arming output is selected, ARM_X can be configured as an open drain, active low output with a pullup current;

PCM Output or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital

output with a PCM signal proportional to the X-axis acceleration data. Reference Section 4.8.9 and Section

4.8.9.1. If unused, this pin must be left unconnected.

TEST/

V_PP

Programming This pin provides the power for factory programming of the OTP registers. This pin must be connected to V_SS

Voltage

in the application.

SPI Data Out This pin functions as the serial data output for the SPI port.

8

9

MISO

V_CC

Supply

This pin supplies power to the device. An external capacitor must be connected between this pin and V_SS

Reference Figure 1.

.

10

11

12

13

14

15

16

17

SCLK

MOSI

CS

SPI Clock

This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin.

SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin.

Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin.

Analog GND This pin is the power supply return node for analog circuitry.

No Connect No Connection

V_SSA

N/C

No Connect No Connection

V_SSA

PAD

Analog GND This pin is the power supply return node for analog circuitry.

Die Attach Pad This pin is the die attach flag, and is internally connected to V_SS

Corner Pads The corner pads are internally connected to V_SS

.

Corner

Pads

.

MMA68xx

Sensors

4

NXP Semiconductors

3

Electrical Characteristics

3.1

Maximum Ratings

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.

#

Rating

Symbol

Value

Unit

V

Supply Voltage

V

–0.3 to +7.0

–0.3 to +3.0

(3)

1

2

3

4

5

6

7

8

9

CC

C

, C

V

REG

REGA

REG

SCLK, CS, MOSI, V /TEST

PP

V

–0.3 to V + 0.3

CC

V

(3)

IN

ARM_X, ARM_Y

V

–0.3 to V + 0.3

CC

V

(3)

IN

MISO (high impedance state)

V

–0.3 to V + 0.3

CC

V

(3)

IN

Acceleration without hitting internal g-cell stops

Acceleration without saturation of internal circuitry

Powered Shock (six sides, 0.5 ms duration)

Unpowered Shock (six sides, 0.5 ms duration)

Drop Shock (to concrete surface)

g

500

375

g

(3, 18)

(3)

gcell_Clip

g

ADC_Clip

g

1500

2000

1.2

g

(5, 18)

(5)

pms

g

shock

h

m

10

DROP

Electrostatic Discharge

Human Body Model (HBM)

Charge Device Model (CDM)

Machine Model (MM)

11

12

13

V

2000

750

200

V

(5)

ESD

Storage Temperature Range

T

–40 to +125

2.5

°C

(5)

14

15

stg

JC

Thermal Resistance - Junction to Case

θ

°C/W

(14)

3.2

Operating Range

The operating ratings are the limits normally expected in the application and define the range of operation.

#

Characteristic

Symbol

Min

Typ

Max

Units

Supply Voltage

V

H

L

TYP

16

17

Standard Operating Voltage, 3.3 V

Standard Operating Voltage, 5.0 V

V

+3.135

—

+3.3

+5.0

+5.25

—

V

(15)

CC

Operating Ambient Temperature Range

Verified by 100 % Final Test

T

–40

T

H

+105

L

18

19

T

⎯

C

(1)

A

Power-on Ramp Rate (V

)

V

0.000033

3300

V/μs

(19)

CC

CC_r

MMA68xx

Sensors

NXP Semiconductors

5

3.3

Electrical Characteristics - Power Supply and I/O

V_L≤ (V_CC- V_SS) ≤ V_H, T_L≤ T_A≤ T_H, |ΔT_A| < 25 K/min unless otherwise specified

#

Characteristic

Symbol

Min

Typ

Max

Units

Supply Current

(4)

I

4.0

⎯

9.0

mA

(1)

20

DD

Power Supply Monitor Thresholds (See Figure 9)

21

22

23

24

25

V

Undervoltage (Falling)

(4)

V

2.74

2.10

2.65

2.20

2.65

⎯

3.02

2.25

2.85

2.35

2.85

V

(3, 6)

CC

CC_UV_f

V

REG

REG_UV_f

V

REG_OV_r

Overvoltage (Rising)

Undervoltage (Falling)

V

REGA

REGA_UV_f

Overvoltage (Rising)

V

REGA_OV_r

Power Supply Monitor Hysteresis

26

27

28

V

Undervoltage (Falling)

V

65

20

100

110

210

150

mV

(3)

CC

HYST

Undervoltage, V

Overvoltage

REG

REGA

REG

Undervoltage, V

Overvoltage

REGA

Power Supply RESET Thresholds

(See Figure 6, and Figure 9)

29

30

31

V

Undervoltage RESET (Falling)

Undervoltage RESET (Rising)

RESET Hysteresis

(4)

V

1.764

1.876

80

⎯

2.024

2.152

140

V

mV

(3, 6)

(3)

REG

REG_UVR_f

REG_UVR_r

V

HYST

Internally Regulated Voltages

32

33

V

(4)

V

2.42

2.50

2.58

V

(1, 3)

REG

V

REGA

External Filter Capacitor (C

Value

, C

)

REGA

REG

34

35

C

ESR

700

⎯

1000

⎯

1500

400

nF

mΩ

(19)

REG

ESR (including interconnect resistance)

Power Supply Coupling

36

37

50 kHz ≤ f ≤ 300 kHz

⎯

0.004

LSB/mv

(19)

n

4 MHz ≤ f ≤ 100 MHz

n

Output High Voltage (MISO, PCM_X, PCM_Y)

38 3.15 V ≤ (V - V ) ≤ 3.45 V (I

= –1 mA)

(4)

V

- 0.2

- 0.4

⎯

V

(2,3)

CC

SS

Load

OH_3

OH_5

CC

39 4.75 V ≤ (V - V ) ≤ 5.25 V (I

CC

SS

Output Low Voltage (MISO PCM_X, PCM_Y)

,

40 3.15 V ≤ (V - V ) ≤ 3.45 V (I

= 1 mA)

(4)

V

⎯

0.2

0.4

V

(2, 3)

CC

SS

Load

OL_3

OL_5

41 4.75 V ≤ (V - V ) ≤ 5.25 V (I

CC

SS

Open Drain Output High Voltage (ARM_X, ARM_Y)

42 3.15 V ≤ (V - V ) ≤ 3.45 V (I

= –1 mA)

(4)

V

- 0.2

- 0.4

⎯

V

(2, 3)

CC

SS

ARM

ODH_3

ODH_5

CC

43 4.75 V ≤ (V - V ) ≤ 5.25 V (I

CC

SS

Open Drain Output Pulldown Current (ARM_X, ARM_Y)

44 3.15 V ≤ (V - V ) ≤ 3.45 V (V

= 1.5 V)

(4)

I

50

⎯

100

μA

(2, 3)

(2,3)

CC

SS

ARM

ODPD_3

ODPD_5

45 4.75 V ≤ (V - V ) ≤ 5.25 V (V

CC

SS

Open Drain Output Low Voltage (ARM_X, ARM_Y)

46 3.15 V ≤ (V - V ) ≤ 3.45 V (I

= 1 mA)

(4)

V

⎯

0.2

0.4

V

(2, 3)

CC

SS

ARM

ODH_3

V

ODH_5

47 4.75 V ≤ (V - V ) ≤ 5.25 V (I

CC

SS

Open Drain Output Pullup Current (ARM_X, ARM_Y)

48 3.15 V ≤ (V - V ) ≤ 3.45 V (V

= 1.5 V)

(4)

I

–100

⎯

–50

μA

(2, 3)

CC

SS

ARM

ODPU_3

ODPU_5

49 4.75 V ≤ (V - V ) ≤ 5.25 V (V

CC

SS

Input High Voltage CS, SCLK, MOSI

Input Low Voltage CS, SCLK, MOSI

Input Voltage Hysteresis CS, SCLK

Input Current

(4)

V

2.0

⎯

1.0

V

(3, 6)

(19)

50

51

52

IH

V

IL

V

0.125

0.500

I_HYST

53

54

High (at V ) (SCLK, MOSI)

Low (at V ) (CS)

IL

(4)

I

–260

30

–50

50

–30

260

μA

(2, 3)

IH

IL

MMA68xx

Sensors

6

NXP Semiconductors

3.4

Electrical Characteristics - Sensor and Signal Chain

V_L≤ (V_CC- V_SS) ≤ V_H, T_L≤ T_A≤ T_H, |ΔT_A| < 25 K/min unless otherwise specified

Characteristic

#

Symbol

Min

Typ

Max

Units

X-axis Digital Sensitivity (SPI, 10-bit Output)

50 g (MMA6813)

55

(4)

SENS

⎯

9.766

8.192

4.883

4.096

⎯

LSB/g

(1, 9)

56

57

58

60 g (MMA6811, MMA6826)

100 g (MMA6825)

120 g (MMA6821, MMA6823)

Y-axis Digital Sensitivity (SPI, 10-bit Output)

25 g (MMA6811, MMA6821)

50 g (MMA6813QR)

59

60

61

62

(4)

SENS

⎯

20.479

9.766

8.192

4.883

⎯

LSB/g

(1, 9)

60 g (MMA6823, MMA6826)

100 g (MMA6825)

Sensitivity Error

63

64

65

T

= 25 °C

(4)

ΔSENS

–4

–5

⎯

+4

+5

%

(1)

(3)

A

–40 °C ≤ T ≤ 105 °C

–40 °C ≤ T ≤ 105 °C,V

A

≤ V - V ≤ V

CC SS L

A

CC_UV_f

Offset at 0 g (No Offset Cancellation)

10-bits, unsigned

66

67

68

69

(4)

OFFSET

452

–60

452

–60

512

0

512

0

572

+60

572

+60

LSB

(1)

(3)

10-bits, signed

10-bits, unsigned, V

10-bits, signed, V

≤ V - V ≤ V

L

CC

CC_UV_f

CC

SS

≤ V - V ≤ V

CC_UV_f

SS

L

Offset Monitor Thresholds

⎯

70

71

Positive Threshold (10-bits, unsigned)

Negative Threshold (10-bits, unsigned)

OFFTHR

612

412

⎯

LSB

(7)

POS

OFFTHR

NEG

Range of Output (SPI, 10-bits unsigned)

Normal

72

73

74

75

RANGE

FAULT

UNUSED

32

—

1

—

0

⎯

992

—

31

LSB

(7)

Fault Response Code

Unused Codes

993

1023

Range of Output (SPI, 10-bits, signed)

Normal

76

77

78

79

RANGE

FAULT

UNUSED

–480

—

–511

481

—

–512

—

480

—

–481

511

LSB

(7)

Fault Response Code

Unused Codes

—

Nonlinearity

(4)

NL

–1

—

1

% FSR

(3)

80

OUT

System Output Noise

81

82

RMS (10-bit, All Ranges, 400 Hz, 4-pole LPF)

Peak to Peak (10-bit, All Ranges, 400 Hz, 4-pole LPF)

n

—

0.5

1.0

LSB

(3)

RMS

P-P

Cross-axis Sensitivity

83

84

85

86

V

(4)

V

–4

—

+4

%

(3)

ZX

YX

ZY

XY

ZX

YX

ZY

XY

Self-test Output Change (Ref Section 4.6)

ΔST

MAX

MIN

NOM

87

88

89

90

91

STMAG_X, STMAG_Y = 0, T = 25 °C

ΔST

11.25

10.68

22.5

15

30

18.75

19.69

37.5

g

(1)

A

Low25

STMAG_X, STMAG_Y = 0, –40 °C ≤ T ≤ 105 °C

(4)

ΔST

A

Low

HI25

STMAG_X, STMAG_Y = 1, T = 25 °C

ΔST

A

STMAG_X, STMAG_Y = 1, –40 °C ≤ T ≤ 105 °C

STMAG_X, STMAG_Y = 0, –40 °C ≤ T ≤ 105 °C

21.37

39.38

A

HI

A

V

≤ V - V ≤ V

ΔST

10.68

21.37

15

30

19.69

39.38

g

(3)

CC_UV_f

CC

SS

L

Low

92

STMAG_X, STMAG_Y = 1, –40 °C ≤ T ≤ 105 °C

A

V

≤ V - V ≤ V

ΔST

HI

CC_UV_f

CC

SS

L

Self-test Cross Axis Output

93

94

Y-axis Output with X-axis Self-test

X-axis Output with Y-axis Self-test

ΔSTCrossAxis

–10

⎯

+10

LSB

(1)

Acceleration (without hitting internal g-cell stops)

95

X/Y-axis, Any Range Positive/Negative

g

500

560

600

g

(19)

g-cell_Clip

MMA68xx

Sensors

NXP Semiconductors

7

3.5

Dynamic Electrical Characteristics - Signal Chain

V_L≤ (V_CC- V_SS) ≤ V_H, T_L≤ T_A≤ T_H, |ΔT_A| < 25 K/min unless otherwise specified

#

Characteristic

Symbol

Min

Typ

Max

Units

DSP Sample Rate (LPF 0, 1, 2, 3, 4, 5)

DSP Sample Rate (LPF 8, 9, 10, 11, 12, 13)

Interpolation Sample Rate

t

⎯

64/f

128/f

t /2

S

⎯

s

(7)

96

97

98

S

OSC

t

S

OSC

t

INTERP

Datapath Latency (excluding g-cell and Low Pass Filter)

99

100

T

= 64/f

= 128/f

(4)

t

33.0

51.9

34.8

54.6

36.5

57.4

μs

(7, 16)

S

OSC

DataPath_8

t

OSC

DataPath_16

Low-Pass Filter (t = 8μs)

s

101

102

103

104

105

106

Cutoff frequency 0: 100 Hz, 4-pole

Cutoff frequency 1: 300 Hz, 4-pole

Cutoff frequency 2: 400 Hz, 4-pole

Cutoff frequency 3: 800 Hz, 4-pole

Cutoff frequency 4: 1000 Hz, 4-pole

Cutoff frequency 5: 400 Hz, 3-pole

(4)

f

95

100

300

400

800

1000

400

105

315

420

840

1050

420

Hz

(3, 7, 17)

(7, 17)

C0(LPF)

C1(LPF)

C2(LPF)

C3(LPF)

C4(LPF)

C5(LPF)

285

380

760

950

380

Low-Pass Filter (t = 16μs)

s

107

108

109

110

111

112

Cutoff frequency 8: 50 Hz, 4-pole

Cutoff frequency 9: 150 Hz, 4-pole

Cutoff frequency 10: 200 Hz, 4-pole

Cutoff frequency 11: 400 Hz, 4-pole

Cutoff frequency 12: 500 Hz, 4-pole

Cutoff frequency 13: 200 Hz, 3-pole

(4)

f

47.5

142.5

190

380

475

50

52.5

157.5

210

420

525

Hz

(7, 17)

C8(LPF)

C9(LPF)

150

200

400

500

200

f

C10(LPF)

C11(LPF)

C12(LPF)

C13(LPF)

f

190

210

Offset Cancellation (Normal Mode, 10-bit Output)

Offset Averaging Period

113

114

115

116

117

118

119

(4)

OFF

⎯

6.291456

0.2384

1049

⎯

s

(7)

AVEPER

Offset Slew Rate

Offset Update Rate

Offset Correction Value per Update Positive

Offset Correction Value per Update Negative

Offset Correction Threshold Positive

Offset Correction Threshold Negative

OFF

LSB/s

ms

LSB

SLEW

RATE

0.25

CORRP

CORRN

–0.25

0.125

THP

THN

OFF

Offset Monitor Bypass Time after Self-test Deactivation

Time Between Acceleration Data Requests (Same Axis)

t

⎯

320

⎯

t

(3, 7)

120

121

ST_OMB

S

t

15

⎯

μs

(3, 7, 20)

ACC_REQ

Arming Output Activation Time (ARM_X, ARM_Y, I

= 200 μA)

ARM

122

123

124

Moving Average and Count Arming Modes (2, 3, 4, 5)

Unfiltered Mode Activation Delay (Reference Figure 28)

Unfiltered Mode Arm Assertion Time (Reference Figure 28)

t

0

5.00

⎯

1.05

6.579

μs

(3, 12)

(3)

ARM

t

ARM_UF_DLY

t

ARM_UF_ASSERT

Sensing Element Natural Frequency (–40 °C ≤ T ≤ 105 °C)

f

10791

0.851

⎯

15879

2.29

Hz

(19)

125

126

A

gcell

Sensing Element Cutoff Frequency (–3 dB ref. to 0 Hz, –40 °C ≤ T

105 °C)

≤

A

f

kHz

gcell

Sensing Element Damping Ratio (–40 °C ≤ T ≤ 105 °C)

ζ

2.46

70

⎯

9.36

187

⎯

μs

(19)

127

128

129

130

A

gcell

Sensing Element Delay (@100 Hz, –40 °C ≤ T ≤ 105 °C)

f

A

gcell_delay

Package Resonance Frequency

Package Quality Factor

f

100

1

kHz

Package

q

5

Package

MMA68xx

Sensors

8

NXP Semiconductors

3.6

Dynamic Electrical Characteristics - Supply and SPI

V_L≤ (V_CC- V_SS) ≤ V_H, T_L≤ T_A≤ T_H, |ΔT_A| < 25 K/min unless otherwise specified

#

Characteristic

Symbol

Min

Typ

Max Units

Power-On Recovery Time(V = V

Power-On Recovery Time(Internal POR to first SPI access)

to first SPI access)

t

⎯

10

840

ms

μs

(3)

(3, 7)

131

132

CC

CCMIN

OP

t

OP

Internal Oscillator Frequency

Test Frequency - Divided from Internal Oscillator

(4)

f

7.6

0.95

8

1

8.4

1.05

MHz

(7)

(1)

133

134

OSC

f

OSCTST

Serial Interface Timing (See Figure 7, C

≤ 80 pF, R

≥ 10 kΩ)

MISO

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Clock (SCLK) period (10 % of V to 10 % of V

)

(4)

t

120

40

⎯

15

⎯

40

28

⎯

60

⎯

40

⎯

60

⎯

ns

(3)

(19)

(3)

(19)

CC

SCLK

Clock (SCLK) high time (90 % of V to 90 % of V

)

t

CC

)

SCLKH

Clock (SCLK) low time (10 % of V to 10 % of V

t

CC

SCLKL

Clock (SCLK) rise time (10 % of V to 90 % of V

)

t

CC

SCLKR

Clock (SCLK) fall time (90 % of V to 10 % of V

)

t

⎯

CC

SCLKF

CS asserted to SCLK high (CS = 10 % of V to SCLK = 10 % of V

)

(4)

t

60

⎯

20

10

0

⎯

60

⎯

CC

LEAD

CS asserted to MISO valid (CS = 10 % of V to MISO = 10/90 % of V

)

t

CC

ACCESS

Data setup time (MOSI = 10/90 % of V to SCLK = 10 % of V

)

t

CC

SETUP

MOSI Data hold time (SCLK = 90 % of V to MOSI = 10/90 % of V

)

t

CC

HOLD_IN

MISO Data hold time (SCLK = 90 % of V to MISO = 10/90 % of V

CC

)

t

CC

HOLD_OUT

SCLK low to data valid (SCLK = 10 % of V to MISO = 10/90 % of V

)

t

CC

VALID

SCLK low to CS high (SCLK = 10 % of V to CS = 90 % of V

)

t

CC

LAG

CS high to MISO disable (CS = 90 % of V to MISO = Hi Z)

CC

t

DISABLE

t

CS high to CS low (CS = 90 % of V to CS = 90 % of V

)

526

60

CC

CSN

SCLK low to CS low (SCLK = 10 % of V to CS = 90 % of V

)

t

CC

CLKCS

CS high to SCLK high (CS = 90 % of V to SCLK = 90 % of V

)

CC

CSCLK

1.

Parameters tested 100 % at final test.

Parameters tested 100 % at wafer probe.

Parameters verified by characterization.

Indicates a critical characteristic.

2.

3.

4.

5.

6.

7.

Verified by qualification testing.

Parameters verified by pass/fail testing in production.

Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is deter-

mined by internal system clock frequency.

8.

9.

N/A.

Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response.

10. Low-pass filter cutoff frequencies shown are –3dB referenced to 0 Hz response.

11. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.

12. Time from falling edge of CS to ARM_X, ARM_Y output valid.

13. N/A.

14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.

15. Device characterized at all values of V and V . Production test is conducted at all typical voltages (V ) unless otherwise noted.

TYP

L

H

16. Data path Latency is the signal latency from g-cell to SPI output disregarding filter group delays.

17. Filter characteristics are specified independently, and do not include g-cell frequency response.

18. Electrostatic Deflection Test completed during wafer probe.

19. Verified by simulation.

20. Acceleration Data Request timing constraint only applies for proper operation of the Arming Function.

MMA68xx

Sensors

NXP Semiconductors

9

V_{CC_UV_r}

V_{CC_UV_f}

V_CC

V_{REGA_UV_r}

V_{REGA_UV_f}

V_REGA

Note: V

& V

rise and fall slopes will be dependent

REG

REGA

on output capacitance and load current

V_{REG_UVR_r}

V_{REG_UVR_f}

V_REG

POR

DEVRES Flag Cleared by User

DEVRES

Time

Figure 6. Powerup Timing

CS

t

SCLKF

SCLKR

t

CSN

t

LEAD

t

SCLKH

SCLK

t

CSCLK

SCLK

t

CLKCS

SCLKL

t

LAG

t

ACCESS

t

HOLD_OUT

VALID

t

DISABLE

MISO

MOSI

t

HOLD_IN

t

SETUP

Figure 7. Serial Interface Timing

MMA68xx

Sensors

10

NXP Semiconductors

4

Functional Description

4.1

Customer Accessible Data Array

A customer accessible data array allows for each device to be customized. The array consists of an OTP factory

programmable block and read/write registers for device programmability and status. The OTP and writable register blocks

incorporate independent CRC circuitry for fault detection (reference Section 4.2). The writable register block includes a locking

mechanism to prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed

trim values. The customer accessible data is shown in Table 3.

Table 3. Customer Accessible Data

Location

Register

Bit Function

Type

Addr

$00

$01

$02

$03

$04

$05

$06

$07

$08

$09

$0A

$0B

$0C

$0D

$0E

$0F

$10

$11

$12

$13

$14

$15

$16

$17

$1C

$1D

7

6

SN[6]

SN[14]

SN[22]

SN[30]

Reserved

0

5

SN[5]

SN[13]

SN[21]

SN[29]

Reserved

0

4

3

SN[3]

SN[11]

SN[19]

SN[27]

Reserved

0

2

SN[2]

SN[10]

SN[18]

SN[26]

Reserved

0

1

SN[1]

SN[9]

SN[17]

SN[25]

Reserved

0

SN[0]

SN[8]

SN[16]

SN[24]

Reserved

1

SN0

SN1

SN[7]

SN[4]

SN[12]

SN[20]

SN[28]

SN[15]

SN2

SN[23]

SN3

SN[31]

Reserved

FCTCFG_X

FCTCFG_Y

PN

Reserved

STMAG_X

STMAG_Y

PN[7]

Reserved

F

Reserved

0

1

PN[6]

PN[5]

PN[4]

PN[3]

PN[2]

PN[1]

PN[0]

Invalid Address: ”Invalid Register Request”

DEVCTL

DEVCFG

RES_1

Reserved

ST_X

RES_0

Reserved

AT_XP[6]

AT_YP[6]

AT_XN[6]

AT_YN[6]

IDE

Reserved

ENDINIT

Reserved

APS_X[1]

APS_Y[1]

AT_XP[5]

AT_YP[5]

AT_XN[5]

AT_YN[5]

SDOV

Reserved

SD

Reserved

OFMON

Reserved

A_CFG[2]

LPF_X[2]

LPF_Y[2]

AWS_XN[0]

AWS_YN[0]

AT_XP[2]

AT_YP[2]

AT_XN[2]

AT_YN[2]

OFF_Y

Reserved

A_CFG[1]

LPF_X[1]

LPF_Y[1]

AWS_XP[1]

AWS_YP[1]

AT_XP[1]

AT_YP[1]

AT_XN[1]

AT_YN[1]

OFF_X

Reserved

A_CFG[0]

LPF_X[0]

LPF_Y[0]

AWS_XP[0]

AWS_YP[0]

AT_XP[0]

AT_YP[0]

AT_XN[0]

AT_YN[0]

DEVRES

COUNT[0]

DEVCFG_X

DEVCFG_Y

ARMCFGX

ARMCFGY

ARMT_XP

ARMT_YP

ARMT_XN

ARMT_YN

DEVSTAT

COUNT

Reserved

APS_X[0]

APS_Y[0]

AT_XP[4]

AT_YP[4]

AT_XN[4]

AT_YN[4]

DEVINIT

COUNT[4]

LPF_X[3]

LPF_Y[3]

AWS_XN[1]

AWS_YN[1]

AT_XP[3]

AT_YP[3]

AT_XN[3]

AT_YN[3]

MISOERR

COUNT[3]

ST_Y

Reserved

AT_XP[7]

AT_YP[7]

AT_XN[7]

AT_YN[7]

UNUSED

COUNT[7]

R/W

COUNT[6]

COUNT[5]

COUNT[2]

COUNT[1]

OFFCORR_X

OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]

R

OFF_CORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0]

Reserved

Type Codes:

F: Factory programmed OTP location

R/W: Read/Write register

R: Read-only register

N/A: Not applicable

MMA68xx

Sensors

NXP Semiconductors

11

4.1.1 Device Serial Number Registers

A unique serial number is programmed into the serial number registers of each MMA68xx device during manufacturing. The

serial number is composed of the following information:

Bit Range

S12 to S0

S31 to S13

Content

Serial Number

Lot Number

Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are

sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on

lot size and quantities, all possible lot numbers and serial numbers may not be assigned.

The serial number registers are included in the OTP shadow register array CRC verification. Reference Section 4.2.1 for

details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device

operation or performance, and are only used for traceability purposes.

4.1.2 Reserved Registers

These reserved registers are read-only and have no impact on device operation or performance.

Table 4. Reserved Registers

Location

Bit

Address

Register

Reserved

7

6

5

4

3

2

1

0

$04

$05

Reserved

4.1.3 Factory Configuration Registers

The factory configuration registers are one time programmable, read only registers which contain customer specific device

configuration information that is programmed by NXP.

Table 5. Factory Configuration Registers

Location

Address Register

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

1

$06

$07

FCTCFG_X STMAG_X

FCTCFG_Y STMAG_Y

4.1.3.1

Self-test Magnitude Selection Bits (STMAG_Y, STMAG_X)

The self-test magnitude selection bits indicate if the nominal self-test deflection value is set to the low or high value as shown

in the table below. The Self-test Magnitude is selected independently for each axis.

STMAG_X /

STMAG_Y

Full-Scale

Acceleration Range

Nominal Self-test Deflection Value

(Reference Section 3.4)

0

1

ℜ ≤ 60 g

> 60 g

ΔST_Low

ΔST_HI

MMA68xx

Sensors

12

NXP Semiconductors

4.1.4 Part Number Register (PN)

The part number register is a one time programmable, read only register which contains two digits of the device part number

to identify the axis and range information. The contents of this register have no impact on device operation or performance.

Table 6. Part Number Register

Location

Bit

Address

Register

7

6

5

4

3

2

1

0

PN[0]

$08

PN

PN[7]

PN[6]

PN[5]

PN[4]

PN[3]

PN[2]

PN[1]

PN Register Value

Decimal

X-axis Range

Reference Section 3.4

Y-axis Range

Reference Section 3.4

HEX

$01

$02

$03

$04

$05

$06

$07

$08

$09

$0A

$0B

$0C

$0D

$0E

$0F

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

$1C

1

20

35

2

3

20

50

4

20

75

5

25

120

20

6

35

7

35

8

35

50

9

35

75

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

35

100

25

60

50

35

50

75

50

100

20

75

35

75

50

75

100

25

120

100

120

100

60

35

60

75

100

60

120

60

120

MMA68xx

Sensors

NXP Semiconductors

13

4.1.5 Device Control Register (DEVCTL)

The device control register is a read-write register which contains device control operations that can be applied during both

initialization and normal operation.

Table 7. Device Control Register

Location

Bit

Address

Register

7

RES_1

0

6

RES_0

0

5

Reserved

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

Reserved

0

$0A

DEVCTL

Reset Value

4.1.5.1

Reset Control (RES_1, RES_0)

A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset.

To reset the internal digital circuitry, the following register write operations must be performed in the order shown below. The

register write operations must be consecutive SPI commands in the order shown or the device will not be reset.

Register Write to DEVCTL

SPI Register Write 1

SPI Register Write 2

SPI Register Write 3

RES_1

RES_0

Effect

No Effect

0

1

0

1

No Effect

Device RESET

The response to the Register Write returns ’0’ for RES_1 and RES_0. A Register Read of RES_1 and RES_0 returns ’0’ and

terminates the reset sequence.

4.1.5.2

Reserved Bits (DEVCTL[5:0])

Bits 5 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ’0’ for normal device

operation and performance.

4.1.6 Device Configuration Register (DEVCFG)

The device configuration register is a read/write register which contains data for general device configuration. The register can

be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC

check. Refer to Section 4.2.2 for details.

Table 8. Device Configuration Register

Location

Bit

Address

Register

7

Reserved

0

6

Reserved

0

5

ENDINIT

0

4

SD

0

3

OFMON

0

2

A_CFG[2]

0

1

A_CFG[1]

0

A_CFG[0]

0

$0B

DEVCFG

Reset Value

4.1.6.1

Reserved Bits (Reserved)

Bits 6 and 7 of the DEVCFG register are reserved. A write to the reserved bits must always be logic ’0’ for normal device

operation and performance.

4.1.6.2

End of Initialization Bit (ENDINIT)

The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests,

and that MMA68xx will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except

for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check

(reference Section 4.2.2) is only enabled when the ENDINIT bit is set.

MMA68xx

Sensors

14

NXP Semiconductors

4.1.6.3

SD Bit

The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ’1’, unsigned results are transmitted,

with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zero-

g level represented by a nominal value of 0.

SD

1

Operating Mode

Unsigned Data Output

Signed Data Output

0

4.1.6.4

OFMON Bit

The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ’1’, the offset monitor is

enabled. Refer to Section 4.8.5 for more information. If the OFMON bit is cleared, the offset monitor is disabled.

OFMON

Operating Mode

1

0

Offset Monitor Circuit Enabled

Offset Monitor Circuit Disabled

4.1.6.5

ARM Configuration Bits (A_CFG[2:0])

The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM_X/PCM_X, ARM_Y/PCM_Y pins.

Table 9. Arming Output Configuration

A_CFG[2]

A_CFG[1]

A_CFG[0]

Operating Mode

Arm Output Disabled

PCM Output

Output Type

Reference

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hi Impedance

Digital Output

Section 4.8.9.1

Section 4.8.9.2

Section 4.8.9.3

Moving Average Mode

Count Mode

Active High with Pulldown Current

Active Low with Pullup Current

Active High with Pulldown Current

Active Low with Pullup Current

Active High with Pulldown Current

Active Low with Pullup Current

Count Mode

Unfiltered Mode

4.1.7 Axis Configuration Registers (DEVCFG_X, DEVCFG_Y)

The Axis configuration registers are read/write registers which contain axis specific configuration information. These registers

can be written during initialization, but are locked once the ENDINIT bit is set. These registers are included in the writable register

CRC check. Refer to Section 4.2.2 for details.

Table 10. Axis Configuration Registers

Location

Bit

Address

Register

DEVCFG_X

DEVCFG_Y

7

6

5

4

3

2

1

0

$0C

$0D

ST_X

ST_Y

0

Reserved

0

Reserved

0

Reserved

0

LPF_X[3]

LPF_Y[3]

0

LPF_X[2]

LPF_Y[2]

0

LPF_X[1]

LPF_Y[1]

0

LPF_X[0]

LPF_Y[0]

0

Reset Value

MMA68xx

Sensors

NXP Semiconductors

15

4.1.7.1

Self-test Control (ST_X, ST_Y)

The ST_X and ST_Y bits enable and disable the self-test circuitry for their respective axes. Self-test circuitry is enabled if a

logic ’1’ is written to ST_X, or ST_Y and the ENDINIT bit has not been set. Enabling the self-test circuitry results in a positive

acceleration value on the enabled axis. Self-test deflection values are specified in Section 3.4. ST_X and ST_Y are always

cleared following internal reset.

When the self-test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status

bits in the Acceleration Data Request Response will indicate ”Self-test Active”. Reference Section 4.8.4 and Section 5.2 for

details. When the self-test circuitry is disabled by clearing the ST_X or ST_Y bit, the offset monitor remains disabled until the time

t_{ST_OMB}, specified in Section 3.5, expires. However, the status bits in the Acceleration Data Request Response will immediately

indicate that self-test has been deactivated.

4.1.7.2

Reserved Bits (Reserved)

Bits 6 through 4 of the DEVCFG_X and DEVCFG_Y registers are reserved. A write to the reserved bits must always be logic

’0’ for normal device operation and performance.

4.1.7.3

Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0])

The Low Pass Filter selection bits independently select a low-pass filter for each axis as shown in Table 11. Refer to Section

4.8.3 for details regarding filter configurations.

Table 11. Low Pass Filter Selection Bits

LPF_X[3] /

LPF_Y[3]

LPF_X[2] /

LPF_Y[2]

LPF_X[1] /

LPF_Y[1]

LPF_X[0] /

LPF_Y[0]

Low Pass Filter Selected Nominal Sample Rate (μs)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100 Hz, 4 pole

300 Hz, 4 Pole

400 Hz, 4 Pole

800 Hz, 4 Pole

1000 Hz, 4 pole

400 Hz, 3 Pole

Reserved

8

Reserved

16

Reserved

50 Hz, 4 pole

150 Hz, 4 Pole

200 Hz, 4 Pole

400 Hz, 4 Pole

500 Hz, 4 Pole

200 Hz, 3 Pole

Reserved

16

Reserved

Note: Filter characteristics do not include g-cell frequency response.

4.1.8 Arming Configuration Registers (ARMCFGX, ARMCFGY)

The arming configuration registers contain configuration information for the arming function. The values in these registers are

only relevant if the arming function is operating in moving average mode, or count mode.

These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 4.1.6.2. These

registers are included in the writable register CRC check. Refer to Section 4.2.2 for details.

Table 12. Arming Configuration Register

Location

Bit

Address

Register

ARMCFGX

ARMCFGY

7

6

5

4

3

2

1

0

$0E

$0F

Reserved

0

Reserved

0

APS_X[1]

APS_Y[1]

0

APS_X[0] AWS_XN[1] AWS_XN[0] AWS_XP[1] AWS_XP[0]

APS_Y[0] AWS_YN[1] AWS_YN[0] AWS_YP[1] AWS_YP[0]

Reset Value

0

1

MMA68xx

Sensors

16

NXP Semiconductors

4.1.8.1

Reserved Bits (Reserved)

Bits 7 through 6 of the ARMCFGX and ARMCFGY registers are reserved. A write to the reserved bits must always be logic ’0’

for normal device operation and performance.

4.1.8.2

Arming Pulse Stretch (APS_X[1:0], APS_Y[1:0])

The APS_X[1:0] and APS_Y[1:0] bits set the programmable pulse stretch time for the arming outputs. Refer to Section 4.8.9

for more details regarding the arming function.

Table 13. Arming Pulse Stretch Definitions

Pulse Stretch Time⁽¹⁾(Typical Oscillator)

0 mS

APS_X[1], APS_Y[1]

APS_X[0], APS_Y[0]

0

1

0

1

0

1

16.256 ms to 16.384 ms

65.408 ms to 65.536 ms

261.888 ms to 262.016 ms

1.Pulse stretch times are derived from the internal oscillator, so the tolerance on this oscillator applies.

4.1.8.3

The AWS_Xx[1:0] and AWS_Yx[1:0] bits have a different function depending on the state of the A_CFG bits in the DEVCFG

register.

Arming Window Size (AWS_Xx[1:0], AWS_Yx[1:0])

If the arming function is set to moving average mode, the AWS bits set the number of acceleration samples used for the arming

function moving average. The number of samples is set independently for each axis and polarity. If the arming function is set to

count mode, the AWS bits set the sample count limit for the arming function. The sample count limit is set independently for each

axis.

Refer to Section 4.8.9 for more details regarding the arming function.

Table 14. X-axis Positive Arming Window Size Definitions (Moving Average Mode)

AWS_XP[1]

AWS_XP[0]

X-axis Positive Window Size

0

1

0

1

0

1

2

4

8

16

Table 15. X-axis Negative Arming Window Size Definitions (Moving Average Mode)

AWS_XN[1]

AWS_XN[0]

X-axis Negative Window Size

0

1

0

1

0

1

2

4

8

16

Table 16. Y-axis Positive Arming Window Size Definitions (Moving Average Mode)

AWS_YP[1]

AWS_YP[0]

Y-axis Positive Window Size

0

1

0

1

0

1

2

4

8

16

MMA68xx

Sensors

NXP Semiconductors

17

Table 17. Y-axis Negative Arming Window Size Definitions (Moving Average Mode)

AWS_YN[1]

AWS_YN[0]

Y-axis Negative Window Size

0

1

0

1

0

1

2

4

8

16

Table 18. Arming Count Limit Definitions (Count Mode)

AWS_XN[1]

Don’t Care

AWS_XN[0]

Don’t Care

AWS_XP[1]

AWS_XP[0]

X-axis Sample Count Limit

0

1

0

1

0

1

3

7

15

Table 19. Arming Count Limit Definitions (Count Mode)

AWS_YN[1]

Don’t Care

AWS_YN[0]

Don’t Care

AWS_YP[1]

AWS_YP[0]

Y-axis Sample Count Limit

0

1

0

1

0

1

3

7

15

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4.1.9 Arming Threshold Registers (ARMT_XP, ARMT_XN, ARMT_YP, ARMT_YN)

These registers contain the X-axis and Y-axis positive and negative thresholds to be used by the arming function. Refer to

Section 4.8.9 for more details regarding the arming function.

These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 4.1.6.2. These

registers are included in the writable register CRC check. Refer to Section 4.2.2 for details.

Table 20. Arming Threshold Registers

Location

Address

Bit

Register

ARMT_XP

ARMT_YP

ARMT_XN

ARMT_YN

7

6

5

4

3

2

1

0

$10

$11

$12

$13

AT_XP[7]

AT_YP[7]

AT_XN[7]

AT_YN[7]

0

AT_XP[6]

AT_YP[6]

AT_XN[6]

AT_YN[6]

0

AT_XP[5]

AT_YP[5]

AT_XN[5]

AT_YN[5]

0

AT_XP[4]

AT_YP[4]

AT_XN[4]

AT_YN[4]

0

AT_XP[3]

AT_YP[3]

AT_XN[3]

AT_YN[3]

0

AT_XP[2]

AT_YP[2]

AT_XN[2]

AT_YN[2]

0

AT_XP[1]

AT_YP[1]

AT_XN[1]

AT_YN[1]

0

AT_XP[0]

AT_YP[0]

AT_XN[0]

AT_YN[0]

0

Reset Value

The values programmed into the threshold registers are the threshold values used for the arming function as described in

Section 4.8.9. The threshold registers hold independent unsigned 8-bit values for each axis and polarity. Each threshold

increment is equivalent to one output LSB. Table 21 shows examples of some threshold register values and the corresponding

threshold.

Table 21. Threshold Register Value Examples

Axis Type

Programmed Thresholds

Range

Sensitivity

Positive

Negative

Positive Threshold

Negative Threshold

(g)

(g/LSB)

(Decimal)

(g)

20

0.04097

0.1024

100

255

50

0

4.10

10.45

5.12

–2.05

Disabled

–2.05

20

50

20

10

120

0.24414

20

4.88

–2.44

If either the positive or negative threshold for one axis is programmed to $00, comparisons are disabled for only that polarity.

The arming function still operates for the opposite polarity. If both the positive and negative arming thresholds for one axis are

programmed to $00, the Arming function for the associated axis is disabled, and the associated output pin is disabled, regardless

of the value of the A_CFG bits in the DEVCFG register.

4.1.10 Device Status Register (DEVSTAT)

The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions.

Reference Section 5.5 for details on the MMA68xx response for each status condition.

Table 22. Device Status Register

Location

Bit

Address

Register

7

6

5

4

3

2

1

0

$14

DEVSTAT

UNUSED

IDE

SDOV

DEVINIT

MISOERR

OFF_Y

OFF_X

DEVRES

4.1.10.1

Unused Bit (UNUSED)

The unused bit has no impact on operation or performance. When read this bit may be ’1’ or ’0’.

4.1.10.2 Internal Data Error Flag (IDE)

The internal data error flag is set if a customer or OTP register data CRC fault or other internal fault is detected as defined in

Section 5.5.5. The internal data error flag is cleared by a read of the DEVSTAT register. If the error is associated with a CRC fault

in the writable register array, the fault will be re-asserted and will require a device reset to clear. If the error is associated with the

data stored in the fuse array, the fault will be re-asserted even after a device reset.

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4.1.10.3

Sigma Delta Modulator Over Range Flag (SDOV)

The sigma delta modulator over range flag is set if the sigma delta modulator for either axis becomes saturated. The SDOV

flag is cleared by a read of the DEVSTAT register.

4.1.10.4

Device Initialization Flag (DEVINIT)

The device initialization flag is set during the interval between negation of internal reset and completion of internal device

initialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register.

4.1.10.5

SPI MISO Data Mismatch Error Flag (MISOERR)

The MISO data mismatch flag is set when a MISO Data mismatch fault occurs as specified in Section 5.5.2. The MISOERR

flag is cleared by a read of the DEVSTAT register.

4.1.10.6

Offset Monitor Over Range Flags (OFF_X, OFFSET_Y)

The offset monitor over range flags are set if the acceleration signal of the associated axis reaches the specified offset limit.

The offset monitor over range flags are cleared by a read of the DEVSTAT register.

4.1.10.7

Device Reset Flag (DEVRES)

The device reset flag is set during device initialization following a device reset. The device reset flag is cleared by a read of

the DEVSTAT register.

4.1.11 Count Register (COUNT)

The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the

primary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases

by one count every 128 μs and the counter rolls over every 32.768 ms.

Table 23. Count Register

Location

Bit

Address

Register

7

COUNT[7]

0

6

COUNT[6]

0

5

COUNT[5]

0

4

COUNT[4]

0

3

COUNT[3]

0

2

COUNT[2]

0

1

COUNT[1]

0

COUNT[0]

0

$15

COUNT

Reset Value

4.1.12 Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)

The offset correction value registers are read-only registers which contain the most recent offset correction increment /

decrement value from the offset cancellation circuit. The values stored in these registers indicate the amount of offset correction

being applied to the SPI output data. The values have a resolution of 1 LSB.

Table 24. Offset Correction Value Register

Location

Bit

Address

$16

Register

7

6

5

4

3

2

1

0

OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]

OFFCORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0]

$17

Reset Value

0

4.1.13 Reserved Registers (Reserved)

Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and

performance.

Table 25. Reserved Registers

Location

Bit

Address

Register

Reserved

7

6

5

4

3

2

1

0

$1C

$1D

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reset Value

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4.2

Customer Accessible Data Array CRC Verification

4.2.1 OTP Shadow Register Array CRC Verification

The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of

g(x) = X ³+ X + 1, with a seed value = ’111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.

4.2.2 Writable Register CRC Verification

The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when

the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X³+ X + 1, with a

seed value = ’111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.

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4.3

Voltage Regulators

Separate internal voltage regulators supply the analog and digital circuitry. External filter capacitors are required, as shown in

Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external

supply and all internal regulated voltages are within predetermined limits. A reference generator provides a stable voltage which

is used by the ΣΔ converters.

V_CC

V_REGA= 2.50 V

VOLTAGE

REGULATOR

C_REGA

BANDGAP

REFERENCE

PRIMARY

OSCILLATOR

BIAS

GENERATOR

TRIM

ΣΔ

REFERENCE

GENERATOR

CONVERTER

V_REF= 1.250 V

DIGITAL

LOGIC

DSP

OTP

ARRAY

TRACKING

REGULATOR

C_REG

Tracks V_REGA

V

_REG= 2.50 V

Figure 8. Power Supply

V

CCUV

V

CC

V

REGOV

REG

V

REGUV

REGAUV

REGAOV

GROUND LOSS

MONITOR

V

MONITOR

BANDGAP

BGMON

SET DEVRES Flag

V

REGA

V

REG

POR

V

REFOV

REF

PORREF

Note: No external access to reference voltage

Limits verified by characterization only

V

REFUV

Figure 9. Voltage Monitoring

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4.3.1 C_REGFailure Detection

The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the V_REGcapacitor

becomes open, the digital supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal

sample time. This failure will result in one of the following:

1. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as

defined in Table 30.

2. MMA68xx will be held in RESET and be non-responsive to SPI requests.

4.3.2 C_REGAFailure Detection

The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the V_REGAcapacitor

becomes open, the analog supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal

sample time. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as

defined in Table 30.

Note: This feature is only supported with a V_CCsupply voltage in the range of 4.75 V to 5.25 V.

4.3.3 V_SSand V_SSAGround Loss Monitor

MMA68xx detects the loss of ground connection to either V_SSor V_SSA. A loss of ground connection to V_SSwill result in a V_REG

overvoltage failure. A loss of ground connection to V_SSAwill result in a V_REGundervoltage failure. Both failures result in a device

reset.

4.3.4 SPI Initiated Reset

In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the

RES_1 and RES_0 bits in the DEVCTL register. Reference Section 4.1.5.1. for details regarding the SPI initiated reset.

4.4

Internal Oscillator

MMA68xx includes a factory trimmed oscillator as specified in Section 3.6.

4.4.1 Oscillator Monitor

The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running

8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the

COUNT register increases by one count every 128 μs, and the register rolls over every 32.768 ms. The SPI master can

periodically read the COUNT register, and verify the difference between subsequent register reads against the system time base.

1. The SPI access rates and deviations must be taken into account for this oscillator verification.

4.5

Transducer

The MMA68xx transducer is an overdamped mass-spring-damper system described by the following transfer function:

2

ω

n

--------------------------------------------------------

s

H(s) =

2

n

+ 2 ⋅ ξ ⋅ ω ⋅ s + ω

n

where:

ζ = Damping Ratio

ω_n= Natural Frequency = 2∗Π∗f_n

Reference Section 3.4 for transducer parameters.

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4.6

Self-test Interface

The self-test interface applies a voltage to the g-cell, causing deflection of the proof mass. The self-test interface is controlled

through SPI write operations to the DEVCFG_X and DEVCFG_Y registers described in Section 4.1.7. The ENDINIT bit in the

DEVCFG register must also be low to enable self-test. A diagram of the self-test interface is shown in Figure 10.

ST_Y

ENDINIT

Y-AXIS

g-CELL

SELF-TEST

VOLTAGE

GENERATOR

X-AXIS

g-CELL

ENDINIT

ST_X

Figure 10. Self-test Interface

The raw self-test deflection can be verified against raw self-test limits using the following equations:

ΔST

= FLOOR ⋅ (ΔST

) ⋅ [SENS ⋅ (1 – ΔSENS)]

MIN

MINLIMIT

MAXLIMIT

ΔST

= CEIL ⋅ (ΔST

) ⋅ [SENS ⋅ (1 + ΔSENS)]

MAX

where:

ΔST_MIN

ΔST_MAX

SENS

The minimum self-test deflection over temperature as specified in Section 3.4.

The maximum self-test deflection over temperature as specified in Section 3.4.

The sensitivity of the device

ΔSENS

The sensitivity tolerance

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4.7

ΣΔ Converters

Two sigma delta converters provide the interface between the g-cell and the DSP. The output of each ΣΔ converter is a data

stream at a nominal frequency of 1 MHz.

g-CELL

FIRST

SECOND

1-BIT

V_X

INTEGRATOR

INTEGRATOR QUANTIZER

α₁=

α₂

C_INT1

z^-1

C_TOP

ΣΔ_OUT

1 - z^-1

C_BOT

ADC

ΔC = C_TOP- C_BOT

β₁

β₂

V = ℜ 2 ℜ× V_REF

DAC

V = ΔC x V_X/ C_INT1

Figure 11. ΣΔ Converter Block Diagram

4.8

Digital Signal Processing Block

A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating

the signal processing flow is shown in Figure 12.

To ARM_x

I

Arm/PCM Output

Section 3.8.9

Section 3.8.10

A

E

G

H

C

D

F

B

To SPI

Offset Cancellation

Section 3.8.4

ΣΔ_OUT

SINC Filter

Section 3.8.2

Compensation

Section 3.8.6

Interpolation

Section 3.8.7

Low Pass Filter

Section 3.8.3

Offset Cancellation

Output Scaling

Raw Output

Scaling

Figure 12. Signal Chain Diagram

Table 26. MMA68xx Signal Chain Characteristics

Sample

Time (μs)

Data Width Over Effective

Rounding

Resolution Bits

Typical Block

Latency

Description

Reference

Bits

A

B

C

D

E

SD

1

—

4

3.2 μs

11.2 μs

Section 4.7

Section 4.8.2

Section 4.8.3

Section 4.8.6

Section 4.8.7

SINC Filter

8

14

20

13

10

Low Pass Filter

Compensation

Interpolation

8/16

4/8

6

Reference Section 4.8.3

7.875 μs

4

t_s/ 2

Offset

Cancellation

F

256

20

6

10

4

N/A

Section 4.8.4

G, H

I

SPI Output

4/8

—

10

9

—

t_s/ 2

—

PCM Output

Section 4.8.10

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4.8.1 DSP Clock

The DSP is clocked at 8 MHz, with an effective 6MHz operating frequency. The clock to the DSP is disabled for 1 clock prior

to each edge of the ΣΔ modulator clock to minimize noise during data conversion. The bit streams from the two ΣΔ converters

are processed through independent data paths within the DSP.

8 MHz OSC

6 MHz Digital

1MHz Modulator

Figure 13. Clock Generation

4.8.2 Decimation Sinc Filter

The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc

filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected.

3

–16

1 – z

------------------------------

H(z) =

–1

16(1 – z

)

Figure 14. Sinc Filter Response, t_S= 8 μs

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4.8.3 Low Pass Filter

Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter.

–1

–2

–3

–4

n

+ (n ⋅ z ) + (n ⋅ z ) + (n ⋅ z ) + (n ⋅ z

)

0

1

2

3

4

----------------------------------------------------------------------------------------------------------------------------------------

H(z) =

–1

–2

–4

d

+ (d ⋅ z ) + (d ⋅ z ) + (d ⋅ z ) + (d ⋅ z

)

0

1

2

3

4

MMA68xx provides the option for one of twelve low-pass filters. The filter is selected independently for each axis with the

LPF_X[3:0] and LPF_Y[3:0] bits in the DEVCFG_X and DEVCFG_Y registers. The filter selection options are listed in

Section 4.1.7.3, Table 11. Response parameters for the low-pass filter are specified in Section 3.4. Filter characteristics are

illustrated in Figures 15, 16, 17, 18, 19 and 20.

Table 27. Low Pass Filter Coefficients

Description

Sample Time (μs)

Filter Coefficients

2.08729034056887e–10

Group Delay

n₀

n₁

n₂

n₃

n₄

n₀

n₁

n₂

n₃

n₄

n₀

n₁

n₂

n₃

n₄

n₀

n₁

n₂

n₃

n₄

n₀

n₁

n₂

n₃

n₄

n₀

n₁

n₂

n₃

n₄

d₀

d₁

d₂

d₃

d₄

d₀

d₁

d₂

d₃

d₄

d₀

d₁

d₂

d₃

d₄

d₀

d₁

d₂

d₃

d₄

d₀

d₁

d₂

d₃

d₄

d₀

d₁

d₂

d₃

d₄

1

50 Hz LPF

16

8.349134489240434e–10

1.25237777794924e–09

8.349103355433541e–10

2.087307211059861e–10

1.639127731323242e–08

6.556510925292969e–08

9.834768482194806e–08

6.556510372902331e–08

1.639128257923422e–08

5.124509334564209e–08

2.049803733825684e–07

3.074705789151505e–07

2.049803958150164e–07

5.124510693742625e–08

2.720393240451813e–06

8.161179721355438e–06

8.161180123840722e–06

2.720393634345496e–06

0

–3.976249694824219

5.929003009577855

–3.929255528257727

0.9765022168437554

1

26816/f_osc

100 Hz LPF

150 Hz LPF

300 Hz LPF

200 Hz LPF

400 Hz LPF

8

16

8

–3.928921222686768

5.789028996785419

–3.791257019240902

0.9311495074496179

1

9024/f_osc

6784/f_osc

5632/f_osc

3392/f_osc

2688/f_osc

16

8

–3.905343055725098

5.72004239520561

–3.723967810019985

0.9092692903507213

1

200 Hz LPF

3-pole

16

8

–2.931681632995605

2.865296718275204

–0.9335933215174919

0

400 Hz LPF

3-pole

7.822513580322266e–07

3.129005432128906e–06

4.693508163398543e–06

3.129005428784364e–06

7.822513604678875e–07

1.865386962890625e–06

7.4615478515625e–06

1.119232176112846e–05

7.4615478515625e–06

1.865386966264658e–06

1

400 Hz LPF

800 Hz LPF

500 Hz LPF

1000 Hz LPF

16

8

–3.811614513397217

5.450666051045118

–3.465805771100349

0.8267667478030489

1

16

8

–3.765105724334717

5.319861050818872

–3.34309015036024

0.7883646729233078

Note: Low Pass Filter Figures do not include g-cell frequency response.

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Figure 15. Low-Pass Filter Characteristics: f_C= 100 Hz, Poles = 4, t_S= 8 μs

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Figure 16. Low-Pass Filter Characteristics: f_C= 300 Hz, Poles = 4, t_S= 8 μs

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Figure 17. Low-Pass Filter Characteristics: f_C= 400 Hz, Poles = 4, t_S= 8 μs

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Figure 18. Low-Pass Filter Characteristics: f_C= 400 Hz, Poles = 3, t_S= 8 μs

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Figure 19. Low-Pass Filter Characteristics: f_C= 800 Hz, Poles = 4, t_S= 8 μs

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Figure 20. Low-Pass Filter Characteristics: f_C= 1000 Hz, Poles = 4, t_S= 8 μs

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4.8.4 Offset Cancellation

MMA68xx provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the SPI command

(reference Section 5.1). A block diagram of the offset cancellation is shown in Figure 21, and response parameters are specified

in Section 3.4 and in Table 28.

OFFTHR_NEG

Accumulator

up to 4096 samples

Downsampled to 256μs

LPF_OUT

OFF_ERR

Shift

T1

T2

T3

T4

T5

T6

OFFTHR_POS

OFF_THN

INC

Offset Inc/Dec

OFF_CORRP

OC_OUT

OFF_CORR_VALUE

OFF_CORRN

DEC

OFF_THP

Correction

for Start Phase

Figure 21. Offset Cancellation Block Diagram

In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data

downsampled to 256 μs. The running average is compared against positive and negative thresholds to determine the offset

correction value that will be applied to the acceleration data.

During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals.

Reference Table 28 for offset cancellation timing information during startup and normal operation.

Table 28. Offset Cancellation Timing Specifications

Start Time of

Phase

(from POR)

Typical

Time in Phase

(ms)

OFF_CORR_VALUE Averaging Maximum Averaging Filter

# of Samples in

Phase

Samples

Averaged

Phase

Update Rate

(ms)

Period

(ms)

Slew Rate –3dB Frequency

(LSB/s)

(Hz)

Start 1

t_OP

524.288

—

2048

—

48

2.048

16.38

131.1

1049

12.288

98.304

122.1

36.05

Start 2 t_OP+ 524.288

Start 3 t_OP+ 1048.576

Normal t_OP+ 1572.864

384

15.26

4.506

3072

24576

786.432

6291.456

1.907

0.5632

0.07040

0.2384

When the self-test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset

correction value is constant. Once the self-test circuitry is disabled, the offset cancellation block remains suspended for the time

t_{ST_OMB}to allow the acceleration output to return to its nominal offset.

4.8.5 Offset Monitor

MMA68xx provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the

DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low

threshold. If the offset correction value exceeds either the OFFTHR_POS, or OFFTHR_NEGthreshold, an Offset Over Range

condition is indicated.

The offset correction value update rate is listed in Table 28. Because the offset monitor uses this value, the offset monitor will

also update at this rate. The time to indicate an Offset Over Range is dependent upon the input signal.

The offset monitor status remains frozen during self-test, because the offset monitor is based on the offset cancellation circuit,

which is also suspended during self-test. The offset monitor is disabled for 2.1 seconds following reset regardless of the state of

the OFMON bit.

4.8.6 Signal Compensation

MMA68xx includes internal OTP and signal processing to compensate for sensitivity error and offset error. This compensation

is necessary to achieve the specified parameters in Section 3.4.

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4.8.7 Data Interpolation

MMA68xx includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal

processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between

sample times. This operation is illustrated in Figure 22.

S_n-3

S_n-2

S_n-1

S_n

Internal Sample Rate

t

t_s

S_{n – 1}+ S_n

------------------------

2

S_{n – 3}+ S_{n – 2}

-------------------------------

2

S_{n – 2}+ S_{n – 1}

-------------------------------

2

S_n-3

S_n-2

S_n-1

Output Sample Rate

t

Response to SPI acceleration request occurring in this window receives interpolated sample

Response to SPI acceleration request occurring in this window receives true sample.

Figure 22. Data Interpolation Timing

The effect of this interpolation at the system level is a 50 % reduction in sample jitter. Figure 23 shows the resulting output

data for an input signal.

80

75

Internally

Sampled Values

70

65

60

Fixed Latency:

Earliest Transmission

Point of Interpolated

Values

t

_S/ 2

55

50

45

40

Earliest Transmission

Point of Internally

Sampled Values

Window of

Transmission for

Interpolated Values

Window of

Transmission for

Sampled Values

= Signal Jitter =

(Maximum:

t

_S/ 2)

(Maximum: t_S/ 2)

0

5

10

15

20

Time

25

30

35

40

Input Signal

Internally Sampled Signal

Interpolated Samples

Figure 23. Data Interpolation Example

MMA68xx

Sensors

NXP Semiconductors

35

4.8.8 Acceleration Data Timing

The MMA68xx SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases.

Reference Section 5 for more details regarding the SPI protocol. In order to provide the most recent acceleration data for each

request, MMA68xx latches the associated data for an acceleration request at the falling edge of CS for the acceleration response

message (the subsequent SPI transfer). The most recent sample available from the DSP (including interpolation), is latched,

providing a maximum latency of 1* t_Srelative to the falling edge of CS.

SCLK

CS

MOSI

Request Y-axis

Request X-axis

Request Y-axis

Request X-axis

X-axis Response

Y-axis Response

X-axis Response

MISO

X-axis Data Latched

Y-axis Data Latched

Y-axis Arm Function updated if applicable

X-axis Arm Function updated if applicable

MMA68xx

36

Sensors

NXP Semiconductors

4.8.9 Arming Function

MMA68xx provides the option for an arming function with 3 modes of operation. The operation of the arming function is

selected by the state of the A_CFG bits in the DEVCFG register.

Reference Section 5.5 for the operation of the Arming function with exception conditions. Error conditions do not impact prior

arming function responses. If an error occurs after an arming activation, the corresponding pulse stretch for the existing arming

condition will continue. However, new acceleration reads will not update the arming function regardless of the acceleration value.

4.8.9.1

Arming Function: Moving Average Mode

In moving average mode, the arming function runs a moving average on the offset cancelled output of each acceleration axis.

The number of samples used for the moving average (k) is programmable via the AWS_Xx[1:0] and ARM_Yx[1:0] bits in the

ARMCFGX and ARMCFGY registers. Reference Section 4.1.8 for register details.

ARM_MA_n= (OC_n+ OC_n-1+ ... + OC_n+1-k)/k

Where n is the current sample.

The sample rate for each axis is determined by the SPI acceleration data sample rate. At the falling edge of CS for an

acceleration data SPI response, the moving average for the associated axis is updated with a new sample. Reference Figure 26.

The SPI acceleration data sample rate must meet the minimum time between requests (t_{ACC_REQ_x}) specified in Section 3.5.

The moving average output is compared against positive and negative 8-bit thresholds that are individually programmed for

each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 4.1.9 for register details. If the moving average equals

or exceeds either threshold, an arming condition is indicated, the ARM_X or ARM_Y output is asserted for the associated axis,

and the pulse stretch counter is set as described in Section 4.8.9.4.

The ARM_X or ARM_Y output is de-asserted only when the pulse stretch counter expires. Figure 26 shows the arming output

operation for different SPI conditions.

ARMT_xP[7:0]

Positive

AWS_xP[1:0]

Offset Cancellation

OffCanc_ARM_x[10:0]

Moving Average

Pulse Stretch

ARM_x

Gating

I/O

Negative

Moving Average

AWS_xN[1:0]

ARMT_xN[7:0]

APS_x[1:0]

Figure 24. Arming Function Block Diagram - Moving Average Mode

MMA68xx

Sensors

NXP Semiconductors

37

4.8.9.2

Arming Function: Count Mode

In count mode, the arming function compares each input sample against positive and negative thresholds that are individually

programmed for each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 4.1.9 for register details. If the sample

equals or exceeds either threshold, a sample counter is incremented. If the sample does not exceed either threshold, the sample

counter is reset to zero.

The sample rate for each axis is determined by the SPI acceleration data sample rate. At the falling edge of CS for an

acceleration data SPI response, a new sample for the associated axis is compared against the thresholds. Reference Figure 26.

The SPI acceleration data sample rate must meet the minimum time between requests (t_{ACC_REQ_x}) specified in Section 3.5.

A sample count limit is programmable via the AWS_Xx[1:0] and AWS_Yx[1:0] bits in the ARMCFGX and ARMCFGY registers.

If the sample count reaches the programmable sample count limit, an arming condition is indicated, the ARM_X or ARM_Y output

is asserted for the associated axis, and the pulse stretch counter is set as described in Section 4.8.9.4.

The ARM_X or ARM_Y output is de-asserted only when the pulse stretch counter expires. Figure 26 shows the arming output

operation for different SPI conditions.

AWS_xP[1:0]

ARMT_xP[7:0]

Offset Cancellation

1-4 Sample

Pulse Stretch

ARM_x

Gating

I/O

Counter

OffCanc_ARM_x[10:0]

ARMT_xN[7:0]

APS_x[1:0]

Figure 25. Arming Function Block Diagram - Count Mode

SCLK

CS

MOSI

Request Y-axis

Request X-axis

Request Y-axis

Request X-axis

Y-axis Response

X-axis Response

Y-axis Response

X-axis Response

MISO

ARM_X

ARM_Y

Y-axis Arm Condition

Not Present

X-axis Arm Condition

Present

Y-axis Arm Condition

Present

X-axis Arm Condition

Not Present

X-axis Data Latched for

Arm Function and SPI

X-axis Data Latched for

Arm Function and SPI

Y-axis Data Latched for

Arm Function and SPI

t_ARM

Y-axis Pulse Stretch

X-axis Pulse Stretch

Figure 26. X and Y Axis Arming Conditions, Moving Average and Count Mode

MMA68xx

38

Sensors

NXP Semiconductors

4.8.9.3

Arming Function: Unfiltered Mode

On the falling edge of CS for an acceleration response, the most recent available DSP sample for the requested axis is

compared against positive and negative thresholds that are individually programmed for each axis via the ARMT_Xx and

ARMT_Yx registers. Reference Section 4.1.9 for register details. If the sample equals or exceeds either threshold, an arming

condition is indicated.

Once an arming condition is indicated for the X-axis, the ARM_X output is asserted when CS is asserted and the MISO data

includes an acceleration response for that axis.

Once an arming condition is indicated for the Y-axis, the ARM_Y output is asserted when CS is asserted and the MISO data

includes an acceleration response for that axis.

The pulse stretch function is not applied in Unfiltered mode.

Figure 27 contains a block diagram of the Arming Function operation in Unfiltered Mode. Figure 28 shows the Arming output

operation under the different SPI request conditions.

ACFG[2]

ACFG[1]

CS

ARM_x

I/O

AXIS Select

ARMING FUNCTION

Interpolated Sample Rate

Figure 27. Arming Function Block Diagram - Unfiltered Mode

SCLK

CS

MOSI

Request Y-axis

Request X-axis

Request Y-axis

Request X-axis

Y-axis Response

X-axis Response

Y-axis Response

X-axis Response

MISO

ARM_X

ARM_Y

Y-axis Arm Condition

Not Present

X-axis Arm Condition

Present

Y-axis Arm Condition

Present

X-axis Arm Condition

Not Present

X-axis Data Latched for

Arm Function and SPI

X-axis Data Latched for

Arm Function and SPI

Y-axis Data Latched for

Arm Function and SPI

t_{ARM_UF_DLY}

t_{ARM_UF_ASSERT}

Figure 28. X and Y Axis Arming Conditions, Unfiltered Mode

MMA68xx

Sensors

NXP Semiconductors

39

4.8.9.4

Arming Pulse Stretch Function

A pulse stretch function can be applied to the arming outputs in moving average mode, or count mode.

If the pulse stretch function is not used (APS_X[1:0] = ’00’ or APS_Y[1:0] = ’00’), the arming output is asserted if and only if

an arming condition exists for the associated axis after the most recent evaluated sample. The arming output is de-asserted if

and only if an arming condition does not exist for the associated axis after the most recent evaluated sample. If the pulse stretch

function is used, (APS_X[1:0] not equal ’00’ or APS_Y[1:0] not equal ’00’), the arming output is controlled only by the value of

the pulse stretch timer value. If the pulse stretch timer value is non-zero, the arming output is asserted. If the pulse stretch timer

is zero, the arming output is de-asserted. The pulse stretch counter continuously decrements until it reaches zero. The pulse

stretch counter is reset to the programmed pulse stretch value if and only if an arming condition exists for the associated axis

after the most recent evaluated sample. Reference Figure 26.

The desired pulse stretch time is individually programmable for each axis via the APS_X[1:0] and APS_Y[1:0] bits in the

ARMCFG register.

Exception conditions listed in Section 5.5 do not impact prior arming function responses. If an exception occurs after an arming

activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will

not reset the pulse stretch counter regardless of the acceleration value.

4.8.9.5

Arming Pin Output Structure

The arming output pin structure can be set to active high, or active low with the A_CFG bits in the DEVCFG register as

described in Section 4.1.6.5. The active high and active low pin output structures are shown in Figure 29.

Open Drain, Active High

Open Drain, Active Low

V_CC

Arm Function

Gating

ARM

Arm Function

Gating

Figure 29. Arming Function - Pin Output Structure

4.8.10 PCM Output Function

MMA68xx provides the option for a PCM output function. The PCM output is enabled by setting the A_CFG bits in the DEVCFG

register to the appropriate state as described in Section 4.1.6.5. When the PCM function is enabled, the upper 9 bits of the

10-bit, offset cancelled, output scaled acceleration values are used to generate 8 MHz Pulse Code Modulated signals

proportional to the respective acceleration onto the PCM_X and PCM_Y pins. A block diagram of the PCM output is shown in

Figure 30.

MMA68xx

Sensors

40

NXP Semiconductors

Exception conditions affect the PCM output as listed in Section 5.5.

9

Output Scaling

OC[9:1]

A

CARRY

ARM/PCM

9 Bit ADDER

SUM

9

Sample updated every 8μS

D

Q

B

D

Q

D

Q

D

Q

FF

D

Q

D

Q

D

Q

CLK

Q

f_CLK= 8 MHz

FF

D

Q

FF

D

Q

9

FF

Q

FF

Q

FF

Q

Figure 30. PCM Output Function Block Diagram

MMA68xx

41

Sensors

NXP Semiconductors

4.9

Serial Peripheral Interface

MMA68xx includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data.

Reference Section 5 for details regarding the SPI protocol and available commands.

To maximize independence between the X and Y channels, MMA68xx includes two interface blocks, one for each axis. The

X-axis interface block responds only to X-axis acceleration requests, or even addressed register commands. The Y-axis interface

block responds only to Y-axis acceleration requests, or odd addressed register commands. To the SPI master, MMA68xx

operates as a single device. The internal independent blocks are transparent.

Each SPI block has an independent shift register. Once a message is received (rising edge of CS), the contents of the two

shift registers are compared. If the contents do not match, the Y-axis SPI block will not respond, and the X-axis SPI block will

respond with a SPI Error as shown in Table 30. If the contents match, each SPI block decodes the message, and the appropriate

block enables MISO for a response during the next SPI message.

Figure 31 shows an internal diagram of the MMA68xx SPI.

X SPI

Registers

If Bit 13 == ’1’

& Bit 14 == ’0’

If Bit 13 = ’0’

& A0 == ’0’

SPI Master

Even Address Regs

X SPI Shift Register

X-axis Raw Data

X-axis OC Data

CS

CS_M

CS

SCLK

MOSI

MISO

SCLKM

MOSIM

MISOM

SCLK

MOSI

MISO

SPI Mismatch Error (SPI Error)

I/O

Y SPI Shift Register

Odd Address Regs

Y-axis Raw Data

Y-axis OC Data

Y SPI

If Bit 13 == ’1’

If Bit 13 = ’0’

& Bit 14 == ’1’

& A0 == ’1’

Figure 31. SPI Diagram

MMA68xx

42

Sensors

NXP Semiconductors

4.10 Device Initialization

Following powerup, undervoltage reset, or a SPI reset command sequence, MMA68xx proceeds through an internal

initialization process as shown below. Figure 32 also shows the MMA68xx performance for an example external system level

initialization procedure.

Internal Initialization

OTP Copy to

Offset Cancellation

Startup Phase 1

Offset Cancellation

Startup Phase 2

Offset Cancellation

Startup Phase 3

Offset Cancellation

Normal Mode

Mirror Registers

t_{OC_PHASE1}

t_{OC_PHASE2}

t_{OC_PHASE3}

External Initialization

Read DEVSTAT

to clear flags

Re-read DEVSTAT

to verify Status Dly

Re-Initialize

Verify X-axis

Self-test &

Verify X-axis

Offset & ARM_X

Deasserted

Verify X-axis

Offset & ARM_X

Deasserted

R/W Registers

(if needed)

Normal

Mode

Verify X-axis

Dly

Offset

ARM_X Asserted

Dly

Delay

Verify Y-axis

Offset & ARM_Y

Deasserted

Verify Y-axis

Self-test &

ARM_Y Asserted

Verify Y-axis

Offset & ARM_Y

Deasserted

Initialize R/W

and

Set ENDINIT

Registers to

Desired State

t_STRISE

t_OP

X_ST

Deassertion

Assertion

t_{ST_OMB}

Dependent on Pulse

Dependent on

Arming Mode

Stretch and/or Arming Mode

X_ARM

Y_ST

t_STFALL

Deassertion

Assertion

Dependent on Pulse

Dependent on

Arming Mode

Stretch and/or Arming Mode

Y_ARM

Deactivate

Activate

Ready for SPI

Internal

Activate

X-axis

Y-axis

Deactivate

Y-axis

POR

Self -test

Self-test

Command

Offset Error

ENDINIT Clear

Corrected to ’0’ Self-test

Self-test

Notes:1) X-axis and Y-axis Self-test can be enabled and evaluated simultaneously to reduce test time.

For failure mode coverage of the arming pins and of potential common axis failures, NXP recommends independent self-test activation.

2) t_STRISEand t_STFALLare dependent on the selected LPF group delay.

Figure 32. Initialization Process

MMA68xx

Sensors

NXP Semiconductors

43

4.11 Overload Response

4.11.1 Overload Performance

MMA68xx is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the

sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon

the overload frequency and amplitude. The MMA68xx g-cell is overdamped, providing the optimal design for overload

performance. However, the performance of the device during an overload condition is affected by many other parameters,

including:

•

g-cell damping

• Non-linearity

• Clipping limits

• Symmetry

Figure 33 shows the g-cell, ADC and output clipping of MMA68xx over frequency. The relevant parameters are specified in

Section 3.1, and Section 3.6.

g-cell

Rolloff

Acceleration (g)

Region Clipped

by Output

LPF

Rolloff

Determined by g-cell

roll-off and ADC clipping

g

g-cell_Clip

Determined by g-cell

roll-off and full scale range

g

ADC_Clip

g

Range_Norm

Region of Interest

Region of No Signal Distortion Beyond

Specification

f

5kHz

10kHz

LPF

g-Cell

Frequency (kHz)

Figure 33. Output Clipping Vs. Frequency

4.11.2 Sigma Delta Over Range Response

Over range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits

of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 3.1 (G_{ADC_CLIP}). The DSP operates

predictably under all cases of over range, although the signal may include residual high frequency components for some time

after returning to the normal range of operation due to non-linear effects of the sensor.

MMA68xx

Sensors

44

NXP Semiconductors

5

SPI Communications

Communication with MMA68xx is completed through synchronous serial transfers via SPI. MMA68xx is a slave device

configured for CPOL = 0, CPHA = 0, MSB first. SPI transfers are completed through a sequence of two phases. During the first

phase, the type of transfer and associated control information is transmitted from the SPI master to MMA68xx. Data from

MMA68xx is transmitted during the second phase. Any activity on MOSI or SCLK is ignored when CS is negated. Consequently,

intermediate transfers involving other SPI devices may occur between phase one and phase two. Reference Figure 34.

SCLK

CS

MOSI

Phase One: Command

Phase One: Response -Previous Command

Phase Two: Response

MISO

SCLK

CS

MOSI

T1P1

T2P1

T1P2

T3P1

T2P2

T3P2

MISO

Figure 34. SPI Transfer Detail

MMA68xx

Sensors

NXP Semiconductors

45

5.1

SPI Command Format

Commands are transferred from the SPI master to MMA68xx. Valid commands fall into two categories: register operations,

and acceleration data requests.

Table 29. SPI Command Message Summary

MSB

14

LSB

0

15

0

13

A

12

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

AR

M

AX

OC

SD

P

Command Type

Reference

AX= Axis Selection

0

1

X-axis Acceleration Data

Y-axis Acceleration Data

A = Acceleration Data Request

0

1

Register Operation

Acceleration Data

Request

OC = Offset Cancelled Data Request

0

1

Offset Cancelled Data Request

Raw Acceleration Data Request

SD = Signed Data Confirmation

Signed Data Enabled

0

1

Unsigned Data Enabled

ARM = ARM Function Status Confirmation

Disabled / PCM Output Enabled

Arming Function Enabled

0

1

P = Odd Parity

AR

0

AX

A

OC

0

SD

P

Accel Data

M

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X-axis OC, Signed Data, Disabled/PCM

X-axis OC, Signed Data, ARM Enabled

X-axis OC, Unsigned Data, Disabled/PCM

X-axis OC, Unsigned Data, ARM Enabled

X-axis Raw, Signed Data, Disabled/PCM

X-axis Raw, Signed Data, ARM Enabled

X-axis Raw, Unsigned Data, Disabled/

PCM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X-axis Raw, Unsigned Data, ARM Enabled

Y-axis OC, Signed Data, Disabled/PCM

Y-axis OC, Signed Data, ARM Enabled

Y-axis OC, Unsigned Data, Disabled/PCM

Y-axis OC, Unsigned Data, ARM Enabled

Y-axis Raw, Signed Data, Disabled/PCM

Y-axis Raw, Signed Data, ARM Enabled

Y-axis Raw, Unsigned Data, Disabled/

PCM

0

1

0

1

0

1

0

Y-axis Raw, Unsigned Data, ARM Enabled

P

AX

0

A

0

D12 D11 D10

D9

A1

D8

A0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Command Type

Register Read

Reference

Section 5.4

A4

A3

A2

Register Address

A3 A2 A1

Register Address

A4

A0

D7

D6

D5

D4

D3

D2

D1

D0

P

1

0

Register Write

Section 5.4

Data to be Written to Register

P = Odd Parity

MMA68xx

46

Sensors

NXP Semiconductors

5.2

SPI Response Format

Table 30. SPI Response Message Summary

MSB

LSB

0

15

14

13

12

P

11

10

Response to Valid Acceleration Request

S0 D9 D8 D7 D6 D5

9

8

7

6

5

4

3

2

1

CMD

A

AX

Data Type

Reference

OC

0

AX

S1

D4

D3

D2

D1

D0

OC = Offset Cancelled Data Requested

0

1

Transferred Accel Data is Offset Cancelled Data

Transferred Accel Data is Raw Data

AX = Axis Requested

0

1

X-axis Acceleration Data Response

Y-axis Acceleration Data Response

P = Odd Parity

S[1:0] = Device Status

0

1

In Initialization (ENDINIT = ’0’)

Normal Data Request

ST Active, ΣΔ/Offset Over range

1

0

Present

1

S1

0

1

S0

1

Internal Error Present / SPI Error

CMD

A

1

AX

0

OC

0

AX

0

P

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Data Type

Accel

Reference

Section 5.3

X- Axis Acceleration Data

X-axis Self-test Active Acceleration Data

0

1

0

Accel

Valid Accel

Data

Request

0

X- Axis Acceleration Data, Initialization in Process (ENDINIT=’0’)

Y-axis Acceleration Data

Accel

1

0

1

Accel

1

0

Y-axis Self-test Active Acceleration Data

Accel

1

0

Y- Axis Acceleration Data, Initialization in Process (ENDINIT=’0’)

Accel

MSB

LSB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Response to Valid Register Access

CMD

A

0

AX

1

Data Type

Reference

D15 D14

AX

1

P

D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Register

Write

0

1

0

Register Write Section 5.4.1

New Contents of Register

D7

D6

D5

D4

D3

D2

D1

D0

Register

Read

Register

Section 5.4.2

Read

0

1

0

P

1

0

8

Contents of Register

MSB

14

LSB

0

15

13

12

P

11

10

9

7

6

5

4

3

2

1

Error Responses

D11 D10 D9 D8 D7

CMD

A

x

AX

x

Data Type

Reference

Section 5.3

D15 D14

AX

D6

D5

D4

D3

D2

D1

D0

Invalid Accel

Request

Register Setting

Mismatch

IDE Bit Set

Internal

Error

Present

(Excl. Self-test),

DEVINIT Bit Set

DEVRES Bit Set

x

Section 5.5.5

Section 5.5.2

MISO Error on

Previous Msg

SD = 1: 00 0000 0000

SD = 0: 10 0000 0000

MISO Error

0

P

1

MOSI Parity

CMD Bit 15 = 1

SPI Timing Err

SPI Mismatch

Err

Section 5.5.1

SPI Error

x

SPI Protocol

Errs

Invalid Reg

Addr,

Write while

ENDINIT set,

Write to R/O

Reg

Invalid

Register

Request

0

x

0

1

0

1

0

Section 5.4

IDE Bit set

due to Self- Section 5.5.5

test Error

Self-test

Error

SD = 1: 00 0000 0000

SD = 0: 10 0000 0000

P

MMA68xx

Sensors

NXP Semiconductors

47

5.3

Acceleration Data Transfers

Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ’1’. The

Axis Selection bit (AX) and the Offset Cancellation Selection bit (OC) of the command message select the type of acceleration

data requested, as shown in Table 31.

Table 31. Acceleration Data Request

Acceleration Data Request Command Information

Data Type

Axis Selection Bit (AX)

Offset Cancellation Select (OC)

0

1

0

1

0

1

X-axis Offset Cancelled Data

X-axis Raw Data

Y-axis Offset Cancelled Data

Y-axis Raw Data

To verify that MMA68xx is configured as expected, each acceleration data request includes the configuration information that

impacts the output data. The requested configuration is compared against the data programmed in the writable register array.

Details are shown in Table 32.

Table 32. Acceleration Data Request Configuration Information

Programmable Option

Signed or Unsigned Data

Command Message Bit

Writable Register Information

DEVCFG[4] (SD)

SD

Arming Function or PCM Output

ARM

DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1])

If the data listed in Table 32 does not does not match, an Acceleration Data Request Mismatch failure is detected and no

acceleration data is transmitted. Reference Section 5.5.3.1.

Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the

acceleration data request command must be an odd number.

Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met:

• The DEVINIT bit in the DEVSTAT register is not set

• The DEVRES bit in the DEVSTAT register is not set

• The IDE bit in the DEVSTAT register is not set (Reference Section 5.5.5)

• No SPI Error is detected (Reference Section 5.5.1)

• No MISO Error is detected (Reference Section 5.5.2)

• No Acceleration Data Request Mismatch failure is detected (Reference Section 5.5.3.1)

• No Self-test Error is present (reference Section 5.5.5.2)

If the above conditions are met, MMA68xx responds with a “valid acceleration data request” response as shown in Table 30.

Otherwise, MMA68xx responds as specified in Section 5.5.

5.4

Register Access Operations

Two types of register access operations are supported; register write, and register read. Register access operations are

initiated when the acceleration bit (A) of the command message is set to a logic ’0’. The operation to be performed is indicated

by the Access Selection bit (AX) of the command message.

Access Selection Bit (AX)

Operation

Register Read

Register Write

0

1

Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the Register Access

operation must be an odd number.

MMA68xx

Sensors

48

NXP Semiconductors

5.4.1 Register Write Request

During a register write request, bits 12 through 8 contain a 5-bit address, and bits 7 through 0 contain the data value to be

written. Writable registers are defined in Table 3.

The response to a register write operation is shown in Table 30. The response is transmitted on the next SPI message if and

only if all of the following conditions are met:

• No SPI Error is detected (Reference Section 5.5.1)

• No MISO Error is detected (Reference Section 5.5.2)

• The ENDINIT bit is cleared (Reference Section 4.1.6.2)

– This applies to all registers with the exception of the DEVCTL register

• No Invalid Register Request is detected (Reference Section 5.5.3.2)

If the above conditions are met, MMA68xx responds to the register write request as shown in Table 30. Otherwise, MMA68xx

Responds as specified in Section 5.5.

Register write operations do not occur internally until the transfer during which they are requested has been completed. In the

event that a SPI Error is detected during a register write transfer, the write operation is not completed.

5.4.2 Register Read Request

During a register read request, bits 12 through 8 contain the 5-bit address for the register to be read. Bits 7 through 0 must be

logic ’0’. Readable registers are defined in Table 3.

The response to a register read operation is shown in Table 30. The response is transmitted on the next SPI message if and

only if all of the following conditions are met:

• No SPI Error is detected (Reference Section 5.5.1)

• No MISO Error is detected (Reference Section 5.5.2)

• No Invalid Register Request is detected (Reference Section 5.5.3.2)

If the above conditions are met, MMA68xx responds to the register read request as shown in Table 30. Otherwise, MMA68xx

responds as specified in Section 5.5.

5.5

Exception Handling

The following sections describe the conditions for each detectable exception, and the MMA68xx response for each exception.

In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 33.

Table 33. SPI Error Response Priority

Effect on Data

Error Priority

Exception

SPI Data

Arming Output

No Update

No Effect

PCM Output

No Effect

Disabled

No Effect

1

2

3

4

5

6

7

8

9

SPI Error

SPI MISO Error

Invalid Request

DEVINIT Bit Set

DEVRES Error

CRC Error

Error Response

No Effect

Self-test Error

Offset Monitor Over Range

ΣΔ Over Range

No Effect

MMA68xx

49

Sensors

NXP Semiconductors

5.5.1 SPI Error

The following SPI conditions result in a SPI error:

• SCLK is high when CS is asserted the number of SCLK rising edges detected while CS is asserted is not equal

to 16

• SCLK is high when CS is negated

• Command message parity error (MOSI)

• Bit 15 of Acceleration Data Request is not equal to ‘0’

• Bits 3 through 11 of an Acceleration Request are not equal to ‘0’

• Bits 0 through 7 of a Register Read Request are not equal to ‘0’

MMA68xx responds to a SPI error with a “SPI Error” response as shown in Table 30. This applies to both acceleration data

request SPI errors, and Register Access SPI errors.

The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.

5.5.2 SPI Data Output Verification Error

MMA68xx includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted

on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch

Fault is detected and the MISOERR flag in the DEVSTAT register is set.

If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI

acceleration request message is ignored and MMA68xx responds with a “MISO Error” response during the subsequent SPI

message (reference Table 30). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not

affected by the MISO mismatch failure.

If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register

write is completed as requested, but MMA68xx responds with a “MISO Error” response as shown in Table 30, during the

subsequent SPI message.

If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register

read is ignored and MMA68xx responds with a “MISO Error” response as shown in Table 30, during the subsequent SPI

message. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared.

In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the

DEVSTAT register is completed.

SPI DATA OUT SHIFT REGISTER

DATA OUT BUFFER

MISO

D

Q

D

Q

R

MISO ERR

D

Q

SCLK

R

Figure 35. SPI Data Output Verification

5.5.3 Invalid Requests

5.5.3.1

Acceleration Data Request Mismatch Failure

MMA68xx detects an “Acceleration Data Request Mismatch” error if the SPI “Acceleration Data Request” Command data listed

in Table 32 does not match the internal register settings. MMA68xx responds to an “Acceleration Data Request Mismatch” error

with an “Invalid Accel Request” response as specified in Table 30 on the subsequent SPI message only. No internal fault is

recorded. The arming function will not be updated if an “Acceleration Data Request Mismatch” Error is detected. The PCM output

is not affected by the “Acceleration Data Request Mismatch” error.

Register operations will be executed as specified in Section 5.4.

MMA68xx

Sensors

50

NXP Semiconductors

5.5.3.2

Invalid Register Request

The following conditions result in an “Invalid Register Request” error:

• An attempt is made to write to an un-writable register (Writable registers are defined in Section 4.1, Table 3).

• An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set

– This applies to all registers with the exception of the DEVCTL register

• An attempt is made to read an un-readable register (Readable registers are defined in Section 4.1, Table 3).

MMA68xx responds to an “Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30.

5.5.4 Device Reset Indications

If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 4.1.10, MMA68xx will respond to

acceleration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The

DEVINIT bit is cleared automatically when device initialization is complete (Reference t_OPin Section 3.6). The DEVRES bit is

cleared on a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if

the DEVINIT or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.

5.5.5 Internal Error

The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:

• OTP CRC Failure

• Writable Register CRC Failure

• Self-test Error

• Invalid internal logic states

5.5.5.1

CRC Error

If the IDE bit is set in the DEVSTAT register due to an OTP Shadow Register or Writable Register CRC failure as described in

Section 4.2, MMA68xx will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is

cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a CRC

Error is detected. The PCM output is not affected by the CRC error.

If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only

be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register.

If the CRC error is in the OTP shadow register array, the error cannot be cleared.

Register operations will be executed as specified in Section 5.4.

5.5.5.2

Self-test Error

If the IDE bit is set in the DEVSTAT register due to a Self-test activation failure, MMA68xx will respond to acceleration data

requests with a “Self-test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be

updated on Acceleration Data Request commands if a Self-test Error is detected. The PCM output is not affected by the Self -

test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal

failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set.

Register operations will be executed as specified in Section 5.4.

5.5.6 Offset Monitor Over Range

If an offset monitor over range is present as described in Section 4.8.5, MMA68xx will respond to an acceleration request for

the corresponding axis with a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The

arming function will be updated on Acceleration Data Request commands even if an Offset Monitor Over Range is detected. Once

the over range condition is removed, MMA68xx will respond to acceleration requests with a “Valid Acceleration Data Request”

response with the Status bits (S[1:0]) set to ’10’ on the next SPI transfer, and a “Valid Acceleration Data Request” response with

normal status on subsequent SPI transfers. The OFFSET_X or OFFSET_Y bit in the DEVSTAT register will remain set until a

read of the DEVSTAT register occurs.

The PCM output is not affected by the offset monitor over range condition.

Register operations will be executed as specified in Section 5.4.

MMA68xx

Sensors

NXP Semiconductors

51

5.5.7 ΣΔ Over Range

If a ΣΔ Over Range failure is present as described in Section 4.11.2, MMA68xx will respond to acceleration data requests with

a "Valid Acceleration Data Request" response, but the Status bits (S[1:0]) will be set to ’10’. The arming function will be updated

on Acceleration Data Request commands even if a ΣΔ Over Range is detected. Once the over range condition is removed,

MMA68xx will respond to acceleration requests with a "Valid Acceleration Data Request" response with the Status bits (S[1:0])

set to ’10’ on the next SPI transfer, and a "Valid Acceleration Data Request" response with normal status on subsequent SPI

transfers. The SDOV bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs.

The PCM output is not affected by the ΣΔ over range condition.

Register operations will be executed as specified in Section 5.4.

5.6

Initialization SPI Response

The first data transmitted by MMA68xx following reset is the SPI Error response shown in Table 30. This ensures that an

unexpected reset will always be detectable. MMA68xx will respond to all acceleration data requests with the "Invalid Acceleration

Data Request" response until the DEVRES bit in the DEVSTAT register is cleared via a read of the DEVSTAT register. The arming

function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared.

5.7

Acceleration Data Representation

Acceleration values are determined from the 10-bit digital output (DV) using the following equations:

Acceleration= Sensitivity

× DV

For Signed Data

LSB

For Unsigned Data

× (DV – 512)

LSB

The linear range of digital values for signed data is –480 to +480, and for unsigned data is 32 to 992. Resulting ranges and

some nominal acceleration values are shown in the following table.

Table 34. Nominal Acceleration Data Values

Nominal Acceleration

Unsigned

Digital Value

Signed

Digital Value

Trimmed for

Maximum Sensitivity

(g)

Trimmed for

Maximum Range

(g)

993 to 1023

992

481 to 511

480

Unused

19.666

19.625

117.19

116.94

991

479

•

514

513

512

511

510

2

1

+0.082

+0.041

0

+0.488

+0.244

0

–1

–2

–0.041

–0.082

–0.244

–0.488

•

33

32

–479

–480

–19.625

–19.666

–116.94

–117.19

1 to 31

0

–481 to –511

–512

Unused

Fault

MMA68xx

Sensors

NXP Semiconductors

52

Figure 36 shows the how the possible output data codes are determined from the input data and the error sources. The

relevant parameters are specified in Section 3.4.

Figure 36. Acceleration Data Output Vs. Acceleration Input

MMA68xx

53

Sensors

NXP Semiconductors

6

Package

6.1 Case Outline Drawing

Reference NXP case outline document 98ASA00690D.

http://cache.nxp.com/assets/documents/data/en/package-information/98ASA00690D.pdf

6.2 Recommended Footprint

Reference NXP application note AN1902, latest revision:

http://www.nxp.com/assets/documents/data/en/application-notes/AN1902.pdf

7

Revision History

Table 35. Revision History

Revision Revision

Description of changes

number

date

9.0

01/2017

• Deleted part numbers MMA6811BKGTW, MMA6813BKGTW,, MMA6821BKGTW, MMA6823BKGTW,

MMA6825BKGTW, MMA6826BKGTW, and MMA6827BKGTW,

• Updated part marking diagram to reflect deletions.

8.0

7

04/2016

01/2016

10/2014

03/2012

12/2011

—

6

5

4

MMA68xx

Sensors

54

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

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Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo, SafeAssure, and the SafeAssure logo, are trademarks of NXP B.V.

Document Number: MMA68xx

Rev. 9.0

01/2017


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