935314523518 [NXP]
Buffer/Inverter Based Peripheral Driver;
| 型号： | 935314523518 |
| 厂家： | 
NXP |
| 描述： | Buffer/Inverter Based Peripheral Driver 驱动 接口集成电路 |
| 文件： | 总32页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC33932
5.0 A throttle control H-bridge
Rev. 6.0 — 10 September 2018
Data sheet: technical data
1 General description
The 33932 is a monolithic H-bridge power IC in a robust thermally enhanced package.
The 33932 has two independent monolithic H-bridge power ICs in the same package.
They are designed primarily for automotive electronic throttle control, but are applicable
to any low voltage DC servo motor control application within the current and voltage limits
stated in this specification. It meets the stringent requirements of automotive applications
and is fully AEC-Q100 grade 1 qualified.
Each H-bridge in the 33932 is able to control inductive loads with currents up to 5.0 A
peak. RMS current capability is subject to the degree of heat sinking provided to the
device package. Internal peak-current limiting (regulation) is activated at load currents
above 6.5 A ± 1.5 A. Output loads can be pulse-width modulated at frequencies up to
11 kHz. A load current feedback feature provides a proportional (0.24 % of the load
current) current output suitable for monitoring by a microcontroller’s A/D input. A status
flag output reports undervoltage, overcurrent and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge totem pole outputs.
Two independent disable inputs are provided to force the H-bridge outputs to 3-state
(high-impedance OFF state).
V
V
PWR
DD
33932
SFA
FBA
VPWRA
CCPA
OUT1
MOTOR
IN1
IN2
D1
EN/D2
OUT2
PGNDA
AGNDA
V
PWR
MCU
IN3
IN4
D3
VPWRB
CCPB
OUT3
EN/D4
FBB
MOTOR
SFB
PGNDB
AGNDB
OUT4
V
DD
Figure 1.ꢀSimplified application diagram
2 Features and benefits
• 8.0 to 28 V continuous operation (transient operation from 5.0 to 40 V)
• 235 mΩ maximum RDS(on) @ TJ = 150 °C (each H-bridge MOSFET)
• 3.0 V and 5.0 V TTL / CMOS logic compatible inputs
• Output short-circuit protection (short to VPWR or GND)
• Overcurrent limiting (regulation) via internal constant-off-time PWM
• Temperature dependent current limit threshold reduction
• All inputs have an internal source/sink to define the default (floating input) state
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
• Sleep mode with current draw < 50 µA (each half with inputs floating or set to match
default logic states)
• AEC-Q100 grade 1 qualified
3 Applications
• Electronic throttle control (ETC)
• Exhaust gas recirculation (EGR)
• Turbo flap control
• Industrial and medical pumps
• Stepper motor control
• Dual motor drive
4 Ordering information
Table 1.ꢀOrdering information
Type number [1]
Package
Name
Description
Operating
Version
temperature
MC33932VW
MC33932EK
HSOP44
HSOP54
HSOP44, plastic, thermal enhanced small
outline package; 44 terminals; 0.65 mm pitch;
15.9 mm x 11 mm x 3 mm body
SOT1305-2
TA = −40 °C to 125 °C
HSOP54, plastic, heat sink small outline
package; 54 terminals; 0.65 mm pitch; 17.9
mm x 7.5 mm x 2.65 mm body
SOT1747-4
[1] To order parts in tape and reel, add the R2 suffix to the part number.
MC33932
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 6.0 — 10 September 2018
2 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
5 Block diagram
VPWRA
VDD
LOGIC SUPPLY
VCP
CHARGE
PUMP
HS1
LS1
HS2
CCPA
OUT1
OUT2
TO GATES
HS1
LS2
LS1
IN1
IN2
HS2
LS2
PGND
EN/D2
D1
GATE DRIVE
AND
PROTECTION
LOGIC
VSENSE
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
SFA
FBA
ILIM PWM
H-Bridge A
AGNDA
PGNDA
H-Bridge B
VDD
VPWRB
LOGIC SUPPLY
VCP
CHARGE
PUMP
HS1
LS1
HS2
CCPB
OUT3
OUT4
TO GATES
HS1
LS2
IN3
IN4
LS1
HS2
LS2
EN/D4
D3
PGND
GATE DRIVE
AND
PROTECTION
LOGIC
VSENSE
CURRENT MIRROR
AND
SFB
FBB
ILIM PWM
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
AGNDB
PGNDB
Figure 2.ꢀBlock diagram
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
3 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
6 Pinning information
6.1 Pinning
Figure 3.ꢀPin configuration for HSOP44
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
4 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Figure 4.ꢀPin configuration for HSOP54
6.2 Pin description
For functional description of each pin, see Section 7.2 "Functional pin description".
Table 2.ꢀPin description
Symbol
Pin HSOP
(VW)
Pin SOICW-EP Function
(EK)
Name
Description
D1
1
3
Logic input
Disable input 1 When D1 is logic high, both OUT1 and
(active high)
OUT2 are 3-stated. Schmitt trigger input
with ~80 μA source so default condition =
disabled.
FBA
2
4
Analog output Feedback
H-bridge A load current feedback output
provides ground referenced 0.24 % of
the high-side output current (tie to GND
through a resistor if not used)
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
5 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Symbol
Pin HSOP
(VW)
Pin SOICW-EP Function
(EK)
Name
Description
EN/D2
3
5
Logic input
Enable input
When EN/D2 is logic high, the H-bridge A
is operational. When EN/D2 is logic low,
the H-bridge A outputs are 3-stated and
placed in Sleep mode (logic input with ~
80 μA sink so default condition = Sleep
mode).
VPWRA
4, 5, 6, 39, 40 1, 9, 46, 53
Power input
Positive power These pins must be connected together
supply
physically as close as possible and
directly soldered down to a wide, thick,
low resistance supply plane on the PCB.
OUT1
7, 8, 9
10, 11
Power output
H-bridge output H-bridge A source of HS1 and drain LS1
1
PGNDA
10, 11, 34, 35 12, 13, 42, 43 Power ground Power ground High-current power ground pins must
be connected together physically as
close as possible and directly soldered
down to a wide, thick, low resistance
ground plane on the PCB. PGNDA
should be connected to PGNDB with a
low-impedance path.
PGNDB
12, 13, 32, 33 15, 16, 39, 40 Power ground Power ground High-current power ground pins must
be connected together physically as
close as possible and directly soldered
down to a wide, thick, low resistance
ground plane on the PCB. PGNDB
should be connected to PGNDA with a
low-impedance path.
OUT4
14, 15, 16
17, 18
Power output
H-bridge output H-bridge B source of HS2 and drain of
LS2
4
VPWRB
17, 18, 26, 27, 19, 26, 28, 36 Power input
28
Positive power These pins must be connected together
supply
physically as close as possible and
directly soldered down to a wide, thick,
low resistance supply plane on the PCB.
CCPB
19
20
Analog output Charge pump
capacitor
External reservoir capacitor connection
for H-bridge B internal charge pump;
connected to VPWRB. Allowable values
are 30 nF to 100 nF [1]
IN4
IN3
SFB
20
21
22
23
24
25
Logic input
Logic input
Input 4
Input 3
Logic input control of OUT4
Logic input control of OUT3
Logic output -
open drain
Status flag B
(active low)
H-bridge B open drain active low Status
flag output (requires an external pull-up
resistor to VDD. Maximum permissible
load current < 0.5 mA. Maximum VSFLOW
< 0.4 V at 0.3 mA. Maximum permissible
pull-up voltage < 7.0 V.
D3
23
30
Logic input
Disable input 3 When D3 is logic high, both OUT3 and
(active high)
OUT4 are 3-stated. Schmitt trigger input
with ~80 μA source so default condition =
disabled.
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Symbol
Pin HSOP
(VW)
Pin SOICW-EP Function
(EK)
Name
Description
FBB
24
31
Analog output Feedback B
H-bridge B load current feedback output
provides ground referenced 0.24 % of
the high-side output current (tie to GND
through a resistor if not used)
EN/D4
25
32
Logic input
Enable input
When EN/D4 is logic high, H-bridge
B is operational. When EN/D4 is logic
low, the H-bridge B outputs are 3-stated
and H-bridge B is placed in Sleep mode
(logic input with ~ 80 μA sink so default
condition = Sleep mode).
OUT3
OUT2
CCPA
29, 30, 31
36, 37, 38
41
37, 38
44, 45
47
Power output
Power output
H-bridge output H-bridge B source of HS1 and drain of
LS1
3
H-bridge output H-bridge A source of HS2 and drain of
2
LS2
Analog output Charge pump
capacitor
External reservoir capacitor connection
for H-bridge B internal charge pump;
connected to VPWRB. Allowable values
are 30 nF to 100 nF.[1]
IN2
IN1
42
43
50
51
Logic input
Logic input
Input 2
Input 1
Logic input control of OUT2
Logic input control of OUT1; e.g., when
IN1 is logic high, OUT1 is set to VPWRA,
and when IN1 is logic low, OUT1 is set to
PGNDA. Schmitt trigger input with ~ 80
μA source so default condition = OUT1
high.
SFA
44
52
Logic output -
open drain
Status flag
(active low)
H-bridge A open drain active low status
flag output requires an external pull-up
resistor to VDD. Maximum permissible
load current < 0.5 mA. Maximum VSFLOW
< 0.4 V at 0.3 mA. Maximum permissible
pull-up voltage < 7.0 V.
AGNDA
AGNDB
TAB
n.a.
n.a.
54
27
Analog ground Analog signal
ground
The low-current analog signal ground
must be connected to PGND via low-
impedance path (<10 mΩ, 0 Hz to 20
kHz)
n.c.
EP
2, 6, 7, 8, 14,
21, 22, 29, 33,
31, 32, 33, 34,
35, 41, 48, 49
None
not connected These pins have no electrical connection
or function
EP
Thermal pad
Exposed pad
Exposed TAB is also the main heat
sinking path for the device and must be
connected to ground
[1] This capacitor is required for proper performance of the device.
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
7 Functional description
7.1 Introduction
The 33932 has two identical H-bridge drivers in the same package. The only connection
that is shared internally is the analog ground (AGND). This description is given for the H-
bridge A half of the total device. However, the H-bridge B half exhibits identical behavior.
Numerous protection and operational features (speed, torque, direction, dynamic
breaking, PWM control, and closed-loop control) make the 33932 a very attractive, cost-
effective solution for controlling a broad range of small DC motors. The 33932 outputs
are capable of supporting peak DC load currents of up to 5.0 A from a 28 V VPWR source.
An internal charge pump and gate drive circuitry are provided that can support external
PWM frequencies up to 11 kHz.
The 33932 has an analog feedback (current mirror) output pin (the FB pin) that provides
a constant-current source ratioed to the active high-side MOSFETs’ current. This can be
used to provide real time monitoring of output current to facilitate closed-loop operation
for motor speed/torque control, or for the detection of openload conditions.
Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge
outputs. Two independent disable inputs, D1 and EN/D2, provide the means to force the
H-bridge outputs to a high-impedance state (all H-bridges switch OFF). The EN/D2 pin
also controls an enable function that allows the IC to be placed in a power conserving
Sleep mode.
The 33932 has output current limiting (via constant OFF time PWM current regulation),
output short-circuit detection with latch-off, and overtemperature detection with latch-off.
Once the device is latched-off due to a fault condition, either of the disable inputs (D1 or
EN/D2), or VPWR must be toggled to clear the status flag.
Current limiting (load current regulation) is accomplished by a constant OFF time PWM
method using current limit threshold triggering. The current limiting scheme is unique in
that it incorporates a junction temperature dependent current limit threshold. This means
that the current limit threshold is reduced to around 4.2 A as the junction temperature
increases above 160 °C. When the temperature is above 175 °C, overtemperature
shutdown (latch-off) occurs. This combination of features allows the device to continue
operating for short periods of time (< 30 seconds) with unexpected loads, while still
retaining adequate protection for both the device and the load.
7.2 Functional pin description
7.2.1 Power ground and analog ground (PGND and AGND)
The power and analog ground pins should be connected together with a very low-
impedance connection.
7.2.2 Positive power supply (VPWR)
VPWR pins are the power supply inputs to the device. All VPWR pins must be connected
together on the printed circuit board with traces as short as possible, offering as low-
impedance as possible between pins.
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
7.2.3 Status flag (SF)
This pin is the device fault status output. This output is an active low open drain structure
requiring a pull-up resistor to VDD. The maximum VDD is < 7.0 V. See Table 7 for the SF
output status definition.
7.2.4 Input 1, 2 and Disable input 1 (IN1, IN2, and D1)
These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V
CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and
OUT2, respectively. D1 input is used to 3-state disable the H-bridge outputs.
When D1 is set (D1 = logic high) in the disable state, outputs OUT1 and OUT2 are both
3-state disabled; however, the rest of the device circuitry is fully operational and the
supply IPWR(STANDBY) current is reduced to a few mA. See Table 5.
7.2.5 H-bridge output (OUT1, OUT2)
These pins are the outputs of the H-bridge with integrated freewheeling diodes. The
bridge output is controlled using the IN1, IN2, D1, and EN/D2 inputs. The outputs have
PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown
(3-state latch-off) with hysteresis as well as short-circuit latch-off protection.
A disable timer (time tB) is incorporated to distinguish between load currents higher
than the ILIM threshold and short-circuit currents. This timer is activated at each output
transition.
7.2.6 Charge pump capacitor (CCP)
This pin is the charge pump output pin and connection for the external charge pump
reservoir capacitor. The allowable value is from 30 nF to 100 nF.
This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot
operate properly without the external reservoir capacitor.
7.2.7 Enable input/Disable input 2 (EN/D2)
The EN/D2 pin performs the same function as D1 pin, when it goes to a logic low, the
outputs are immediately 3-stated. It is also used to place the device in a Sleep mode so
as to consume very low currents. When the EN/D2 pin voltage is a logic Low state, the
device is in the Sleep mode.
The device is enabled and fully operational when the EN pin voltage is logic high. An
internal pull-down resistor maintains the device in Sleep mode in the event EN is driven
through a high-impedance I/O or an unpowered microcontroller, or the EN/D2 input is
disconnected.
7.2.8 Feedback (FB)
The 33932 has a feedback output (FB) for real time monitoring of H-bridge high-side
output currents to facilitate closed-loop operation for motor speed and torque control.
The FB pin provides current sensing feedback of the H-bridge high-side drivers.
When running in the forward or reverse direction, a ground-referenced 0.24 % of load
current is output to this pin. Through the use of an external resistor to ground, the
proportional feedback current can be converted to a proportional voltage equivalent and
MC33932
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Data sheet: technical data
Rev. 6.0 — 10 September 2018
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
the controlling microcontroller can read the current proportional voltage with its analog-
to-digital converter (ADC). This is intended to provide the user with only first-order motor
current feedback for motor torque control. The resistance range for the linear operation of
the FB pin is 100 Ω < RFB < 300 Ω.
If PWM-ing is implemented using the disable pin input (only D1), a small filter
capacitor (~1.0 μF) may be required in parallel with the RFB resistor to ground for spike
suppression.
8 Maximum ratings
Table 3.ꢀMaximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Symbol
Parameter
Value
Unit
Electrical ratings
[1]
Power supply voltage
V
VPWR(SS)
VPWR(T)
•
•
Normal operation (steady-state)
Transient overvoltage
−0.3 to 28
−0.3 to 40
[2]
[3]
VIN
Logic input voltage
SFA , SFB output
Continuous output current
ESD voltage
−0.3 to 7.0
−0.3 to 7.0
5.0
V
V
A
V
VSF
[4]
[5]
IOUT(CONT)
VESD1
VESD2
•
•
•
Human body model
Machine model
± 2000
± 200
Charge device model
– Corner pins
±750
±500
– All other pins
TSTG
TA
Storage temperature
−65 to 150
−40 to 125
−40 to 150
°C
°C
°C
°C
[6]
[6]
Operational ambient temperature
Operation junction temperature
Peak package reflow temperature during reflow
TJ
[7] [8]
TPPRT
[1] Device will survive repetitive transient overvoltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 10 %. External protection is
required to prevent device damage in case of a reverse battery condition.
[2] Exceeding the maximum input voltage on IN1, IN2, IN3, IN4, EN/D2, EN/D4, D1, or D3 may cause a malfunction or permanent damage to the device.
[3] Exceeding the pull-up resistor voltage on the open drain SFA or SFB pin may cause permanent damage to the device.
[4] Continuous output current capability is dependent on sufficient package heat sinking to keep junction temperature ≤ 150 °C.
[5] ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and
the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
[6] The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief non-repetitive
excursions of junction temperature above 150 °C can be tolerated, provided the duration does not exceed 30 seconds maximum. Non-repetitive events
are defined as not occurring more than once in 24 hours.
[7] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction
or permanent damage to the device.
[8] NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture
Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes and enter the core ID) to view all orderable parts, and
review parametrics.
MC33932
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 6.0 — 10 September 2018
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
9 Thermal characteristics
Table 4.ꢀThermal characteristics
Symbol
Parameter
Value
Unit
[1]
RθJC
Approximate junction-to-case thermal resistance
< 1.0
°C/W
[1] Exposed heat sink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board) values will vary
depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die temperature represents ~16 W of
conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJA must be < 5.0 °C/W for maximum current at 70 °C ambient. Module
thermal design must be planned accordingly.
10 Static characteristics
Table 5.ꢀStatic characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V, −40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise
noted.
Symbol
Power inputs (VPWR)
Operating voltage range
Parameter
Min
Typ
Max
Unit
[1] [2]
V
VPWR(SS)
VPWR(t)
•
•
Steady-state
5.0
—
—
—
28
40
Transient (t < 500 ms)
[3]
IPWR(SLEEP)
Sleep state supply current
µA
•
EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT
0 A
=
—
—
—
—
50
20
IPWR(STANDBY)
Standby supply current (part enabled)
IOUT = 0 A, VEN = 5.0 V
mA
•
Undervoltage lockout thresholds
VUVLO(ACTIVE)
VUVLO(INACTIVE)
VUVLO(HYS)
•
•
•
VPWR(FALLING)
VPWR(RISING)
Hysteresis
4.15
—
—
—
V
—
5.0
350
V
150
200
mV
Charge pump
VCP − VPWR
Charge pump voltage (CP capacitor = 33 nF), no PWM
V
V
•
•
VPWR = 5.0 V
VPWR = 28 V
3.5
—
—
—
—
12
VCP − VPWR
Charge pump voltage (CP capacitor = 33 nF), PWM =
11 kHz,
•
•
VPWR = 5.0 V
VPWR = 28 V
3.5
—
—
—
—
12
Control inputs
VI
Operating input voltage (IN1, IN2, D1, EN/D2, IN3, IN4,
D3, EN/D4)
—
—
5.5
V
Input voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
VIH
•
•
•
Logic threshold high
Logic threshold low
Hysteresis
2.0
—
—
—
V
VIL
—
1.0
—
V
VHYS
250
400
mV
IIN
Logic input currents, VPWR = 8.0 V
µA
•
•
Inputs EN/D2, EN/D4 (internal pull-downs), VIH = 5.0 V
20
80
200
−20
Inputs IN1, IN2, D1, IN3, IN4, D3 (internal pull-ups),
VIL = 0 V
−200
−80
Power outputs OUT1, OUT2
[4]
RDS(on)
Output-on resistance, ILOAD = 3.0 A
mΩ
•
•
•
VPWR = 8.0 V, TJ = 25 °C
VPWR = 8.0 V, TJ = 150 °C
VPWR = 5.0 V, TJ = 150 °C
—
—
—
120
—
—
235
325
—
MC33932
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
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NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Symbol
Parameter
Min
Typ
Max
Unit
[5]
ILIM
Output current regulation threshold
A
•
•
TJ < TFB
5.2
—
6.5
4.2
8.0
—
TJ ≥ TFB (foldback region - see Figure 10 and
Figure 12)
[5]
[5]
[6]
ISCH
High-side short-circuit detection threshold (short-circuit to
GND)
11
13
11
16
14
A
ISCL
Low-side short-circuit detection threshold (short-circuit to
9.0
A
VPWR
)
IOUTLEAK
Output leakage current, outputs off, VPWR = 28 V
µA
•
•
VOUT = VPWR
—
—
—
100
—
−60
VOUT = Ground
VF
Output MOSFET body diode forward voltage drop
IOUT = 3.0 A
V
•
—
—
2.0
[5]
Overtemperature shutdown
°C
TLIM
•
•
Thermal limit at TJ
Hysteresis at TJ
175
—
—
200
—
THYS
12
[5]
[5]
TFB
Current foldback at TJ
165
10
—
—
185
15
°C
°C
TSEP
Current foldback to thermal shutdown separation
High-side current sense feedback
[7]
IFB
Feedback current (pin FB sourcing current)
•
•
•
•
•
•
IOUT = 0 mA
IOUT = 300 mA
IOUT = 500 mA
IOUT = 1.5 A
IOUT = 3.0 A
IOUT = 6.0 A
0.0
—
50
µA
0.0
270
750
µA
0.35
2.86
5.71
11.43
0.775
3.57
7.14
14.29
1.56
4.28
8.57
17.15
mA
mA
mA
mA
Status flag [8]
ISFLEAK
[9]
Status flag leakage current
VSF = 5.0 V
µA
V
•
—
—
—
—
5.0
0.4
[10]
VSFLOW
Status flag set voltage
ISF = 300 µA
•
[1] Device specifications are characterized over the range of 8.0 V ≤ VPWR ≤ 28 V. Continuous operation above 28 V may degrade device reliability. Device is
operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.
[2] Device survives the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once every 10 seconds.
[3] IPWR(SLEEP) is with Sleep mode activated and EN/D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
[4] Output-on resistance as measured from output to VPWR and from output to GND.
[5] This parameter is guaranteed by design.
[6] Outputs switched OFF via D1 or EN/D2.
[7] Accuracy is better than 20 % from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 Ω.
[8] Status flag output is an open drain output requiring a pull-up resistor to logic VDD
.
[9] Status flag leakage current is measured with status flag high and not set.
[10] Status flag set voltage measured with status flag low and set with IFS = 300 μA. Maximum allowable sink current from this pin is <500 μA. Maximum
allowable pull-up voltage < 7.0 V.
11 Dynamic characteristics
Table 6.ꢀDynamic characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V, −40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise
noted.
Symbol
Parameter
Min
Typ
Max
Unit
Timing characteristics
[1]
[2]
fPWM
fMAX
PWM frequency
—
—
—
—
11
20
kHz
kHz
Maximum switching frequency during current
limit regulation
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5.0 A throttle control H-bridge
Symbol
Parameter
Min
Typ
Max
Unit
[3]
[3]
tDON
Output on delay
µs
•
VPWR = 14 V
Output off delay
VPWR = 14 V
—
—
18
tDOFF
µs
•
—
—
12
[4] [5]
[5] [6]
[7]
tA
ILIM output constant-off time
ILIM blanking time
15
12
—
20.5
16.5
—
32
µs
µs
µs
µs
µs
tB
27
tDDISABLE
tF, tR
tFAULT
Disable delay time
8.0
8.0
8.0
[8]
Output rise and fall time
1.5
—
3.0
—
[9] [10]
Short-circuit/overtemperature turn-off (latch-
off) time
[10]
[10]
tPOD
tRR
Power-on delay time
—
1.0
5.0
ms
ns
Output MOSFET body diode reverse recovery
time
75
100
150
[10]
fCP
Charge pump operating frequency
—
7.0
—
MHz
[1] The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the
high-side MOSFETs.
[2] The internal current limit circuitry produces a constant-off-time pulse width modulation of the output current. The output load’s inductance, capacitance,
and resistance characteristics affect the total switching period (OFF time + ON time), and thus the PWM frequency during current limit.
[3] Output delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20 % or 80 % point (dependent on the transition direction) of the OUT1
or OUT2 signal. If the output is transitioning high-to-low, the delay is from 1.5 V on the input signal to the 80 % point of the output response signal. If the
output is transitioning low-to-high, the delay is from 1.5 V on the input signal to the 20 % point of the output response signal. See Figure 5.
[4] The time during which the internal constant-off time PWM current regulation circuit has 3-stated the output bridge.
[5] Parameter is guaranteed by characterization
[6] The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time to act.
[7] Disable delay time measurement is defined in Figure 6.
[8] Rise time is from the 10 % to the 90 % level and fall time is from the 90 % to the 10 % level of the output signal with VPWR = 14 V, RLOAD = 3.0 Ω. See
Figure 7.
[9] Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 8). The short-circuit currents possess a di/dt
that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection and causing the shutdown circuitry
to force the output into an immediate 3-state latch-off (see Figure 9). Operation in current limit mode may cause junction temperatures to rise. Junction
temperatures above ~160 °C causes the output current limit threshold to “foldback”, or decrease, until ~175 °C is reached, after which the tLIM thermal
latch-off occurs. Permissible operation within this foldback region is limited to non-repetitive transient events of duration not to exceed 30 seconds (see
Figure 10).
[10] Parameter is guaranteed by design.
12 Timing diagrams
5.0
V
IN1, IN2
(V)
1.5 V
1.5 V
0
0
t
t
DOFF
DON
V
PWR
80 %
V
OUT1, 2
(V)
20 %
time
aaa-028117
Figure 5.ꢀOutput delay time
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MC33932
5.0 A throttle control H-bridge
5.0 V
V
D1, EN/D2
1.5 V
(V)
0 V
t
DDISABLE
V
OUT1, 2
= 100 mA
90 %
I
O
0 V
time
Figure 6.ꢀDisable delay time
t
t
R
F
V
PWR
90 %
90 %
V
OUT1, 2
(V)
10 %
10 %
0 V
time
aaa-028119
Figure 7.ꢀOutput switching time
Overload Condition
l
sc
Short-circuit Detection Threshold
t
= l Blanking Time
lim
= Constant-OFF Time (OUT1 and OUT2 Tri-stated)
B
9.0
t
A
l
OUT, current
(A)
t
t
A
B
l
lim
6.5
0.0
time
t
ON
aaa-028120
Figure 8.ꢀCurrent limit blanking time and constant-off time
Short-circuit Condition
t
FAULT
l
Short-circuit Detection Threshold
Hard Short Occurs
SC
9.0
OUT1, OUT2 Tri-stated
SF set Low
l
, CURRENT
(A)
t
B
OUT
l
lim
6.5
0.0
time
t
B
(~16 µs)
aaa-028121
Figure 9.ꢀShort-circuit detection turn-off time tFAULT
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5.0 A throttle control H-bridge
Nominal current limit threshold
Current limit threshold foldback.
Operation within this region must be
limited to non-repetitive events not to
exceed 30 s per 24 hr.
6.5
4.2
I
current
(A)
LIM
T
SEP
T
LIM
T
HYS
thermal shutdown
time
T
T
LIM
FB
aaa-028122
Figure 10.ꢀOutput current limiting foldback region
13 Functional internal block description
Figure 11.ꢀFunctional internal block diagram
13.1 Analog control and protection circuitry
An on-chip voltage regulator supplies the internal logic. The charge pump provides gate
drive for the H-bridge MOSFETs. The current and temperature sense circuitry provides
detection and protection for the output drivers. Output undervoltage protection shuts
down the MOSFETs.
13.2 Gate control logic
The 33932 is a monolithic H-bridge power IC designed primarily for any low-voltage DC
servo motor control application within the current and voltage limits stated for the device.
Two independent inputs provide polarity control of two half-bridge totem-pole outputs.
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Two independent disable inputs are provided to force the H-bridge outputs to 3-state
(high-impedance OFF state).
13.3 H-bridge output drivers: OUT1 and OUT2
The H-bridge is the power output stage. The current flow from OUT1 to OUT2 is
reversible and under full control of the user by way of the input control logic. The output
stage is designed to produce full load control under all system conditions.
All protective and control features are integrated into the control and protection blocks.
The sensors for current and temperature are integrated directly into the output MOSFET
for maximum accuracy and dependability.
14 Functional device operation
14.1 Operational modes
typical short-circuit detection threshold
9.0
6.5
typical current limit threshold
high current load being regulated via constant-OFF-Time PWM
PWM
current
limiting
moderate
current load
I
LOAD,
output current
(A)
0
IN1 or IN2
IN2 or IN1
IN1 or IN2
IN2 or IN1
[1]
IN
logic in
n,
IN1 IN2
[0]
[1]
D1,
logic in
[0]
[1]
EN/D2,
logic in
[0]
[1]
[0]
SF,
logic out
outputs
tri-stated
outputs operation
(per input control condition)
outputs
tri-stated
time
Figure 12.ꢀOperating states
MC33932
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5.0 A throttle control H-bridge
14.2 Logic commands
Table 7.ꢀTruth table
The 3-state conditions and the status flag are reset using D1 or EN/D2. The truth table uses the
following notations: L = low, H = high, X = high or low, and Z = high-impedance.
Input conditions
Status
Outputs
Device state
EN/D2
D1
L
IN1
H
L
IN2
L
SF
H
H
H
H
L
OUT1
OUT2
Forward
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
L
Reverse
L
H
L
Freewheeling low
Freewheeling high
Disable 1 (D1)
L
L
L
L
H
X
Z
H
X
X
Z
H
Z
H
X
Z
Z
Z
Z
Z
Z
H
Z
X
H
Z
Z
Z
Z
Z
Z
H
L
IN1 disconnected
IN2 disconnected
D1 disconnected
Undervoltage lockout [1]
Overtemperature [2]
Short-circuit [2]
H
H
L
L
X
X
X
X
X
X
X
Z
X
X
X
X
X
X
X
X
X
X
X
L
L
L
Sleep mode EN/D2
EN/D2 disconnected
H
H
Z
[1] In the event of an undervoltage condition, the outputs 3-state and status flag are set to logic low. Upon undervoltage
recovery, status flag is reset automatically or automatically cleared and the outputs are restored to their original operating
condition.
[2] When a short-circuit or overtemperature condition is detected, the power outputs are 3-state latched-off, independent of
the input signals, and the status flag is latched to logic low. To reset from this condition requires the toggling of either D1,
EN/D2, or VPWR
.
Forward
High-Side Recirculation
(Forward)
Reverse
Low-Side Recirculation
(Forward)
V
V
V
V
PWR
V
V
V
V
PWR
PWR
PWR
PWR
PWR
PWR
PWR
load
load
current
current
load
current
ON
OUT1
OFF
OUT2
ON
OUT1
ON
OUT2
OFF
OUT1
ON
OUT2
OFF
OUT1
OFF
OUT2
LOAD
LOAD
LOAD
LOAD
load
current
OFF
ON
OFF
OFF
ON
OFF
ON
ON
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
aaa-028125
Figure 13.ꢀPower stage operation
14.3 Protection and diagnostic features
14.3.1 Short-circuit protection
If an output short-circuit condition is detected, the power outputs 3-state (latch-off)
independent of the input (IN1 and IN2) states, and the fault status output flag (SF) is set
to logic low. If the D1 input changes from logic high to logic low, or if the EN/D2 input
changes from logic low to logic high, the output bridge becomes operational again and
the fault status flag resets (cleared) to a logic High state.
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The output stage always switches into the mode defined by the input pins (IN1, IN2, D1,
and EN/D2), provided the device junction temperature is within the specified operating
temperature range.
14.3.2 Internal PWM current limiting
The maximum current flow under normal operating conditions should be less than 5.0 A.
The instantaneous load currents will be limited to ILIM via the internal PWM current
limiting circuitry. When the ILIM threshold current value is reached, the output stages are
3-stated for a fixed time (t A) of 20 μs typical. Depending on the time constant associated
with the load characteristics, the output current decreases during the 3-state duration
until the next output ON cycle occurs.
The PWM current limit threshold value is dependent on the device junction temperature.
When −40 °C < TJ < 160 °C, ILIM is between the specified minimum/maximum values.
When TJ exceeds 160 °C, the ILIM threshold decreases to 4.2 A. Shortly above 175
°C, the device overtemperature circuit detects TLIM and an overtemperature shutdown
occurs. This feature implements a graceful degradation of operation before thermal
shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the
motor’s gear reduction train to be handled.
Important: Die temperature excursions above 150 °C are permitted only for non-
repetitive durations < 30 seconds. Provision must be made at the system level to prevent
prolonged operation in the current-foldback region.
14.3.3 Overtemperature shutdown and hysteresis
If an overtemperature condition occurs, the power outputs are 3-stated (latched-off), and
the fault status flag (SF) is set to a logic low.
To reset from this condition, D1 must change from a logic high to logic low, or EN/D2
must change from a logic low to logic high. When reset, the output stage switches on
again, provided the junction temperature is now below the overtemperature threshold
limit minus the hysteresis.
Important: Resetting from the fault condition clears the fault status flag. Powering down
and powering up the device also resets the 33932 from the fault condition.
14.3.4 Output avalanche protection
If VPWR becomes an open circuit, the outputs likely 3-state simultaneously due to the
disable logic. This could result in an unclamped inductive discharge. The VPWR input
to the 33932 should not exceed 40 V during this transient condition, to prevent electrical
overstress of the output drivers. This can be accomplished with a zener clamp or MOV,
and/or an appropriately valued input capacitor with sufficiently low ESR (see Figure 14).
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5.0 A throttle control H-bridge
V
PWR
VPWR
100 nF
bulk
low ESR
cap
OUT1
M
OUT2
l/Os
9
AGND
PGND
aaa-028126
Figure 14.ꢀAvalanche protection
15 Application information
A typical application schematic is shown in Figure 15. For precision high current
applications in harsh, noisy environments, the VPWR bypass capacitor may need to be
substantially larger.
Figure 15.ꢀTypical application schematic half device
16 Package outline
Note: The most current package outline is available at www.nxp.com.
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MC33932
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Figure 16.ꢀPackage outline SOT1305-2 (HSOP44)
MC33932
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MC33932
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MC33932
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5.0 A throttle control H-bridge
Figure 17.ꢀPackage outline SOT1747-4 (HSOP54)
MC33932
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17 Thermal addendum
17.1 Introduction
This thermal addendum is provided as a supplement to the MC33932 technical data
sheet. The addendum provides thermal performance information that may be critical
in the design and development of system applications. All electrical, application and
packaging information is provided in the data sheet.
17.2 Packaging and thermal considerations
The 33932 is offered in a 54-pin SOICW-EP and a 44-pin HSOP single die package.
There is a single heat source (P), a single junction temperature (TJ), and thermal
resistance (RθJA). This thermal addendum is specific to the 54-pin SOICW-EP package.
{TJ} = [RθJA] · {P}
The stated values are solely for a thermal performance comparison of one package to
another in a standardized environment. This methodology is not meant to, and will not
predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards
listed in Table 8.
Table 8.ꢀThermal resistance data
Symbol
Parameter
Conditions
Value
Unit
[1] [2]
[1] [3]
RθJA
Junction to Ambient
Natural Convection
Single layer board (1s)
58.8
°C/W
RθJA
Junction to Ambient
Natural Convection
Four layer board (2s2p)
24.4
°C/W
[4]
[5]
[6]
[7]
RθJB
Junction to Board
7.0
0.36
18
°C/W
°C/W
°C/W
°C/W
RθJC(bottom)
RθJC(top)
ΨJT
Junction to Case (bottom / flag)
Junction to Case (top)
Junction to Package Top
Natural convection
2.0
[1] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
[2] Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
[3] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
[4] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board
near the package.
[5] Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).
[6] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
[7] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
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Figure 18.ꢀTransient thermal resistance RθJA MC33932EK on 2s2p test board
18 References
[1] AN4146 — Thermal modeling and simulation of 12 V Gen3 eXtreme switch devices with SPICE
https://www.nxp.com/files-static/analog/doc/app_note/AN4146.pdf
[2] BASICTHERMALWP — Basic principles of thermal analysis for semiconductor systems
https://www.nxp.com/files-static/analog/doc/white_paper/BasicThermalWP.pdf
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19 Revision history
Table 9.ꢀRevision history
Document ID
MC33932 v.6.0
Modifications
Release date
9/2018
Data sheet status
Change notice
Supersedes
Technical Data
-
DOC_ID v.5.0
• The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors. Legal texts have been adapted to the new company name where appropriate.
• Added AEC-Q100 grade 1 qualified to Section 1 and Section 2
• Updated package drawings to comply with the new identity guidelines of NXP Semiconductors (no
technical change)
MC33932 v.5.0
Modifications
10/2012
Technical Data
-
DOC_ID v.4.0
DOC_ID v.3.0
• PC33932EK changed to MC33932EK and released to production
• Document level changed from Advance Information to Technical Data
• Changed SOIC to SOICW-EP
MC33932 v.4.0
Modifications
6/2012
Advance information
-
• Added PC33932EK to Table 1
• Added EK ordering information
• Form and style corrections
• Added note "Parameter guaranteed by characterization" to Table 6
• Added Thermal Addendum and Reference Document sections
• Added 98ASA99334D package drawing
• Minor corrections throughout the spec
MC33932 v.3.0
Modifications
11/2008
Advance information
-
DOC_ID v.2.0
• Changed maximum RDS(on) from 225 to 235 mΩ
• Changed Peak Package Reflow Temperature During Reflow
• Changed Approximate Junction-to Case Thermal Resistance
MC33932 v.2.0
Modifications
8/2008
• Added parameters (tbd) for charge pump voltages in Table 5
8/2007 Advance information
Advance information
-
DOC_ID v.1.0
-
MC33932 v.1.0
-
MC33932
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20 Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
[short] Data sheet: product preview
Development
This document contains certain information on a product under development.
NXP reserves the right to change or discontinue this product without notice.
[short] Data sheet: advance information
[short] Data sheet: technical data
Qualification
Production
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
This document contains the product specification. NXP Semiconductors
reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
20.2 Definitions
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a
technical data data sheet shall define the specification of the product as
agreed between NXP Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed otherwise in writing.
In no event however, shall an agreement be valid in which the NXP
Semiconductors product is deemed to offer functions and qualities beyond
those described in the technical data data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
MC33932
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 6.0 — 10 September 2018
29 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
SMARTMOS — is a trademark of NXP B.V.
MC33932
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 6.0 — 10 September 2018
30 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Ordering information ..........................................2
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Dynamic characteristics .................................. 12
Truth table .......................................................17
Thermal resistance data ..................................26
Revision history ...............................................28
Pin description ...................................................5
Maximum ratings .............................................10
Thermal characteristics ................................... 11
Static characteristics ....................................... 11
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Simplified application diagram ...........................1
Fig. 10. Output current limiting foldback region ............15
Fig. 11. Functional internal block diagram ....................15
Fig. 12. Operating states ..............................................16
Fig. 13. Power stage operation .................................... 17
Fig. 14. Avalanche protection .......................................19
Fig. 15. Typical application schematic half device ........19
Fig. 16. Package outline SOT1305-2 (HSOP44) ..........20
Fig. 17. Package outline SOT1747-4 (HSOP54) ..........23
Block diagram ................................................... 3
Pin configuration for HSOP44 ...........................4
Pin configuration for HSOP54 ...........................5
Output delay time ............................................13
Disable delay time ...........................................14
Output switching time ......................................14
Current limit blanking time and constant-off
time ..................................................................14
Short-circuit detection turn-off time tFAULT .... 14
Fig. 18. Transient
thermal
resistance
RθJA
Fig. 9.
MC33932EK on 2s2p test board .....................27
MC33932
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 6.0 — 10 September 2018
31 / 32
NXP Semiconductors
MC33932
5.0 A throttle control H-bridge
Contents
1
General description ............................................ 1
2
3
4
5
Features and benefits .........................................1
Applications .........................................................2
Ordering information .......................................... 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................5
Functional description ........................................8
Introduction ........................................................ 8
Functional pin description ..................................8
Power ground and analog ground (PGND
6
6.1
6.2
7
7.1
7.2
7.2.1
and AGND) ........................................................8
Positive power supply (VPWR) ..........................8
Status flag (SF) ................................................. 9
Input 1, 2 and Disable input 1 (IN1, IN2, and
7.2.2
7.2.3
7.2.4
D1) ..................................................................... 9
H-bridge output (OUT1, OUT2) ......................... 9
Charge pump capacitor (CCP) .......................... 9
Enable input/Disable input 2 (EN/D2) ................9
Feedback (FB) ...................................................9
Maximum ratings ...............................................10
Thermal characteristics ....................................11
Static characteristics ........................................11
Dynamic characteristics ...................................12
Timing diagrams ............................................... 13
Functional internal block description ............. 15
Analog control and protection circuitry .............15
Gate control logic ............................................ 15
H-bridge output drivers: OUT1 and OUT2 ....... 16
Functional device operation ............................ 16
Operational modes .......................................... 16
Logic commands ............................................. 17
Protection and diagnostic features .................. 17
Short-circuit protection .....................................17
Internal PWM current limiting .......................... 18
Overtemperature shutdown and hysteresis ..... 18
Output avalanche protection ............................18
Application information ....................................19
Package outline .................................................19
Thermal addendum ...........................................26
Introduction ...................................................... 26
Packaging and thermal considerations ............26
References .........................................................27
Revision history ................................................ 28
Legal information ..............................................29
7.2.5
7.2.6
7.2.7
7.2.8
8
9
10
11
12
13
13.1
13.2
13.3
14
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
15
16
17
17.1
17.2
18
19
20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 September 2018
Document identifier: MC33932
相关型号：
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