935314697518 [NXP]
Interface Circuit;
| 型号： | 935314697518 |
| 厂家： | 
NXP |
| 描述： | Interface Circuit 电信 电信集成电路 |
| 文件： | 总37页 (文件大小：1387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33663
Rev. 2.0, 12/2013
escale Semiconductor
Advance Information
LIN 2.1 / SAEJ2602-2 Dual LIN
Physical Layer
33663
The local interconnect network (LIN) is a serial communication
protocol designed to support automotive networks in conjunction with
controller area network (CAN). As the lowest level of a hierarchical
network, LIN enables cost-effective communication with sensors and
actuators when all the features of CAN are not required.
DUAL LIN TRANSCEIVER
The 33663 product line integrates two physical layer LIN bus
dedicated to automotive LIN sub-bus applications. The MC33663LEF
and MC33663SEF devices offer normal baud rate (20 kbps) and the
MC33663JEF slow baud rate (10 kbps). Both devices integrate fast
baud rate (above 100 kbps) for test and programming modes. They
present excellent electromagnetic compatibility (EMC) and radiated
emission performance, electrostatic discharge (ESD) robustness and
safe behavior, in the event of LIN bus short-to-ground or LIN bus
leakage during low-power mode.
EF SUFFIX (PB-FREE)
98ASB42565B
14-PIN SOICN
Features
ORDERING INFORMATION
• Operational from VSUP 7.0 to 18 V DC, functional up to 27 V DC,
and handles 40 V during load dump
• Compatible with LIN protocol specification 2.1, and SAEJ2602-2
• Very high immunity against electromagnetic interference
• Low standby current in Sleep mode
Device
(add an R2 suffix for
Tape and reel orders)
Temperature
Range (T )
A
Package
MC33663ALEF
MC33663AJEF
MC33663ASEF
-40 to 125°C
14 SOICN
• Over-temperature protection
• Permanent dominant state detection
• Fast baud rate mode selection reported by RXD
• Active bus waveshaping offering excellent radiated emission
performance
• Sustains ±15.0 kV ESD IEC6100-4-2 on LIN BUS and VSUP pins
• 5.0 and 3.3 V compatible digital inputs without any external components required
VBAT
33663
VSUP
WAKE1
WAKE2
INH1
INH2
EN1
Regulator
MCU
RXD1
TXD1
EN2
VDD
12 V
5.0 or
3.3 V
RXD2
TXD2
1.0 k
1.0 k
LIN1
LIN Interface 1
LIN Interface 2
GND LIN2
Figure 1. 33663 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
CE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
(Add an R2 suffix for
Tape and reel orders)
Temperature Range (T )
A
Package
Maximum Baud Rate
MC33663ALEF
MC33663ASEF
MC33663AJEF
20 kbps
20 kbps with restricted limits for transmitter
and receiver symmetry
-40 to 125 °C
14 SOICN
10 kbps
33663
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VSUP
INH_ON
X 1
INH1
LIN1
EN_SLEEP
EN1
Control
Unit
200 k
30 k
725 k
( LIN Module 1)
RxD_INT
RxD1
Receiver
EN_RxD
LIN_EN
35µA
Slope
Control
TxD_INT
TxD1
WAKE1
INH_ON
X 1
INH2
LIN2
EN2
EN_SLEEP
RxD_INT
Control
Unit
(LIN Module 2)
200 k
30 k
725 k
RxD2
Receiver
EN_RxD
LIN_EN
35µA
Slope
Control
TxD_INT
TxD2
WAKE2
GND
Figure 2. 33663 Simplified Internal Block Diagram
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
CONNECTIONS
PIN CONNECTIONS
WAKE1
TXD1
LIN1
1
2
3
4
14
13
EN1
RXD1
12
11
INH1
LIN2
VSUP
10
5
6
7
TXD2
INH2
RXD2
EN2
9
8
GND
WAKE2
Figure 3. 33663 14-SOIC Pin Connections
Table 2. 33663 Pin Definitions
Pin
Pin Name
Formal Name
Definition
1
2
WAKE1
TXD1
Wake Input
Data Input
This pin is a high-voltage input used to wake-up the LIN1 from Sleep mode.
This pin is the transmitter input of the LIN1 interface which controls the state of the bus
output.
3
4
5
LIN1
LIN2
INH2
LIN Bus
LIN Bus
This bidirectional pin represents the LIN1 single-wire bus transmitter and receiver.
This bidirectional pin represents the LIN2 single-wire bus transmitter and receiver.
Inhibit Output
This pin can have two main functions: controlling an external switchable voltage
regulator having an inhibit input, or driving an external bus resistor connected to LIN2 in
the master node application.
6
RXD2
Data Output
This pin is the receiver output of the LIN2 interface, which reports the state of the bus
voltage to the MCU interface.
7
8
EN2
WAKE2
GND
Enable Control
Wake Input
Ground
This pin controls the operation mode of the LIN2 interface.
This pin is a high-voltage input used to wake-up the LIN2 device from Sleep mode.
This pin is the device ground pin.
9
10
TXD2
Data Input
This pin is the transmitter input of the LIN2 interface, which controls the state of the bus
output.
11
12
VSUP
INH1
Power Supply
Inhibit Output
This pin is device battery level power supply.
This pin can have two main functions: controlling an external switchable voltage
regulator having an inhibit input, or driving an external bus resistor connected to LIN1 in
the master node application.
13
14
RXD1
EN1
Data Output
This pin is the receiver output of the LIN1 interface, which reports the state of the bus
voltage to the MCU interface.
Enable Control
This pin controls the operation mode of the LIN1 interface.
33663
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage (VSUP)
Normal Operation (DC)
V
VSUP(SS)
-0.3 to 27
Transient input voltage with external component (according to ISO7637-2 &
ISO7637-3 & “Hardware Requirements for LIN, CAN, and Flexray Interfaces
in Automotive Applications” specification Rev. 1.1/December 2nd, 2009) (See
Table 4 and Figure 4)
- Pulse 1 (test up to the limit for Damage - Class A(1)
)
-100
+75
VSUP(S1)
VSUP(S2A)
VSUP(S3A)
VSUP(S3B)
VSUP(S5B)
- Pulse 2a (test up to the limit for Damage - Class A(1)
- Pulse 3a (test up to the limit for Damage - Class A(1)
- Pulse 3b (test up to the limit for Damage - Class A(1)
- Pulse 5b (Class A)(1)
)
)
)
-150
+100
-0.3 to 40
Logic Voltage (RXD1,2, TXD1,2, EN1,2 Pins)
VLOG
-0.3 to 5.5
-27 to 40
V
V
WAKE (VWAKE1,VWAKE2
)
Normal Operation with in series 2*18 k resistor (DC)
VWAKE(SS)
Transient input voltage with external component (according to ISO7637-2 &
ISO7637-3 & “Hardware Requirements for LIN, CAN and Flexray Interfaces
in Automotive Applications” specification Rev1.1 / December 2nd, 2009) (See
Table 4 and Figure 5)
- Pulse 1 (test up to the limit for Damage - Class D(2)
)
VWAKE(S1)
VWAKE(S2A)
VWAKE(S3A)
VWAKE(S3B)
-100
+75
- Pulse 2a (test up to the limit for Damage - Class D(2)
- Pulse 3a (test up to the limit for Damage - Class D(2)
- Pulse 3b (test up to the limit for Damage - Class D(2)
)
)
)
-150
+100
LIN Bus Voltage (VLIN1, VLIN2
)
V
Normal Operation (DC)
VLIN(SS)
-27 to 40
Transient (Coupled Through 1.0 nF Capacitor) (according to ISO7637-2 &
ISO7637-3) (See Table 4 and Figure 6)
- Pulse 1 (test up to the limit for Damage - Class D(2)
)
VLIN(S1)
VLIN(S2A)
VLIN(S3A)
VLIN(S3B)
-100
+75
- Pulse 2a (test up to the limit for Damage - Class D(2)
- Pulse 3a (test up to the limit for Damage - Class D(2)
- Pulse 3b (test up to the limit for Damage - Class D(2)
)
)
)
-150
+100
Notes
1. Class A: All functions of a device/system perform as designed during and after exposure to disturbance.
2. Class D: At least one function of the Transceiver stops working properly during the test and will return into proper operation automatically
when the exposure to the disturbance has ended. No physical damage of the IC occurs.
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
INH Voltage/Current (VINH1, VINH2
DC Voltage
)
V
VINH
-0.3 to VSUP + 0.3
Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 &
ISO7637-3 & “Hardware Requirements for LIN, CAN and Flexray Interfaces
in Automotive Applications” specification Rev1.1 / December 2nd, 2009) (See
Table 4 and Figure 7)
- Pulse 1 (test up to the limit for Damage - Class D(3)
)
VINH(S1)
VINH(S2a)
VINH(S3a)
VINH(S3b)
-100
+75
- Pulse 2a (test up to the limit for Damage - Class D(3)
- Pulse 3a (test up to the limit for Damage - Class D(3)
- Pulse 3b (test up to the limit for Damage - Class D(3)
)
)
)
-150
+100
Notes
3. Class D: At least one function of the Transceiver stops working properly during the test and will return into proper operation automatically
when the exposure to the disturbance has ended. No physical damage of the IC occurs.
33663
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
ESD Capability
AECQ100
V
Human Body Model - JESD22/A114 (C
LIN1, LIN2 pins versus GND
= 100 pF, R
= 1500 )
ZAP
ZAP
V
V
V
±10.0 k
±8.0 k
±4.0 k
ESD1-1
ESD1-2
ESD1-4
WAKE1, WAKE2 pins versus GND
All other Pins
Charge Device Model - JESD22/C101 (C
= 4.0 pF
ZAP
V
V
±750
±750
Corner pins (Pins 1, 7, 8 and 14)
All other pins (Pins 2-6, 9-13)
ESD2-1
ESD2-2
Machine Model - JESD22/A115 (C
All pins
= 220 pF, R
= 0 )
ZAP
ZAP
V
±200
ESD3-1
According to “Hardware Requirements for LIN, CAN and Flexray Interfaces in
Automotive Applications” specification Rev1.1 / December 2nd, 2009
(C
= 150 pF, R
= 330 )
ZAP
ZAP
Contact Discharge, Unpowered
LIN1, LIN2 pins without capacitor
±15 k
±15 k
±25 k
±20 k
±15 k
V
V
V
V
V
ESD4-1
ESD4-2
ESD4-3
ESD4-4
ESD4-5
LIN1, LIN2 pins with 220 pF capacitor
VSUP (10 µF to ground)
WAKE1, WAKE2 (2*18 k serial resistor)
LIN1, LIN2 pins with 220 pF capacitor and indirect ESD coupling
(according to ISO10605 - Annex F)
According to ISO10605 - Rev 2008 test specification
(2.0 k / 150 pF) - Unpowered - Contact discharge
LIN1, LIN2 pins without capacitor
V
V
V
V
±25 k
±25 k
±25 k
±25 k
ESD5-1
ESD5-2
ESD5-3
ESD5-4
LIN1, LIN2 pins with 220 pF capacitor
VSUP (10 µF to ground)
WAKE1, WAKE2 (2*18 k serial resistor)
(2.0 k / 330 pF) - Powered - Contact discharge
LIN1, LIN2 pins without capacitor
V
V
V
V
±8 k
±8 k
ESD6-1
ESD6-2
ESD6-3
ESD6-4
LIN1, LIN2 pins with 220 pF capacitor
±25 k
±25 k
VSUP (10 µF to ground)
WAKE1, WAKE2 (2*18 k serial resistor)
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Thermal Ratings
Operating Temperature
Ambient
C
T
-40 to 125
-40 to 150
A
T
Junction
J
Storage Temperature
TSTG
RJA
-40 to 150
150
C
°C/W
C
Thermal Resistance, Junction to Ambient
Peak package reflow temperature during reflow(4),(5)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis Temperature
Notes
TPPRT
Note 5
150 to 200
20
T
°C
SHUT
HYST
T
°C
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Table 4. Limits / Maximum test voltage for transient immunity tests
Pulse repetition
Test Pulse
VS [V]
Test duration [min]
Ri []
Remarks
frequency [Hz] (1/T1)
1
-100
+75
2
2
1 for function test
10 for damage test
10
2
t2 = 0s
2a
3a
3b
-150
+100
10
10
50
50
DUT
Transient Pulse
Generator
(Note)
VSUP
D1
10 µF
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b
Figure 4. Test Circuit for Transient Test Pulses (VSUP
)
33663
Analog Integrated Circuit Device Data
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
DUT
Transient Pulse
Generator
(Note)
1.0 nF
WAKE
18 k
18 k
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 5. Test Circuit for Transient Test Pulses (WAKE1,WAKE2)
DUT
Transient Pulse
Generator
(Note)
1.0 nF
LIN
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b
Figure 6. Test Circuit for Transient Test Pulses (LIN1,LIN2)
DUT
Transient Pulse
Generator
(Note)
1.0 nF
INH
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 7. Test Circuit for Transient Test Pulses (INH1,INH2)
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
VSUP PIN (DEVICE POWER SUPPLY)
Symbol
Min
Typ
Max
Unit
Nominal Operating Voltage
V
7.0
6.7
–
13.5
–
18.0
27
V
V
V
V
SUP
Functional Operating Voltage(6)
Load Dump
VSUPOP
VSUPLD
VPOR
–
40
Power-On Reset (POR) Threshold
VSUP Ramp Down and INH1, INH2 goes High to Low
3.5
–
–
5.3
–
Power-On Reset (POR) Hysteresis
VPORHYST
270
mV
V
V
Under-voltage Threshold (positive and negative)
VUVL, VUVH
SUP
Transmission disabled and LIN1,LIN2 bus goes in recessive
5.8
–
–
6.7
–
V
Under-voltage Hysteresis (VUVL - VUVH
)
VUVHYST
130
mV
SUP
Supply Current LIN1 and LIN2 in Sleep Mode
13.5 V, Recessive State
A
V
I
–
–
–
12.0
–
22
36
SUP
S1
13.5 V < V
< 27 V
I
SUP
S2
I
48
140
V
13.5 V, Shorted to GND
S3
SUP
Supply Current LIN1 Normal Mode - LIN2 Sleep Mode (and vice versa)
Bus1 Recessive, BUS2 Sleep, Excluding INH1,INH2
mA
mA
I
–
–
4.0
6.0
5.0
8.0
S_N_REC1,2
S_N_DOM1,2
OR (Bus2 Recessive, BUS1 Sleep, Excluding INH1,INH2)
Bus1 Dominant, BUS2 Sleep, Excluding INH1,INH2
I
OR (Bus2 Dominant, BUS1 Sleep, Excluding INH1,INH2)
Supply Current when LIN1 and LIN2 are in Normal or Slow or Fast Mode
Bus1 Recessive, Bus2 Recessive, Excluding INH1,INH2 Output Current
Bus1 Recessive, Bus2 Dominant, Excluding INH1,INH2 Output Current
Bus1 Dominant, Bus2 Recessive, Excluding INH1,INH2 Output Current
Bus1 Dominant, Bus2 Dominant, Excluding INH1,INH2 Output Current
I
–
–
–
–
8.0
9.0
S(REC1,REC2)
I
I
12.0
12.0
12.0
13.0
13.0
16.0
S(REC1,DOM2)
S(DOM1,REC2)
I
S(DOM1,DOM2)
RXD1, RXD2 OUTPUT PINS (LOGIC)
Low Level Output Voltage
V
V
V
OL
I
1.5 mA
0.0
–
0.9
IN
High Level Output Voltage
V
OH
V
V
= 5.0 V, I
= 3.3 V, I
250 A
250 A
4.25
3.0
–
–
5.25
3.5
EN
EN
OUT
OUT
Notes
6. Device is functional. All features are operating. Electrical parameters are not guaranteed.
33663
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
TXD1, TXD2 INPUT PINS (LOGIC)
Symbol
Min
Typ
Max
Unit
Low Level Input Voltage
V
–
–
–
0.8
–
V
V
IL
High Level Input Voltage
Input Threshold Voltage Hysteresis
Pull-up Current Source
V
2.0
100
IH
V
300
600
mV
A
INHYST
I
PU
V
= 5.0 V, 1.0 V < V
< 3.5 V
TXD
-60
-35
-20
EN
EN1, EN2 INPUT PINS (LOGIC)
Low Level Input Voltage
V
–
–
0.8
–
V
V
IL
High Level Input Voltage
V
2.0
100
100
–
IH
Input Voltage Threshold Hysteresis
Pull-down Resistor
V
400
230
600
350
mV
kohm
INHYST
RPD
LIN PHYSICAL LAYER - TRANSCEIVER LIN (LIN1, LIN2)(7)
Operating Voltage Range(8)
VBAT
VSUP
VSUP_NON_OP
IBUS_LIM
8.0
7.0
–
–
–
18
18
40
V
V
Supply Voltage Range
Voltage Range (within which the device is not destroyed)
-0.3
V
Current Limitation for Driver Dominant State
Driver ON, VBUS = 18 V
mA
40
-1.0
–
90
–
200
–
Input Leakage Current at the Receiver
Driver off; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
mA
µA
Leakage Output Current to GND
IBUS_PAS_REC
Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT;
VBUS VSUP
–
20
Control Unit Disconnected from Ground(9)
IBUS_NO_GND
mA
GNDDEVICE = VSUP; VBAT = 12 V; 0 < V
< 18 V
-1.0
–
1.0
BUS
V
Disconnected; VSUP_DEVICE = GND; 0 V < V
< 18 V(10)
BUS
IBUSNO_BAT
VBUSDOM
VBUSREC
–
–
–
–
–
10
0.4
–
µA
BAT
Receiver Dominant State(11)
Receiver Recessive State(12)
Notes
VSUP
VSUP
0.6
7. Parameters guaranteed for 7.0 V VSUP 18 V.
8. Voltage range at the battery level, including the reverse battery diode.
9. Loss of local ground must not affect communication in the residual network.
10. Node has to sustain the current that can flow under this condition. The bus must remain operational under this condition.
11. LIN threshold for a dominant state.
12. LIN threshold for a recessive state.
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Receiver Threshold Center
(VTH_DOM + VTH_REC)/2
VBUS_CNT
VSUP
0.475
0.5
0.525
Receiver Threshold Hysteresis
(VTH_REC - VTH_DOM
VHYS
VSUP
)
–
–
0.175
LIN dominant level with 500 680 and 1.0 k load on the LIN bus
VLINDOM_LEVEL
VSHIFT_BAT
VSHIFT_GND
VBUSWU
–
0.0
0.0
–
–
–
0.25
11.5%
11.5%
5.3
VSUP
VBAT
VBAT
V
VBAT_SHIFT
GND_SHIFT
–
LIN Wake-up Threshold from Sleep Mode
4.3
30
–
LIN Pull-up Resistor to V
SUP
RSLAVE
20
–
60
k
LIN internal capacitor(13)
CLIN
30
pF
Over-temperature Shutdown(14)
Over-temperature Shutdown Hysteresis
INH1, INH2 OUTPUT PINS
TLINSD
150
–
160
20
200
–
°C
TLINSD_HYS
°C
Driver ON Resistance (Normal Mode)
IINH = 50 mA
INH
ON
–
–
–
–
–
50
30
Current load capability
IINH_load
mA
A
From 7.0 V < VSUP < 18 V
Leakage Current (Sleep Mode)
I
LEAK
0 < V
< V
SUP
-5.0
5.0
INH
Over-temperature Shutdown(15)
Over-temperature Shutdown Hysteresis
Notes
TINHSD
150
–
160
20
200
–
°C
°C
TINHSD_HYS
13. This parameter is guaranteed by process monitoring but not production tested.
14. When an over-temperature shutdown occurs, the LIN transmitter and receiver are in recessive state and INH switched off. This
parameter is tested with a test mode on ATE and characterized at laboratory.
15. When an over-temperature shutdown occurs, the INH1, INH2 high side are switched off and the LIN transmitter and receiver are in
recessive state. This parameter is tested with a test mode on ATE and characterized at laboratory.
33663
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
WAKE1, WAKE2 INPUT PINS
Symbol
Min
Typ
Max
Unit
High to Low Detection Threshold (5.5 V < VSUP < 7 V)
Low to High Detection Threshold (5.5 V < VSUP < 7 V)
Hysteresis (5.5 V < VSUP < 7 V)
VWUHL1
VWULH1
VWUHYS1
VWUHL2
VWULH2
VWUHYS2
IWU
2.0
2.4
0.2
2.4
2.9
0.2
–
–
–
–
–
–
–
–
3.9
4.3
0.8
3.9
4.3
0.8
5.0
V
V
V
High to Low Detection Threshold (7 V VSUP < 27 V)
Low to High Detection Threshold (7 V VSUP < 27 V)
Hysteresis (7 V VSUP < 27 V)
V
V
V
Wake-up Input Current (VWAKE < 27 V)
µA
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTIC
DYNAMIC ELECTRICAL CHARACTERISTIC
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN1, LIN2 PHYSICAL LAYER
DRIVERS CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION(16)(17)
33663L AND 33663S DEVICE
Duty Cycle 1:
D1
D2
THREC(MAX) = 0.744 * VSUP; THDOM(MAX) = 0.581 * VSUP
0.396
–
–
–
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V VSUP18 V
Duty Cycle 2:
THREC(MIN) = 0.422 * VSUP; THDOM(MIN) = 0.284 * VSUP
–
0.581
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V VSUP18 V
LIN1, LIN2 PHYSICAL LAYER
DRIVERS CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION(16)(18)
33663J DEVICE
Duty Cycle 3:
D3
D4
THREC(MAX) = 0.778 * VSUP; THDOM(MAX) = 0.616 * VSUP
0.417
–
–
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V VSUP18 V
Duty Cycle 4:
THREC(MIN) = 0.389 * VSUP; THDOM(MIN) = 0.251 * VSUP
–
–
–
–
0.590
100
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V VSUP18 V
LIN1, LIN2 PHYSICAL LAYER - DRIVERS CHARACTERISTICS FOR FAST SLEW RATE
Fast Bit Rate (Programming Mode)
BRFAST
kBit/s
LIN1, LIN2 PHYSICAL LAYER - TRANSMITTER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(19)
33663S DEVICE
Symmetry of Transmitter delay(20)
s
-7.25
–
7.25
tTRAN_SYM
tTRAN_SYM = MAX (tTRAN_SYM60%, tTRAN_SYM40%
tTRAN_SYM60% = | tTRAN_PDF60% - tTRAN_PDR60%
tTRAN_SYM40% = | tTRAN_PDF40% - tTRAN_PDR40%
)
|
|
Notes
16. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660, 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 8.
17. See Figure 9
18. See Figure 10
19. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
20. See Figure 11
33663
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTIC
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN1, LIN2 PHYSICAL LAYER - RECEIVERS CHARACTERISTICS ACCORDING LIN2.1(21)
33663L AND 33663J AND 33663S
Propagation Delay and Symmetry(22)
s
tREC_PD
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
)
–
–
–
6.0
2.0
tREC_SYM
-2.0
LIN1, LIN2 PHYSICAL LAYER: RECEIVER CHARACTERISTICS WITH TIGHTEN LIMITS(21)
33663S DEVICE
Propagation Delay and Symmetry(22)
s
s
µs
tREC_PD_S
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
)
—
—
—
5.0
1.3
tREC_SYM_S
-1.3
LIN1, LIN2 PHYSICAL LAYER: RECEIVER CHARACTERISTICS - LIN SLOPE 1V/ns(21)
33663S DEVICE
Propagation Delay and Symmetry(23)
tREC_PD_FAST
Propagation Delay of Receiver, tREC_PD _FAST= MAX (tREC_PDR_FAST
tREC_PDF_FAST
,
—
—
—
6.0
1.3
)
Symmetry of Receiver Propagation Delay, tREC_PDF_FAST - tREC_PDR_FAST
tREC_SYM_FAST
-1.3
SLEEP MODE AND WAKE-UP TIMINGS
Sleep Mode Delay Time(24)
t
SD
after EN High to Low to INH High to Low with 100µA load on INH
50
—
91
WAKE-UP TIMINGS
Bus Wake-up Deglitcher (Sleep Mode) (25)
t
40
—
10
70
—
48
100
15
s
s
WUF
EN Wake-up Deglitcher (26)
EN High to INH Low to High
t
LWUE
Wake-up Deglitcher (27)
t
s
WF
Wake state change to INH Low to High
70
Notes
21. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
22. See Figure 12
23. See Figure 13
24. See Figures 22 and 23
25. See Figures 15 and 17
26. See Figures 14, 18, 22, and 23
27. See Figures 16, 22, and 23
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
CTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
3.75
—
Typ
5.0
50
Max
6.25
80
Unit
ms
ms
s
TXD TIMING
TXD Permanent Dominant State Delay(28)
FIRST DOMINANT BIT VALIDATION
tTXDDOM
First dominant bit validation delay when device in Normal Mode(29)
FAST BAUD RATE TIMING
tFIRST_DOM
EN Low Pulse Duration to Enter in Fast Baud Rate Using Toggle Function (30)
EN High to Low and Low to High
t
1
—
—
—
45
—
TXD Low Pulse Duration to Enter in Fast Baud Rate Using Toggle Function (30)
t
t
12.5
µs
µs
2
3
Delay Between EN Falling Edge and TXD Falling Edge to Enter in Fast Baud
Rate Using Toggle Function (30)
12.5
12.5
—
—
—
—
Delay Between TXD Rising Edge and EN Rising Edge to Enter in Fast Baud
Rate Using Toggle Function (30)
t
t
µs
µs
4
5
RXD Low Level duration after EN rising edge to validate the Fast Baud Rate
entrance(30)
1.875
6.25
Notes
28. The LIN is in recessive state and the receiver is still active
29. See Figures 14, 15, 16, and 21
30. See Figures 19 and 20
TIMING DIAGRAMS
V
SUP
VSUP
TXD
R0
LIN
RXD
GND
C0
Note R0 and C0: 1.0 k/1.0 nF, 660 /6.8 nF, and 500 /10 nF.
Figure 8. Test Circuit for Timing Measurements
33663
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
TBIT
TBIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
REC(MAX)74.4% VSUP
TH
Thresholds of
receiving node 1
58.1% V
SUP
TH
TH
DOM(MAX)
LIN
Thresholds of
receiving node 2
42.2% V
28.4% V
SUP
TH
REC(MIN)
SUP
DOM(MIN)
t
(MIN)
BUS_DOM
t
(MAX)
BUS_REC
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 9. LIN1, LIN2 Timing Measurements for Normal Baud Rate (33663L, 33663S)
TXD
TBIT
TBIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
REC(MAX)77.8% VSUP
Thresholds of
receiving node 1
TH
61.6% V
SUP
TH
DOM(MAX)
LIN
Thresholds of
receiving node 2
38.9% V
25.1% V
SUP
SUP
TH
REC(MIN)
TH
DOM(MIN)
t
(MIN)
BUS_DOM
t
(MAX)
BUS_REC
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 10. LIN1, LIN2 Timing Measurements for Slow Baud Rate (33663J)
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
CTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
VLIN_REC
LIN BUS SIGNAL
60% V
40% V
SUP
V
BUSREC
V
SUP
SUP
V
BUSDOM
t
t
t
TRAN_PDR40%
TRAN_PDF60%
TRAN_PDF40%
t
TRAN_PDR60%
Figure 11. LIN1, LIN2 Transmitter Timing for 33663S
VLIN_REC
60% V
40% V
SUP
V
BUSREC
V
SUP
LIN BUS SIGNAL
SUP
V
BUSDOM
RXD
t
t
REC_PDF
REC_PDR
Figure 12. LIN1, LIN2 Receiver Timing
VLIN_REC
1V/ns
60% V
40% V
SUP
V
BUSREC
V
SUP
LIN BUS SIGNAL
SUP
V
BUSDOM
RXD
t
t
REC_PDF_FAST
REC_PDR_FAST
Figure 13. LIN1, LIN2 Receiver Timing LIN Slope 1.0 V/ns
33663
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
FUNCTIONAL DIAGRAMS
EN1
EN1
INH1
INH1
Normal Mode
Normal Mode
tLWUE
TXD1
TXD1 (High or Low)
LIN1
LIN1
RXD1
RXD1
(High Z)
WAKE1
WAKE1
LIN2
EN2
VBUSWU
tWUF
INH2
INH2
Normal Mode
Normal Mode
TXD2
tFIRST_DOM
EN2
LIN2
TXD2 (High or Low)
Awake Mode
RXD2
(High Z)
RXD2
WAKE2
WAKE2
Figure 15. LIN Module 1 in Normal Mode & LIN Module 2
LIN2 Wake-up with TXD2 LOW
Figure 14. LIN Module 1 EN1 Pin Wake-up with TXD1
High & LIN Module 2 in Normal Mode
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
CTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
WAKE1
WAKE after deglitcher
tWF
INH1
EN1
tFIRST_DOM
TXD1 (High or Low)
Normal Mode
LIN1
RXD1 RXD2
(High Z)
Awake Mode
WAKE2
WAKE after deglitcher
tWF
INH2
EN2
tFIRST_DOM
TXD2 (High or Low)
Normal Mode
LIN2
RXD2
Awake Mode
(High Z)
Figure 16. LIN Module 1 Wake1 Pin Wake-up with TXD1
Low & LIN Module 2 Wake2 Pin Wake-up with TXD2 High
33663
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
INH
EN
TXD
LIN
No wake-up
t>tWUF
RXD
(High Z)
WAKE
Preparation to Sleep Mode
No communication available
Sleep Mode
Awake
Mode
No communication available
Device in
Communication Mode
Normal Mode
Wake & LIN wake-up events not taken into
Wake & LIN wake-up events
allowed
account
t
SD
Figure 17. Bus Wake-up with LIN bus in Dominant During the Preparation to Sleep Mode
(same sequence for LIN1 & LIN2)
EN pin
tLWUE
EN internal signal
t
LWUE
EN pin
t < t
LWU
E
EN internal signal
5V
5V
EN pin
t < t
LWU
E
EN internal signal
Figure 18. EN1, EN2 Pin Deglitcher
t1 (45 s)
EN
Fast Baud Rate entrance
t2 (12.5 s)
TXD
t
(12.5
s)
t
4 (12.5 s)
3
LIN
Fast Baud Rate validation
RXD
t5
Figure 19. Fast Baud Rate Selection (Toggle Function) for LIN1 or LIN2
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
CTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
t1 (45 s)
EN
Exit Fast Baud Rate
t2 (12.5 s)
TXD
t
(12.5
s)
t4 (12.5 s)
3
LIN
RXD stays High for Normal or Slow Mode validation
RXD
Figure 20. Fast Baud Rate Mode Exit (Back to Normal or Slow Slew Rate) for LIN1 or LIN2
VSUP
VUVL
POR (3.5-5.3 V)
POR (3.5-5.3 V)
VSUP
160 µs *
EN1
(High or Low)
INH1
EN1
INH1
LIN1 in Normal Mode
TXD1
(High or Low)
(High or Low)
TXD1
LIN1
LIN1
Awake Mode
RXD1
EN2
(High Z)
RXD1
(High Z)
(High or Low)
INH2
EN2
LIN2 in Normal Mode
INH2
(High or Low)
TXD2
(High or Low)
TXD2
LIN2
LIN2
Awake Mode
RXD2
RXD2
(High Z)
(High Z)
*: this parameter is guaranteed by design
Figure 21. Power Up and Down Sequences
33663
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
INH
t
LWUE
EN
TXD
LIN
(High Z)
RXD
t
WF
WAKE
WAKE after deglitcher
Preparation to Sleep Mode
Sleep
Mode
Device in
Communication Mode
No communication allowed
LIN & Wake wake up events not taken
into account
t
SD
Figure 22. Sleep Mode Sequence for LIN1 or LIN2
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
CTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
INH
INH
EN
t
t
LWUE
LWUE
EN
TXD
TXD
No communication
No communication
allowed
LIN
LIN
allowed
(High Z)
(High Z)
RXD
RXD
WAKE
(case 1)
WAKE
(case 2)
WAKE after deglitcher
(case 1)
WAKE after deglitcher
(case 2)
t = tWF
t tWF
Awake Mode
Preparation to
Sleep Mode
Awake Mode
Device in
Communication Mode
Device in
Communication Mode
t < t
SD
Sleep Mode (t < tSD
)
Preparation to
The device does not enter in Sleep Mode
The device does not enter in Sleep Mode
INH
EN
t
LWUE
TXD
No communication
allowed
LIN
(High Z)
RXD
WAKE
(case 3)
t tWF
WAKE after deglitcher
(case 3)
t tSD
Device in
Communication Mode
Sleep
Mode
Preparation to
Sleep Mode
Awake Mode
Figure 23. Examples of Sleep Mode Sequences for LIN1 or LIN2
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33663L and 33663J are both a Physical Layer component dedicated to automotive LIN sub-bus applications.
The 33663L features include a 20 kbps baud rate and the 33663J a 10 kbps baud rate. Both integrate fast baud rate for test
and programming modes, excellent ESD robustness, immunity against disturbance, and radiated emission performance. They
have safe behavior, in case of a LIN bus short-to-ground, or a LIN bus leakage during low power mode.
Digital inputs are 5.0 and 3.3 V compatible without any external required components.
The INH1 and INH2 outputs may be used to control an external voltage regulator, or to drive a LIN bus pull-up resistor.
FUNCTIONAL PIN DESCRIPTION
POWER SUPPLY PIN (VSUP)
The VSUP supply pin is the power supply pin for the 33663L or 33663J. In an application, the pin is connected to a battery
through a serial diode, for reverse battery protection. The DC operating voltage is from 7.0 to 18 V. This pin sustains standard
automotive condition, such as 40 V during load dump. To avoid a false bus message, an under-voltage on VSUP disables the
transmission path (from TXD to LIN) when VSUP falls below 6.7 V. Supply current in the Sleep mode is typically 6.0 A for one
LIN Module.
GROUND PIN (GND)
In case of a ground disconnection at the module level, the 33663L and 33663J do not have significant current consumption
on the LIN bus pin when in the recessive state.
LIN BUS PIN (LIN1, LIN2)
The LIN1 and LIN2 pins represent the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is
compliant to the LIN bus specification 1.3, 2.0, 2.1, and SAEJ2602-2.
The LIN interface is only active during Normal mode.
LIN overtemperature
OR
INH overtemperature
INH switched off &
LIN transmitter and receiver disabled
VSUP
LIN Wake up
INH_ON
INH
LIN Driver
Slope Control
EN_sleep
LIN Undervoltage
TXD Dominant
30 k
725 k
LIN
X 1
EN
35µA
TXD
RXD
Receiver
Transmitter Characteristics
The LIN driver is a low side MOSFET with internal over-current thermal shutdown. An internal pull-up resistor with a serial
diode structure is integrated, so no external pull-up components are required for the application in a slave node. An additional
pull-up resistor of 1.0 k must be added when the interface is used in the master node.
The LIN pin exhibits no reverse current from the LIN bus line to VSUP, even in the event of a GND shift or VSUP disconnection.
The 33663 is tested according to the application conditions (i.e. in normal mode and recessive state during communication).
The transmitter has a 20 kbps baud rate (Normal baud rate) for the 33663L and 33663S devices, or 10 kbps baud rate (Slow
baud rate) for the 33663J device.
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
CTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
As soon as the device enters Normal mode, the LIN transmitter will be able to send the first dominant bit only after the
tFIRST_DOM delay. tFIRST_DOM delay has no impact on the receiver. The receiver will be enabled as soon as the device enters
Normal mode.
Receiver Characteristics
The receiver thresholds are ratiometric with the device supply pin.
If the VSUP voltage goes below the VSUP under-voltage threshold (VUVL, VUVH), the bus LIN1 and bus LIN2 enter into a recessive
state even if communication is sent to TXD1 or TXD2.
For the LIN Module 1, in case of LIN1 Thermal Shutdown, the transceiver and receiver are in recessive and INH1 turned off.
When the temperature is below the TLINSD, INH1 and LIN1 will be automatically enabled. The same behavior is valid for LIN
Module 2.
For each LIN Module, the Fast Baud Rate selection is reported by the RXD pin. Fast Baud Rate is activated by the toggle
function (See Figure 19). At the end of the toggle function, just after EN rising edge, RXD pin is kept low for t5 to flag the Fast
Baud Rate entry (See Figure 19).
To exit the Fast Baud Rate and return in Normal or Slow baud rate, a toggle function is needed. At the end the toggle function,
RXD pin stays high to signal Fast Baud Rate exit (See Figure 20). The device enters into Fast Baud Rate at room and hot
temperature.
DATA INPUT PINS (TXD1, TXD2)
The TXD1 and TXD2 inputs pins are the MCU interface to control the state of the LIN1 and LIN2 outputs. When TXD1 (TXD2)
is LOW (dominant), LIN1 (LIN2) output is LOW; when TXD1 (TXD2) is HIGH (recessive), the LIN1 (LIN2) output transistor is
turned OFF. TXD1/TXD2 pins thresholds are 3.3 V and 5.0 V compatible.
These pins have an internal pull-up current source to force the recessive state if the input pins are left floating.
If TXD1 (TXD2) stays low (dominant sate) more than 5.0 ms (typical value), the LIN1 (LIN2) transmitter of LIN Module goes
automatically into recessive state.
DATA OUTPUT PINS (RXD1, RXD2)
Each LIN Modules integrate the same RXD output structure and functionality. Both pins are independent. The following
description is the same for both.
RXD output pin is the MCU interface, which reports the state of the LIN bus voltage.
In Normal or Slow baud rate, LIN HIGH (recessive) is reported by a high voltage on RXD; LIN LOW (dominant) is reported by
a low voltage on RXD. The RXD output structure is a tristate output buffer.
X 1
EN
200 k
LIN_RXD
VSUP
RXD
EN_RXD
30 k
Receiver
LIN
Slope
Control
Figure 24. RXD interface
The RXD output pins are the receiver output of the LIN interface. The low level is fixed. The high level is dependent on EN
voltage. If EN is set at 3.3 V, RXD VOH is 3.3 V. If EN is set at 5.0 V, RXD VOH is 5.0 V. The RXD1 and RXD2 VOH level can be
defined independently.
In sleep mode, RXD are high-impedance. When a wake-up event is recognized from the WAKE pin or from the LIN bus pin,
RXD is pulled LOW to report the wake-up event. An external pull-up resistor may be needed.
33663
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ENABLE INPUT PINS (EN1, EN2)
EN1 (EN2) input pin controls the operation mode of the interface. If EN1 (EN2) = 1, the interface is in Normal mode, TXD1
(TXD2) to LIN1 (LIN2) after tFIRS_DOM delay and LIN1 (LIN2) to RXD1 (RXD2) paths are both active. EN1 (EN2) pin thresholds are
3.3 V and 5.0 V compatible. RXD1 (RXD2) VOH level follows EN1 (EN2) pin high level. One LIN Module enters the Sleep Mode
by setting EN1 (EN2) LOW for a delay higher than tSD (70 µs typ. value) and if the WAKE1 (WAKE2) pin state doesn’t change
during this delay. (see Figure 22). Both LIN Modules enter Sleep Mode if EN1 & EN2 LOW.
A combination of the logic levels on EN1 (EN2) and TXD1 (TXD2) pins allows the device to enter in Fast Baud Rate mode of
operation (see Figure 19).
INHIBIT OUTPUT PINS (INH1, INH2)
The INH1 (INH2) output pin is connected to an internal high side power MOSFET. The pin has two possible main functions. It
can be used to control an external switchable voltage regulator having an inhibit input. It can also be used to drive the LIN bus
external resistor in the master node application, thanks to its high drive capability. This is illustrated in Figure 26.
In Sleep mode, INH1 (INH2) is turned OFF. If a voltage regulator inhibit input is connected to INH1 (INH2), the regulator will
be disabled. If the master node pull-up resistor is connected to INH1 (INH2), the pull-up resistor will be unpowered and left
floating.
In case of a INH1 (INH2) thermal shutdown, the high side is turned off and the LIN1 (LIN2) transmitter and receiver are in
recessive state. An external 10 to 100 pF capacitor on INH1 (INH2) pin is advised in order to improve EMC performances.
WAKE INPUT PINS (WAKE1, WAKE2)
The WAKE1 (WAKE2) pin is a high-voltage input used to wake-up the device from the Sleep mode. WAKE1 (WAKE2) is
usually connected to an external switch in the application.
The WAKE1 (WAKE2) pin has a special design structure and allows wake-up from both HIGH to LOW or LOW to HIGH
transitions. When entering into Sleep mode, the corresponded LIN Module monitors the state of its WAKE pin and stores it as a
reference state. The opposite state of this reference state will be the wake-up event used by the LIN Module to enter again into
Normal mode.
If the WAKE1 (WAKE2) pin state changes during the Sleep mode Delay Time (tSD) or before EN1 (EN2) goes low with a
deglitcher lower than tWF, the LIN Module will not enter in Sleep mode, but will go into Awake mode (See Figure 23).
An internal filter is implemented to avoid false wake-up event due to parasitic pulses (See Figure 16). WAKE1 (WAKE2) pin
input structure exhibits a high-impedance, with extremely low input current when voltage at this pin is below 27 V. Two serial
resistors should be inserted in order to limit the input current mainly during transient pulses and ESD. The total recommended
resistor value is 33 k. An external 10 to 100 nF capacitor is advised for better EMC and ESD performances.
Important The WAKE1 (WAKE2) pin should not be left open. If the wake-up function is not used, WAKE1 (WAKE2) should
be connected to ground to avoid a false wake-up.
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27
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
As described by the following, the 33663L, 33663J, and 33663S have two operational modes, Normal and Sleep. In addition,
there are two transitional modes: Awake mode which allows the device to go into Normal mode, and Preparation to Sleep mode
which allows the device to go into Sleep mode.
NORMAL OR SLOW BAUD RATE
In the Normal mode, the LIN bus can transmit and receive information.
The 33663L and 33663S (20 kbps) have a slew rate and timing compatible with Normal Baud Rate and LIN protocol
specification 1.3, 2.0, 2.1, and 2.2.
The 33663J (10 kbps) has a slew rate and timing compatible with Low Baud Rate.
From Normal mode, the three devices can enter into Fast Baud Rate (Toggle function).
FAST BAUD RATE
In fast baud rate, the slew rate is around 10 times faster than the normal baud rate. This allows very fast data transmission
(>100 kbps) -- for example, electronic control unit (ECU) tests and microcontroller program download. The bus pull-up resistor
might be adjusted to ensure a correct RC time constant in line with the high baud rate used.
The following sequence is applicable to both LIN Modules independently.
Fast baud rate is entered via a special sequence (called toggle function) as follows:
1. EN1 pin set LOW while TXD1 is HIGH
2. TXD1 stays HIGH for 12.5 µs min
3. TXD1 set LOW for 12.5 µs min
4. TXD1 pulled HIGH for 12.5 µs min
5. EN1 pin set LOW to HIGH while TXD1 still HIGH
The LIN Module enters into the fast baud rate if the delay between step 1 to step 5 is 45 µs maximum. The toggle function is
described in Figures 19. Once in fast baud rate, the same toggle function just described previously is used to bring the LIN Module
1 back into normal baud rate.
Fast baud rate selection is reported to the MCU by the RXD1 pin. Once the LIN Module 1 enters in this fast baud rate, the
RXD1 pin goes at low level for t5. When LIN Module 1 returns to normal baud rate with the same toggle function, the RXD1 pin
stays high. Both sequences are illustrated in Figures 19 and 20.
PREPARATION TO SLEEP MODE
The following sequence is applicable to both LIN Modules simultaneously or separately. Here it is detailed with the LIN Module
1.
To enter the Preparation to Sleep mode, EN1 must be low for a delay higher than tLWUE
.
• If the WAKE1 pin state doesn’t change during tSD and tLWUE, then the LIN Module 1 goes in Sleep Mode.
• If the WAKE1 pin state changes during tSD and if tWF is reached after end of tSD, then the LIN Module 1 goes into Sleep
mode after the end of tSD timing.
• If the WAKE1 pin state changes during tSD and tWF delay has been reached before end of tSD, then the LIN Module 1 goes
into Awake Mode.
• If the WAKE1 pin state changes before tSD and the delay tWF ends during tSD, then the LIN Module 1 goes in Awake Mode.
• If EN1 goes high for a delay higher than tLWUE, the LIN Module 1 returns in Normal mode.
SLEEP MODE
The following Sleep mode paragraph is applicable to both LIN Modules simultaneously or separately. LIN Module 1 is an
example.
To enter into Sleep mode, EN1 must be low for a delay longer than tSD and the WAKE1 pin must stay in the same state (High
or Low) during this delay. The LIN Module 1 conditions to not enter Sleep mode, but enter Awake mode are detailed in the
Preparation into Sleep Mode chapter. See Figure 23.
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
In Sleep mode, the transmission path is disabled and the LIN Module 1 is in Low Power mode. Supply current from VSUP is
very low. Wake-up can occur from LIN1 bus activity, from the EN1 pin and from the WAKE1 input pin. If during the preparation
to Sleep mode delay (tSD), the LIN1 bus goes low due to LIN1 network communication, the LIN Module 1 still enters Sleep mode.
The LIN Module 1 can be awakened by a recessive to dominant start, followed by a dominant to recessive state after t > tWUF
.
After a wake-up event, the LIN Module 1 enters into Awake mode. In Sleep mode, the LIN Module 1 internal 725 kOhm pull-
up resistor is connected and the 30 kOhm is disconnected.
DEVICE POWER-UP (Awake Transitional Mode)
At power-up (VSUP rises from zero), when VSUP is above the Power-On Reset voltage, both LIN Modules automatically switch
after a 160 µs delay time to the Awake transitional mode. Both INH pins (INH1 and INH2) go to a HIGH state and RXD1and RXD2
to a LOW state. See Figure 21.
DEVICE WAKE-UP EVENTS
The 33663L, 33663J and 33663S can be awakened from Sleep mode by three wake-up events:
• Remote wake-up via LIN1 and/or LIN2 bus activity
• Via the EN1 and/or EN2 pin
• Toggling the WAKE1 and/or WAKE2 pin
Remote Wake from LIN1, LIN2 Bus (Awake Transitional Mode)
Each LIN Transceiver is awakened by its LIN dominant pulse longer than tWUF. Dominant pulse means: a recessive to
dominant transition, wait for t > tWUF, then a dominant to recessive transition. This is illustrated in Figure 15. Once the wake-up
is detected (during the dominant to recessive transition), the LIN Module waken up by its LIN enters into Awake mode, with its
INH HIGH and RXD pulled LOW.
Once in the Awake mode, its EN pin has to be set to 3.3 V or 5.0 V (depending on the system) to enter into Normal mode.
Once in Normal mode, the LIN Module has to wait tFIRST_DOM delay before transmitting the first dominant bit.
Wake-up from EN1, EN2 pins
Each LIN Module can be awakened by a LOW to HIGH transition of its EN pin. When EN is switched from LOW to HIGH and
stays HIGH for a delay higher than tLWUE, the LIN Module is awakened and enters into Normal mode. See Figure 14. Once in
Normal mode, the LIN Module has to wait tFIRST_DOM delay before transmitting the first dominant bit.
Wake-up from WAKE1, WAKE2 Pins (Awake Transitional Mode)
Just before entering the Sleep mode, the WAKE pin state of the concerned LIN Module is stored. A change in the level longer
than the deglitcher time (70 µs maximum) will generate a wake-up, and the LIN Module enters into the Awake Transitional mode,
with its INH HIGH and RXD pulled LOW. See Figure 16. The LIN Module goes into Normal mode when its EN is switched from
LOW to HIGH and stays HIGH for a delay higher than tLWUE. Once in Normal mode, the LIN Module has to wait tFIRST_DOM delay
before transmitting the first dominant bit.
33663
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Freescale Semiconductor
29
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
FAIL-SAFE FEATURES
Tables 7 describes the 33663 protections.
Table 7. Fail Safe Features
RECOVERY
FUNCTIONALITY
MODE
FUNCTIONA
L MODE
RECOVERY
CONDITION
BLOCK
FAULT
CONDITION
FALLOUT
Device goes in Awake
mode whatever the
previous device mode
Power
Supply
Power on Reset
(POR)
VSUP < 3.5 V (min) then
power up
Condition
gone
All modes
No internal supplies
INH1 AND/OR
INH2 Thermal
Shutdown.
For the failed
LIN Module:
INH high side of the
failed LIN Moduleturned
off and its LIN
transmitter and receiver
in recessive State
INH1
INH2
Temperature > 160 °C
(typ)
Condition
gone
LIN Module returns in
same functional mode
Normal,
Awake &
Preparationto
Sleep modes
Each LIN Module
has its own INH
Thermal
Shutdown.
VSUP under-
voltage
Both LIN transmitters in
recessive state
Condition
gone
Device returns in same
functional mode
VSUP < VUVL
TXD1 AND/OR
TXD2 Pins
Permanent
Dominant
Normal
LIN transmitter of the
failed LIN Module in
recessive state
TXD pin low for more than
5.0 ms (typ)
Condition
gone
LIN Module returns in
same functional mode
LIN1
LIN2
LIN1 AND/OR
LIN2 Thermal
Shutdown.
LIN transmitter and
receiver of the failed LIN
Module in recessive
state and its INH high
side turned off
Normal mode
Temperature > 160 °C
(typ)
Condition
gone
LIN Module returns in
same functional mode
Each LIN Module
has its own LIN
Thermal
Shutdown.
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
EN1 HIGH TO LOW for t >tLWUE
Toggle Function (4)
Fast Baud Rate
(10x)
EN1 LOW TO HIGH for t>tLWUE
EN1 HIGH TO LOW for t>tLWUE
EN1 LOW TO HIGH for t> tLWUE
Internal WAKE1 (1)
State changes during tSD
LIN1
Preparation
to Sleep
Normal Baud Rate or
Slow Baud Rate
Awake
Toggle Function (4)
LIN1 bus dominant pulse
(2)
for t>tWUF
Or
Internal WAKE1 (1)
state doesn’t change
during tSD
WAKE1 pin state changes
(3)
for t>tWF
EN1 LOW TO HIGH for t>tLWUE
Sleep
LIN MODULE 1
VSUP > VPOR
Power-Up
EN2 HIGH TO LOW for t >tLWUE
Fast Baud Rate
(10x)
Toggle Function (4)
EN2 LOW TO HIGH for t >tLWUE
EN2 HIGH TO LOW for t >tLWUE
Internal WAKE2 (1)
State changes during tSD
LIN2
Preparation to
Sleep
Awake
Normal Baud Rate or
Toggle Function (4)
Slow Baud Rate
EN2 LOW TO HIGH for t> tLWUE
LIN2 bus dominant pulse
(2)
for t>tWUF
Or
WAKE2 pin state changes
Internal WAKE2 (1)
State doesn’t change
during tSD
(3)
for t>tWF
EN2 LOW TO HIGH for t>tLWUE
Sleep
LIN MODULE 2
(1):internal WAKE is the WAKE signal filtered by tWF (WAKE deglitcher)
(2):see figures 15 and 18
(3):see figures 14 and 17
(4):the Toogle Function is guaranteed at ambiant and hot temperature
Figure 25. Operational and Transitional Modes State
Table 7. Explanation of Operational and Transitional Modes State Diagram (each transceiver)
Operational/
Transitional
INH1
INH2
EN1
EN2
LIN1, LIN2
TXD1, TXD2
RXD1, RXD2
Recessive state, driver off with
725 k pull-up.
High-impedance. HIGH if
Sleep Mode
OFF
(low)
LOW
X
external pull-up to V
DD.
Recessive state, driver off.
725 k pull-up active.
LOW.
Awake
ON
LOW
X
X
If external pull-up, HIGH-to-LOW
transition reports wake-up.
(high)
Recessive state, driver off with
725 k pull-up
High-impedance. HIGH if
external pull-up to V
Preparation
to Sleep
Mode
ON
LOW
DD.
(high)
Driver active. 30 k pull-up
active.
Normal Baud Rate for 33662L
LOW to drive LIN bus in dominant Report LIN bus state:
Normal Mode
ON
HIGH
• Low LIN bus dominant
• High LIN bus recessive
HIGH to drive LIN bus in
(high)
recessive.
and 33662S
Slow Baud Rate for 33662J
Fast Baud Rate (> 100 kbps) for
33662L, 33662S & 33662J
X = Don’t care.
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31
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
COMPATIBILITY WITH LIN1.3
Following the Consortium LIN specification Package, Revision 2.1, November 24, 2006, Chapter 1.1.7.1 Compatibility with
LIN1.3 page 15:
The LIN 2.1 physical layer and is backward compatible with the LIN 1.3 physical layer, but not the other way around. The LIN
2.1 physical layer sets harder requirements, i.e. a node using the LIN 2.1 physical layer can operate in a LIN 1.3 cluster.
33663
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Freescale Semiconductor
TYPICAL APPLICATION
OPERATIONAL MODES
TYPICAL APPLICATION
The 33663 can be configured for several applications. The figure below shows LIN2 as a slave node and LIN1 as a master
node application. An additional pull-up resistor of 1.0 k in series with a diode must be added when the device is used in the
master node.
D1
C1
47μF
C2
100nF
VBAT
Regulator
VSUP
12V
R3
2.2k
INH2
EN1
5V or
3.3V
WAKE1
C3
R1
R2
18k
33663
100nF
18k
VDD
I/O
INH1
LIN
MODULE 1
VDD
*
D2
R6
1kꢀ
RXD1
TXD1
RXD1
TXD1
R6
2.2k
(LIN 1)
LIN1
LIN Bus1
MCU
EN2
I/O_2
WAKE2
VDD
*
LIN
C4
R4
18k
R5
18k
100nF
MODULE 2
RXD2
TXD2
RXD2
TXD2
(LIN 2)
LIN2
LIN Bus2
GND
*: Optional 2.2k if implemented
Figure 26. 33663 Typical Application
33663
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33
KAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and do a keyword search on the 98A.
Dimensions shown are provided for reference ONLY.
EF SUFFIX
14-PIN
98ASB42565B
REVISION J
33663
Analog Integrated Circuit Device Data
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Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EF SUFFIX
14-PIN
98ASB42565B
REVISION J
33663
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
SION HISTORY
REVISION HISTORY
REVISION
1.0
DATE
DESCRIPTION OF CHANGES
7/2012
12/2013
•
Initial Release.
•
•
Removed HBM row: INH1, INH2 pins versus GND - VESD1-3 - 8.0 k
Changed LIN dominant level with 500 680 and 1.0 k load on the LIN bus Max from 0.3 to
2.0
0.25
33663
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC33663
Rev. 2.0
12/2013
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