935314729557 [NXP]
RISC Microcontroller;
| 型号： | 935314729557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总60页 (文件大小：2056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K20P48M50SF0
Rev. 4 5/2012
Freescale Semiconductor
Data Sheet: Technical Data
K20P48M50SF0
K20 Sub-Family
Supports the following:
MK20DN32VLF5, MK20DX32VLF5,
MK20DN64VLF5, MK20DX64VLF5,
MK20DN128VLF5, MK20DX128VLF5,
MK20DN32VFT5, MK20DX32VFT5,
MK20DN64VFT5, MK20DX64VFT5,
MK20DN128VFT5, MK20DX128VFT5
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
•
•
•
– 128-bit unique identification (ID) number per chip
Analog modules
– 16-bit SAR ADC
– Two analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Performance
– Up to 50 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
– Up to 128 KB program flash.
Timers
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two-channel quadrature decoder/general purpose
timer
– Up to 32 KB FlexNVM on FlexMemory devices
– 2 KB FlexRAM on FlexMemory devices
– Up to 16 KB RAM
– Serial programming interface (EzPort)
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Clocks
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
Communication interfaces
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
– SPI module
– I2C module
•
System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– 4-channel DMA controller, supporting up to 41
request sources
– External watchdog monitor
– Software watchdog
– Three UART modules
– I2S module
– Low-leakage wakeup unit
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
5.4.1 Thermal operating requirements...........................21
5.4.2 Thermal attributes.................................................21
6 Peripheral operating requirements and behaviors....................22
6.1 Core modules....................................................................22
6.1.1 JTAG electricals....................................................22
6.2 System modules................................................................25
6.3 Clock modules...................................................................25
6.3.1 MCG specifications...............................................25
6.3.2 Oscillator electrical specifications.........................27
6.3.3 32 kHz Oscillator Electrical Characteristics...........29
6.4 Memories and memory interfaces.....................................30
6.4.1 Flash electrical specifications................................30
6.4.2 EzPort Switching Specifications............................34
6.5 Security and integrity modules..........................................35
6.6 Analog...............................................................................35
6.6.1 ADC electrical specifications.................................35
6.6.2 CMP and 6-bit DAC electrical specifications.........40
6.6.3 Voltage reference electrical specifications............43
6.7 Timers................................................................................44
6.8 Communication interfaces.................................................44
6.8.1 USB electrical specifications.................................44
6.8.2 USB DCD electrical specifications........................45
6.8.3 USB VREG electrical specifications......................45
6.8.4 DSPI switching specifications (limited voltage
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
3 Terminology and guidelines......................................................4
3.1 Definition: Operating requirement......................................4
3.2 Definition: Operating behavior...........................................5
3.3 Definition: Attribute............................................................5
3.4 Definition: Rating...............................................................6
3.5 Result of exceeding a rating..............................................6
3.6 Relationship between ratings and operating
requirements......................................................................6
3.7 Guidelines for ratings and operating requirements............7
3.8 Definition: Typical value.....................................................7
3.9 Typical value conditions....................................................8
4 Ratings......................................................................................9
4.1 Thermal handling ratings...................................................9
4.2 Moisture handling ratings..................................................9
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings...............................9
5 General.....................................................................................10
5.1 AC electrical characteristics..............................................10
5.2 Nonswitching electrical specifications...............................11
5.2.1 Voltage and current operating requirements.........11
5.2.2 LVD and POR operating requirements.................11
5.2.3 Voltage and current operating behaviors..............12
5.2.4 Power mode transition operating behaviors..........13
5.2.5 Power consumption operating behaviors..............14
5.2.6 EMC radiated emissions operating behaviors.......18
5.2.7 Designing with radiated emissions in mind...........19
5.2.8 Capacitance attributes..........................................19
5.3 Switching specifications.....................................................19
5.3.1 Device clock specifications...................................19
5.3.2 General switching specifications...........................20
5.4 Thermal specifications.......................................................21
range)....................................................................46
6.8.5 DSPI switching specifications (full voltage range).47
6.8.6 I2C switching specifications..................................49
6.8.7 UART switching specifications..............................49
6.8.8 I2S/SAI Switching Specifications..........................49
6.9 Human-machine interfaces (HMI)......................................54
6.9.1 TSI electrical specifications...................................54
7 Dimensions...............................................................................55
7.1 Obtaining package dimensions.........................................55
8 Pinout........................................................................................56
8.1 K20 Signal Multiplexing and Pin Assignments..................56
8.2 K20 Pinouts.......................................................................58
9 Revision History........................................................................58
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK20 and MK20 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K20
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
3
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• ML = 104 MAPBGA (8 mm x 8 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK20DN32VLF5
3 Terminology and guidelines
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
8
Freescale Semiconductor, Inc.
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
2
TSDR
Solder temperature, lead-free
—
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
9
General
Symbol
IDD
VDIO
Description
Min.
Max.
Unit
Digital supply current
—
155
mA
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
–0.3
VDD + 0.3
VDD + 0.3
25
V
V
Analog1, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all port pins)
Analog supply voltage
VAIO
ID
–25
mA
V
VDDA
VDD – 0.3
–0.3
VDD + 0.3
3.63
VUSB_DP
VUSB_DM
VREGIN
VBAT
USB_DP input voltage
V
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
10
Freescale Semiconductor, Inc.
General
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
–0.1
–0.1
1.71
3.6
0.1
0.1
3.6
V
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
—
V
I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
1
mA
-3
—
—
+3
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
11
General
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
12
Freescale Semiconductor, Inc.
General
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
100
mA
Input leakage current (per pin)
• @ full temperature range
• @ 25 °C
—
—
1.0
0.1
μA
μA
1
IOZ
IOZ
Hi-Z (off-state) leakage current (per pin)
Total Hi-Z (off-state) leakage current (all input pins)
Internal pullup resistors
—
—
22
22
1
4
μA
μA
kΩ
kΩ
RPU
RPD
50
50
2
3
Internal pulldown resistors
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
13
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
Unit
Notes
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
—
—
—
—
—
—
—
130
130
70
μs
μs
μs
μs
μs
μs
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
70
6
5.2
5.2
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
—
—
13.7
13.9
15.1
15.3
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
16.1
18.2
mA
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
—
16.3
16.7
17.7
18.4
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
7.5
5.6
8.4
6.4
mA
mA
2
5
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
14
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
867
—
μA
6
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
1.1
—
—
mA
μA
7
8
IDD_VLPW Very-low-power wait mode current at 3.0 V
509
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
310
384
629
426
458
μA
μA
μA
• @ 70°C
1100
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
3.5
20.7
85
22.6
52.9
220
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
2.1
7.7
3.7
43.1
68
μA
μA
μA
• @ 70°C
32.2
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
1.5
4.8
20
2.9
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
22.5
37.8
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
1.4
4.1
2.8
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
19.2
32.4
17.3
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
0.678
2.8
1.3
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
13.6
24.5
13.6
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
—
—
—
0.367
2.4
1.0
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
13.3
24.1
13.2
• @ 105°C
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
—
—
—
0.176
2.2
0.859
13.1
23.9
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
13
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
• @ 105°C
IDD_VBAT Average current when CPU is not accessing
RTC registers
9
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.57
0.90
2.4
0.67
1.2
μA
μA
μA
• @ 105°C
• @ 3.0V
3.5
• @ –40 to 25°C
• @ 70°C
—
—
—
0.67
1.0
0.94
1.4
μA
μA
μA
• @ 105°C
2.7
3.9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral
clocks disabled.
3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash.
7. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode
• USB regulator disabled
• No GPIOs toggled
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
16
Freescale Semiconductor, Inc.
General
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
Figure 2. Run mode supply current vs. core frequency
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
17
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64LQFP
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
19
21
19
11
L
dBμV
dBμV
dBμV
dBμV
—
1 , 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
18
Freescale Semiconductor, Inc.
General
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
50
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
Bus clock
—
—
—
50
25
25
MHz
MHz
MHz
fFLASH
fLPTMR
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
4
4
MHz
MHz
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
19
General
Table 9. Device clock specifications (continued)
Symbol
fFLASH
fERCLK
Description
Min.
Max.
Unit
Notes
Flash clock
—
1
MHz
External reference clock
LPTMR clock
—
—
—
—
—
16
25
MHz
MHz
MHz
MHz
MHz
fLPTMR_pin
fLPTMR_ERCLK LPTMR external reference clock
16
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
50
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
13
7
ns
ns
• Slew enabled
—
—
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
36
24
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
20
Freescale Semiconductor, Inc.
General
Table 10. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
Port rise and fall time (low drive strength)
• Slew disabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
—
—
12
6
ns
ns
—
—
36
24
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75pF load
5. 15pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
48 LQFP
48 QFN
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
70
81
°C/W
1, 2
ambient (natural
convection)
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
47
28
°C/W
1, 3
ambient (natural
convection)
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Board type
Symbol
Description
48 LQFP
48 QFN
Unit
Notes
Single-layer
(1s)
RθJMA
Thermal
resistance,
58
66
°C/W
1,3
junction to
ambient (200 ft./
min. air speed)
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
40
24
23
11
°C/W
°C/W
,
—
RθJB
Thermal
resistance,
junction to
board
5
—
—
RθJC
Thermal
resistance,
junction to case
18
3
1.4
4
°C/W
°C/W
6
7
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
2.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
3.
5.
6.
7.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.1.1 JTAG electricals
Table 12. JTAG voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
TCLK frequency of operation
• JTAG
2.7
5.5
J1
MHz
—
—
10
5
• CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• JTAG
1/J1
—
ns
100
200
—
—
ns
ns
ns
ns
ns
• CJTAG
J4
J5
TCLK rise and fall times
—
1
TMS input data setup time to TCLK rise
53
112
8
—
—
—
• JTAG
• CJTAG
J6
J7
TDI input data setup time to TCLK rise
ns
ns
TMS input data hold time after TCLK rise
3.4
3.4
3.4
—
—
—
• JTAG
• CJTAG
J8
J9
TDI input data hold time after TCLK rise
ns
ns
TCLK low to TMS data valid
• JTAG
—
—
—
—
48
85
48
3
• CJTAG
J10
J11
TCLK low to TDO data valid
ns
ns
Output data hold/invalid time after clock edge1
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
J2
J3
J3
TCLK (input)
J4
J4
Figure 4. Test clock input timing
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 5. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 6. Test Access Port timing
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 7. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
3
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
kHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
—
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
ffll_ref FLL reference frequency range
fdco
Min.
Typ.
Max.
Unit
Notes
31.25
—
39.0625
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20
40
60
80
—
—
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
25
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
• fvco = 48 MHz
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
8
• fvco = 48 MHz
• fvco = 100 MHz
—
—
1350
600
—
—
ps
ps
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
%
%
s
150 × 10-6
+ 1075(1/
tpll_lock
9
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 14. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
—
—
8
MHz
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32 kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 16. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
100
—
MΩ
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 16. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
Vpp
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32kHz oscillator frequency specifications
Table 17. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
fec_extal32
vec_extal32
Oscillator crystal
Crystal start-up time
—
—
1
2
Externally provided input clock frequency
Externally provided input clock amplitude
—
—
kHz
mV
VBAT
700
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 18. NVM program/erase timing specifications
Symbol Description
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
7.5
18
μs
—
—
—
13
52
52
113
452
452
ms
ms
ms
1
1
1
thversblk32k Erase Block high-voltage time for 32 KB
thversblk128k Erase Block high-voltage time for 128 KB
1. Maximum time based on expectations at cycling end-of-life.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 19. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk32k
• 32 KB data flash
—
—
—
—
0.5
1.7
ms
ms
• 128 KB program flash
trd1blk128k
trd1sec1k
tpgmchk
trdrsrc
Read 1s Section execution time (flash sector)
Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
1
Read Resource execution time
30
tpgm4
Program Longword execution time
145
Erase Flash Block execution time
• 32 KB data flash
2
2
tersblk32k
—
—
55
61
465
495
ms
ms
• 128 KB program flash
tersblk128k
tersscr
Erase Flash Sector execution time
—
14
114
ms
Program Section execution time
• 512 B flash
tpgmsec512
tpgmsec1k
—
—
4.7
9.3
—
—
ms
ms
• 1 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
65
115
—
—
tersall
Erase All Blocks execution time
1000
30
2
1
tvfykey
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
• 32 KB FlexNVM
tpgmpart32k
—
70
—
ms
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram8k
tsetram32k
—
—
—
50
0.3
0.7
—
μs
ms
ms
• 8 KB EEPROM backup
• 32 KB EEPROM backup
0.5
1.0
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b8k
teewr8b16k
teewr8b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 19. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b8k
teewr16b16k
teewr16b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b8k
teewr32b16k
teewr32b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
545
630
810
1950
2050
2250
μs
μs
μs
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 20. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 21. NVM reliability specifications (continued)
Typ.1
Symbol Description
Min.
Max.
—
Unit
years
cycles
Notes
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
20
10 K
100
50 K
—
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
Write endurance
5
50
—
—
years
years
20
100
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 8192
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
20 M
100 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical values
assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash
memory module to obtain an effective endurance increase for the EEPROM data. The
built-in EEPROM record management system raises the number of program/erase cycles
that can be attained prior to device wear-out by cycling the EEPROM data through a
larger EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESIZE
Writes_FlexRAM =
× Write_efficiency × nnvmcycd
where
• Writes_FlexRAM — minimum number of writes to each FlexRAM location
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
• EEPROM — allocated FlexNVM based on DEPART; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000
cycles)
Figure 8. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
—
fSYS/2
MHz
READ)
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
17
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EZP_CS
EP3
EP4
EP2
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VADIN
CADIN
Input voltage
VREFH
V
Input
capacitance
• 16 bit modes
—
—
8
4
10
5
pF
• 8/10/12 bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13 bit modes
clock frequency
4
4
5
1.0
2.0
—
—
—
18.0
12.0
MHz
MHz
Ksps
ADC conversion 16 bit modes
clock frequency
ADC conversion ≤ 13 bit modes
rate
No ADC hardware
20.000
818.330
averaging
Continuous
conversions enabled,
subsequent conversion
time
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion 16 bit modes
rate
5
No ADC hardware
37.037
—
461.467
Ksps
averaging
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 10. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
• ADLPC=1, ADHSC=0
Typ.2
2.4
Symbol Description
Min.
1.2
3.0
2.4
4.4
Max.
3.9
Unit
Notes
ADC
asynchronous
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
4.0
7.3
clock source
fADACK
5.2
6.1
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
LSB4
LSB4
TUE
DNL
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
—
4
6.8
2.1
5
5
1.4
Differential non-
linearity
• 12 bit modes
—
0.7
-1.1 to
+1.9
-0.3 to 0.5
• <12 bit modes
• 12 bit modes
—
—
0.2
1.0
LSB4
INL
EFS
Integral non-
linearity
-2.7 to
+1.9
5
-0.7 to
+0.5
• <12 bit modes
—
0.5
LSB4
LSB4
Full-scale error
• 12 bit modes
• <12 bit modes
—
—
-4
-5.4
-1.8
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16 bit differential mode
6
of bits
• Avg=32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg=4
16 bit single-ended mode
• Avg=32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg=4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
—
—
–94
-85
—
—
dB
dB
16 bit single-ended mode
• Avg=32
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
7
82
95
—
dB
16 bit single-ended mode
• Avg=32
78
90
—
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
25°C
—
—
1.715
719
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 25. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
IDDLS
VAIN
VAIO
VH
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
—
—
—
—
200
20
μA
μA
V
VSS – 0.3
—
VDD
20
Analog input offset voltage
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 Voltage reference electrical specifications
Table 26. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
105
°C
nF
Output load capacitance
100
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
Table 27. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 27. VREF full-range operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
Voltage reference output — user trim
Voltage reference trim step
1.193
—
—
0.5
—
1.197
—
V
Vstep
Vtdrift
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 28. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 29. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 30. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
VLGC
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
7
—
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.33
6.8.3 USB VREG electrical specifications
Table 31. USB VREG electrical specifications
Typ.1
Symbol Description
Min.
2.7
—
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
—
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
1.54
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
Table 31. USB VREG electrical specifications
(continued)
Typ.1
Symbol Description
Min.
1.76
1
Max.
8.16
100
Unit
μF
Notes
COUT
ESR
External output capacitor
2.2
External output capacitor equivalent series
resistance
—
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 32. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
ns
(tBUS x 2) −
2
—
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
0
8
ns
ns
ns
ns
—
—
—
14
0
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 15. DSPI classic SPI timing — master mode
Table 33. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
14
14
2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 16. DSPI classic SPI timing — slave mode
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
6.8.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
(tBUS x 2) −
4
—
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-1.2
19.1
0
8.5
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 17. DSPI classic SPI timing — master mode
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 35. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
24
—
—
—
19
19
3.2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 18. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.6
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
6.8.8 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.8.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 36. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 19. I2S/SAI timing — master modes
Table 37. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
10
2
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
29
—
—
—
21
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 20. I2S/SAI timing — slave modes
6.8.8.2 VLPR, VLPW, and VLPS mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 38. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
250
45%
—
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 21. I2S/SAI timing — master modes
Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
30
3
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
63
—
—
—
72
ns
ns
ns
ns
ns
30
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
53
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 22. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 40. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
Electrode oscillator frequency
Internal reference capacitor
Oscillator delta voltage
1
20
8
500
15
pF
MHz
MHz
pF
1
fREFmax
fELEmax
CREF
—
—
—
—
2, 3
2, 4
1
1.8
—
1
VDELTA
IREF
500
—
mV
μA
2, 5
2, 6
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
—
—
2
3
36
50
• 32 μA setting (REFCHRG = 15)
IELE
Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
μA
2, 7
—
—
2
3
36
50
• 32 μA setting (EXTCHRG = 15)
Pres5
Electrode capacitance measurement precision
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
1.46
38400
38400
38400
—
fF/count
fF/count
fF/count
fF/count
bits
8
9
Pres20
—
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
10
11
0.008
—
Res
Resolution
—
16
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
54
Freescale Semiconductor, Inc.
Dimensions
Table 40. TSI electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
TCon20
Response time @ 20 pF
8
15
25
μs
12
ITSI_RUN Current added in run mode
—
—
55
—
μA
μA
ITSI_LP
Low power mode current adder
1.3
2.5
13
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
I
ext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
ext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
I
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
48-pin LQFP
Then use this document number
98ASH00962A
48-pin QFN
98ARH99048A
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
55
Pinout
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
-QFN
1
2
VDD
VDD
VDD
VSS
VSS
VSS
3
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
VDDA
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
VDDA
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
VDDA
4
5
6
7
8
9
10
11
12
13
VREFH
VREFH
VREFH
VREFL
VREFL
VREFL
VSSA
VSSA
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
14
15
16
17
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_
b/
UART0_COL_b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
18
19
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_SWO/
EZP_DO
JTAG_TDO/
TRACE_SWO
EZP_DO
20
21
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_b FTM0_CH0
FTM0_CH1
JTAG_TMS/
SWD_DIO
PTA4/
NMI_b/
PTA4/
NMI_b
EZP_CS_b
LLWU_P3
EZP_CS_b
LLWU_P3
22
23
VDD
VSS
VDD
VSS
VDD
VSS
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
56
Freescale Semiconductor, Inc.
Pinout
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
-QFN
24
25
26
27
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
PTA19
XTAL0
XTAL0
PTA19
LPTMR0_ALT1
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_QD_
PHA
28
29
30
PTB1
PTB2
PTB3
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
PTB2
PTB3
FTM1_CH1
FTM1_QD_
PHB
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
UART0_RTS_b
FTM0_FLT3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
UART0_CTS_
b/
FTM0_FLT0
UART0_COL_b
31
32
33
PTB16
PTB17
PTC0
TSI0_CH9
TSI0_CH9
PTB16
PTB17
PTC0
UART0_RX
UART0_TX
EWM_IN
TSI0_CH10
TSI0_CH10
EWM_OUT_b
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_EXTRG
34
35
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_b FTM0_CH0
UART1_CTS_b FTM0_CH1
I2S0_TXD0
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
I2S0_TX_FS
36
37
38
39
40
41
PTC3/
LLWU_P7
CMP1_IN1
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
DISABLED
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_RX
FTM0_CH2
I2S0_TX_BCLK
CMP1_OUT
CMP0_OUT
I2S0_MCLK
PTC4/
LLWU_P8
PTC4/
LLWU_P8
UART1_TX
FTM0_CH3
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_ALT2
PDB0_EXTRG
I2S0_RXD0
I2S0_RX_BCLK
I2S0_RX_FS
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PTC7
PTC7
USB_SOF_
OUT
PTD0/
PTD0/
SPI0_PCS0
UART2_RTS_b
LLWU_P12
LLWU_P12
42
43
PTD1
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_b
UART2_RX
PTD2/
PTD2/
SPI0_SOUT
LLWU_P13
LLWU_P13
44
45
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
UART2_TX
PTD4/
PTD4/
SPI0_PCS1
UART0_RTS_b FTM0_CH4
EWM_IN
LLWU_P14
LLWU_P14
46
PTD5
ADC0_SE6b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI0_PCS2
UART0_CTS_
b/
UART0_COL_b
FTM0_CH5
EWM_OUT_b
47
48
PTD6/
LLWU_P15
ADC0_SE7b
DISABLED
PTD6/
LLWU_P15
SPI0_PCS3
CMT_IRO
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
FTM0_FLT0
FTM0_FLT1
PTD7
PTD7
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
57
Revision History
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
PTC3/LLWU_P7
PTC2
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC1/LLWU_P6
PTC0
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
VDDA
3
4
PTB17
5
PTB16
6
PTB3
7
PTB2
8
PTB1
9
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
10
11
12
VREFL
VSSA
Figure 23. K20 48 LQFP/QFN Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
58
Freescale Semiconductor, Inc.
Revision History
Table 41. Revision History
Rev. No.
Date
2/2012
4/2012
Substantial Changes
2
3
Initial public release
• Replaced TBDs throughout.
• Updated "Power mode transition operating behaviors" table.
• Updated "Power consumption operating behaviors" table.
• For "Diagram: Typical IDD_RUN operating behavior" section, added "VLPR mode
supply current vs. core frequency" figure.
• Updated "EMC radiated emissions operating behaviors" section.
• Updated "Thermal operating requirements" section.
• Updated "MCG specifications" table.
• Updated "VREF full-range operating behaviors" table.
• Updated "I2S/SAI Switching Specifications" section.
• Updated "TSI electrical specifications" table.
4
5/2012
• For the "32kHz oscillator frequency specifications", added specifications for an
externally driven clock.
• Renamed section "Flash current and power specfications" to section "Flash high
voltage current behaviors" and improved the specifications.
• For the "VREF full-range operating behaviors" table, removed the Ac (aging coefficient)
specification.
• Corrected the following DSPI switching specifications: tightened DS5, DS6, and DS7;
relaxed DS11 and DS13.
• For the "TSI electrical specifications", changed and clarified the example calculations
for the MaxSens specification.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
59
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Document Number: K20P48M50SF0
Rev. 4 5/2012
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