935314839557 [NXP]

Microcontroller;


型号：	935314839557
厂家：	NXP
描述：	Microcontroller 微控制器外围集成电路
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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5645S

Rev. 13, 04/2015

MPC5645S

208 LQFP

28 mm × 28 mm

416 TEPBGA

27 mm × 27 mm

Qorivva MPC5645S

Microcontroller Data Sheet

176 LQFP

24 mm × 24 mm

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1 176 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 24

2.2 208 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 25

2.3 416 TEPBGA package pinout. . . . . . . . . . . . . . . . . . . . 26

2.4 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

System design information. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.1 Power-up sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . 59

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 60

4.4 Recommended operating conditions . . . . . . . . . . . . . . 62

4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 64

4.6 EMI (electromagnetic interference) characteristics . . . 69

4.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.8 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . . 74

4.9 SSD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.10 RESET electrical characteristics . . . . . . . . . . . . . . . . . 84

4.11 Fast external crystal oscillator (4–16 MHz) electrical

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.12 Slow external crystal oscillator (32 KHz) electrical

The Qorivva MPC5645S represents a new generation of

32-bit microcontrollers targeting single-chip automotive

instrument cluster applications. MPC5645S devices are part

of the MPC56xxS family of Power Architecture -based

devices. This family has been designed with an emphasis on

providing cost-effective and high quality graphics capabilities

in order to satisfy the increasing market demand for color

Thin Film Transistor (TFT) displays within the vehicle

cockpit. Traditional cluster functions, such as gauge drive,

real time counter, and sound generation are also integrated on

each device.

Devices in the MPC56xxS family contain between 256 KB

and 2 MB internal flash memory. The family allows for easy

expansion and covers a broad range of cluster applications

from low to high-end enabling users to design a complete

platform around one common architecture. Serial flash

memory and DRAM interfaces are provided to allow even

greater system flexibility.

The MPC5645S is designed to reduce development and

production costs of TFT-based instrument cluster displays by

providing a single-chip solution with the processing and

storage capacity to host and execute real-time application

software and drive TFT displays directly.

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.13 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 89

4.14 Fast internal RC oscillator (16 MHz) electrical

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.15 Slow internal RC oscillator (128 kHz) electrical

The MPC5645S features a 2D OpenVG graphics accelerator,

Video Input Unit (VIU2) and two on-chip display control

units (DCU3 and DCULite) designed to drive two color TFT

displays simultaneously. The MPC5645S includes an

enhanced QuadSPI Serial Flash Controller and an optional

DRAM controller allowing graphics RAM expansion

externally.

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.16 Flash memory electrical characteristics . . . . . . . . . . . . 91

4.17 ADC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.19 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.2 208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.3 416 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

The MPC5645S is compatible with the existing development

infrastructure of current Power Architecture devices and are

supported with software drivers, operating systems and

configuration code to assist with application development.

Overview

1.1

Device comparison

Table 1. MPC5645S device comparison

Feature

MPC5645S

Package

CPU

208 LQFP

416 TEPBGA

176 LQFP

e200z4d

4 KB Instruction-Cache

16-entry Memory Management Unit (MMU)

Floating Point Unit (FPU)

Signal Processing Extension (SPE)

Execution speed

Flash memory (ECC)

RAM (ECC)

Static–125 MHz

2 MB

64 KB

On-chip graphics RAM (no ECC)

MPU

1 MB

16 entry

eDMA

16 channels

DRAM controller

Yes

OpenVG Graphics Accelerator

(GFX2D)

Yes (OpenVG 1.1)

Display Control Unit (DCU3)

Yes

Display Control Unit Lite (DCULite)

Timing Controller (TCON) and RSDS

interface

Video Input Unit (VIU2)

Yes

QuadSPI serial flash interface

Stepper Motor Controller (SMC)

Stepper Stall Detect (SSD)

Yes

4 motors

6 motors

Yes

Sound Generator Module (SGM)

32 kHz external crystal oscillator

Yes

Real Time Counter and Autonomous

Periodic Interrupt (RTC/API)

Yes

Periodic interrupt timer (PIT)

Software Watchdog Timer (SWT)

System Timer Module (STM)

Timed I/O¹

8 ch, 32-bit

Yes

4 ch, 32-bit

20 ch, 16-bit: IC / OC / OPWM

8 ch, 16-bit: IC / OC

4 ch, 16-bit: IC / OC / OPWM / QDEC

Analog-to-Digital Converter (ADC)²

16 channels, 10-bit

20 channels, 10-bit

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 1. MPC5645S device comparison (continued)

MPC5645S

Feature

Package

208 LQFP

416 TEPBGA

176 LQFP

CAN (64 mailboxes)

3 × FlexCAN

Yes

CAN sampler

Serial communication interface

3 × LINFlex

2 × DSPI

4 × LINFlex

3 × DSPI

SPI

I²C

GPIO

Debug

128

150

177³

Nexus Class 3 (12×MDO)

Nexus Class 3 (4×MDO)⁴

IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation, QDEC- Quadrature Decode Mode

Support for external multiplexer enabling up to 8 channels

The 416-pin GPIO count does not include the DRAM interface, which is dedicated to DRAM only.

Nexus pins are multiplexed with other functional pins on 176 LQFP and 208 LQFP package options.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

1.2

Block diagram

System

integration

Debug

Crossbar switch masters

e200z4d

JTAG

VReg

Oscillator

FMPLL 0

FMPLL 1

RTC/32Kosc

INTC

Nexus 3+

GFX2D

DCULite

TCON / RSDS

MMU

I-CACHE

VIU2

DCU3

eDMA

Crossbar Switch

Memory Protection Unit

PIT

Flash

memory

SRAM

64 KB

Graphics

SRAM

STM

PBRIDGE

QuadSPI

2 MB

1 MB

DRAM interface

SWT

BAM

EEE

RLE decoder

Crossbar switch slaves

Communication I/O system

SSD

ADC

BAM

eDMA

DCU3

– Analog-to-Digital Converter

– Boot Assist Module

– Enhanced Direct Memory Access Controller

– Display Control Unit

PBRIDGE – Peripheral Bridge

PIT

RLE

– Periodic Interrupt Timer

– Run Length Encoding

RSDS

RTC

SGM

SMC

SSD

STM

SWT

TCON

VIU2

VReg

– Reduced-Swing Differential Signal interface

– Real Time Clock

– Sound Generator Module

– Stepper Motor Controller

– Stepper Stall Detect

– System Timer Module

– Software Watchdog Timer

– Timing Controller

DCULite – Display Control Unit Lite

DSPI

eMIOS

– Serial Peripherals Interface

– Enhanced Modular Input/Output System

FlexCAN – Controller Area Network Controller

FMPLL

GFX2D

INTC

JTAG

MMU

– Frequency-Modulated Phase-Locked Loop

– OpenVG Graphics Accelerator

– Interrupt Controller

– Joint Test Action Group interface

– Memory Management Unit

– Video Input Unit

– Voltage regulator

QuadSPI – Quad IO serial flash interface

Figure 1. MPC5645S block diagram

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

1.3

Feature list

•

Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d)

— Memory Management Unit (MMU)

— 4 KB, 2/4-way instruction cache

•

2 MB on-chip ECC flash memory with:

— Flash memory controller

— Prefetch buffers

•

64 KB on-chip ECC SRAM

1 MB on-chip non-ECC graphics SRAM with two-port graphics SRAM controller

Memory Protection Unit (MPU) with up to 16 region descriptors and 32-byte region granularity to provide basic

memory access permission and ensure separation between different codes and data

•

Interrupt Controller (INTC) with 163 peripheral interrupt sources and eight software interrupts

Two Frequency-Modulated Phase-Locked Loops (FMPLLs)

— Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz

— Auxiliary FMPLL (FMPLL1) is available for use as an alternate, modulated or non-modulated clock source to

eMIOS modules, QuadSPI and as alternate clock to the DCU and DCU-Lite for pixel clock generation

•

Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus

masters

16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA

channel multiplexer

Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code supports boot options including

download of boot code via a serial link (CAN or SCI)

Two Display Control Units (DCU3 and DCULite) for direct drive of up to two TFT LCD displays up to XGA

resolution

•

Timing Controller (TCON) and RSDS interface for the DCU3 module

2D OpenVG 1.1 and raster graphics accelerator (GFX2D)

Video Input Unit (VIU2) supporting 8/10-bit ITU656 video input, YUV to RGB conversion, video down-scaling,

de-interlacing, contrast adjustment and brightness adjustment.

•

DRAM controller supporting DDR1, DDR2, and LPDDR1 DRAMs

Stepper Motor Controller (SMC)

— High-current drivers for up to six instrument cluster gauges driven in full dual H-bridge configuration

— Stepper motor return-to-zero and stall detection module

— Stepper motor short circuit detection

•

Sound Generator Module (SGM)

— 4-channel mixer

— Supports PCM wave playback and synthesized tones

— Optional PWM or I S outputs

•

Two 16-channel Enhanced Modular Input Output System (eMIOS) modules

— Support a range of 16-bit Input Capture, Output Compare, Pulse Width Modulation and Quadrature Decode

functions

10-bit Analog-to-Digital Converter (ADC) with a maximum conversion time of 1 μs

— Up to 20 internal channels

— Up to 8 external channels

•

Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with

external devices

QuadSPI serial flash memory controller

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

— Supports single, dual and quad IO serial flash memory

— Interfaces to external, memory-mapped serial flash memories

— Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth

RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA

Four local interconnect network (LINFlex) controller modules

•

— Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART

support

— Compliant with LIN protocol rev 2.1

Three controller-area network (FlexCAN) modules

— Compliant with the CAN protocol version 2.0 C

— 64 configurable buffers

•

— Programmable bit rate of up to 1 Mb/s

•

Four Inter-Integrated Circuit (I C) internal bus controllers with master/slave bus interface

Low-power loop controlled pierce crystal oscillator supporting 4–16MHz external crystal or resonator

Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous

wake-up with 1 ms resolution with maximum timeout of 2 seconds

— Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting

wake-up with 1 s resolution and maximum timeout of one hour

— RTC optionally clocked by fast 4–16 MHz external oscillator

System timers:

•

— Four-channel 32-bit System Timer Module (STM)

— Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger)

— Software Watchdog Timer (SWT)

•

System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control

System Status and Configuration Module (SSCM)

— Provides information for identification of the device, last boot mode, or debug status

— Provides an entry point for the censorship password mechanism

•

Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,

enabling access to all clock sources

Clock Monitor Unit (CMU)

— Monitors the integrity of the fast (4–16 MHz) external crystal oscillator and the primary FMPLL (FMPLL0)

— Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock

Mode Entry Module (MC_ME)

•

— Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY

— Controls mode transition sequences

— Manages the power control, voltage regulator, clock generation and clock management modules

Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains

Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up

Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features:

— Watchpoint Triggering

•

— Processor Overrun Control

•

Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)

On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires

external ballast transistor)

•

Package:

— 176 LQFP, 0.5 mm pitch, 24 mm × 24 mm outline

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

— 208 LQFP, 0.5 mm pitch, 28 mm × 28 mm outline

— 416 TEPBGA, 1mm ball pitch, 27 mm × 27 mm outline

1.4

Feature details

1.4.1

Low-power operation

The MPC5645S is designed for optimized low-power operation and dynamic power management of the CPU and peripherals.

Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize

leakage in low-power modes.

There are three low-power modes:

•

STANDBY

STOP

HALT

and five dynamic power modes — RUN[0..3] and DRUN. All low-power modes use clock gating to halt the clock for all or part

of the device.

STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode.

The device can be awakened from STANDBY mode via from any of up to 23 I/O pins, a reset or from a periodic wake-up using

a low power oscillator. If required, it is possible to enable the internal 16 MHz oscillator, the external 4–16 MHz oscillator, and

the external 32 KHz oscillator.

In STANDBY mode the contents of the CPU, on-chip peripheral registers, and potentially some of the volatile memory are lost.

The two possible configurations in STANDBY mode are:

•

The device retains 64 KB of the on-chip SRAM, but the content of the graphics SRAM is lost.

The device retains 8 KB of the on-chip SRAM, but the content of the graphics SRAM is lost.

STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a

faster recovery low power mode than the lowest-power STANDBY mode. There is no need to reconfigure the device before

executing code. The clocks to the CPU and peripherals are halted and can be optionally stopped to the oscillator or PLL at the

expense of a slower start-up time.

STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic

wake-up, if enabled.

RUN modes are the main operating modes where the entire device can be powered and clocked and from which most processing

activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN

modes enables different clocks and power configurations to be supported with respect to each other and to allow switching

between different operating conditions. The necessary peripherals, clock sources, clock speed, and system clock prescalers can

be independently configured for each of the four RUN modes of the device.

HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the

CPU system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more

efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency.

The system returns to RUN mode as soon as an event or interrupt is pending.

The following table summarizes the operating modes of the MPC5645S.

1. See the device comparison table for package offerings for each device in the family.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 2. Operating mode summary

Clock sources

SoC features

Wake-up time¹

RUN

Off

OP OP OP²On OP OP On OP On OP

OP OP OP²On OP OP On OP On OP OP OP FP

—

HALT

STOP

30 µs ³

CG CG OP²CG CG CG OP OP On OP OP OP LP 350 µs 4 µs 20 µs 1 ms 200 µs — 30 µs ³

STAND

Off Off 64K Off Off Off OP OP On OP OP OP LP 350 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs

Off

Off Off 8K⁵Off Off Off OP OP On OP OP OP LP 200 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs

POR

500 µs 8 µs 100 µs 1 ms 200 µs

BAM⁶

Table key:

• On — Powered and clocked

• OP — Optionally configurable to be enabled or disabled (clock gated)

• CG — Clock Gated, Powered but clock stopped

• Off — Powered off and clock gated

• FP — VREG Full Performance mode

• LP — VREG Low Power mode, reduced output capability of VREG but lower power consumption

• Var — Variable duration, based on the required reconfiguration and execution clock speed

• BAM — Boot Assist Module Software and Hardware used for device start-up and configuration

A high level summary of some key durations that need to be considered when recovering from low power modes. This

does not account for all durations at wake up. Other delays will be necessary to consider including, but not limited to the

external supply start-up time.

IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.

All other wake-up times must be added to determine the total start-up time.

Either 64 KB or 8 KB available.

Flash configured in disabled mode.

64 KB of the RAM contents is retained, but not accessible in STANDBY mode.

8 KB of the RAM contents is retained, but not accessible in STANDBY mode.

Dependent on boot option after reset.

Additional notes on low power operation:

•

Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low

power modes

•

The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected

as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external

oscillator delay

•

The device includes an internal voltage regulator that includes the following features:

— Regulates input to generate all internal supplies

— Manages power gating

— External ballast transistor for high power regulator

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

— Low-Power and Ultra-Low-Power regulators support operation when in STOP and STANDBY modes,

respectively, to minimize power consumption

— Startup on-chip regulators in <350μs for rapid exit of STOP and STANDBY modes

— Low voltage detection on main supply and 1.2 V regulated supplies

1.4.2

e200z4d core

The e200z4d Power Architecture core provides the following features:

•

Dual issue, 32-bit Power Architecture Book E compliant CPU

Implements the VLE APU for reduced code footprint

In-order execution and retirement

Precise exception handling

Branch processing unit

— Dedicated branch address calculation adder

— Branch target prefetching using 8-entry BTB

•

Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory

via independent Instruction and Data BIUs.

Load/store unit

— 2 cycle load latency

— Fully pipelined

— Big and Little endian support

— Misaligned access support

•

64-bit General Purpose Register file

Dual AHB 2.v6 64-bit System buses

Memory Management Unit (MMU) with 16-entry fully-associative TLB and multiple page size support

4 KB, 2/4-Way Set Associative Instruction Cache

Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose

•

Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,

using the 64-bit General Purpose Register file

•

Nexus Class 3 real-time Development Unit

Dynamic power management of execution units, cache and MMU

1.4.3

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between seven master ports and eight slave ports.

The crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows concurrent transactions to occur from any master port to any slave port but one of those transfers must be

an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration

logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access

to a slave port in round-robin fashion, based upon the ID of the last master to be granted access.

The crossbar provides the following features:

•

Seven master ports:

— e200z4d core instruction port

— e200z4d core complex load/store data port

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

— eDMA controller

— DCU

— DCULite

— VIU

— 2D Graphics Accelerator (GFX2D)

Seven slave ports:

•

— Platform Flash Controller (2 Ports)

— Platform SRAM Controller

— Graphics SRAM Controller (2 Ports)

— QuadSPI serial flash Controller and RLE Decoder

— Peripheral Bridge

•

32-bit internal address bus, 64-bit internal data bus

Programmable Arbitration Priority

— Requesting masters can be treated with equal priority and will be granted access to a slave port in round-robin

fashion, based upon the ID of the last master to be granted access, or a priority order can be assigned by software

at application run time

•

Temporary dynamic priority elevation of masters

1.4.4

Enhanced Direct Memory Access (eDMA)

The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with

minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source

and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing

the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The

eDMA module provides the following features:

•

16 channels support independent 8-, 16-, or 32-bit single value or block transfers

Supports variable sized queues and circular queues

Source and destination address registers are independently configured to post-increment or remain constant

Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request

Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

DMA transfers possible between system memories, QuadSPI, RLE Decoder, DSPIs, I C, ADC, eMIOS, and General

Purpose I/Os (GPIOs)

Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to

a total of 64 potential request sources

1.4.5

Interrupt Controller (INTC)

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that

all tasks which share the resource can not preempt each other.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software

setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion

and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a

software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt

requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following

features:

•

Unique 9-bit vector for each of the possible 128 separate interrupt sources

Eight software triggerable interrupt sources

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

Ability to modify the ISR or task priority

— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources

External non maskable interrupt directly accessing the main CPU critical interrupt mechanism

32 external interrupts

•

1.4.6

QuadSPI serial flash memory controller

The QuadSPI module enables use of external serial flash memories supporting single, dual, and quad modes of operation. It

features the following:

•

Maximum serial clock frequency 80 MHz

Memory mapped read access for AHB crossbar switch masters

Automatic serial flash read command generation by CPU, eDMA, DCU, or DCULite read access on AHB bus

Supports single, dual, and quad serial flash read commands

Simultaneous mode:

— Supports concurrent read of two external serial flashes

— The quad data streams from the two flashes can be recombined in the QuadSPI to achieve up to 80 MB/s read

bandwidth with 80 MHz serial flash

•

16×64-bit buffer with speculative fetch and buffer flush mechanisms to maximize read bandwidth of serial flash

DMA support

All Serial Flash program, erase, read, and configuration commands available via IP bus interface

1.4.7

System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal

peripheral multiplexing, and the system reset operation.

The GPIO features the following:

•

Up to four levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for

each package

•

Centralized general purpose input output (GPIO) control

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels

which support alternative configuration as general purpose inputs

•

Direct readback of the pin value supported on all digital output pins through the SIU

Configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on

external interrupts

•

modification until next reset

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

1.4.8

On-chip flash memory with ECC

The MPC5645S microcontroller has the following flash memory features:

•

2 MB of flash memory

— Typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 125 MHz

— Two 4×128-bit page buffers with programmable prefetch control

–

One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any

access

–

One set of page buffers allocated to Display Controller Units, Graphics Accelerator, and the eDMA

— 64-bit ECC with single-bit correction, double-bit detection for data integrity

•

Small block flash arrangement to support features such as boot block, EEPROM Emulation, operating system block

— 8×16 KB

— 2×64 KB

— 2×128 KB

— 6×256 KB

•

Hardware managed flash writes, erase and verify sequence

Censorship protection scheme to prevent Flash content visibility

1.4.9

SRAM

The MPC5645S microcontroller has 64 KB general-purpose on-chip SRAM with the following features:

•

Typical SRAM access time: 1 wait-state for reads and 32-bit writes

32-bit ECC with single-bit correction, double bit detection for data integrity

Supports byte (8-bit), half word (16-bit), word (32-bit), and double-word (64-bit) writes for optimal use of memory

User transparent ECC encoding and decoding for byte, half word, and word accesses

Separate internal power domains applied to 56 KB and 8 KB SRAM blocks during STANDBY modes to retain

contents during low power mode

1.4.10 On-chip graphics SRAM

The MPC5645S microcontroller has 1 MB on-chip graphics SRAM with the following features:

•

Two crossbar slave ports:

— One dedicated to the 2D Graphics Accelerator (GFX2D) access

— One dedicated to all other crossbar masters

•

Usable as general purpose SRAM

Supports byte (8-bit), half word (16-bit), word (32-bit), and double-word (64-bit) writes for optimal use of memory

RAM controller with hardware RAM fill function supporting all-zeroes or all-ones SRAM initialization

Independent data buffers (one per AHB port) for maximum system performance

— Optimized for burst transfers (read + write)

— Programmable read prefetch capabilities

1.4.11 Memory Protection Unit (MPU)

The MPU features the following:

•

Sixteen region descriptors for per master protection

Start and end address defined with 32-byte granularity

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Overlapping regions supported

Protection attributes can optionally include process ID

Protection offered for 4 concurrent read ports

Read and write attributes for all masters

Execute and supervisor/user mode attributes for processor masters

1.4.12 2D Graphics Accelerator (GFX2D)

•

Native vector graphics rendering

— Compatible with OpenVG1.1

— Complete hardware OpenVG 1.1 rendering pipeline

— Both geometry and pixel processing

— Adaptive processing of Bezier curves and strokes

16-sample edge anti-aliasing

•

— High image quality, font scalability, etc.

— 4× Rotated Grid Supersampling (RGSS) AA for Flash

3D perspective texturing, reflections, and shadowing

Shading (linear or radial gradient)

•

Separate 2D engine for BitBlt, fill, and ROP operations

Significant performance improvement when compared to software or 3D GPU-based OpenVG implementations

1.4.13 Display Control Unit (DCU3)

The DCU3 is a display controller designed to drive TFT LCD displays up to WVGA resolution using direct blit graphics and

video.

The DCU3 generates all the necessary signals required to drive the TFT LCD displays: up to 24-bit RGB data bus, Pixel Clock,

Data Enable, Horizontal-Sync, and Vertical-Sync.

The flexible architecture of the DCU3 enables the display of OpenVG-rendered frame buffer content and direct blit rendered

graphics simultaneously.

An optional Timing Controller (TCON) and RSDS interface is available to directly drive the row and column drivers of a

display panel.

Internal memory resource of the device allows to easily handle complex graphics contents (pictures, icons, languages, fonts).

The DCU3 supports 4-plane blending and 16 graphics layers. Control Descriptors (CDs) associated with each of the 16 layers

enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be

constructed from graphic content of various resolutions including indexed colors of 1, 2, 4, and 8 bpp, direct colors of 16, 24,

and 32 bpp, and a YUV 4:2:2 color space. The ability of the DCU3 to handle input data in resolutions as low as 1bpp, 2bpp,

and 4bpp enables a highly efficient use of internal memory resources of the MPC5645S. A special tiled mode can be enabled

on any of the 16 layers to repeat a pattern optimizing graphic memory usage.

A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal

DCU3 resources.

To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical

data along the whole system data path from the memory to the TFT pads.

The DCU3 features the following:

•

Display color depth: up to 24 bpp

Generation of all RGB and control signals for TFT

Four-plane blending

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Maximum number of Input Layers: 16 (fixed priority)

Dynamic Look-Up-Table (Color and Gamma Look-Up)

α−blending range: up to 256 levels

Transparency Mode

Gamma Correction

Tiled mode on all the layers

Hardware Cursor

Supports YCrCb 4:2:2 input data format

RLE decode inline supporting direct read of RLE compressed images from system memory

Critical display content integrity monitoring for Functional Safety support

Internal Direct Memory Access (DMA) module to transfer data from internal and / or external memory

Support displays up to 800 x 480 pixel resolutions

The DCU3 also features a Parallel Data Interface (PDI) to receive external digital video or graphic content into the DCU3. The

PDI input is directly injected into the DCU3 background plane FIFO. When the PDI is activated, all the DCU3 synchronization

is extracted from the external video stream to guarantee the synchronization of the two video sources.

The PDI can be used to:

•

Connect a video camera output directly to the PDI

Connect a secondary display driver as slave with a minimum of extra cost

Connect a device gathering various Video sources

Provide flexibility to allow the DCU to be used in slave mode (external synchronization)

The PDI features the following:

•

Supported color modes:

— 8-bit mono

— 8-bit color multiplexed

— RGB565

— 16-bit/18-bit RAW color

Supported synchronization modes:

— embedded ITU-R BT.656-4 (RGB565 mode 2)

— HSYNC, VSYNC

•

— Data Enable

•

Direct interface with DCU3 background plane FIFO

Synchronization generation for the DCU3

1.4.14 Display Control Unit Lite (DCULite)

The DCULite is a display controller designed to enable the MPC5645S to drive a second TFT LCD display up to XGA

resolution using direct blit graphics and video. The DCULite includes all features of the DCU3, including the PDI with the

following exceptions:

•

Reduced from 4-plane to 2-plane blending

Reduced from 16 layers to 4 layers

Reduced CLUT size

1.4.15 Timing Controller (TCON) and RSDS interface

The TCON enables direct drive of the row and column drivers of display panels enabling emulation of TCON ICs used in

display panels.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Programmable Timing Generation unit featuring 12 waveform generators allowing high degree of flexibility in panel

waveform generation

•

Reduced Swing Differential Signaling (RSDS) interface for RGB data and pixel clock

Conforms to “RSDS ‘Intra Panel’ Interface Specification” Rev. 1.0 (National Semiconductor)

1.4.16 RLE decoder

The RLE decoder is a crossbar slave sharing a slave port with the QuadSPI module. The platform eDMA is used to stream

compressed image data into and extract decompressed data out of the RLE Decoder.

•

Lossless decompression

Pixel formats supported: 8 bpp, 16 bpp, 24 bpp, and 32 bpp

AHB mapped read and write registers in RLE_DEC to achieve higher throughput

Programmable fill levels of read and write buffers for initiating burst transfers

Crop feature: Support for selectively reading out a part of decompressed image data taking complete compressed data

for the full image as input

1.4.17 DRAM controller

The DRAM controller is a multi-port DRAM controller supporting LPDDR1, DDR-1, and DDR-2 memories. The DRAM

controller listens to the incoming requests to the seven buses in parallel and then sends commands to the DRAM from the

highest priority bus at the current time

The seven incoming 64-bit buses are:

•

DCU3

DCULite

e200z4d core — instruction bus

e200z4d core — data bus

VIU2

GFX2D

eDMA

The DRAM controller features the following:

•

Supports CAS latency of 2, 3, and 4 clock cycles

Master buses

— 7 incoming master buses

— Supports 16-byte and 32-byte bursts

— Supports byte enables

— Supports 4-bit priority signal for each bus

Write buffer contains five 32-byte entries

Supports 16-wide and 32-wide DDR1, DDR2, and LPDDR1 DRAM devices

Controller supports one chip select, 8-bank DRAM system

Supports dynamic on-die termination in the host device and in the DRAM

Supports memory sizes as small as 64 Mbit

•

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

1.4.18 Video Input Unit (VIU2)

The VIU2 is a crossbar master module accepting an ITU656 compatible video input stream on a parallel interface, converting

the pixel data to RGB or YUV format and transferring the video image to internal frame buffer memory or external DRAM if

available.

•

Supports 8-bit/10-bit ITU656 video input

Output formats:

— RGB888

— RGB565

— 8-bit monochrome

— YCrCb 4:2:2

•

Video downscaling

Contrast and Brightness adjustment

De-interlace for interlaced video image

Internal DMA engine for data transfer to memory

1.4.19 Boot Assist Module (BAM)

The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time

the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:

•

Booting from internal flash memory

Serial boot loading (A program is downloaded into RAM via FlexCAN or LINFlex and then executed)

Booting from external memory

Additionally the BAM:

•

Enables and manages the transition of the MCU from reset to user code execution

Configures device for serial bootload

Enables multiple bootcode starting locations out of reset through implementation of search for valid Reset

Configuration Halfword

1.4.20 Enhanced Modular Input/Output System (eMIOS)

This device has two eMIOS modules, each with 16 channels supporting a range of 16-bit Input Capture, Output Compare, Pulse

Width Modulation, and Quadrature Decode functions.

•

Selectable clock source from primary FMPLL, secondary FMPLL, external 4 - 16 MHz oscillator or 16 MHz Internal

RC oscillator on a per module basis

•

Timed I/O channels with 16-bit counter resolution

Buffered updates

Support for shifted PWM outputs to minimize occurrence of concurrent edges

Edge aligned output pulse width modulation

— Programmable pulse period and duty cycle

— Supports 0% and 100% duty cycle

— Shared or independent time bases

Programmable phase shift between channels

4 channels of Quadrature Decode

•

DMA transfer support

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

1.4.21 Analog-to-Digital Converter (ADC)

The ADC features the following:

•

10-bit A/D resolution

0–5 V or 0–3.3 V common mode conversion range

Supports conversions speeds of up to 1μs

20 internal and 8 external channels support

Up to 20 single-ended inputs channels

— 10 channels configured as input only pins

–

10-bit ± 2 counts accuracy (TUE)

— 10 channels configured to have alternate function as general purpose input/output pins

10-bit ± 3 counts accuracy (TUE)

–

•

External multiplexer support to increase up to 27 channels

— Automatic 1 × 8 multiplexer control

— External multiplexer connected to a dedicated input channel

— Shared register between the 8 external channels

Result register available for every non-multiplexed channel

Configurable Left or Right aligned result format

Supports for one-shot, scan, and injection conversion modes

Injection mode status bit implemented on adjacent 16-bit register for each result

— Supports Access to Result and injection status with single 32-bit read

Independently enabling of function for channels:

— Pre-sampling

•

— Offset error cancellation

— Offset Refresh

•

Conversion Triggering support

— Internal conversion triggering from periodic interrupt timer (PIT)

Four configurable analog comparator channels offering range comparison with triggered alarm

— Greater than

— Less than

— Out of range

•

All unused analog pins available as general purpose input pins

Selected unused analog pins available as general purpose pins

Power Down mode

Optional support for DMA transfer of results

1.4.22 Deserial Serial Peripheral Interface (DSPI)

The DSPI modules provide a synchronous serial interface for communication between the MCU and external devices.

The DSPI features:

•

Full duplex, synchronous transfers

Master or slave operation

Programmable master bit rates

Programmable clock polarity and phase

End-of-transmission interrupt flag

Programmable transfer baud rate

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Programmable data frames from 4 to 16 bits

Up to 3 chip select lines available, depending on package and pin multiplexing, enable 8 external devices to be selected

using external muxing from a single DSPI

•

Eight clock and transfer attributes registers

Chip select strobe available as alternate function on one of the chip select pins for de-glitching

FIFOs for buffering up to 4 transfers on the transmit and receive side

General purpose I/O functionality on pins when not used for SPI

Queueing operation possible through use of eDMA

1.4.23 FlexCAN

The MPC5645S includes up to three controller area network (FlexCAN) modules. The FlexCAN module is a communication

controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to

be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable

operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth.

Each FlexCAN module offers the following:

•

Compliant with CAN protocol specification, Version 2.0B active

64 mailboxes, each configurable as transmit or receive

— Mailboxes configurable while module remains synchronized to CAN bus

Transmit features

•

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

Receive features

•

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

Listen only mode capabilities

•

CAN Sampler

— Can catch the 1st message sent on the CAN network while the MCU is stopped, which guarantees a clean startup

of the system without missing messages on the CAN network

— The CAN sampler is connected to one of the CAN RX pins

1.4.24 Serial communication interface module (LINFlex)

The MPC5645S devices include up to four LINFlex modules and support for LIN Master mode, LIN Slave mode, and UART

mode. The modules are LIN state machine compliant to the LIN 1.3, 2.0, and 2.1 Specifications and handle LIN frame

transmission and reception without CPU intervention.

Other features include:

•

Autonomous LIN frame handling

Message buffer to store identifier and up to eight data bytes

Supports message length of up to 64 bytes

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Detection and flagging of LIN errors

Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors

Classic or extended checksum calculation

Configurable Break duration of up to 36-bit times

Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)

Diagnostic features

— Loop back

— Self Test

— LIN bus stuck dominant detection

Interrupt driven operation with 16 interrupt sources

LIN slave mode features

•

— Autonomous LIN header handling

— Autonomous LIN response handling

— Discarding of irrelevant LIN responses using up to 16 ID filters

UART mode

•

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit or 9-bit words)

— Error detection and flagging

–

Parity, noise, and framing errors

— Interrupt driven operation with 4 interrupts sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— Two receiver wakeup methods

1.4.25 Inter-Integrated Circuit (I²C) controller modules

The MPC5645S includes four I C modules. Each module features the following:

•

Two-wire bi-directional serial bus for on-board communications

Compatibility with I C bus standard

Multi-master operation

Software-programmable for one of 256 different serial clock frequencies

Software-selectable acknowledge bit

Interrupt-driven, byte-by-byte data transfer

Arbitration-lost interrupt with automatic mode switching from master to slave

Calling address identification interrupt

Start and stop signal generation/detection

Repeated START signal generation

Acknowledge bit generation/detection

Bus-busy detection

1.4.26 System clocks and clock generation modules

The system clock on the MPC5645S can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz

oscillator.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

The source system clock frequency can be changed via an on-chip programmable clock divider (÷1 to ÷32). An additional

programmable peripheral bus clock divider (ratios ÷1 to ÷15) is also available.

The MPC5645S has two on-chip FMPLLs (primary and secondary). Each features the following:

•

Input clock frequency from 4 MHz to 16 MHz

Lock detect circuitry continuously monitors lock status

Loss Of Clock (LOC) detection for reference and feedback clocks

On-chip loop filter (for improved electromagnetic interference performance and reduction of number of external

components required)

•

Support for frequency ramping from PLL

The primary FMPLL module is for use as a system clock source. The secondary FMPLL is available for use as an alternate,

modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation.

The fast external oscillator provides the following features:

•

Input frequency range 4–16 MHz

Square-wave input mode

Oscillator input mode 3.3 V (5.0 V)

Automatic level control

Low power consumption

PLL reference

The MPC5645S also includes the following oscillators:

•

32 KHz low power external oscillator for slow execution, low power, and RTC

Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up

— ±10% accuracy across voltage and temperature (after factory trimming)

— Trimming registers to support improved accuracy with in-application calibration

Dedicated 16 MHz internal RC oscillator

•

— Used as default clock source out of reset

— Provides a clock for rapid start-up from low power modes

— Provides a back-up clock in the event of PLL or External Oscillator clock failure

— Offers an independent clock source for the SWT

— ±5% accuracy across voltage and temperature (after factory trimming)

— Trimming registers to support frequency adjustment with in-application calibration

1.4.27 Periodic Interrupt Timer (PIT)

The PIT features the following:

•

Eight general purpose interrupt timers

Two dedicated interrupt timers for triggering ADC conversions

32-bit counter resolution

Clocked by system clock frequency

1.4.28 Real Time Counter (RTC)

The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation

•

Configurable resolution for different timeout periods

— 1 s resolution for >1 hour period

— 1 ms resolution for 2 second period

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal 128 kHz RC oscillator or

divided internal 16 MHz RC oscillator

1.4.29 System Timer Module (STM)

The STM is a 32-bit timer designed to support commonly required system and application software timing functions. The STM

includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is

driven by the system clock divided by an 8-bit prescale value (1 to 256).

•

One 32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

Independent interrupt source for each channel

Counter can be stopped in debug mode

1.4.30 Software Watchdog Timer (SWT)

The SWT features the following:

•

Watchdog supporting software activation or enabled out of Reset

Supports normal or windowed mode

Watchdog timer value writable once after reset

Watchdog supports optional halting during low power modes

Configurable response on timeout: reset, interrupt, or interrupt followed by reset

Clock source: 128 kHz RC oscillator

1.4.31 Stepper Motor Controller (SMC)

The SMC module is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring

a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total) driving up to 6

stepper motors.

The SMC module includes the following features:

•

10/11-bit PWM counter

11-bit resolution with selectable PWM dithering function

Left, right, or center aligned PWM

Output slew rate control

Output Short Circuit Detection

This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This

module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive

capabilities of the module.

1.4.32 Stepper Stall Detect (SSD)

The SSD module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using

full steps when the gauge pointer is returning to zero (RTZ).

The SSD module features the following:

•

Programmable full step state

Programmable integration polarity

Blanking (recirculation) state

16-bit integration accumulator register

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

16-bit modulus down counter with interrupt

1.4.33 Sound Generator Module (SGM)

The SGM features the following:

•

4-channel audio mixer

Each channel capable of independent Tone generation or Wave playback

Individual channel volume control (8-bit resolution)

Tone Mode:

—

Programmable Tone frequency

Programmable amplitude envelope: attack, duration, and decay

Programmable number of tone pulses and inter-tone duration

•

Wave Mode:

—

One FIFO per channel working in conjunction with eDMA

Supports standard audio sampling rates (4 kHz, 8 kHz, 11.025 kHz, 16 kHz, 22.050 kHz, 32 kHz, 44.100 kHz,

48 kHz)

—

Same sample rate applies to all channels

8-bit, 12-bit, 16-bit input data formats

Programmable wave duration and inter-wave duration

Repeat mode with programmable number of wave playbacks

•

SGM Output:

—

16-bit PWM channel

Integrated I S master interface for connection to external audio DAC

1.4.34 IEEE 1149.1 JTAG controller (JTAGC)

JTAGC features the following:

•

Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface

Support for boundary scan testing

1.4.35 Nexus Development Interface (NDI)

The Nexus 3 module is compliant with Class 3 of the IEEE-ISTO 5001-2008 standard, with additional Class 4 features

available. The following features are implemented:

•

Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between

the discontinuities. Thus static code may be traced.

•

Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the

development tool to trace reads and/or writes to selected internal memory resources.

Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by providing visibility of

which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new

process/task is activated, allowing the development tool to trace ownership flow.

•

Run-time access to embedded processor memory map via the JTAG port. This allows for enhanced download/upload

capabilities.

•

Watchpoint Messaging via the auxiliary pins provides visibility when debugging.

Watchpoint Trigger enablement of Program and/or Data Trace Messaging enhances debug capability.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

•

Data Acquisition Messaging (DQM) allows code to be instrumented to export customized information to the Nexus

Auxiliary Output Port.

Address Translation Messaging via program correlation messages displays updates to the TLB for use by the debugger

in correlating virtual and physical address information.

•

Auxiliary interface for higher data input/output.

Registers for Program Trace, Data Trace, Ownership Trace, and Watchpoint Trigger.

All features are controllable and configurable via the JTAG port.

Nexus Auxiliary port is supported on the 416BGA package.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Pinout and signal descriptions

2.1

176 LQFP package pinout

Figure 2 shows the pinout for the 176-pin LQFP package.

DCU_VSYNC / PG8

VDDE_B

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

DCU_HSYNC / PG9

PA13 / DCU_G5

DCU_DE / PG10

PA12 / DCU_G4

eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1

PA11 / DCU_G3

eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 / PJ2

PA10 / DCU_G2

VDDE_B

PA9 / DCU_G1 / SDA_2 / eMIOS0[19]

PA8 / DCU_G0 / SCL_2 / eMIOS0[20]

PA7 / DCU_R7

VSS

eMIOS0[13] / eMIOS0[17] / PDI4_VIU6 / PJ8

eMIOS0[12] / eMIOS1[22] / PDI5_VIU7 / PJ9

PA6 / DCU_R6

eMIOS0[11] / eMIOS1[17] / PDI6_VIU8 / PJ10

VSS

eMIOS0[10] / eMIOS1[15] / PDI7_VIU9 / PJ11

VDDE_B

RXD_0 / CNRX_0 / PB1

PA5 / DCU_R5

TXD_0 / CNTX_0 / PB0

PA4 / DCU_R4

I2S_DO / CNRX_1 / PB10

PA3 / DCU_R3

SGM_MCLK / CNTX_1 / PB11

PA2 / DCU_R2

DCU_TAG / eMIOS1[22] / PDI13_VIU5 / PM5

PA1 / DCU_R1 / SCL_1 / eMIOS0[17]

PA0 / DCU_R0 / SDA_1 / eMIOS0[18]

PM11 / TXD_2 / CNTX_2 / eMIOS0[23]

PM10 / RXD_2 / CNRX_2 / eMIOS0[16]

PM9/ PDI_PCLK/ SGM_MCLK/ eMIOS0[8]

VDDE_B

eMIOS1[23] / PDI14_VIU6 / PM6

VSS

VDDE_B

VDDR

VSSR

MPC5645S

176 LQFP

Top view

VSUP_TEST

VSS

VDD12

VSS

PD15 / M3C1P / SSD3_3 / eMIOS0[15]

PD14 / M3C1M / SSD3_2 / eMIOS0[14]

PD13 / M3C0P / SSD3_1 / eMIOS0[13]

PD12 / M3C0M / SSD3_0 / eMIOS0[12]

VSSM

VDDPLL

VREG_BYPASS

EXTAL

XTAL

VRC_CTRL

VDDM

RESET

PD11 / M2C1P / SSD2_3 / eMIOS0[11]

PD10 / M2C1M / SSD2_3 / eMIOS0[10]

PD9 / M2C0P / SSD2_1 / eMIOS0[9]

PD8 / M2C0M / SSD2_0

PD7 / M1C1P / SSD1_3

PD6 / M1C1M / SSD1_2 / eMIOS0[23]

PD5 / M1C0P / SSD1_1 / eMIOS0[16]

PD4 / M1C0M / SSD1_0 / eMIOS0[8]

VSSM

eMIOS1[10] / PDI8_VIU0 / PK2

eMIOS1[11] / PDI9_VIU1 / PK3

eMIOS1[12] / PDI10_VIU2 / PK4

eMIOS1[13] / PDI11_VIU3 / PK5

eMIOS1[9] / PDI12_VIU4 / PK6

VSS

VDDE_B

eMIOS1[8] / I2S_FS / PDI15_VIU7 / PH5

eMIOS1[16] / I2S_DO / PDI16_VIU8 / PM7

VDDM

eMIOS1[23] / I2S_SCK / PDI17_VIU9 / PM8

PD3 / M0C1P / SSD0_3 / eMIOS0[9]

PD2 / M0C1M / SSD0_2 / eMIOS1[23]

PD1 / M0C0P / SSD0_1 / eMIOS1[16]

PD0 / M0C0M / SSD0_0 / eMIOS1[8]

VDDE_B

TCK / PH0

TDI / PH1

TDO / PH2

TMS / PH3

Note: Functions in bold are

available only on this package.

Figure 2. 176-pin LQFP pinout

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

2.2

208 LQFP package pinout

Figure 3 shows the pinout for the 208-pin LQFP package.

DCU_VSYNC_TCON2 / PG8

DCU_HSYNC_TCON1 / PG9

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

VDDE_B

PA13 / DCU_G5 / RSDS6M

PA12 / DCU_G4 / RSDS6P

PA11 / DCU_G3 / RSDS5M

PA10 / DCU_G2 / RSDS5P

PA9 / DCU_G1 / SDA_2 / eMIOS0[19] / RSDS4M

PA8 / DCU_G0 / SCL_2 / eMIOS0[20] / RSDS4P

PA7 / DCU_R7 / RSDS3M

PA6 / DCU_R6 / RSDS3P

VSS

DCU_DE_TCON3 / PG10

eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1

eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 / PJ2

VDDE_B

VSS

eMIOS0[13] / eMIOS0[17] / PDI4_VIU6 / PJ8

eMIOS0[12] / eMIOS1[22] / PDI5_VIU7 / PJ9

eMIOS0[11] / eMIOS1[17] / PDI6_VIU8 / PJ10 10

eMIOS0[10] / eMIOS1[15] / PDI7_VIU9 / PJ11 11

RXD_0 / CNRX_0 / PB1 12

TXD_0 / CNTX_0 / PB0 13

I2S_DO / CNRX_1 / PB10 14

SGM_MCLK / CNTX_1 / PB11 15

TCON4 / RXD_3 / CNRX_2 / PM3 16

TCON5 / TXD_3 / CNTX_2 / PM4 17

VSS 18

VDDE_B

VREF_RSDS

PA5 / DCU_R5 / RSDS2M

PA4 / DCU_R4 / RSDS2P

PA3 / DCU_R3 / RSRS1M

PA2 / DCU_R2 / RSDS1P

PA1 / DCU_R1 / SCL_1 / eMIOS0[17] / RSDS0M

PA0 / DCU_R0 / SDA_1 / eMIOS0[18] / RSDS0P

VDDE_B

VDDE_B 19

MPC5645S

208 LQFP

Top view

VDDR 20

VSS

VDD12

VSSR 21

VSUP_TEST 22

PE7 / M5C1P / SSD5_3

PE6 / M5C1M / SSD5_2

PE5 / M5C0P / SSD5_1

PE4 / M5C0M / SSD5_0

VSSM

VDD12 23

VSS 24

VDDPLL 25

VREG_BYPASS 26

EXTAL 27

VDDM

XTAL 28

PE3 / M4C1P / SSD4_3

PE2 / M4C1M / SSD4_2

PE1 / M4C0P / SSD4_1

PE0 / M4C0M / SSD4_0

PD15 / M3C1P / SSD3_3 / eMIOS0[15]

PD14 / M3C1M / SSD3_2 / eMIOS0[14]

PD13 / M3C0P / SSD3_1 / eMIOS0[13]

PD12 / M3C0M / SSD3_0 / eMIOS0[12]

VSSM

VRC_CTRL 29

RESET 30

TCON6 / PDI13_VIU5 / CS2_2 / PL4 31

TCON7 / PDI14_VIU6 / CS1_2 / PL5 32

eMIOS1[18] / PDI15_VIU7 / CS0_2 / PL6 33

eMIOS1[19] / PDI16_VIU8 / SIN_2 / PL7 34

eMIOS1[20] / PDI17_VIU9 / SOUT_2 / PL8 35

eMIOS1[21] / PDI_PCLK / SCK_2 / PL9 36

VDDE_B 37

VDDM

VSS 38

PD11 / M2C1P / SSD2_3 / eMIOS0[11]

PD10 / M2C1M / SSD2_2 / eMIOS0[10]

PD9 / M2C0P / SSD2_1 / eMIOS0[9]

PD8 / M2C0M / SSD2_0

PD7 / M1C1P / SSD1_3

PD6 / M1C1M / SSD1_2 / eMIOS0[23]

PD5 / M1C0P / SSD1_1 / eMIOS0[16]

PD4 / M1C0M / SSD1_0 / eMIOS0[8]

VSSM

DCULITE_TAG / eMIOS1[10] / PDI8_VIU0 / PK2 39

DCULITE_DE / eMIOS1[11] / PDI9_VIU1 / PK3 40

DCULITE_HSYNC / eMIOS1[12] / PDI10_VIU2 / PK4 41

DCULITE_VSYNC / eMIOS1[13] / PDI11_VIU3 / PK5 42

DCULITE_PCLK / eMIOS1[9] / PDI12_VIU4 / PK6 43

TCON8 / DCULITE_R2 / RXD_2 / PK7 44

TCON9 / DCULITE_R3 / TXD_2 / PK8 45

TCON10 / DCULITE_R4 / I2S_DO / PK9 46

VSS 47

VDDM

VDDE_B 48

PD3 / M0C1P / SSD0_3 / eMIOS0[9]

PD2 / M0C1M / SSD0_2 / eMIOS1[23]

PD1 / M0C0P / SSD0_1 / eMIOS1[16]

PD0 / M0C0M / SSD0_0 / eMIOS1[8]

VDDE_B

TCK / PH0 49

TDI / PH1 50

TDO / PH2 51

TMS / PH3 52

Figure 3. 208-pin LQFP pinout

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

2.3

416 TEPBGA package pinout

Figure 4 shows the pinout for the 416 TEPBGA package.

ddr_dq[2 ddr_dq[2 ddr_dq[2 ddr_dq[2

ddr_addr ddr_addr ddr_addr ddr_addr ddr_addr

30]

31] ddr_ba[0]ddr_ba[1]ddr_ba[2]

PG12

PF14

PF10

PF8

PF5

PF3

PK0

PB3

PJ12

PL11

PG7

PG6

ess[0]

ess[4]

ess[6]

ess[8]

ess[12]

ddr_dq[2

ddr_dqs[ ddr_dm[3

ddr_addr

ess[1]

ddr_addr ddr_addr

ddr_addr

ess[15]

VSS

ddr_cas ddr_ras

VSS

ddr_web

VSS

PF13

PF12

PF11

VDDE

VSS

PF15

PF7

VSS

VDDE

PF4

PF1

PF0

PK1

VDDE

VSS

PJ15

PJ14

PJ13

PL13

PL12

PM2

PG11

PA15

PA11

PA10

PA3

VDDE

PL10

VSS

PG3

PG5

PG4

PG1

PG0

PA12

PA7

]

ess[7]

VSS

ess[9]

ddr_dq[2 VDDE_DD

3]]

ddr_dq[2 VDDE_DD

ddr_dramVDDE_DD

_clk DR

ddr_addr VDDE_DD

ess[2]

ddr_addr VDDE_DD

ess[10]

VSS

ddr_dq[1 ddr_dq[2 ddr_dq[2 ddr_dq[2

VDD33_D ddr_dram

ddr_addr ddr_addr VDD33_D ddr_addr ddr_addr ddr_addr

VREF_RS

DS2

ddr_cke ddr_cs

PF9

PF6

PB2

PG2

ddr_odt

_clkb

ess[3]

ess[5]

ess[11] ess[13] ess[14]

ddr_dq[1

VDDE_DD ddr_dq[1

VSS

PA14

PA9

VDDE

PA13

PA8

ddr_dq[1

VDD33_D

MVTT3

VSS

ddr_dq[1 ddr_dqs[ ddr_dm[2 ddr_dq[1

]

ddr_dq[1

VDDE_DD ddr_dq[1

VSS

VDDE

VSS

VA6

PA4

ddr_dq[1

VREF_RS

DS1

MVTT2

VSS

MVREF

PA5

ddr_dqs[ ddr_dm[1 ddr_dq[1

ddr_dq[9]

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

PA2

VSS

PM12

PO6

PA1

PA0

]

VDDE_DD

ddr_dq[8] VSS

ddr_dq[7]

PM13

PO7

PO3

PO0

PE7

VDDE

PO5

PO2

VSS

PJ0

ddr_dq[5] MVTT1

VSS ddr_dq[6]

VDD12

VSS

VDD12

VSS

PO4

PO1

PN14

PN12

PE2

ddr_dqs[ VDDE_DD

ddr_dq[3]

ddr_dq[4]

VDD12

VSS

VDD12

VSS

VDDE

PN15

PE6

ddr_dm[0

ddr_dq[1] VSS

ddr_dq[2]

VDD12

VSS

VDD12

VSS

]

VDD33_D

ddr_dq[0] MVTT0

VSS

VDD12

VSS

VDD12

VSS

PN13

PE3

VDDE_DD

PG10

PJ9

PG9

PJ8

PG8

PJ1

VDD12

VSS

VDD12

VSS

VDD12

VSS

VDD12

VSS

PE5

PE4

PJ2

PJ11

VDDE

PM3

VDD12

PE1

VSSM

PD14

VDDM

PD8

VDDM

PD13

VSSM

PD7

PE0

PB1

VSS

PJ10

PD15

PD11

PD9

PD12

PD10

PD6

PD4

PD0

PC2

PC5

PC8

RESET

VSS

PB10

PM4

PB0

PB11

VDDREG

VDDPLL

PK4

VREG_BY VRC_CTR

XTAL

EXTAL

PD5

VSSM

PD2

VDDM

PD1

PASS

PL4

VSS

PD3

VSUP_TE

VSSEH_A

PL5

VDDE

VSS

PN0

PN1

PK2

PK6

PK7

PK8

PH0

PH1

PH2

PF2

VDDE

VSS

PB13

EVTI

PK11

MSEO

PM0

PN2

VSS

PN4

PN5

PN6

PN8

PN9

PB9

VDDE

VSS

PB7

PJ4

PJ5

PJ7

PJ3

PB5

VSS

MCKO

MDO6 MDO10 MVO0

PC0

PC6

PL1

VDDA

VSSA

PL0

PC3

PC1

VDDEH_A

PL6

PL7

VSS

MSEO2 MDO7

VDDE

VSS

MDO1

MDO2

PC4

PC7

VDDE

EVTO

VDDE

PN10

PH4

VDDE

MDO4

MDO8

PC10

PC11

PC9

PL8

PL9

PK3

PK5

PK9

PH3

PB12

PK10

PM1

PN3

PN7

PN11

PB8

PJ6

PB4

PB6

MDO5

MDO9 MDO11 MDO3

18 20

PL3

PL2

PC15

PC14

PC13

PC12

416 TEPBGA pinout

Figure 4. 416 TEPBGA package pinout

2.4

Signal description

The following sections provide signal descriptions and related information about the signals’ functionality and configuration.

2.4.1

Pad configuration during reset phases

All pads have a fixed configuration under reset.

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are floating with the following exceptions:

•

PB[5] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash memory.

RESET pad is driven low. This is released only after PHASE2 reset completion.

Fast (4-16 MHz) external oscillator pads (EXTAL, XTAL) are tristate.

The following pads are pull-up:

— PB[6]

— PH[0]

— PH[1]

— PH[3]

NOTE

TCK pin must have an external pull-down resistor of 4.7 K.

2.4.2

Voltage supply pins

Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 3. Voltage supply pin descriptions

Pin number

208 LQFP

Supply pin

Function

176 LQFP

416 TEPBGA

V_DD12

1.2 V core supply (1.08 V - 1.32 V)

23, 50, 67, 110, 138, 23, 58, 79, 136, 162, K10,K12,K14,K16,L

175

186, 207

11,L13,L15,L17,M1

0,M16,N11,N17,P1

0,P16,R11,R17,T10

,T12,T14,T16,U11,

U13,U15,U17

V_SS

1.2 V ground

7, 18, 36, 49, 66, 68, 7, 18, 38, 47, 57, 64, AB3,AD10,AD16,A

111, 123, 133, 139, 78, 80, 137, 147, D4,AE13,AE19,AE2

154, 167, 176

157, 163, 185, 199, ,AE7,B11,B14,B19,

208

B2,B25,B5,B8,C12,

C15,C17,C21,C3,C

6,C9,E2,E24,F3,H2

,H25,J3,K11,K13,K

15,K17,K24,L10,L1

2,L14,L16,L2,M11,

M12,M13,M14,M15,

M17,M3,N10,N12,N

13,N14,N15,N16,P

11,P12,P13,P14,P1

5,P17,P2,P25,R10,

R12,R13,R14,R15,

R16,R3,T11,T13,T1

5,T17,U10,U12,U14

,U16,V2,Y1

VDD12 ground and VDDPLL ground

(VSSPLL)

—

V_{DDE_B}

3.3 V I/O supply. This supply is shared with 6, 19, 37, 48, 65, 89, 6, 19, 37, 48, 56, 63, AD13,AD19,AD2,A

internal flash, 16 MHz IRC oscillator and

4–16MHz crystal oscillator.

112, 122, 132, 140, 77, 105, 138, 146, D7,AE10,AE16,AE4

166

156, 164, 184, 198 ,B17,B21,B24,C19,

E25,H24,L25,N24,

V_DDA

3.3 V/5 V reference voltage and analog

supply for A/D converter. This supply is

shared with the SXOSC.

AC22

AD22

V_SSA

Reference ground and analog ground for A/D

converter

V_DDR

V_SSR

Voltage regulator VREG supply

Voltage regulator ground

AA4

—

V_{DDE_A}

3.3 V/5 V I/O supply. This supply is shared

with the SXOSC.

AD23

V_{SSE_A}

V_DDM

3.3 V/5 V I/O supply ground

AC23

Stepper motor 3.3 V/5 V pad supply. SSD

shares this supply.

94, 104

110, 120, 130

U25,W24,AA25

V_SSM

Stepper motor ground

95, 105

111, 121, 131

U24,W24,AA24

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 3. Voltage supply pin descriptions (continued)

Pin number

Supply pin

Function

176 LQFP

208 LQFP

416 TEPBGA

V_DDPLL

1.2 V PLL supply

—

AB4

AC1

V_{SUP_TEST}

9 V - 12 V flash test analog write signal

1.8V, 2.5V, and 3.3V DDR SDRAM supply

V_{DD_DR}

C2,C5,C8,C11,C14,

E3,H3,L3,N3,T3

V_{DD33_DR}

Functional supply for SDRAM pads (where

available must be >= VDD_DR)

—

D6, D12, F4, R4

Decoupling capacitors must be connected between these pins and the nearest V_SSpin.

VDDA must be at the same voltage as VDDE_A.

This signal needs to be connected to ground during normal operation.

2.4.3

System pins

The system pins are listed in Table 4.

Table 4. System pin descriptions

Pin number

176 LQFP 208 LQFP

I/O

Pad

RESET

System pin

Function

direction type configuration¹

416 TEPBGA

RESET

Bidirectional reset with

Schmitt-Trigger

characteristics and noise

filter.

I/O

Input, weak pull

EXTAL

XTAL

Analog input to the oscillator

amplifier circuit. Input for the

clock generator in bypass

mode.

—

AB1

AA1

Analog output of the

oscillator amplifier circuit.

Needs to be grounded if

oscillator bypass mode is

used.

EXTAL32 Analog input of the 32KHz

oscillator amplifier circuit.

—

AF24

AF23

XTAL32

Analog output of the 32 KHz

oscillator amplifier circuit.

Input for the clock generator

in bypass mode.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 4. System pin descriptions (continued)

Pin number

176 LQFP 208 LQFP

I/O

Pad

RESET

System pin

Function

direction type configuration¹

416 TEPBGA

NMI

Non-Maskable Interrupt

I/O

Input, none

—

AC7

AA3

VRC_CTRL Voltage Regulator external

Analo

NPN Ballast base control

VREF_

RSDS²

RSDS interface reference

voltage

Analo

—

145, 165

J24,D24

AA2

VREG_

Pin used for factory testing

—

BYPASS³

Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).

Although this signal is not a supply for RSDS pads, it needs to be terminated in an external capacitor with a value of 47 pF.

VREG_BYPASS should be connected to ground during normal operation.

2.4.4

Nexus pins

On the 176 LQFP and the 208 LQFP package options a reduced set of Nexus pins are optionally available, multiplexed with

GPIO pins.

On the 416 TEPBGA package option all Nexus pins are dedicated to Nexus only.

Table 5. Nexus pins

Pin number¹

Pad

type

System pin

Function

PCR

176 LQFP

208 LQFP

416 TEPBGA

EVTI

Nexus Event In

PCR[80]

PCR[70]

PCR[85]

PCR[71]

PCR[73]

PCR[81]

PCR[82]

PCR[83]

PCR[84]

PCR[197]

PCR[198]

PCR[200]

PCR[199]

PCR[201]

PCR[185]

169

157

174

158

159

170

171

172

173

n/a

201

189

206

190

191

202

203

204

205

n/a

A17

C20

B18

EVTO

Nexus Event Out

MCKO

MSEO[0]

MSEO[2]

MDO[0]

MDO[1]

MDO[2]

MDO[3]

EVTI

Nexus Msg Clock Out

Nexus Msg Start/End Out

Nexus Msg Data Out

Nexus Event In

B20

A20

D16

C16

B16

A16

AD8

AE8

AC17

AD9

AD17

AC20

EVTO

Nexus Event Out

n/a

MCKO

MSEO[0]

MSEO[2]

MDO[0]

Nexus Msg Clock Out

Nexus Msg Start/End Out

Nexus Msg Data Out

n/a

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 5. Nexus pins (continued)

Pin number¹

208 LQFP

Pad

type

System pin

Function

PCR

176 LQFP

416 TEPBGA

MDO[1]

MDO[2]

MDO[3]

MDO[4]

MDO[5]

MDO[6]

MDO[7]

MDO[8]

MDO[9]

MDO[10]

MDO[11]

Nexus Msg Data Out

PCR[186]

PCR[187]

PCR[188]

PCR[189]

PCR[190]

PCR[191]

PCR[192]

PCR[193]

PCR[194]

PCR[195]

PCR[196]

n/a

AD20

AE20

AF20

AE17

AF17

AC18

AD18

AE18

AF18

AC19

AF19

On the 176 LQFP and 208 LQFP package options the Nexus pins are multiplexed with other GPIO. On the 416 TEPBGA

package, there are additional dedicated Nexus pins.

2.4.5

DRAM interface

The DRAM interface pins are listed in Table 6.

Table 6. DRAM interface pin summary

Pin number

I/O

direction

Pad

type

RESET

config²

Port pin¹

Function

PCR

416 TEPBGA

DRAM Data Bus

DDR_DQ[31]

DDR_DQ[30]

DDR_DQ[29]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[26]

DDR_DQ[25]

DDR_DQ[24]

DDR_DQ[23]

DDR_DQ[22]

DDR_DQ[21]

DDR_DQ[20]

DDR_DQ[19]

DRAM Data Bus [31]

DRAM Data Bus [30]

DRAM Data Bus [29]

DRAM Data Bus [28]

DRAM Data Bus [27]

DRAM Data Bus [26]

DRAM Data Bus [25]

DRAM Data Bus [24]

DRAM Data Bus [23]

DRAM Data Bus [22]

DRAM Data Bus [21]

DRAM Data Bus [20]

DRAM Data Bus [19]

I/O

DDR

PCR[237] None, None

PCR[238] None, None

PCR[239] None, None

PCR[240] None, None

PCR[241] None, None

PCR[242] None, None

PCR[243] None, None

PCR[244] None, None

PCR[245] None, None

PCR[246] None, None

PCR[247] None, None

PCR[248] None, None

PCR[249] None, None

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 6. DRAM interface pin summary (continued)

Pin number

I/O

direction

Pad

type

RESET

config²

Port pin¹

Function

PCR

416 TEPBGA

DDR_DQ[18]

DDR_DQ[17]

DDR_DQ[16]

DDR_DQ[15]

DDR_DQ[14]

DDR_DQ[13]

DDR_DQ[12]

DDR_DQ[11]

DDR_DQ[10]

DDR_DQ[9]

DDR_DQ[8]

DDR_DQ[7]

DDR_DQ[6]

DDR_DQ[5]

DDR_DQ[4]

DDR_DQ[3]

DDR_DQ[2]

DDR_DQ[1]

DDR_DQ[0]

DRAM Data Bus [18]

DRAM Data Bus [17]

DRAM Data Bus [16]

DRAM Data Bus [15]

DRAM Data Bus [14]

DRAM Data Bus [13]

DRAM Data Bus [12]

DRAM Data Bus [11]

DRAM Data Bus [10]

DRAM Data Bus [9]

DRAM Data Bus [8]

DRAM Data Bus [7]

DRAM Data Bus [6]

DRAM Data Bus [5]

DRAM Data Bus [4]

DRAM Data Bus [3]

DRAM Data Bus [2]

DRAM Data Bus [1]

DRAM Data Bus [0]

I/O

DDR

PCR[250] None, None

PCR[251] None, None

PCR[252] None, None

PCR[253] None, None

PCR[254] None, None

PCR[255] None, None

PCR[256] None, None

PCR[257] None, None

PCR[258] None, None

PCR[259] None, None

PCR[260] None, None

PCR[261] None, None

PCR[262] None, None

PCR[263] None, None

PCR[264] None, None

PCR[265] None, None

PCR[266] None, None

PCR[267] None, None

PCR[268] None, None

DRAM Data Strobes

DDR_DQS[3]

DDR_DQS[2]

DDR_DQS[1]

DDR_DQS[0]

DRAM Data Strobe [3]

I/O

DDR

PCR[232] None, None

PCR[231] None, None

PCR[230] None, None

PCR[229] None, None

DRAM Data Strobe [2]

DRAM Data Strobe [1]

DRAM Data Strobe [0]

DRAM Data Enables

DDR_DM[3]

DDR_DM[2]

DDR_DM[1]

DDR_DM[0]

DRAM Address

DRAM Data Enable [3]

Output

DDR

PCR[236]

PCR[235]

PCR[234]

PCR[233]

Output,

None

DRAM Data Enable [2]

DRAM Data Enable [1]

DRAM Data Enable [0]

Output,

None

Output,

None

Output,

None

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 6. DRAM interface pin summary (continued)

Pin number

I/O

direction

Pad

type

RESET

config²

Port pin¹

Function

PCR

416 TEPBGA

DDR_A[15]

DDR_A[14]

DDR_A[13]

DDR_A[12]

DDR_A[11]

DDR_A[10]

DDR_A[9]

DDR_A[8]

DDR_A[7]

DDR_A[6]

DDR_A[5]

DDR_A[4]

DDR_A[3]

DDR_A[2]

DDR_A[1]

DDR_A[0]

DRAM address [15]

Output

DDR

PCR[217]

PCR[216]

PCR[215]

PCR[214]

PCR[213]

PCR[212]

PCR[211]

PCR[210]

PCR[209]

PCR[208]

PCR[207]

PCR[206]

PCR[205]

PCR[204]

PCR[203]

PCR[202]

Output,

None

B15

DRAM address [14]

DRAM address [13]

DRAM address [12]

DRAM address [11]

DRAM address [10]

DRAM address [9]

DRAM address [8]

DRAM address [7]

DRAM address [6]

DRAM address [5]

DRAM address [4]

DRAM address [3]

DRAM address [2]

DRAM address [1]

DRAM address [0]

Output,

None

D15

D14

A14

D13

C13

B13

A13

B12

A12

D11

A11

D10

C10

B10

A10

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

Output,

None

DRAM Bank Address

DDR_BA[2]

DDR_BA[1]

DDR_BA[0]

DRAM Control

DRAM Bank Address[2]

Output

DDR

PCR[220]

PCR[219]

PCR[218]

Output,

None

DRAM Bank Address[1]

DRAM Bank Address[0]

Output,

None

Output,

None

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 6. DRAM interface pin summary (continued)

Pin number

I/O

direction

Pad

type

RESET

config²

Port pin¹

Function

PCR

416 TEPBGA

DDR_CAS

DDR_RAS

DDR_WEB

DDR_ODT

DDR_CLK

DDR_CLKB

DDR_CK

Column Address Strobe

Row Address Strobe

Write Enable

Output

DDR

PCR[221]

PCR[227]

PCR[228]

PCR[226]

PCR[225]

Output,

None

Output,

None

Output,

None

DRAM On-die termination

DRAM Clock

Output,

Pull Down

Output,

None

DRAM Clock bar

Output,

None

DRAM Clock Enable

DRAM Chip Select

PCR[222]

PCR[223]

Output,

Pull Down

DDR_CS

Output,

None

MVREF

MVTT

DDR Reference Voltage

Input

—

DRAM Termination Voltage

F2,J2,M2,R2

These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out.

Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).

2.4.6

VIU muxing

The DCU3, DCULite and VIU2 modules share the same pins for input video. It is, however, possible to feed independent video

streams to VIU2 and DCU3 (operating in narrow mode). Figure 5 explains the pin sharing arrangement.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

PDI_PCLK

VSYNC

Direct feed of PDI interface

to DCU3 or DCULite

HSYNC

DATA[17:0]

VIU_PCLK

VIU[9:0]

VIU2

DCU3

DCULite

PDI

RGB565

RGB888

8-bit mono

YUV422

XBAR

Figure 5. VIU2, DCU3, and DCULite pin sharing

VIU input data selection is done based on select bit (bit 0) of Miscellaneous control register (0xC3FE0340).

•

VIU pix data: VIU[9:0]

Select bit 1’b0: PDI[7:0],HSYNC,VSYNC

Select bit 1’b1: PDI[17:8]

2.4.7

SGM muxing

The SGM shares pins between the PWM output signals and the I2S bus signals as shown in the “Port pin summary” table. When

the PWM function is enabled in the SGM (SGMCTL[PWME]) the PWM (PWMO, PWMOA) signals are available. When the

PWM function is disabled the I2S bus signals (I2S_DO, I2S_SCK) are available.

2.4.8

RSDS special function muxing

Ports PA[0:15], PG[0:7], PG[11] and PM[2] have the RSDS signalling option as a special function. The SIUL allocates pad

control registers to these functions (PCR[270:282]), but because these pads share a common pin with the normal GPIO pins

they do not operate in the same way as the normal GPIO ports. PG[11] in particular has a special configuration separate from

the other pads.

The special-function pads are output-only, and the associated PCR[OBE] bit is controlled by the TCON_CTRL1 register

(TCON_BYPASS and RSDS_MODE bits). However, the alternate function selection is taken from the associated normal GPIO

pad. This allows selection of the DCU3 function as the alternate function of the pad and then the TCON module to select if the

output style is TCON/RSDS or digital RGB format.

Therefore, when the TCON bypass is active (bypass disabled with or without RSDS active), it is important not to configure the

normal GPIO ports for output operation with a non-DCU3 alternate function on ports PA[0:15] and PG[0:7].

For PG[11], the PCR[282] OBE bit is fully controlled by the TCON module and will become an output whenever the DCU3

alternate option is selected. Therefore, only select the DCU3 function on this pin when ready to configure it as a clock for a TFT

panel.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

2.4.9

Functional ports

The functional port pins are listed in Table 7.

Table 7. Port pin summary

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PORT A

PA[0]

PCR[0]

Option 0 GPIO[0]

Option 1 DCU_R0

Option 2 SDA_1

RSDS0P

RSDS0M

RSDS1P

RSDS1M

RSDS2P

RSDS2M

RSDS3P

RSDS3M

SIUL

I/O

M /

None,

116

117

118

119

120

121

124

125

139

140

141

142

143

144

148

149

K26

K25

K23

J23

J26

J25

H26

G26

DCU3

RSDS none

I²C_1

Option 3 eMIOS0[18]

PWM/Timer

PA[1]

PA[2]

PA[3]

PA[4]

PA[5]

PA[6]

PA[7]

PCR[1]

PCR[2]

PCR[3]

PCR[4]

PCR[5]

PCR[6]

PCR[7]

Option 0 GPIO[1]

Option 1 DCU_R1

Option 2 SCL_1

SIUL

M /

None,

DCU3

RSDS none

I²C_1

Option 3 eMIOS0[17]

PWM/Timer

Option 0 GPIO[2]

Option 1 DCU_R2

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Option 0 GPIO[3]

Option 1 DCU_R3

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Option 0 GPIO[4]

Option 1 DCU_R4

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Option 0 GPIO[5]

Option 1 DCU_R5

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Option 0 GPIO[6]

Option 1 DCU_R6

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Option 0 GPIO[7]

Option 1 DCU_R7

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PA[8]

PCR[8]

Option 0 GPIO[8]

Option 1 DCU_G0

Option 2 SCL_2

RSDS4P

RSDS4M

RSDS5P

RSDS5M

RSDS6P

RSDS6M

RSDS7P

RSDS7M

SIUL

I/O

M /

None,

126

127

128

129

130

131

134

135

150

151

152

153

154

155

158

159

G25

G24

H23

G23

F26

F25

F24

F23

DCU3

RSDS none

I²C_2

Option 3 eMIOS0[20]

PWM/Timer

PA[9]

PCR[9]

Option 0 GPIO[9]

Option 1 DCU_G1

Option 2 SDA_2

SIUL

M /

None,

DCU3

RSDS none

I²C_2

Option 3 eMIOS0[19]

PWM/Timer

PA[10] PCR[10] Option 0 GPIO[10]

Option 1 DCU_G2

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PA[11] PCR[11] Option 0 GPIO[11]

Option 1 DCU_G3

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PA[12] PCR[12] Option 0 GPIO[12]

Option 1 DCU_G4

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PA[13] PCR[13] Option 0 GPIO[13]

Option 1 DCU_G5

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PA[14] PCR[14] Option 0 GPIO[14]

Option 1 DCU_G6

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PA[15] PCR[15] Option 0 GPIO[15]

Option 1 DCU_G7

SIUL

DCU3

—

M /

None,

RSDS none

Option 2

Option 3

—

PORT B

PB[0] PCR[16] Option 0 GPIO[16]

Option 1 CANTX_0

—

SIUL

I/O

None,

none

FlexCAN_0

LINFlex_0

—

Option 2 TXD_0

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PB[1] PCR[17] Option 0 GPIO[17]

Option 1 CANRX_0

—

SIUL

I/O

None,

none

153

152

183

182

FlexCAN_0

LINFlex_0

—

Option 2 RXD_0

Option 3

—

PB[2] PCR[18] Option 0 GPIO[18]

Option 1 TXD_0

SIUL

LINFlex_0

—

None,

none

D21

Option 2

Option 3

—

PB[3] PCR[19] Option 0 GPIO[19]

Option 1 RXD_0

SIUL

LINFlex_0

—

None,

none

A22

Option 2

Option 3

—

PB[4] PCR[20] Option 0 GPIO[20]

Option 1 SCK_1

SIUL

DSPI_1

ADC

—

None,

none

AF15

AC16

AF16

AC14

AF13

AC13

Option 2 MA0

Option 3

—

PB[5] PCR[21] Option 0 GPIO[21]

Option 1 SOUT_1

SIUL

DSPI_1

ADC

Input,

pull-

down

Option 2 MA1

Option 3 FABM

Control

PB[6] PCR[22] Option 0 GPIO[22]

Option 1 SIN_1

SIUL

DSPI_1

ADC

Input,

pull-

Option 2 MA2

Option 3 ABS[0]

Control

PB[7] PCR[23] Option 0 GPIO[23]

Option 1 SIN_0

SIUL

None,

none

DSPI_0

PWM/Timer

SGM

Option 2 eMIOS1[20]

Option 3 I2S_SCK/PWMO

PB[8] PCR[24] Option 0 GPIO[24]

Option 1 SOUT_0

SIUL

None,

none

DSPI_0

PWM/Timer

SGM

Option 2 eMIOS1[19]

Option 3 I2S_DO/PWMOA

PB[9] PCR[25] Option 0 GPIO[25]

Option 1 SCK_0

SIUL

None,

none

DSPI_0

PWM/Timer

SGM

Option 2 eMIOS1[18]

Option 3 I2S_FS

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PB[10] PCR[26] Option 0 GPIO[26]

Option 1 CANRX_1

—

SIUL

FlexCAN_1

SGM

I/O

None,

none

Option 2 I2S_DO/PWMOA

Option 3

—

PB[11] PCR[27] Option 0 GPIO[27]

Option 1 CANTX_1

SIUL

FlexCAN_1

SGM

None,

none

Option 2 SGM_MCLK

Option 3

—

PB[12] PCR[28] Option 0 GPIO[28]

Option 1 RXD_1

SIUL

None,

none

AF7

AC8

LINFlex_1

PWM/Timer

DSPI_0

Option 2 eMIOS1[10]

Option 3 CS2_0

PB[13] PCR[29] Option 0 GPIO[29]

Option 1 TXD_1

SIUL

None,

none

LINFlex_1

PWM/Timer

DSPI_0

Option 2 eMIOS1[11]

Option 3 CS1_0

PB[14]

PB[15]

PORT C

—

Reserved

—

PC[0] PCR[30] Option 0 GPIO[30]

ANS[0]

ANS[1]

ANS[2]

ANS[3]

SIUL

—

I/O

None,

none

104

103

102

101

AC21

AC25

AC26

AC24

Option 1

Option 2

Option 3

—

PC[1] PCR[31] Option 0 GPIO[31]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[2] PCR[32] Option 0 GPIO[32]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[3] PCR[33] Option 0 GPIO[33]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PC[4] PCR[34] Option 0 GPIO[34]

ANS[4]

ANS[5]

ANS[6]

ANS[7]

ANS[8]

ANS[9]

ANS[10]

ANS[11]

ANS[12]

SIUL

—

I/O

None,

none

100

AD24

AD26

AD21

AD25

AE26

AE25

AE23

AE24

AF26

Option 1

Option 2

Option 3

—

PC[5] PCR[35] Option 0 GPIO[35]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[6] PCR[36] Option 0 GPIO[36]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[7] PCR[37] Option 0 GPIO[37]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[8] PCR[38] Option 0 GPIO[38]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[9] PCR[39] Option 0 GPIO[39]

SIUL

—

None,

none

Option 1

Option 2

Option 3

—

PC[10] PCR[40] Option 0 GPIO[40]

Option 1

Option 2 I2S_DO/PWMO

Option 3

SIUL

—

SGM

—

None,

none

—

PC[11] PCR[41] Option 0 GPIO[41]

Option 1

SIUL

—

ADC

DSPI_1

None,

None

—

Option 2 MA0

Option 3 CS2_1

PC[12] PCR[42] Option 0 GPIO[42]

SIUL

—

None,

None

Option 1

—

Option 2 MA1

Option 3 CS1_1

ADC

DSPI_1

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PC[13] PCR[43] Option 0 GPIO[43]

Option 1

ANS[13]

SIUL

—

ADC

DSPI_1

I/O

None,

None

AF25

AF24

AF23

—

Option 2 MA2

Option 3 CS0_1

PC[14] PCR[44] Option 0 GPIO[44]

ANS[14]

EXTAL32

SIUL

—

None,

None

Option 1

Option 2

Option 3

—

PC[15] PCR[45] Option 0 GPIO[45]

ANS[15]

XTAL32

SIUL

—

None,

None

Option 1

Option 2

Option 3

—

PORT D

PD[0] PCR[46] Option 0 GPIO[46]

Option 1 M0C0M

—

SIUL

SMD

SSD

PWM/Timer

I/O

SMD

None,

None

106

107

108

109

112

113

AB26

AB25

AB24

AB23

AA26

AA23

Option 2 SSD0_0

Option 3 eMIOS1[8]

PD[1] PCR[47] Option 0 GPIO[47]

Option 1 M0C0P

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD0_1

Option 3 eMIOS1[16]

PD[2] PCR[48] Option 0 GPIO[48]

Option 1 M0C1M

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD0_2

Option 3 eMIOS1[23]

PD[3] PCR[49] Option 0 GPIO[49]

Option 1 M0C1P

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD0_3

Option 3 eMIOS0[9]

PD[4] PCR[50] Option 0 GPIO[50]

Option 1 M1C0M

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD1_0

Option 3 eMIOS0[8]

PD[5] PCR[51] Option 0 GPIO[51]

Option 1 M1C0P

SIUL

SMC

None,

None

Option 2 SSD1_1

SSD

Option 3 eMIOS0[16]

PWM/Timer

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PD[6] PCR[52] Option 0 GPIO[52]

Option 1 M1C1M

—

SIUL

SMC

SSD

PWM/Timer

I/O

SMD

None,

None

114

115

116

117

118

119

122

123

124

Y26

Y25

Y24

Y23

W26

W23

V26

V25

V24

Option 2 SSD1_2

Option 3 eMIOS0[23]

PD[7] PCR[53] Option 0 GPIO[53]

Option 1 M1C1P

SIUL

SMC

SSD

—

None,

None

Option 2 SSD1_3

Option 3

—

PD[8] PCR[54] Option 0 GPIO[54]

Option 1 M2C0M

SIUL

SMC

SSD

—

None,

None

100

101

102

103

106

107

108

Option 2 SSD2_0

Option 3

—

PD[9] PCR[55] Option 0 GPIO[55]

Option 1 M2C0P

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD2_1

Option 3 eMIOS0[9]

PD[10] PCR[56] Option 0 GPIO[56]

Option 1 M2C1M

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD2_2

Option 3 eMIOS0[10]

PD[11] PCR[57] Option 0 GPIO[57]

Option 1 M2C1P

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD2_3

Option 3 eMIOS0[11]

PD[12] PCR[58] Option 0 GPIO[58]

Option 1 M3C0M

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD3_0

Option 3 eMIOS0[12]

PD[13] PCR[59] Option 0 GPIO[59]

Option 1 M3C0P

SIUL

SMC

SSD

PWM/Timer

None,

None

Option 2 SSD3_1

Option 3 eMIOS0[13]

PD[14] PCR[60] Option 0 GPIO[60]

Option 1 M3C1M

SIUL

SMC

None,

None

Option 2 SSD3_2

SSD

Option 3 eMIOS0[14]

PWM/Timer

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PD[15] PCR[61] Option 0 GPIO[61]

Option 1 M3C1P

—

SIUL

SMC

I/O

SMD

None,

None

109

125

V23

Option 2 SSD3_3

SSD

Option 3 eMIOS0[15]

PWM/Timer

PORT E

PE[0] PCR[62] Option 0 GPIO[62]

Option 1 M4C0M

—

SIUL

SMC

SSD

—

I/O

SMD

None,

None

—

126

127

128

129

132

133

134

135

U26

U23

T26

T25

T24

T23

R24

R23

Option 2 SSD4_0

Option 3

—

PE[1] PCR[63] Option 0 GPIO[63]

Option 1 M4C0P

SIUL

SMC

SSD

—

None,

None

Option 2 SSD4_1

Option 3

—

PE[2] PCR[64] Option 0 GPIO[64]

Option 1 M4C1M

SIUL

SMC

SSD

—

None,

None

Option 2 SSD4_2

Option 3

—

PE[3] PCR[65] Option 0 GPIO[65]

Option 1 M4C1P

SIUL

SMC

SSD

—

None,

None

Option 2 SSD4_3

Option 3

—

PE[4] PCR[66] Option 0 GPIO[66]

Option 1 M5C0M

SIUL

SMC

SSD

—

None,

None

Option 2 SSD5_0

Option 3

—

PE[5] PCR[67] Option 0 GPIO[67]

Option 1 M5C0P

SIUL

SMC

SSD

—

None,

None

Option 2 SSD5_1

Option 3

—

PE[6] PCR[68] Option 0 GPIO[68]

Option 1 M5C1M

SIUL

SMC

SSD

—

None,

None

Option 2 SSD5_2

Option 3

—

PE[7] PCR[69] Option 0 GPIO[69]

Option 1 M5C1P

SIUL

SMC

SSD

—

None,

None

Option 2 SSD5_3

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PORT F

PF[0]

PCR[70] Option 0 GPIO[70]

Option 1 eMIOS1[19]

Option 2 EVTO

—

SIUL

I/O

None,

None

157

158

189

190

C20

B20

AC7

A20

D19

A19

D18

C18

A18

PWM/Timer

NEXUS

DCULite

Option 3 DCULITE_B2

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PF[8]

PCR[71] Option 0 GPIO[71]

Option 1 eMIOS1[20]

Option 2 MSEO

SIUL

None,

None

PWM/Timer

NEXUS

DCULite

Option 3 DCULITE_B3

PCR[72] Option 0 GPIO[72]

Option 1 NMI

SIUL

NMI

—

None,

None

Option 2

Option 3

—

PCR[73] Option 0 GPIO[73]

Option 1 eMIOS1[21]

Option 2 MSEO

SIUL

None,

None

159

160

161

162

163

164

191

192

193

194

195

196

PWM/Timer

NEXUS

DCULite

Option 3 DCULITE_B4

PCR[74] Option 0 GPIO[74]

Option 1 eMIOS1[14]

Option 2 SDA_1

SIUL

None,

None

PWM/Timer

I²C_1

Option 3 DCULITE_B5

DCULite

PCR[75] Option 0 GPIO[75]

Option 1 QUADSPI_IO1_B

Option 2 eMIOS1[15]

SIUL

None,

None

QuadSPI

PWM/Timer

VIU2/PDI

Option 3 VIU8_PDI16

PCR[76] Option 0 GPIO[76]

Option 1 QUADSPI_IO0_B

Option 2 eMIOS1[16]

SIUL

None,

None

QuadSPI

PWM/Timer

VIU2/PDI

Option 3 VIU9_PDI17

PCR[77] Option 0 GPIO[77]

Option 1 eMIOS1[15]

Option 2 SCL_1

SIUL

None,

None

PWM/Timer

I²C_1

Option 3 DCULITE_B6

DCULite

PCR[78] Option 0 GPIO[78]

Option 1 SDA_0

SIUL

None,

None

I²C_0

Option 2 CS2_1

Option 3 RXD_1

DSPI_1

LINFlex_1

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PF[9]

PCR[79] Option 0 GPIO[79]

Option 1 SCL_0

—

SIUL

I/O

None,

None

165

169

170

171

172

173

174

197

201

202

203

204

205

206

D17

A17

D16

C16

B16

A16

B18

I²C_0

Option 2 CS1_1

Option 3 TXD_1

DSPI_1

LINFlex_1

PF[10] PCR[80] Option 0 GPIO[80]

Option 1 QUADSPI_PCS_A

Option 2

SIUL

QuadSPI

—

None,

None

—

Option 3 EVTI

NEXUS

PF[11] PCR[81] Option 0 GPIO[81]

SIUL

QuadSPI

—

None,

None

Option 1 QUADSPI_IO2_A

Option 2

—

Option 3 MDO0

NEXUS

PF[12] PCR[82] Option 0 GPIO[82]

SIUL

QuadSPI

—

None,

None

Option 1 QUADSPI_IO3_A

Option 2

—

Option 3 MDO1

NEXUS

PF[13] PCR[83] Option 0 GPIO[83]

SIUL

QuadSPI

—

None,

None

Option 1 QUADSPI_IO0_A

Option 2

—

Option 3 MDO2

NEXUS

PF[14] PCR[84] Option 0 GPIO[84]

SIUL

QuadSPI

—

None,

None

Option 1 QUADSPI_IO1_A

Option 2

—

Option 3 MDO3

NEXUS

PF[15] PCR[85] Option 0 GPIO[85]

SIUL

None,

None

Option 1 QUADSPI_CLK_A

Option 2 CLKOUT

Option 3 MCKO

QuadSPI

Control

NEXUS

PORT G

PG[0] PCR[86] Option 0 GPIO[86]

Option 1 DCU_B0

RSDS8P SIUL

DCU3

I/O

None,

None

136

137

160

161

E26

D26

Option 2 SCL_3

Option 3 eMIOS0[21]

I²C_3

PWM/Timer

PG[1] PCR[87] Option 0 GPIO[87]

Option 1 DCU_B1

RSDS8M SIUL

DCU3

None,

None

Option 2 SDA_3

I²C_3

Option 3 eMIOS0[22]

PWM/Timer

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PG[2] PCR[88] Option 0 GPIO[88]

Option 1 DCU_B2

RSDS9P SIUL

I/O

None,

None

141

142

143

144

145

146

166

167

168

169

170

171

D25

C25

C26

B26

A26

A25

DCU3

—

Option 2

Option 3

—

PG[3] PCR[89] Option 0 GPIO[89]

Option 1 DCU_B3

RSDS9M SIUL

None,

None

DCU3

—

Option 2

Option 3

—

PG[4] PCR[90] Option 0 GPIO[90]

Option 1 DCU_B4

RSDS10P SIUL

None,

None

DCU3

—

Option 2

Option 3

—

PG[5] PCR[91] Option 0 GPIO[91]

Option 1 DCU_B5

RSDS10M SIUL

None,

None

DCU3

—

Option 2

Option 3

—

PG[6] PCR[92] Option 0 GPIO[92]

Option 1 DCU_B6

RSDS11P SIUL

None,

None

DCU3

—

Option 2

Option 3

—

PG[7] PCR[93] Option 0 GPIO[93]

Option 1 DCU_B7

RSDS11M SIUL

None,

None

DCU3

—

Option 2

Option 3

—

PG[8] PCR[94] Option 0 GPIO[94]

Option 1 DCU_VSYNC

—

SIUL

DCU3

—

None,

None

Option 2

Option 3

—

PG[9] PCR[95] Option 0 GPIO[95]

Option 1 DCU_HSYNC

SIUL

DCU3

—

None,

None

Option 2

Option 3

—

PG[10] PCR[96] Option 0 GPIO[96]

Option 1 DCU_DE

SIUL

DCU3

—

None,

None

Option 2

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PG[11] PCR[97] Option 0 GPIO[97]

Option 1 DCU_PCLK

RSDSCLKP SIUL

I/O

None,

None

147

172

E23

DCU3

—

Option 2

Option 3

—

PG[12] PCR[98] Option 0 GPIO[98]

Option 1 CS0_1

—

SIUL

None,

None

168

200

A15

DSPI_1

PDI

Option 2 PDI_DE

Option 3 DCULITE_B7

DCULite

PG[13]

PG[14]

PG[15]

PORT H

—

Reserved

—

PH[0]⁶PCR[99] Option 0 GPIO[99]

Option 1 TCK

—

SIUL

JTAG

—

I/O

Input,

Pull Up

—

AC6

AD6

AE6

AF6

AE15

—

Option 2

Option 3

—

PH[1]⁶PCR[100] Option 0 GPIO[100]

Option 1 TDI

SIUL

JTAG

—

Input,

Pull Up

Option 2

Option 3

—

PH[2]⁶PCR[101] Option 0 GPIO[101]

Option 1 TDO

SIUL

JTAG

—

Output,

None

Option 2

Option 3

—

PH[3]⁶PCR[102] Option 0 GPIO[102]

Option 1 TMS

SIUL

JTAG

—

Input,

Pull Up

Option 2

Option 3

—

PH[4] PCR[103] Option 0 GPIO[103]

Option 1 CS0_0

SIUL

None,

None

DSPI_0

PWM/Timer

DCULite

Option 2 eMIOS1[21]

Option 3 DCULITE_G6

PH[5] PCR[104] Option 0 GPIO[104]

Option 1 VIU7_PDI15

SIUL

VIU2/PDI

SGM

None,

None

Option 2 I2S_FS

Option 3 eMIOS1[8]

PWM/Timer

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PH[6]

—

Reserved

—

PH[7]

Reserved

PH[8]

PH[9]

PH[10]

PH[11]

PH[12]

PH[13]

PH[14]

PH[15]

PORT J

PJ[0]

PCR[105] Option 0 GPIO[105]

Option 1 DCULITE_B6

—

SIUL

DCULite

—

I/O

None,

None

—

L26

Option 2

Option 3 I2S_DO / PWMO

—

SGM

PJ[1]

PJ[2]

PJ[3]

PJ[4]

PCR[106] Option 0 GPIO[106]

Option 1 VIU1_PDI_HSYNC

Option 2 eMIOS1[9]

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 3 eMIOS0[8]

PCR[107] Option 0 GPIO[107]

Option 1 VIU0_PDI_VSYNC

Option 2 eMIOS1[14]

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 3 eMIOS0[9]

PCR[108] Option 0 GPIO[108]

Option 1 VIU_PCLK

SIUL

VIU2

None,

None

AD15

AD14

Option 2 eMIOS0[22]

Option 3 PDI_DE

PWM/Timer

PDI

PCR[109] Option 0 GPIO[109]

Option 1 VIU2_PDI0

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS0[21]

Option 3 eMIOS0[23]

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PJ[5]

PJ[6]

PJ[7]

PJ[8]

PJ[9]

PCR[110] Option 0 GPIO[110]

Option 1 VIU3_PDI1

—

SIUL

I/O

None,

None

AE14

AF14

AC15

VIU2/PDI

PWM/Timer

Option 2 eMIOS0[20]

Option 3 eMIOS0[16]

PCR[111] Option 0 GPIO[111]

Option 1 VIU4_PDI2

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS0[19]

Option 3 eMIOS0[15]

PCR[112] Option 0 GPIO[112]

Option 1 VIU5_PDI3

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS0[18]

Option 3 eMIOS0[14]

PCR[113] Option 0 GPIO[113]

Option 1 VIU6_PDI4

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS0[17]

Option 3 eMIOS0[13]

PCR[114] Option 0 GPIO[114]

Option 1 VIU7_PDI5

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS1[22]

Option 3 eMIOS0[12]

PJ[10] PCR[115] Option 0 GPIO[115]

Option 1 VIU8_PDI6

SIUL

None,

None

148

149

178

179

VIU2/PDI

PWM/Timer

Option 2 eMIOS1[17]

Option 3 eMIOS0[11]

PJ[11] PCR[116] Option 0 GPIO[116]

Option 1 VIU9_PDI7

SIUL

None,

None

VIU2/PDI

PWM/Timer

Option 2 eMIOS1[15]

Option 3 eMIOS0[10]

PJ[12] PCR[117] Option 0 GPIO[117]

Option 1 DCU_TAG

SIUL

DCU3

—

None,

None

A23

D22

Option 2

—

Option 3 DCULITE_G6

DCULite

PJ[13] PCR[118] Option 0 GPIO[118]

Option 1 QUADSPI_PCS_B

Option 2 eMIOS1[8]

SIUL

None,

None

QuadSPI

PWM/Timer

VIU2/PDI

Option 3 VIU5_PDI13

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PJ[14] PCR[119] Option 0 GPIO[119]

Option 1 QUADSPI_CLK_B

—

SIUL

I/O

None,

None

150

180

C22

QuadSPI

PWM/Timer

PDI

Option 2 eMIOS1[17]

Option 3 PDI_PCLK

PJ[15] PCR[120] Option 0 GPIO[120]

Option 1 QUADSPI_IO3_B

Option 2 eMIOS1[9]

—

SIUL

None,

None

151

181

B22

QuadSPI

PWM/Timer

VIU2/PDI

Option 3 VIU6_PDI14

PORT K

PK[0]

PK[1]

PK[2]

PK[3]

PK[4]

PK[5]

PK[6]

PCR[121] Option 0 GPIO[121]

Option 1 eMIOS1[18]]

—

SIUL

PWM/Timer

—

I/O

None,

None

155

156

187

188

A21

D20

AE3

AF3

AC4

AF4

AC5

Option 2

—

Option 3 DCULITE_G7

DCULite

PCR[122] Option 0 GPIO[122]

Option 1 QUADSPI_IO2_B

Option 2 eMIOS1[14]

SIUL

None,

None

QuadSPI

PWM/Timer

VIU2/PDI

Option 3 VIU7_PDI15

PCR[123] Option 0 GPIO[123]

Option 1 VIU0_PDI8

SIUL

None,

None

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[10]

Option 3 DCULITE_TAG

PCR[124] Option 0 GPIO[124]

Option 1 VIU1_PDI9

SIUL

None,

None

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[11]

Option 3 DCULITE_DE

PCR[125] Option 0 GPIO[125]

Option 1 VIU2_PDI10

SIUL

None,

None

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[12]

Option 3 DCULITE_HSYNC

PCR[126] Option 0 GPIO[126]

Option 1 VIU3_PDI11

SIUL

None,

None

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[13]

Option 3 DCULITE_VSYNC

PCR[127] Option 0 GPIO[127]

Option 1 VIU4_PDI12

SIUL

None,

None

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[9]

Option 3 DCULITE_PCLK

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PK[7]

PK[8]

PK[9]

PCR[128] Option 0 GPIO[128]

Option 1 RXD_2

—

SIUL

I/O

None,

None

—

AD5

AE5

AF5

AF8

AC9

LINFlex_2

DCULite

TCON

Option 2 DCULITE_R2

Option 3 TCON[8]

PCR[129] Option 0 GPIO[129]

Option 1 TXD_2

SIUL

None,

None

LINFlex_2

DCULite

TCON

Option 2 DCULITE_R3

Option 3 TCON[9]

PCR[130] Option 0 GPIO[130]

Option 1 I2S_DO / PWMO

Option 2 DCULITE_R4

Option 3 TCON[10]

SIUL

SGM

DCULite

TCON

None,

None

PK[10] PCR[131] Option 0 GPIO[131]

Option 1 SDA_1

SIUL

None,

None

I²C_1

Option 2 eMIOS1[12]

Option 3 DCULITE_TAG

PWM/Timer

DCULite

PK[11] PCR[132] Option 0 GPIO[132]

Option 1 SCL_1

SIUL

None,

None

I²C_1

Option 2 eMIOS1[13]

Option 3 DCU_TAG

PWM/Timer

DCU3

PK[12]

PK[13]

PK[14]

PK[15]

PORT L

PL[0]

—

Reserved

—

PCR[133] Option 0 GPIO[133]

Option 1

ANS[19]

ANS[18]

SIUL

—

I/O

M /

None,

—

AE22

AE21

—

ANALO None

Option 2 CANRX_1

Option 3 SDA_1

FlexCAN_1

I2C1

PL[1]

PCR[134] Option 0 GPIO[134]

SIUL

M /

None,

Option 1

Option 2 CANTX_1

Option 3 SCL_1

—

ANALO None

FlexCAN_1

I2C1

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PL[2]

PL[3]

PL[4]

PL[5]

PL[6]

PL[7]

PL[8]

PL[9]

PCR[135] Option 0 GPIO[135]

Option 1

ANS[17]

SIUL

—

FlexCAN_0

PWM/Timer

I/O

S /

None,

—

174

AF22

AF21

AB2

AC2

AD1

AE1

AF1

AF2

C24

—

ANALO None

Option 2 CANRX_0

Option 3 eMIOS1[22]

PCR[136] Option 0 GPIO[136]

ANS[16]

SIUL

—

FlexCAN_0

PWM/Timer

S /

None,

Option 1

—

ANALO None

Option 2 CANTX_0

Option 3 eMIOS1[23]

PCR[137] Option 0 GPIO[137]

Option 1 CS2_2

—

SIUL

None,

None

DSPI_2

VIU2/PDI

TCON

Option 2 VIU5_PDI13

Option 3 TCON[6]

PCR[138] Option 0 GPIO[138]

Option 1 CS1_2

SIUL

None,

None

DSPI_2

VIU2/PDI

TCON

Option 2 VIU6_PDI14

Option 3 TCON[7]

PCR[139] Option 0 GPIO[139]

Option 1 CS0_2

SIUL

None,

None

DSPI_2

VIU2/PDI

PWM/Timer

Option 2 VIU7_PDI15

Option 3 eMIOS1[18]

PCR[140] Option 0 GPIO[140]

Option 1 SIN_2

SIUL

None,

None

DSPI_2

VIU2/PDI

PWM/Timer

Option 2 VIU8_PDI16

Option 3 eMIOS1[19]

PCR[141] Option 0 GPIO[141]

Option 1 SOUT_2

SIUL

None,

None

DSPI_2

VIU2/PDI

PWM/Timer

Option 2 VIU9_PDI17

Option 3 eMIOS1[20]

PCR[142] Option 0 GPIO[142]

Option 1 SCK_2

SIUL

DSPI_2

PDI

None,

None

Option 2 PDI_PCLK

Option 3 eMIOS1[21]

PWM/Timer

PL[10] PCR[143] Option 0 GPIO[143]

Option 1 eMIOS1[10]

SIUL

None,

None

PWM/Timer

DCULite

—

Option 2 DCULITE_G2

Option 3

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PL[11] PCR[144] Option 0 GPIO[144]

Option 1 eMIOS1[11]

—

SIUL

I/O

None,

None

—

175

176

177

A24

C23

B23

PWM/Timer

DCULite

—

Option 2 DCULITE_G3

Option 3

—

PL[12] PCR[145] Option 0 GPIO[145]

Option 1 eMIOS1[12]

SIUL

None,

None

PWM/Timer

DCULite

—

Option 2 DCULITE_G4

Option 3

—

PL[13] PCR[146] Option 0 GPIO[146]

Option 1 eMIOS1[13]

SIUL

None,

None

PWM/Timer

DCULite

—

Option 2 DCULITE_G5

Option 3

—

PL[14]

—

Reserved

—

PL[15]

PORT M

PM[0] PCR[147] Option 0 GPIO[147]

Option 1 I2S_SCK / PWMO

—

SIUL

SGM

DCULite

TCON

I/O

None,

None

—

AE9

AF9

D23

Option 2 DCULITE_R5

Option 3 TCON[11]

PM[1] PCR[148] Option 0 GPIO[148]

Option 1 I2S_FS

SIUL

SGM

DCULite

—

None,

None

Option 2 DCULITE_R6

Option 3

—

PM[2] PCR[149] Option 0 GPIO[149]

Option 1 eMIOS1[17]

RSDSCLKM SIUL

PWM/Timer

None,

None

173

Option 2 DCULITE_R7

Option 3 DCULITE_DE

DCULite

PM[3] PCR[150] Option 0 GPIO[150]

Option 1 CANRX_2

—

SIUL

None,

None

FlexCAN_2

LINFlex_3

TCON

Option 2 RXD_3

Option 3 TCON[4]

PM[4] PCR[151] Option 0 GPIO[151]

Option 1 CANTX_2

SIUL

None,

None

FlexCAN_2

LINFlex_3

TCON

Option 2 TXD_3

Option 3 TCON[5]

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PM[5] PCR[152] Option 0 GPIO[152]

Option 1 VIU5_PDI13

—

SIUL

I/O

None,

None

—

VIU2/PDI

PWM/Timer

DCU3

Option 2 eMIOS1[22]

Option 3 DCU_TAG

PM[6] PCR[153] Option 0 GPIO[153]

Option 1 VIU6_PDI14

SIUL

None,

None

—

VIU2/PDI

PWM/Timer

DCULite

Option 2 eMIOS1[23]

Option 3 DCULITE_TAG

PM[7] PCR[154] Option 0 GPIO[154]

Option 1 VIU8_PDI16

SIUL

VIU2/PDI

SGM

None,

None

—

Option 2 I2S_DO / PWMOA

Option 3 eMIOS1[16]

PWM/Timer

PM[8] PCR[155] Option 0 GPIO[155]

Option 1 VIU9_PDI17

SIUL

VIU2/PDI

SGM

None,

None

—

Option 2 I2S_SCK / PWMO

Option 3 eMIOS1[23]

PWM/Timer

PM[9] PCR[156] Option 0 GPIO[156]

Option 1 PDI_PCLK

SIUL

PDI

SGM

PWM/Timer

None,

None

113

114

115

—

Option 2 SGM_MCLK

Option 3 eMIOS0[8]

PM[10] PCR[157] Option 0 GPIO[157]

Option 1 RXD_2

SIUL

None,

None

—

LINFlex_2

FlexCAN_2

PWM/Timer

Option 2 CANRX_2

Option 3 eMIOS0[16]

PM[11] PCR[158] Option 0 GPIO[158]

Option 1 TXD_2

SIUL

None,

None

—

LINFlex_2

FlexCAN_2

PWM/Timer

Option 2 CANTX_2

Option 3 eMIOS0[23]

PM[12] PCR[159] Option 0 GPIO[159]

Option 1 DCULITE_B7

SIUL

DCULite

—

None,

None

L24

L23

—

Option 2

—

Option 3 I2S_SCK / PWMO

SGM

PM[13] PCR[160] Option 0 GPIO[160]

Option 1 DCULITE_PCLK

Option 2

Option 3 SGM_MCLK

SIUL

DCULite

—

None,

None

—

SGM

PM[14]

—

Reserved

—

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PM[15]

PORT N

PN[0]

—

Reserved

—

PCR[161] Option 0 GPIO[161]

Option 1 DCULITE_HSYNC

Option 2

SIUL

I/O

None,

None

—

AC3

DCULite

—

TCON

—

Option 3 TCON[4]

PN[1]

PN[2]

PN[3]

PN[4]

PN[5]

PN[6]

PN[7]

PCR[162] Option 0 GPIO[162]

—

SIUL

None,

None

—

AD3

AC10

AF10

AC11

AD11

AE11

AF11

Option 1 DCULITE_VSYNC

Option 2

Option 3 TCON[5]

DCULite

—

TCON

—

PCR[163] Option 0 GPIO[163]

Option 1 DCULITE_R0

Option 2 RXD_2

SIUL

None,

None

DCULite

LINFlex_2

VIU2/PDI

Option 3 VIU0_PDI8

PCR[164] Option 0 GPIO[164]

Option 1 DCULITE_R1

Option 2 TXD_2

SIUL

None,

None

DCULite

LINFlex_2

VIU2/PDI

Option 3 VIU1_PDI9

PCR[165] Option 0 GPIO[165]

Option 1 DCULITE_R2

SIUL

None,

None

DCULite

—

TCON

Option 2

Option 3 TCON[6]

—

PCR[166] Option 0 GPIO[166]

Option 1 DCULITE_R3

SIUL

None,

None

DCULite

—

TCON

Option 2

Option 3 TCON[7]

—

PCR[167] Option 0 GPIO[167]

Option 1 DCULITE_R4

SIUL

None,

None

DCULite

—

TCON

Option 2

Option 3 TCON[8]

—

PCR[168] Option 0 GPIO[168]

Option 1 DCULITE_R5

SIUL

None,

None

DCULite

—

Option 2

—

Option 3 TCON[9]

TCON

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PN[8]

PCR[169] Option 0 GPIO[169]

Option 1 DCULITE_R6

—

SIUL

DCULite

—

I/O

None,

None

—

AC12

AD12

AE12

AF12

R26

Option 2

—

Option 3 TCON[10]

TCON

PN[9]

PCR[170] Option 0 GPIO[170]

Option 1 DCULITE_R7

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 TCON[11]

TCON

PN[10] PCR[171] Option 0 GPIO[171]

Option 1 DCULITE_G0

Option 2 RXD_3

SIUL

None,

None

DCULite

LINFlex_3

VIU2/PDI

Option 3 VIU2_PDI10

PN[11] PCR[172] Option 0 GPIO[172]

Option 1 DCULITE_G1

Option 2 TXD_3

SIUL

None,

None

DCULite

LINFlex_3

VIU2/PDI

Option 3 VIU3_PDI11

PN[12] PCR[173] Option 0 GPIO[173]

Option 1 DCULITE_G2

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 eMIOS0[17]

PWM/Timer

PN[13] PCR[174] Option 0 GPIO[174]

Option 1 DCULITE_G3

SIUL

DCULite

—

None,

None

R25

Option 2

—

Option 3 eMIOS0[18]

PWM/Timer

PN[14] PCR[175] Option 0 GPIO[175]

Option 1 DCULITE_G4

SIUL

DCULite

—

None,

None

P26

Option 2

—

Option 3 eMIOS0[19]

PWM/Timer

PN[15] PCR[176] Option 0 GPIO[176]

Option 1 DCULITE_G5

SIUL

DCULite

—

None,

None

P24

Option 2

—

Option 3 eMIOS0[20]

PWM/Timer

PORT P

PP[0]

PCR[177] Option 0 GPIO[177]

Option 1 DCULITE_G6

—

SIUL

DCULite

—

I/O

None,

None

—

P23

Option 2

—

Option 3 eMIOS0[21]

PWM/Timer

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PP[1]

PP[2]

PP[3]

PP[4]

PP[5]

PP[6]

PP[7]

PCR[178] Option 0 GPIO[178]

Option 1 DCULITE_G7

—

SIUL

DCULite

—

I/O

None,

None

—

N26

N25

N23

M26

M25

M24

M23

Option 2

—

Option 3 eMIOS0[22]

PWM/Timer

PCR[179] Option 0 GPIO[179]

Option 1 DCULITE_B0

Option 2 CANRX_2

SIUL

None,

None

DCULite

FlexCAN_2

VIU2/PDI

Option 3 VIU4_PDI12

PCR[180] Option 0 GPIO[180]

Option 1 DCULITE_B1

Option 2 CANTX_2

SIUL

None,

None

DCULite

FlexCAN_2

PDI

Option 3 PDI_DE

PCR[181] Option 0 GPIO[181]

Option 1 DCULITE_B2

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 eMIOS0[11]

PWM/Timer

PCR[182] Option 0 GPIO[182]

Option 1 DCULITE_B3

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 eMIOS0[13]

PWM/Timer

PCR[183] Option 0 GPIO[183]

Option 1 DCULITE_B4

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 eMIOS0[15]

PWM/Timer

PCR[184] Option 0 GPIO[184]

Option 1 DCULITE_B5

SIUL

DCULite

—

None,

None

Option 2

—

Option 3 I2S_FS

SGM

PP[8]

—

Reserved

—

PP[9]

PP[10]

PP[11]

Table 7. Port pin summary (continued)

Pin number

Port

Alternate

function¹

Special

I/O

Pad RESET

PCR

Function

Peripheral³

function²

direction Type⁴config⁵

176 LQFP 208 LQFP 416 TEPBGA

PP[12]

PP[13]

PP[14]

PP[15]

—

Reserved

—

Reserved

Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIUL module.

PCR[PA] = 00 selects Option 0

PCR[PA] = 01 selects Option 1

PCR[PA] = 10 selects Option 2

PCR[PA] = 11 selects Option 3

This is intended to select the output functions. To use one of the input functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values selected in

the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

Special functions are enabled independently from the standard digital pin functions. Enabling standard I/O functions in the PCR registers may interfere with

their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module.

Using the PSMI registers in the System Integration Unit Lite (SIUL), different pads can be multiplexed to the same peripheral input. Please see the SIUL chapter

of the MPC5645S Microcontroller Reference Manual for details.

See the “Pad types” table for an explanation of the letters in this column.

Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”.

Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed.

The location of TCON[0:3] pins is mentioned in the following table.

Table 8. Location of TCON[0:3] Pins

Function

Port Name

PCR

Ball Number

DCU_TAG / TCON0

DCU_HSYNC/TCON1

DCU_VSYNC / TCON2

DCU_DE / TCON3

PK11

PJ12

PG9

PCR[132]

PCR[117]

PCR[95]

PCR[94]

PCR[96]

PCR[152]

Ball No: AC09

Ball No: A23

Ball No: T02

PG8

Ball No: T04

PG10

PM5

Ball No: T01

DCU_TAG/TCON3

NC (only on 176)

The following pad types are available for system pins and functional port pins:

Table 9. Pad Types

Pad

Function

Slow (pad_ssr, pad_ssr_hv)

Medium (pad_msr, pad_msr_hv)

Fast (pad_fc)

Input/output with analog features (pad_tgate, pad_tgate_hv)

Input only with analog features (pad_ae, pad_ae_hv)

Stepper Motor Detector

Analog

SMD

DDR

RSDS

DDR pads

RSDS pads

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

System design information

3.1

Power-up sequencing

The preferred power-up sequence for MPC5645S is as follows:

1. Generic IO supplies or noise-free supplies, consisting of:

— VDDA

— VDDE_A

— VDDE_B

— VDDM

— VDD_DR

— VDD33_DR

— VDDPLL

2. All 3.3V supplies (VDDE_B & VDD33_DR) should be ramped up first, and then the rest of the I/O supplies should

be ramped up (VDDA, VDDE_A, VDDM, VDD_DR).

3. VDDR, the regulator input supply, should be the last supply to ramp up; all supplies can be ramped up together as long

as VDDR is included. So all 5V supplies should be ramped up after the 3.3V supplies, and if all the supplies are of the

same level, they can be ramped up together as well.

4. LV supply (VDD12). If Vreg is in bypass mode and the core supply (1.2V) is supplied externally, then this should be

the last supply given.

NOTE

For DDR, the 3.3 V supply (VDD33_DR) should come before VDD_DR.

NOTE

Vreg bypass mode is for factory testing only.

This sequence ensures that when VREG releases its LVDs, the IO and other HV segments are powered properly. This is

important because MPC5645S doesn't monitor LVDs on IO HV supplies.

Electrical characteristics

4.1

Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take

precautions to avoid application of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by

internal pull up and pull down, which is provided by the product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller

Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” for System Requirement is included in the Symbol column.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.2

Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the

customer a better understanding, the classifications listed in Table 10 are used and the parameters are

tagged accordingly in the tables where appropriate.

Table 10. Parameter Classifications

Classification tag

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter

tables where appropriate.

4.3

Absolute maximum ratings

Table 11. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Max

V_DDA

SR D Voltage on VDDA pin (ADC reference) with

respect to ground (V_SSA

—

–0.3

+5.5

D1.1

)

Relative to V_DDV_DD–0.3

V_DD+0.3

V_SS+0.1

V_SSA

SR D Voltage on VSSA (ADC reference) pin with

respect V_SS

—

V_SS–0.1

D1.2

D1.3

V_DDPLL

CC D Voltage on VDDPLL (1.2 V PLL supply) pin with

—

1.08

1.4

respect to ground (V_SSPLL

)

Relative to V_DDV_DD–0.3

–0.3

Relative to V_DDV_DD–0.3

V_DD+0.3

+5.5

V_DDR

SR D Voltage on VDDR pin (regulator supply) with

respect to ground (V_SSR

—

D1.4

)

V_DD+0.3

V_SS+0.1

V_SSR

V_DD12

V_SS12

SR D Voltage on VSSR (regulator ground) pin with

respect to V_SS

—

V_SS–0.1

D1.5

D1.6

CC D Voltage on VDD12 pin with respect to ground

—

1.08

1.4

(V_SS12

)

CC D Voltage on VSS12 pin with respect to V_SS

—

V_SS–0.1

–0.3

V_SS+0.1

+5.5

D1.7

D1.8

V_{DDE_A}

SR D Voltage on VDDE_A (I/O supply) pin with

respect to ground (V_{SSE_A}

)

V_{DDE_B}

SR D Voltage on VDDE_B (I/O supply) pin with

—

–0.3

+3.6

D1.9

respect to ground (V_SS

)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 11. Absolute maximum ratings (continued)

Value

Max

Symbol

Parameter

Conditions

Unit SpecID

Min

V_DDM

SR D Voltage on VDDM (stepper motor supply) pin

with respect to ground (V_SSM

—

–0.3

+5.5

D1.10

)

V_SS

SR D I/O supply ground

—

D1.11

D1.12

D1.13

—

V_{DD_DR}

V_RSDS

V_IN

D Voltage on V_DDDDRwith respect to V_SS

D Voltage on V_DDRSDSwith respect to V_SS

–0.3

3.6

SR D Voltage on any GPIO pin with respect to ground

V_DDmax

(V_DDEmaxof

that

(V_SS

)

segment)

I_INJPAD

I_INJSUM

SR D Injected input current on any pin during

overload condition

—

–10

–50

D1.15

D1.16

SR D Absolute sum of all injected input currents

during overload condition

T_STORAGESR T Storage temperature

—

–55

—

150

°C

D1.17

D1.18

ESD_HBMSR T ESD Susceptibility (Human Body Model)

2000

Throughout the remainder of this document V_DDrefers collectively to I/O voltage supplies, i.e., V_{DDE_A}, V_{DDE_B}, and V_DDM

unless otherwise noted.

Throughout the remainder of this document V_SSrefers collectively to I/O voltage supply grounds, i.e., V_{SSE_A}, V_SSPLL, and

V_SSM, unless otherwise noted.

NOTE

Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. During overload conditions (V > V or

< V ), the voltage on pins with respect to ground (V ) must not exceed the

SS SS

recommended values.

4.4

Recommended operating conditions

Table 12. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Max

V_DDA

SR P Voltage on VDDA pin (ADC reference) with re-

—

+3.0

+3.6

D2.1

spect to ground (V_SS

)

Relative to V_DDV_DD–0.1

V_DD+0.1

V_SS+0.1

V_SSA

SR P Voltage on VSSA (ADC reference) pin with

respect V_SS

—

V_SS–0.1

D2.2

D2.3

V_DDPLLCC P Voltage on VDDPLL (1.2 V PLL supply) pin

with respect to ground (V_SSPLL

—

1.08

1.32

)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 12. Recommended operating conditions (3.3 V) (continued)

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Max

V_DDR

SR P Voltage on VDDR pin (regulator supply) with

respect to ground (V_SSR

—

+3.0

+3.6

D2.4

)

Relative to V_DDV_DD–0.1

V_DD+0.1

V_SS+0.1

V_SSR

SR D Voltage on VSSR (regulator ground) pin with

respect to V_SS

—

V_SS–0.1

D2.5

D2.6

3,4

V_DD12

CC P Voltage on VDD12 pin with respect to ground

—

1.08

1.4

(V_SS12

)

V_SS12CC D Voltage on VSS12 pin with respect to V_SS

—

V_SS–0.1

V_SS+0.1

D2.7

D2.8

5,6,7

V_DD

SR P Voltage on V_DDpins (V_{DDE_A}, V_{DDE_B}

V_DDmin

V_DDmax

V_{DD_DR}, V_DDM) with respect to ground (V_SS

)

V_SS

SR D I/O supply ground

—

D2.9

V_{DDE_A}SR P Voltage on VDDE_A (I/O supply) pin with

respect to ground (V_{SSE_A}

+3.0

+3.6

D2.10

)

V_{DDE_B}SR P Voltage on VDDE_B (I/O supply) pin with

respect to ground (V_{SSE_B}

—

+3.0

+3.6

D2.11

D2.12

)

V_DDM

SR P Voltage on VDDM (stepper motor supply) pin

with respect to ground (V_SSM

)

V_{DD_DR}

V_{SS_DR}

V_RSDS

TV_DD

T_A

P Voltage on V_DDDDRwith respect to V_SS

D Voltage on V_SSRSDSwith respect to V_SS

P Voltage on V_DDDDRwith respect to V_SS

SR D V_DDslope to ensure correct power up¹⁰

SR P Ambient temperature under bias

SR D Junction temperature under bias

—

+1.62

+3.0

—

+3.6

D2.13

D2.14

D2.15

D2.16

D2.17

D2.18

V/ms

°C

-40

+105

+140

T_J

-40

100 nF capacitance needs to be provided between V_DDA/V_SSApair.

10 μF capacitance must be connected between V_DDRand V_SS12because of a sharp surge due to external ballast.

V_DD12cannot be used to drive any external component.

Each V_DD12/V_SS12supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF. Preferably,

all the VDD12 supply pads should be shorted and then connected to a 4×10 μF capacitance. This is to ensure the ESR of

external capacitance does not exceed 0.2 Ω. A 100 nF capacitor must be placed close to the pin.

V_DDrefers collectively to I/O voltage supplies, i.e., V_{DDE_A}, V_{DDE_B}, V_{DD_DR}, and V_DDM

100 nF capacitance needs to be provided between each V_DD/V_SSpair. VDDmin value for is 3 V for VDDE_A & VDDM as well

as for VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 3.6 V for VDDE_A & VDDM as well as for VDDE_B &

VDD_DR.

Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical characteristics

and I/O’s DC electrical specification may not be guaranteed.

When voltage drops below V_LVDHVLdevice is reset.

V_SSrefers collectively to I/O voltage supply grounds, i.e., V_{SSE_A}, V_SS, and V_SSMunless otherwise noted.

V_{DDE_A}should not be less than V_DDA

¹⁰Guaranteed by device validation.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.5

Thermal characteristics

Table 13. Recommended operating conditions (5.0 V)

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Max

V_DDA

SR P Voltage on VDDA pin (ADC reference) with re-

—

+4.5

+3.0

+5.5

D2.19

spect to ground (V_SS

)

Voltage drop²

Relative to V_DDV_DD–0.1

V_DD+0.1

V_SS+0.1

V_SSA

SR D Voltage on VSSA (ADC reference) pin with

respect V_SS

—

V_SS–0.1

D2.20

D2.21

D2.22

V_DDPLLCC P Voltage on VDDPLL (1.2 V PLL supply) pin

with respect to ground (V_SSPLL

—

1.08

1.32

)

V_DDR

SR P Voltage on VDDR pin (regulator supply) with

—

+4.5

+5.5

respect to ground (V_SSR

)

Voltage drop²

Relative to V_DDV_DD–0.1

V_DD+0.1

V_SS+0.1

V_SSR

SR D Voltage on VSSR (regulator ground) pin with

respect to V_SS

—

V_SS–0.1

D2.23

D2.24

4,5

V_DD12

CC P Voltage on VDD12 pin with respect to ground

—

1.08

1.4

(V_SS12

)

V_SS12

CC D Voltage on VSS12 pin with respect to V_SS

—

V_SS–0.1

V_SS+0.1

D2.25

D2.26

V_DD

SR P Voltage on VDD pins (VDDE_A, VDDE_B,

VDD_DR, VDDMA, VDDMB, VDDMC) with

Voltage drop²

V_DDmin

V_DDmax

6,7

respect to ground (V_SS

)

V_SS

SR D I/O supply ground

—

D2.27

D2.28

V_{DDE_A}

SR P Voltage on VDDE_A (I/O supply) pin with

respect to ground (V_{SSE_A}

+4.5

+5.5

)

V_{DDE_B}

V_DDM

SR P Voltage on VDDE_B (I/O supply) pin with

respect to ground (V_{SSE_B}

—

+3.0

+4.5

+3.6

+5.5

D2.29

D2.30

)

SR P Voltage on VDDMA (stepper motor supply)

pin with respect to ground (V_SSMA

)

V_{DD_DR}

V_{SS_DR}

V_RSDS

TV_DD

T_A

P Voltage on V_{DD_DR}with respect to V_SS

D Voltage on V_SSRSDSwith respect to V_SS

P Voltage on V_{DD_DR}with respect to V_SS

SR D V_DDslope to ensure correct power up¹²

SR P Ambient temperature under bias

—

+1.62

+3.0

—

+3.6

D2.31

D2.32

D2.33

V/ms D2.34

–40

+105

+140

°C

D2.35

–40

T_J

SR D Junction temperature under bias

—

–40

—

D2.36

100 nF capacitance needs to be provided between V_DDA/V_SSApair.

Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical

characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.

10 μF capacitance must be connected between V_DDRand V_SS12. It is recommended that this cap should be placed, as close

as possible to the DUT pin on board.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

V_DD12cannot be used to drive any external component.

Each V_DD12/V_SS12supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF. Preferably,

all the VDD12 supply pads should be shorted and then connected to a 4×10 μF capacitance. This is to ensure the ESR of

external capacitance does not exceed 0.2 Ω. A 100 nF capacitor must be placed close to the pin.

V_DDrefers collectively to I/O voltage supplies, i.e., V_{DDE_A}, V_{DDE_B}, V_{DD_DR}, V_DDMA, V_DDMBand V_DDMC. VDDmin value for

is 4.5 V for VDDE_A & VDDM, 3 V VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 5.5 V for VDDE_A & VDDM

and 3.6 V for VDDE_B & VDD_DR.

100 nF capacitance needs to be provided between each V_DD/V_SSpair.

V_SSrefers collectively to I/O voltage supply grounds, i.e., V_{SSE_A}, V_{SSE_B}, V_{SSE_A}, V_{SSE_E}, V_SSMA, V_SSMBand V_SSMC

)

unless otherwise noted.

V_{DDE_A}should not be less than V_DDA

¹⁰VDDE_B cannot go beyond 3.6V under any operating condition.

¹¹VDD_DR can be 1.8, 2.5 and 3.3V (typical) based on type of SDR memory.

¹²Guaranteed by device validation.

Table 14. Thermal characteristics for 176-pin LQFP

Symbol

R_θJA

Parameter

CC D Junction to Ambient Natural Convection²Single layer board - 1s

CC D Junction to Ambient Natural Convection²Four layer board - 2s2p

Conditions

Value

Unit

SpecID

°C/W

D3.1

D3.2

D3.3

R_θJA

R_θJMA

CC D Junction to Ambient²

@200 ft./min., single layer

board - 1s

R_θJMA

CC D Junction to Ambient²

@200 ft./min., Four layer

board - 2s2p

°C/W

D3.4

R_θJB

R_θJCtop

Ψ_JT

CC D Junction to Board³

CC D Junction to Case (Top)⁴

—

°C/W

D3.5

D3.6

D3.7

CC D Junction to Package Top Natural Convec-

tion⁵

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

Table 15. Thermal characteristics for 208-pin LQFP

Symbol

R_θJA

Parameter

Conditions

Value

Unit

SpecID

CC D Junction to Ambient Natural Convection²

CC D Junction to Ambient²

Single layer board - 1s

Four layer board - 2s2p

°C/W

D3.8

D3.9

R_θJA

R_θJMA

@200 ft./min., single layer

board - 1s

D3.10

R_θJMA

CC D Junction to Ambient²

@200 ft./min., Four layer

board - 2s2p

°C/W

D3.11

R_θJB

CC D Junction to Board³

CC D Junction to Case (Top)⁴

—

°C/W

D3.12

D3.13

R_θJCtop

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 15. Thermal characteristics for 208-pin LQFP (continued)

Symbol

Ψ_JT

Parameter

Conditions

Value

Unit

SpecID

CC D Junction to Package Top Natural Convec-

tion⁵

—

°C/W

D3.14

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as

Psi-JT.

Table 16. Thermal characteristics for 416-pin TEPBGA

Symbol

R_θJA

Parameter

Conditions

Value

Unit

SpecID

CC D Junction to Ambient Natural Convection²Single layer board - 1s

CC D Junction to Ambient Natural Convection²Four layer board - 2s2p

CC D Junction to Ambient²

°C/W

D3.15

D3.16

D3.17

R_θJA

R_θJMA

@200 ft./min., single layer

board - 1s

R_θJMA

CC D Junction to Ambient²

@200 ft./min., Four layer

board - 2s2p

°C/W

D3.18

R_θJB

R_θJCtop

Ψ_JT

CC D Junction to Board³

CC D Junction to Case (Top)⁴

—

°C/W

D3.19

D3.20

D3.21

CC D Junction to Package Top Natural Convec-

tion⁵

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

4.5.1

General notes for specifications at maximum junction temperature

An estimate of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

* P )

Eqn. 1

θJA

where:

T = ambient temperature for the package ( C)

= junction to ambient thermal resistance ( C/W)

θJA

P = power dissipation in the package (W)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for

estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a

four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance

is not a constant. The thermal resistance depends on the:

•

Construction of the application board (number of planes)

Effective size of the board which cools the component

Quality of the thermal and electrical connections to the planes

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package

to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance

between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit

board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

•

One oz. (35 micron nominal thickness) internal planes

Components are well separated

Overall power dissipation on the board is less than 0.02 W/cm2

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the

ambient temperature varies widely within the application. For many natural convection and especially closed box applications,

the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the

device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

* P )

Eqn. 2

θJB

where:

T = board temperature for the package perimeter ( C)

= junction-to-board thermal resistance ( C/W) per JESD51-8S

θJB

P = power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction

temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to

a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal

resistance:

= R

+ R

θCA

Eqn. 3

θJA

θJC

where:

= junction to ambient thermal resistance ( C/W)

θJA

θJC

θCA

θJC

= junction to case thermal resistance ( C/W)

= case to ambient thermal resistance ( C/W)

s device related and is not affected by other factors. The thermal environment can be controlled to change the

. For example, change the air flow around the device, add a heat sink, change the

case-to-ambient thermal resistance, R

θCA

mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding

the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat

sink to ambient. For most packages, a better model is required.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the

junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a

substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the

thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple

estimations and for computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization

parameter (Ψ ) to determine the junction temperature by measuring the temperature at the top center of the package case using

the following equation:

T = T + (Ψ x P )

Eqn. 4

where:

T = thermocouple temperature on top of the package ( C)

Ψ = thermal characterization parameter ( C/W)

P = power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests

on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from

the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling

effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

805 East Middlefield Rd.

Mountain View, CA 94043

(415) 964-5111

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.6

EMI (electromagnetic interference) characteristics

1 2

Table 17. EMI testing specifications

Frequency

Range

Level

(Typ)

Symbol

Parameter

Conditions

Clocks

Unit

Radiated

Emissions

V_EME

Device Configuration,

test conditions and EM

testing per standard

IEC61967-2

FOSC – 8MHz, External

Crystal

150 kHz – 50

MHz

dBµV

FCPU – 124MHz

FBUS – 124MHz

50 MHz –

150 MHz

No PLL Frequency

Modulation

150 MHz –

500 MHz

500 MHz –

1000 MHz

IEC Level

—

FOSC - 8MHz, External

Crystal

150 kHz – 50

MHz

dBµV

FCPU -124MHz

FBUS -124MHz

50 MHz –

150 MHz

2% PLL Frequency

Modulation

150 MHz –

500 MHz

500 MHz –

1000 MHz

IEC Level

—

The reported emission level is the value of the maximum emission, rounded up to the next whole number.

IEC Level Maximum:, L is less than or equal to 24 dBµV, K is less than or equal to 30 dBµV.

4.7

Power management

4.7.1

Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN (BCP68 or NJD2873) ballast to be connected as shown in Figure 6 as

well as an external capacitance (C ) to be connected to the device in order to provide a stable low voltage digital supply to

REG

the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to

limit the serial inductance of the board to less than 15 nH.

For the MPC5645S microcontroller, 100 nF should be placed between each V

supply pair and also between the

DD12 SS12

pair. Additionally, 10 μF should be placed between the V

pin and the adjacent V pin.

DDPLL SSPLL

DDR SS

= 3.0 V to 3.6 V / 4.5 V to 5.5 V, T = -40 to 105 °C, unless otherwise specified.

DDR

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

DDR

VRC_CTRL

DD12

Figure 6. External NPN ballast connections

Table 18. Voltage regulator electrical characteristics

Symbol

Parameter

Conditions

Min

Max Unit SpecID

V_DDRSR P Power supply

3.0

5.5

D5.1

D5.2

D5.3

—

T_J

SR D Junction temperature

-40

—

140

°C

I_REG

Current consumption

Reference included,

@ 55 °C No load

@ Full load

I_L

Output current capacity

DC load current

—

450

D5.4

D5.5

V_DD12CC D Output voltage (value @ I_L= 0 @ 27°C)

Pre-trimming sigma

< 7 mV

1.330

Post-trimming

1.145

10 * 4

1.32

—

Output voltage (value @ I_L= Imax)

SR D External decoupling/stability capacitor

4 capacitances of

10 µF each

µF

D5.6

ESR of external cap

0.05

0.2

1 bond wire R + 1

pad R

L_BONDCC D Bonding Inductance for Bipolar Base Control pad

CC D Power supply rejection @ DC @ no load

D5.7

D5.8

—

Cload = 10 µF * 4

—

–30

–100

–30

@ 200 kHz @ no load

@ DC @ 400 mA

@ 200 kHz @ 400 mA

–30

CC D Load current transient

Cload = 10 µF * 4

—

10% to 90%

of I_L(max) in

100 ns

D5.9

t_SU

Start-up time after input supply stabilizes¹

500

µs

D5.10

Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power

OK signal.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 19. Low-power voltage regulator electrical characteristics

Symbol

Parameter

Conditions

Min

Max Unit SpecID

T_J

SR D Junction temperature

–40

140

°C

D5.2

D5.3

—

I_REG

Current consumption

Reference included,

@ 55 °C No load

@ Full load

—

µA

600

I_L

Output current capacity

DC load current

—

D5.4

D5.5

V_DD12CC D Output voltage

Pre-trimming sigma

< 7 mV

1.33

Post-trimming

1.14

1.32

Table 20. Ultra low-power voltage regulator electrical characteristics

Symbol

Parameter

Conditions

Min

Max Unit SpecID

T_J

SR D Junction temperature

–40

140

°C

D5.2

D5.3

—

I_REG

Current consumption

Reference included,

@ 55 °C No load

@ Full load

—

µA

100

I_L

Output current capacity

DC load current

—

D5.4

D5.5

V_DD12CC D Output voltage (value @ I_L= 0 @ 27°C)

Pre-trimming sigma

< 7 mV

1.33

Post-trimming

1.14

1.32

4.7.2

Voltage monitor electrical characteristics

The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors

to monitor the V and the V voltage while device is supplied:

DD12

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

LVDHV3 monitors V to ensure device reset below minimum functional supply

LVDHV5 monitors V when application uses device in the 5.0V ± 10% range

LVDLVCOR monitors power domain No. 1

LVDLVBKP monitors power domain No. 0

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 21. Low voltage monitor electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min Typ Max

V_PORH

CC C Power-on reset threshold

—

1.5

—

2.7

2.9

—

D5.11

D5.12

D5.13

D5.14

D5.15

D5.16

D5.17

V_LVDHV3HCC C LVDHV3 low voltage detector high threshold

V_LVDHV3LCC C LVDHV3 low voltage detector low threshold

V_LVDHV5HCC C LVDHV5 low voltage detector high threshold

V_LVDHV5LCC C LVDHV5 low voltage detector low threshold

2.5

—

4.4

—

3.9

—

V_LVDLVCORHCC C LVDLVCOR low voltage detector high threshold T_A= 25°C,

1.185

—

after trimming

V_LVDLVCORLCC C LVDLVCOR low voltage detector low threshold

1.095

V_DD= 3.3V ± 10% / 5.0V ± 10%, T_A= -40 / +105°C, unless otherwise specified

All values need to be confirmed during device validation.

4.7.3

Low voltage domain power consumption

Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual

consumption depends on the application.

Table 22. DC electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit

Min Typ

Max

I_DDMAX

CC D RUN mode maximum

average current

—

295

375³mA

I_DDRUN

CC P RUN mode typical

average current⁵

f_CPU= 125MHz, Dual Display Drive

with external DRAM, 416 TEPBGA

package option only

—

275

—

_CPU= 125MHz, Single Display Drive,

—

240

no external DRAM, 176 LQFP / 208

LQFP package options

I_DDHALTCC C HALT mode current⁶

Slow internal RC oscillator (128KHz) T_A= 25 ^oC

—

17.5 23.5 mA

running

T_A= 105 ^oC

45.5

—

I_DDSTOPCC D STOP mode current^{7 8}Slow internal RC oscillator (128KHz) T_A= –40^oC

running

645

1100

μA

T_A= 0^oC

—

T_A= 25^oC

T_A= 55^oC

T_A= 85^oC

T_A= 105^oC

1531 5500

3.8

9.7

—

17.67 36.5

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 22. DC electrical characteristics (continued)

Value²

Min Typ

Symbol

Parameter

Conditions¹

Unit

Max

I_DDSTDBY2CC D STANDBY2 mode

SXOSC (32KHz) ON and RTC

running

T_A= –40^oC

T_A= 0^oC

—

470

480

481

525

650

870

—

μA

current⁹

(64K SRAM on)

T_A= 25^oC

T_A= 55^oC

T_A= 85^oC

T_A= 105^oC

T_A= –40^oC

T_A= 0^oC

490

—

910

—

SXOSC (32KHz) and RTC OFF

μA

—

T_A= 25^oC

T_A= 55^oC

T_A= 85^oC

T_A= 105^oC

T_A= –40^oC

T_A= 0^oC

100

—

190

390

415

422

426

575

680

810

—

430

—

I_DDSTDBY1CC D STANDBY1 mode

SXOSC (32KHz) ON and RTC

running

current

—

(8K SRAM on)¹⁰

T_A= 25^oC

T_A= 55^oC

T_A= 85^oC

T_A= 105^oC

T_A= –40^oC

T_A= 0^oC

430

—

915

—

SXOSC (32 KHz) and RTC OFF

—

T_A= 25^oC

T_A= 55^oC

T_A= 85^oC

T_A= 105^oC

—

118

236

—

410

V_DD= 3.0V to 5.5V, T_A= -40 to 105 °C, unless otherwise specified.

I_DDMAXis composed of the current consumption on all supplies (V_DD12, V_{DDE_A}, V_{DDE_B}, V_DDA, V_DDR, V_DDM, V_DDPLL

V_{DD_DR}). It does not include current consumption linked to I/Os toggling which is highly dependent on the application. The

given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify

operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application; switch-off not

used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use

low power mode when possible.

Higher current may be sinked by device during power-up and standby exit. Please refer to inrush current in Table 23.

RUN current measured with typical application and accesses on both flash and RAM.

Data and Code Flash in Normal Power. Code fetched from RAM: DCUs running with 20MHz pixel clock, QuadSPI fetching

data at 80MHz, GPU accessing internal SRAM and external DRAM, DMA, RLE, and VIU active, Serial IPs CAN and LIN in

loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/ADC/SMD/SSD/SGM) and

running at max frequency, periodic SW/WDG timer reset enabled.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Flash in Low Power. RC-osc128KHz & RC-OSC 16MHzon. 10MHz XTAL clock.FlexCAN: instances: 0, 1ON (clocked but no

reception or transmission), LINFLEX: instances 0, 1, 2 ON (clocked but no reception or transmission). eMIOS: instance: 0, 1

ON - 16 channels on with PWM20KHz. DSPI: instance: 0 (clocked but no communication). DCUs, TCON, VIU, GPU clock

gated, RTC/API ON.PIT ON. STM ON. ADC ON but not converting.

For Tj > 105 ⁰C , HPvreg needs to be kept ON. The consumption increases beyond this temperature and to handle the extra

current, HPvreg should be ON.

No clock, RC 16MHz off, RCI 128KHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock

gated. Flash in power down mode.

ULPreg ON, HP/LPVreg off, 64KB RAM on, device configured for minimum consumption, all possible modules switched-off.

¹⁰ULPreg ON, HP/LPVreg off, 8KB RAM on, device configured for minimum consumption, all possible modules switched-off.

4.8

DC electrical specifications

4.8.1

DC specification for CMOS090LP2 library @ VDDE = 3.3 V

NOTE

These pad specifications are applicable for pads in the Digital segment Only. See the "GPIO

power bank supplies and functionality" table in the "Voltage Regulators and Power

Supplies" chapter of the reference manual for details.

Table 23. DC electrical specifications

Value

Symbol

Parameter

Condition

Unit SpecID

Min

Max

Vdd

Vdde

Vdd33

Vih_c

SR P Core supply voltage

SR P I/O supply voltage

—

1.08

3.0

1.32

3.6

D9.1

D9.2

D9.3

D9.4

SR P I/O pre-driver supply voltage

3.0

3.6

SR P CMOS input buffer high

voltage

With hysteresis enabled 0.65×Vdde

With hysteresis disabled 0.55×Vdde

Vdde+0.3

0.35×Vdde

0.40×Vdde

—

Vil_c

SR P CMOS input buffer low

voltage

With hysteresis enabled

With hysteresis disabled

—

Vss–0.3

0.1×Vdde

D9.5

Vhys_c

SR T CMOS input buffer

hysteresis

D9.6

D9.7

D9.8

D9.9

D9.10

Vih_fod_h SR P 5 V tolerant CMOS input

buffer high voltage

With hysteresis enabled 0.65×Vdd33 Vdd33+0.3

Vil_fod_h SR P 5 V tolerant CMOS input

buffer low voltage

With hysteresis enabled

—

Vss–0.3

0.35×Vdd33

Iact_s

SR T Selectable weak

pullup/pulldown current

150

2.5

μA

Iinact_d

SR P Digital pad input leakage

current

Weak pull inactive

–2.5

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 23. DC electrical specifications (continued)

Value

Symbol

Parameter

Condition

Unit SpecID

Min

Max

Iinact_a

SR P Analog pad input leakage

current

Weak pull inactive

–150

150

D9.11

Voh

Vol

SR P Output high voltage

SR P Output low voltage

Refer to Table 24

0.8 ×Vdde

—

D9.12

D9.13

D9.16

—

0.2×Vdde

0.2×Vdd33

Vol_fod_h SR C Fast open-drain output low Iol_fod_h = 10 mA

voltage

—

Table 24. Drive current, VDDE=3.3 V (+/- 10%)

Pad

Drive mode

Minimum Ioh (mA)¹

Minimum Iol (mA)²

pad_fc

All

16.1

31.8

47.2

47.9

70.6

114.5

83.6

pad_msr

pad_ssr

61.9

Ioh is defined as the current sourced by the pad to drive the output to Voh.

Iol is defined as the current sunk by the pad to drive the output to Vol.

Table 25. Supply leakage

VDDE

VDD33

(Typ/Max)

Pad

VDD

(Typ/Max)

pad_fc

pad_msr

pad_ssr

90 μA

—

3 nA / 4 μA

1 nA / 30 μA

—

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.8.2

DC specification for CMOS090LP2fg library @ VDDE = 5.0 V

NOTE

These pad specifications are applicable for pads in the Analog segment Only. See the

"GPIO power bank supplies and functionality" table in the "Voltage Regulators and Power

Supplies" chapter of the reference manual for details.

Table 26. DC electrical specifications

Value

Symbol

Parameter

Condition

Unit SpecID

Min

Max

Vdd

Vdde

SR P Core supply voltage

SR P I/O supply voltage

—

1.08

4.5

1.32

5.5

D9.17

D9.18

D9.19

D9.20

Vdd33

Vih_hys

SR P I/O pre-driver supply voltage

3.0

3.6

SR P CMOS input buffer high

voltage

With hysteresis enabled 0.65×Vdde

With hysteresis enabled Vss–0.3

With hysteresis disabled 0.55×Vdde

Vdde+0.3

Vil_hys

Vih

SR P CMOS input buffer low

voltage

0.35×Vdde

Vdde+0.3

0.40×Vdde

—

D9.21

D9.22

D9.23

D9.24

SR P CMOS input buffer high

voltage

Vil

SR P CMOS input buffer low

voltage

With hysteresis disabled

—

Vss–0.3

Vhys

SR T CMOS input buffer

hysteresis

0.1×Vdde

Pull_Ioh

Pull_Iol

Iinact_d

SR P Weak pullup current

—

135

200

2.5

μA

D9.25

D9.26

D9.27

SR P Weak pulldown current

SR P Digital pad input leakage

current

Weak pull inactive

–2.5

Iinact_a

Voh

SR P Analog pad input leakage

current

Weak pull inactive

–150

0.8×Vdde

—

150

—

D9.28

D9.29

D9.30

D9.31

SR P Slew rate controlled output

high voltage

—

Vol

SR P Slew rate controlled output

low voltage

0.2×Vdde

—

Voh_ls

SR C Low swing output pad output

high voltage

2.64

Ioh_msr

Iol_msr

Ioh_ssr

Iol_ssr

Rtgate

SR C pad_msr_hv Ioh

SR C pad_msr_hv Iol

SR C pad_ssr_hv Ioh

SR C pad_ssr_hv Iol

—

11.6

17.7

6.0

40.7

68.2

21.3

36.3

800

D9.32

D9.33

D9.34

D9.35

D9.39

9.2

SR D Pad_tgate_hv input

resistance

250

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 27. DC electrical specifications

Condition

Value

Symbol

Parameter

Unit SpecID

Min

Max

Vdd

Vdde

SR Core supply voltage

SR I/O supply voltage

—

1.08

3.0

1.32

3.6

D9.45

D9.46

D9.47

D9.48

—

Vdd33

Vih_hys

SR I/O pre-driver supply voltage

—

3.0

3.6

SR CMOS input buffer high

voltage

With hysteresis enabled

0.65×Vdde

Vdde+0.3

0.35×Vdde

Vdde+0.3

0.40×Vdde

—

Vil_hys

Vih

SR CMOS input buffer low

voltage

With hysteresis enabled

With hysteresis disabled

—

Vss–0.3

0.55×Vdde

Vss–0.3

D9.49

D9.50

D9.51

D9.52

SR CMOS input buffer high

voltage

Vil

SR CMOS input buffer low

voltage

Vhys

SR CMOS input buffer

hysteresis

0.1×Vdde

Pull_Ioh

Pull_Iol

Iinact_d

SR Weak pullup current

—

μA

D9.53

D9.54

D9.55

SR Weak pulldown current

SR Digital pad input leakage

current

Weak pull inactive

–2.5

2.5

Iinact_a

Voh

SR Analog pad input leakage

current

Weak pull inactive

–150

0.8×Vdde

—

150

—

D9.56

D9.57

D9.58

SR Slew rate controlled output

high voltage

—

Vol

SR Slew rate controlled output

low voltage

0.2×Vdde

Ioh_msr

Iol_msr

Ioh_ssr

Iol_ssr

Rtgate

SR pad_msr_hv Ioh

SR pad_msr_hv Iol

SR pad_ssr_hv Ioh

SR pad_ssr_hv Iol

—

5.4

8.1

2.8

4.2

325

D9.59

D9.60

D9.61

D9.62

D9.65

38.6

11.2

20.6

1250

SR Pad_tgate_hv input

resistance

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 28. Supply leakage

VDD VDDE

VDD33

Pad

Typ

Max

Typ

Max

Typ

Max

pad_msr_hv

pad ssr_hv

0.818 nA

83.7 nA

0.81 nA

118 nA

88.7 nA

30 nA

—

0.818 nA

83.7 nA

0.858 nA

88.2 pA

—

pad_i_hv

0.307 nA

48.4 nA

—

biasref_hv

—

core_v_det_hv

—

core_v_det_lp_hv

corner_esdpadcell_hv

corner_esdpadcell_id00_hv

corner_esdpadcell_id11_hv

corner_esdpadcell_lp_hv

esd_term_35_84_hv

pad_9v_hv

—

pad_ae_hv

—

pad_esdspacer_hv

pad_tgate_hv

—

pad_vdd33_hv

—

pad_vdde_hv

—

pad_vddint3v_hv

pad_vddint_hv

—

pad_vss_hv

—

pad_vsse_hv

—

pad_vssint3v_hv

pad_vssint_hv

—

spcr_17_82_hv

spcr_35_84_hv

spcr_71_88_hv

spcr_143_38_hv

spcr_vdde_lvl_hv

—

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 29. AVG IDDE specifications

Cell

Period (ns)

Load (pF)¹

VDDE (V)

Drive/slew select

IDDE (mA)

pad_msr_hv²

5.5

5.3

1.1

317

425

200

pad_ssr_hv²

130

650

840

2.5

0.5

1.5

200

All loads are lumped loads.

Average current is for pad configured as output only. Use pad_i current for input.

4.8.3

DC specification for CMOS090_ddr library @ VDDE = 3.3 V

Table 30. DC electrical specifications at 3.3 V VDDE

Value

Symbol

Parameter

Unit

SpecID

Min

Max

Vdd

Vdde

Vdd33

Vref

Vtt

SR Core supply voltage

SR I/O supply voltage

SR I/O pre-driver supply voltage

SR Input reference voltage

SR Termination voltage

SR Input high voltage

1.08

3.0

1.32

3.6

D9.71

D9.72

D9.73

D9.74

D9.75

D9.76

D9.77

D9.78

D9.79

3.0

3.6

1.3

1.7

Vref–0.05

Vref+0.20

—

Vref+0.05

—

Vih

Vil

SR Input low voltage

Vref–0.2

—

Voh

Vol

SR Output high voltage

SR Output low voltage

Vtt+0.8

—

Vtt–0.8

Table 31. Output drive current @ VDDE = 3.3 V (+/-10%)

Pad

Drive mode

Minimum Ioh (mA)

Minimum Iol (mA)

pad_st_acc

pad_st_dq

111

–16

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 31. Output drive current @ VDDE = 3.3 V (+/-10%) (continued)

Pad

Drive mode

Minimum Ioh (mA)

Minimum Iol (mA)

pad_st_clk

pad_st

111

–16

pad_st_odt

pad_st_ck

4.8.4

DC specification for CMOS090_ddr library @ VDDE = 2.5 V

Table 32. DC electrical specifications at 2.5 V VDDE

Value

Symbol

Parameter

Unit

SpecID

Min

Max

Vdd

Vdde

Vdd33

Vref

Vtt

Core supply voltage

I/O supply voltage

1.08

2.3

1.32

2.7

D9.80

D9.81

D9.82

D9.83

D9.84

D9.85

D9.86

D9.87

D9.88

I/O pre-driver supply voltage

Input reference voltage

Termination voltage

Input high voltage

3.0

3.6

0.49×Vdde

Vref–0.04

Vref+0.15

—

0.51×Vdde

Vref+0.04

—

Vih

Vil

Input low voltage

Vref–0.15

—

Voh

Vol

Output high voltage

Output low voltage

Vtt+0.81

—

Vtt–0.81

Table 33. Output drive current @ VDDE = 2.5 V (+/-200mV)

Pad

Drive mode

Minimum Ioh (mA)

Minimum Iol (mA)

Libraries

pad_st_acc

pad_st_dq

pad_st_ck

011

–16.2

16.2

6MDDR

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.8.5

DC specification for CMOS090_ddr library @ VDDE = 1.8 V

Table 34. DC electrical specifications for 1.8 V VDDE

Value

Symbol

Parameter

Unit

SpecID

Min

Max

Vdd

Vdde

Vdd33

Vref

Vtt

Core supply voltage

I/O supply voltage

1.08

1.7

1.32

1.9

D9.89

D9.90

D9.91

D9.92

D9.93

D9.94

D9.95

D9.96

D9.97

I/O pre-driver supply voltage

Input reference voltage

Termination voltage

Input high voltage

3.0

3.6

0.49×Vdde

Vref–0.04

Vref+0.125

—

0.51×Vdde

Vref+0.04

—

Vih

Vil

Input low voltage

Vref–0.125

—

Voh

Vol

Output high voltage

Output low voltage

Vtt+0.81

—

Vtt–0.81

Table 35. Output drive current @ VDDE = 1.8 V (+/-100mV)

Pad

Drive mode

Minimum Ioh (mA)

Minimum Iol (mA)

Libraries

pad_st_acc

pad_st_dq

pad_st_clk

000

001

010

110

000

001

010

110

000

001

010

110

–3.57

–7.84

–5.36

–13.4

–3.57

–7.84

–5.36

–13.4

–3.57

–7.84

–5.36

–13.4

3.57

7.84

5.36

13.4

3.57

7.84

5.36

13.4

3.57

7.84

5.36

13.4

6MDDR

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 36. ODT DC electrical characteristics

Value

Symbol

Parameter

Condition

Unit SpecID

Min

Typ

Max

Rtt SR C Effective impedance Rainbow supports only 150

120

150

180

D9.98

value

ohm termination and that

can be enabled by enabling

any bit of the termination

control register (all of them

are OR’ed).

Table 37. core_v_det_odt and core_v_det33_odt specifications

VDDE

VDD

Vtrip max (V)

Vtrip min

Hysteresis min (V)

3.5

Rising

Falling

Rising

Falling

0.0

0.79

0.56

0.65

0.33

1.40

0.44

0.07

1.62

0.3

0.16

—

Rising

0.3

4.8.6

SMD Characteristics

Table 38. SMD pad electrical characteristics

Value

Typ

Symbol

Parameter

Conditions

Unit

Max

Min

V_IL

V_IH

CC P Low level input voltage

CC P High level input voltage

CC C Schmitt trigger hysteresis

CC P Low level output voltage

—

–0.4

0.65×V_DDM

0.1×V_DDM

—

0.35×V_DDM

V_DDM+0.4

—

V_HYST

V_OL

—

I_OL= 20 mA¹

I_OL= 30 mA²

I_OH= –20 mA¹

I_OH= –30 mA²

0.32

0.48

—

V_OH

CC P High level output voltage

V_DDM–0.32

V_DDM–0.48

—

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 38. SMD pad electrical characteristics (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

I_PU

CC P Internal pull-up device current V_in=V_IL

V_in=V_IH

–130

—

μA

I_PD

CC P Internal pull-down device

current

V_in=V_IL

V_in=V_IH

—

130

—

I_IN

CC P Input leakage current

—

–1

—

R_DSONHCC C SMD pad driver active high

impedance

I_OH≤ –30 mA²

R_DSONLCC C SMD pad driver active low

impedance

I_OL≤ 30 mA²

—

V_OMATCHCC C Output driver matching

V_OH/ V_OL

I_OH/ I_OL≤ 30 mA²

VDD = 5.0 V ±10%, Tj = –40 to +140 °C.

VDD = 5.0 V ±10%, Tj = –40 to +120 °C.

V_DD/2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

V_OL

Pad

Output

Figure 7. Pad output delay

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 39. SMD pad delays

Conditions

Value

Symbol

Parameter

Unit

Min

Typ

Max

—

CC D SMD pad delay

CL=50pf

—

165

V_DD=5V±10%

SRE=1

CL=50pf

—

350

V_DD=5V±10%

SRE=0

—

CC D SMD pad delay

CL=50pf

V_DD=3.3V±10%

SRE=1

CL=50pf

V_DD=3.3V±10%

SRE=0

4.9

SSD Characteristics

Table 40. SSD electrical characteristics

Value¹

Symbol

Parameter

Unit

Min

Typ

Max

V_VREF

I_VREF

R_IN

CC P Reference voltage (I_VREF= 0)

CC P Reference voltage output current

CC D Input resistance (against V_DDM/2)

CC C Input common mode range

V_DDM/2 – 0.03

V_DDM/2

—

V_DDM/2 + 0.03

MΩ

1.85

0.8

—

1.2

1.0

V_IN

V_SSM

0.549

–9

—

V_DDM

0.597

SSD_CONSTCC C SSD constant

0.572

—

SSD_OFFSETCC C SSD offset (unipolar, N_sample

256)

counts

SSD offset (bipolar, N_sample= 256)

–8

–5

—

SSD offset (bipolar with offset

cancellation, N_sample= 256)

f_SSDSMP

CC D SSD cmpout sample rate

0.5

—

2.0

MHz

Vdd = 5.0V 10%, Tj = –40 to +140 °C.

4.10 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Figure 8. Startup reset requirements

V_RESET

hw_rst

‚Äò

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

FRST

NFRST

Figure 9. Noise filtering on reset signal

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 41. Reset electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ

Max

V_IH

V_IL

SR P Input High Level CMOS

Schmitt Trigger

—

0.65V_DD

—

V_DD+0.4

D8.1

D8.2

D8.3

D8.4

SR P Input low Level CMOS

Schmitt Trigger

-0.4

0.1V_DD

—

0.35V_DD

—

V_HYS

V_OL

CC³D Input hysteresis CMOS

Schmitt Trigger

CC⁴P Output low level

Push Pull, I_OL= 2mA,

V_DD= 5.0V ± 10%, ipp_hve =

0.1V_DD

(recommended)

Push Pull, I_OL= 1mA,

V_DD= 5.0V ± 10%, ipp_hve =

1⁵

—

0.1V_DD

0.5

Push Pull, I_OL= 1mA,

V_DD= 3.3V ± 10%, ipp_hve =

1 (recommended)

T_tr

CC⁴T Output transition time out- C_L= 25pF,

D8.5

put pin⁶

MEDIUM configuration

V_DD= 5.0V ± 10%, ipp_hve =

C_L= 50pF,

V_DD= 5.0V ± 10%, ipp_hve =

C_L= 100pF,

V_DD= 5.0V ± 10%, ipp_hve =

C_L= 25pF,

V_DD= 3.3V ± 10%, ipp_hve =

C_L= 50pF,

V_DD= 3.3V ± 10%, ipp_hve =

C_L= 100pF,

V_DD= 3.3V ± 10%, ipp_hve =

W_FRST

SR T RESET Input Filtered Pulse

—

D8.6

D8.7

W_NFRSTSR T RESET Input Not Filtered

Pulse

400

|I_WPU

CC⁴T Weak pull-up current abso-

lute value

—

µA D8.8

V_DD= 3.3V ± 10% / 5.0V ± 10%, T_A= -40 / +105^oC, unless otherwise specified.

All values need to be confirmed during device validation.

Data based on characterization results, not tested in production.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Guaranteed by design simulation.

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the refer-

ence manual).

C_Lcalculation should include device and package capacitance (C_PKG< 5pF).

4.11 Fast external crystal oscillator (4–16 MHz) electrical

characteristics

This device implements the fast external oscillator (FXOSC) using a low power Loop Controlled Pierce Oscillator (LCP)

configuration.

Table 42. Fast external crystal oscillator electrical characteristics

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Typ

Max

f_OSC

Crystal oscillator range

Startup current

Loop controlled Pierce

4.0

100

—

4¹

—

MHz

µA

O9.1

O9.2

O9.3

O9.4

O9.5

i_OSC

—

t_UPOSC

t_CQOUT

f_CMFA

Oscillator start-up time

Clock quality check time-out

Loop controlled Pierce

50²

2.5

800

—

0.45

200

Clock monitor failure assert

frequency

400

—

kHz

f_EXT

t_EXTL

t_EXTH

External square wave input

frequency²

—

2.0

9.5

—

MHz

O9.6

O9.7

O9.8

External square wave pulse

width low

—

External square wave pulse

width high

—

t_EXTR

t_EXTF

External square wave rise time

External square wave fall time

Input capacitance

—

O9.9

O9.10

O9.11

O9.12

—

C_IN

EXTAL and XTAL pins

—

V_IH,EXTAL

EXTAL pin input high voltage²

0.75×

V_DDPLL

—

V_DDPLL

+0.3

V_IL,EXTAL

EXTAL pin input low voltage²

EXTAL pin input hysteresis²

—

0.25×

V_DDPLL

O9.13

V_SSPLL

0.3

—

V_HYS,EXTAL

V_PP,EXTAL

—

180

1.0

—

O9.14

O9.15

EXTAL pin oscillation amplitude Loop controlled Pierce

f_OSC= 4 MHz, C = 22 pF.

Maximum value is for extreme cases using high Q, low frequency crystals.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.12 Slow external crystal oscillator (32 KHz) electrical characteristics

The device provides a slow external oscillator/resonator driver (SXOSC).

PC[15]

PC[14]

DEVICE

Figure 10. Crystal oscillator and resonator connection scheme

NOTE

PC[14]/PC[15] must not be directly used to drive external circuits.

DDMIN

XTAL

1/f

XOSCLP

90%

10%

valid internal clock

XOSCLPSU

Figure 11. Slow external crystal oscillator electrical characteristics

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 43. Slow external crystal oscillator electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ

Max

f_XOSCLPSR C Oscillator frequency

V_XOSCLPCC³C Oscillation amplitude

—

kHz O10.1

_DDA=3.3V 10%,

1.12

1.33

1.74

O10.2

V_{DDE_A}=3.3V 10%

V_DDA=5.0V 10%,

1.12

1.37

1.74

V_{DDE_A}=5.0V 10%

I_XOSCLPCC³D Oscillator consumption

—

µA

O10.3

O10.4

T_XOSCLPSCC³D Oscillator start-up time

V_IH

SR C Input high level CMOS Oscillator bypass mode 0.65V_DDA

Schmitt Trigger 0.65V_{DDE_A}

—

V_DDA+0.4

V_{DDE_A}+0.4

O10.5

O10.6

V_IL

SR C Input low level CMOS Oscillator bypass mode V_SS–0.4

Schmitt Trigger

0.35V_DDA

0.35V_{DDE_A}

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Granted by device validation.

4.13 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the fast

external oscillator driver.

Table 44. FMPLL electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ

Max

120 MHz O11.1

52.5 O11.2

f_PLLIN

SR T PLL reference clock³

—

47.5

—

Δ_PLLIN

SR T PLL reference clock duty cycle³

—

f_PLLOUTCC⁴T PLL output clock frequency

f_CPU

CC⁴T System clock frequency

—

250⁵MHz O11.3

125⁶MHz O11.4

—

T_LOCKCC⁴T PLL lock time

Stable oscillator (f_PLLIN= 10 MHz)

—

100

509

µs O11.5

ps O11.6

ΔT_PKJITCC⁴T PLL jitter

f_PLLOUT(PHI i.e. FMPLL O/P) = –509

15.625 MHz @ 10 MHz resonator

ΔT_LTJITCC⁴T PLL long term jitter

f_PLLIN= 10 MHz (resonator)

T_A= 25°C

–2.4

—

2.4

ns O11.7

µA O11.8

I_PLL

CC⁷D Current Consumption (Normal

Mode for Analog Supply)

500

V_DDPLL= 1.2 V ± 10%, T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in functional

mode. When bypass mode is used, oscillator input clock should verify f_PLLINand Δ_PLLIN

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Data based on device simulation.

2x sys clock required for generation of DDR timing.

f_CPUof 125 MHz can be achieved only at temperatures up to 105 °C with a maximum FM depth of 2%.

Data based on characterization results, not tested in production

4.14 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.

Table 45. Fast internal oscillator electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ Max

f_RCM

CC³P RC oscillator high frequency

T_A= 25 °C, trimmed

—

MHz O12.1

I_RCMRUNCC³D RC oscillator high frequency current in run- T_A= 25 °C, trimmed

ning mode

200 µA O12.2

I_RCMPWDCC³D RC oscillator high frequency current in power T_A= 25 °C

down mode

—

µA O12.3

O12.5

ΔRCMVAR CC⁴C RC oscillator variation in temperature and

supply with respect to f_RCat T_A= 55 °C in

high-frequency configuration

—

–5

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Guaranteed by device simulation, not tested in production.

Guaranteed by device characterization, not tested in production.

4.15 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module.

Table 46. Slow internal RC oscillator electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ Max

f_RCL

I_RCL

CC³P RC oscillator low frequency

T_A= 25 °C, trimmed

—

128

—

kHz O13.1

CC³D RC oscillator low frequency current

µA

O13.2

O13.4

ΔRCLVAR CC³C RC oscillator variation in temperature and High frequency config- –10

—

+10

supply with respect to f_RCat T_A= 55 °C in uration

high frequency configuration

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Guaranteed by device simulation, not tested in production

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.16 Flash memory electrical characteristics

Table 47. Program and erase specifications

Min

Value

Typical

Value¹

Initial

Max²

Symbol

Parameter

Max³Unit

SpecID

T_dwprogram

T_16kpperase

T_64kpperase

C Double Word (64 bits) Program Time⁴

C 16 KB Block Pre-program and Erase Time

C 64 KB Block Pre-program and Erase Time

—

500

5000

7500

15000

μs

D14.1

D14.2

D14.3

D14.4

D14.5

1000

1800

2600

5200

T_128kpperaseC 128 KB Block Pre-program and Erase Time

T_256kpperaseC 256 KB Block Pre-program and Erase Time

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change

pending device characterization.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program & erase times occur after the specified number of program/erase cycles. These maximum values are

characterized but not guaranteed.

Actual hardware programming times. This does not include software overhead.

Table 48. Flash module life

Value

Symbol

Parameter

Conditions

Unit SpecID

Min

Typ

P/E

C Number of program/erase cycles per block

for 16 KB, 48KB and 64KB blocks, across

full operating temperature range (Tj)

—

100,000

—

P/E

cycles

D14.6

D14.7

D14.8

P/E

C Number of program/erase cycles per block

for 128KB and 256KB blocks, across full

operating temperature range (Tj)

—

1, 000

100,000

P/E

cycles

Data

retention

C Minimum data retention at 85 °C average Blocks with 0 - 1,000 P/E

—

Years

ambient temperature¹

cycles

Blocks with 1,001 -

10,000 P/E cycles

Blocks with 10,001 -

100,000 P/E cycles

Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature

range.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.17 ADC parameters

The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.

Offset Error OSE

Gain Error GE

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DDA

1018

(2)

code out

(1)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

1 LSB (ideal)

1017 1018 1019 1020 1021 1022 1023

(LSB

)

ideal

in(A)

Offset Error OSE

Figure 12. ADC Characteristics and Error Definitions

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

4.17.1 Input Impedance and ADC Accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered.

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor

with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as

possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources

charge during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to

be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being

substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path

to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330kΩ is obtained (R

1 / (fc*C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage

partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit

must be designed to respect the Equation 5:

Eqn. 5

R + R + R + R

+ R

--------------------------------------------------------------------------

V •

< -- LSB

Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R

and R ) can be neglected with respect to external resistances.

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

Channel

Sampling

Selection

Source

Filter

Current Limiter

SW1

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

SW1

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

Figure 13. Input Equivalent Circuit (Precise Channels)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

EXTERNAL CIRCUIT

Filter

INTERNAL CIRCUIT SCHEME

Channel

Selection

Extended

Switch

Sampling

Source

Current Limiter

SW2

SW1

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance (two contributions R

Sampling Switch Impedance

and R

)

SW1

SW2

Pin Capacitance (three contributions, C , C and C )

Sampling Capacitance

Figure 14. Input Equivalent Circuit (Extended Channels)

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are

initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 13): A charge sharing phenomenon

is installed when the sampling phase is started (A/D switch close).

Voltage Transient on C_S

ΔV < 0.5 LSB

τ₁< (R_SW+ R_AD) C_S<< T_S

τ₂= R_L(C_S+ C_P1+ C_P2)

Figure 15. Transient Behavior during Sampling Phase

In particular two different transient periods can be distinguished:

A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C

•

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be

faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,

and the time constant is

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Eqn. 6

C • C

--------------------

) •

= (R

+ R

C + C

Equation 6 can again be simplified considering only C as an additional worst condition. In reality, the transient is

faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T

is always much longer than the internal time constant:

Eqn. 7

τ < (R

+ R

) • C « T

AD S S

The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance

according to Equation 8:

Eqn. 8

• (C + C + C ) = V • (C + C

)

•

A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance

R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality

would be faster), the time constant is:

Eqn. 9

τ < R • (C + C + C )

P1 P2

In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed

well before the end of sampling time T , a constraints on R sizing is obtained:

Eqn. 10

10 • τ = 10 • R • (C + C + C ) < T

P1 P2 S

Of course, R shall be sized also according to the current limitation constraints, in combination with R (source

impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V

P1 P2

(at the end of the charge transfer transient) will be much higher than V . Equation 11 must be respected (charge

balance assuming now C already charged at V ):

Eqn. 11

• (C + C + C + C ) = V • C + V • (C + C + C )

P1 P2 A1 P1 P2

The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to

provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of

F F

the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Analog Source Bandwidth (V )

ℜ≤ 2 R C (Conversion Rate vs. Filter Pole)

F F

Noise

= f (Anti-aliasing Filtering Condition)

2 f ℜ≤ f (Nyquist

Anti-Aliasing Filter (f = RC Filter pole)

Sampled Signal Spectrum (f = conversion Rate)

Figure 16. Spectral Representation of Input Signal

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),

according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater

than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a

specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the

sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the

sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage

drop on C ; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled

voltage on C :

Eqn. 12

+ C + C

----------- = -------------------------------------------------------

+ C + C + C

P2 S

From this formula, in the worst case (when V is maximum, that is for instance 5V), assuming to accept a maximum error of

half a count, a constraint is evident on C value:

Eqn. 13

> 2048 • C

4.17.2 ADC electrical characteristics

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 49. ADC electrical characteristics

Value²

Symbol

Parameter

Conditions¹

Min

Unit SpecID

Typ

Max

V_SSA

SR D Voltage on VSSA (ADC

—

-0.1

—

0.1

D15.1

D15.2

D15.3

reference) pin with re-

spect to ground (V_SS

)

V_DDA

SR D Voltage on VDDA pin

(ADC reference) with re-

—

V_{DDE_A}–0.1

—

V_{DDE_A}+0.1

spect to ground (V_SS

)

V_AINx

f_ADC

SR D Analog input voltage⁴

—

V_SSA-0.1

—

V_DDA+0.1

SR D ADC analog frequency

1.5

—

MHz D15.4

t_{ADC_PU}SR D ADC power up delay

t_{ADC_S}CC⁵T Sample time⁶

—

µs

D15.5

D15.6

f_ADC= 32 MHz,

ADC_conf_sample_input=

0.5

_ADC= 6 MHz,

—

ADC_conf_sample_input=

127

t_{ADC_C}CC⁵T Conversion time⁷

f_ADC= 32 MHz,

ADC_conf_comp = 2

0.625

—

µs

D15.7

D15.8

D15.9

D15.10

D15.11

C_S

CC⁵D ADC input sampling

capacitance

—

C_P1

C_P2

C_P3

CC⁵D ADC input pin

capacitance 1

—

CC⁵D ADC input pin

capacitance 2

—

CC⁵D ADC input pin

capacitance 3

—

R_SW1CC⁵D Internal resistance of

analog source

—

kΩ D15.12

kΩ D15.13

kΩ D15.14

mA D15.15

R_SW2CC⁵D Internal resistance of

analog source

—

R_AD

CC⁵D Internal resistance of

analog source

—

0.1

I_INJ

SR T Input current Injection

Current injection on one

ADC input, different from

the converted one

-10

INL

CC⁵P Integral Non Linearity

No overload

-1.5

-1.0

—

1.5

1.0

—

LSB D15.16

LSB D15.17

LSB D15.18

LSB D15.19

DNL CC⁵P Differential Non Linearity

OFS CC⁵T Offset error

After offset cancellation

—

0.5

0.6

GNE CC⁵T Gain error

—

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 49. ADC electrical characteristics (continued)

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ

Max

TUEP CC⁵T Total Unadjusted Error for No overload

precise channels, input

-2

—

LSB D15.22

LSB

overload conditions on

adjacent channel

—

only pins

TUEX CC⁵T Total Unadjusted Error for No overload

extended channel,

-3

—

LSB D15.23

LSB

overload conditions on

adjacent channel

—

V_DDA= 3.3 V ± 10% / 5.0 V ± 10%, T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Analog and digital V_SSmust be common (to be tied together externally).

V_AINxmay exceed V_SSAand V_DDAlimits, remaining on absolute maximum ratings, but the results of the conversion will be

clamped respectively to 0x000 or 0x3FF.

Guaranteed by design.

During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal resistance

of the analog source must allow the capacitance to reach its final voltage level within t_{ADC_S}. After the end of the sample time

t_{ADC_S}, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t_{ADC_S}

depend on programming.

This parameter does not include the sample time t_{ADC_S}, but only the time for determining the digital result and the time to

load the result’s register with the conversion result.

4.18 AC specifications

4.18.1 AC specification for CMOS090LP2 library @ VDDE = 3.3 V

Table 50. Functional pad type AC specifications

Prop. delay (ns)

Drive/slew

rate select

Rise/fall edge (ns)

L>H / H>L¹

Drive load

Name

(pF)

Min

Max

Min

Max

MSB, LSB

pad_ssr

—

4.5 / 4.5

8 / 8

—

2.2 / 2.2

6 / 6

200

11²

45 / 45

22 / 22

28 / 28

42 / 42

50 / 50

210 / 210

220 / 220

60 / 60

200

90 / 90

110 / 110

430 / 430

480 / 480

200

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 50. Functional pad type AC specifications (continued)

Prop. delay (ns)

Drive/slew

rate select

Rise/fall edge (ns)

L>H / H>L¹

Drive load

Name

(pF)

Min

Max

Min

Max

MSB, LSB

pad_fc

—

2.5 / 2.5

4.0 / 4.5

7.3 / 8.3

24 / 22

—

1.2 / 1.2

1.02 / 1.4

3.5 / 4.2

9.1 / 10.3

14 / 15

11²

pad_msr

200

33 / 31

200

49 / 44

18 / 21

60 / 53

24 / 25

200

332 / 302

362 / 325

126 / 151

136 / 158

200

L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay.

Can be used on the tester.

4.18.2 AC specification for CMOS090LP2fg library @ VDDE = 5.0 V

Table 51. Functional pad type AC specifications

Prop. delay (ns)

L>H / H>L¹

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

(pF)

Name

Min

Max

Min

Max

MSB, LSB

pad_msr_hv²

4.6 / 3.7

13 / 10

12 / 12

32 / 32

2.2 / 2.2

9 / 9

5.3 / 5.9

22 / 22

11³

200

N/A

10⁴

12 / 13

23 / 23

69 / 71

95 / 90

28 / 34

52 / 59

5.6 / 6

11 / 14

34 / 35

44 / 51

12 / 15

28 / 31

70 / 74

96 / 96

200

152 / 165

205 / 220

200

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

Table 51. Functional pad type AC specifications (continued)

Prop. delay (ns)

Drive/slew

rate select

Rise/fall edge (ns)

L>H / H>L¹

Drive load

Name

(pF)

Min

Max

Min

Max

MSB, LSB

pad_ssr_hv²

7.3 / 5.7

24 / 19

19 / 18

58 / 58

4.4 / 4.3

17 / 15

N/A

10 / 11

40 / 42

11³

200

10⁴

26 / 27

49 / 45

61 / 69

115 / 115

320 / 330

420 / 420

1.9 / 1.9

13 / 13

27 / 23

72 / 74

90 / 85

0.3 / 0.3

30 / 34

61 / 61

200

137 / 142

182 / 172

0.5 / 0.5

156 / 164

200 / 200

1.5 / 1.5

200

0.5

pad_i_hv

N/A

L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay.

For input buffer timing, look at pad_i_hv.

Can be used on the tester.

This drive select value is not supported. If selected, it will be approximately equal to 11.

4.18.3 AC specification for CMOS090LP2fg library @ VDDE = 3.3 V

Table 52. Functional pad AC type specifications

Prop. delay (ns)

L>H / H>L

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

(pF)

Name

Min

Max

Min

Max

MSB, LSB

pad_msr_hv

5.8 / 4.4

16 / 13

18 / 17

46 / 49

2.7 / 2.1

11.2 / 8.6

N/A

7.6 / 8.5

30 / 34

200

14 / 16

27 / 27

37 / 45

69 / 82

6.5 / 6.7

15 / 13

38 / 38

53 / 46

15.5 / 19

38 / 43

200

83 / 86

200 / 210

270 / 285

86 / 86

113 / 109

120 / 120

200

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

100

Freescale Semiconductor

Table 52. Functional pad AC type specifications (continued)

Prop. delay (ns)

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

L>H / H>L

Name

(pF)

Min

Max

Min

Max

MSB, LSB

pad_ssr_hv

9.2 / 6.9

30 / 23

27 / 28

81 / 87

5.5 / 4.1

21 / 16

15 / 17

57 / 63

200

N/A

31 / 31

58 / 52

80 / 90

144 / 155

415 / 415

533 / 540

3 / 3

15.4 / 15.4

32 / 26

38 / 42

82 / 85

200

162 / 168

216 / 205

0.5 / 0.5

80 / 82

190 / 190

250 / 250

1.5 / 1.5

106 / 95

0.4 / 0.4

200

0.5

pad_i_hv

N/A

4.18.4 AC specification for CMOS090_ddr library @ VDDE = 3.3 V

Table 53. AC specifications at 3.3 V VDDE

Prop. delay (ns)

L>H / H>L

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

(pF)

Name

Libraries

6MDDR

Min

Max

Min

Max

MSB, LSB

pad_st_acc

pad_st_dq

pad_st_clk

1.4/1.4

1.7/1.7

1.4/1.4

1.7/1.7

1.4/1.4

1.6/1.6

2.4/2.4

2.7/2.7

2.4/2.4

2.7/2.7

2.4/2.4

2.6/2.6

3.1/2.5

0.9/1.1

3.1/2.5

0.9/1.1

3.1/2.5

1.1/1.3

5.6/5.4

1.7/2.0

5.6/5.4

1.7/2.0

5.7/5.7

2.3/2.3

111

4.18.5 AC specification for CMOS090_ddr library @ VDDE = 2.5 V

Table 54. AC specifications at 2.5 V VDDE

Prop. delay (ns)

L>H / H>L

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

(pF)

Name

Libraries

6MDDR

Min

Max

Min

Max

MSB, LSB

pad_st_acc

pad_st_dq

pad_st_clk

1.4/1.5

1.7/1.7

1.4/1.5

1.7/1.7

1.4/1.4

1.1/1.6

2.5/2.4

2.8/2.7

2.5/2.4

2.8/2.7

2.4/2.4

2.7/2.7

2.1/2.1

0.6/0.7

2.1/2.1

0.6/0.7

2.1/2.1

0.6/0.7

4.3/4.1

1.1/1.3

4.3/4.1

1.1/1.3

4.4/4.1

1.6/1.8

011

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

101

4.18.6 AC specification for CMOS090_ddr library @ VDDE = 1.8 V

Table 55. AC electrical specifications at 1.8 V VDD

Prop. delay (ns)

L>H / H>L

Drive/slew

rate select

Rise/fall edge (ns)

Drive load

(pF)

Name

Libraries

Min

Max

Min

Max

MSB, LSB

pad_st_acc

1.4/1.4

1.7/1.7

1.4/1.5

1.7/1.7

1.4/1.5

1.7/1.7

1.4/1.5

1.7/1.8

1.4/1.4

1.7/1.7

1.4/1.5

1.7/1.7

1.4/1.5

1.7/1.7

1.4/1.5

1.7/1.8

1.4/1.4

1.6/1.6

1.4/1.4

1.7/1.7

1.4/1.4

1.6/1.6

1.4/1.5

1.7/1.8

2.4/2.4

2.8/2.7

2.4/2.5

2.8/2.8

2.4/2.4

2.8/2.7

2.5/2.5

2.8/2.8

2.4/2.4

2.8/2.7

2.4/2.5

2.8/2.8

2.4/2.4

2.8/2.7

2.5/2.5

2.8/2.8

2.4/2.4

2.7/2.7

2.4/2.4

2.7/2.7

2.4/2.4

2.7/2.7

2.5/2.5

2.7/2.7

0.6/1.0

0.2/0.4

1.1/1.1

0.4/0.4

1.0/1.1

0.3/0.4

1.5/1.1

0.4/0.4

0.6/1.0

0.2/0.4

1.1/1.1

0.4/0.4

1.0/1.1

0.3/0.4

1.5/1.1

0.4/0.4

0.4/0.6

0.7/0.9

1.1/1.1

0.3/0.4

0.9/1.1

0.3/0.4

1.5/1.2

0.4/0.4

2.7/2.6

0.5/0.6

3.0/2.7

0.7/0.7

2.9/2.7

0.6/0.7

3.1/2.6

0.7/0.6

2.7/2.6

0.5/0.6

3.0/2.7

0.7/0.7

2.9/2.7

0.6/0.7

3.1/2.6

0.7/0.6

2.7/2.7

1.8/3.4

3.0/2.8

1.0/1.1

3.0/2.8

0.9/1.0

3.2/2.6

1.1/1.2

000

6MDDR

001

010

110

000

001

010

110

000

001

010

110

pad_st_dq

6MDDR

pad_st_clk

6MDDR

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

102

Freescale Semiconductor

4.19 AC timing

4.19.1 IEEE 1149.1 interface timing

Table 56. JTAG Interface Timing

Num

Symbol

t_JCYC

Characteristic

Min

Max

Unit

SpecID

CC²D TCK Cycle Time

100

—

A1.1

A1.2

A1.3

A1.4

A1.5

A1.6

A1.7

A1.8

A1.9

A1.10

t_JDC

CC²D TCK Clock Pulse Width (Measured at V_DD/2)

CC²D TCK Rise and Fall Times (40% – 70%)

t_TCKRISE

_TMSS,t_TDISCC²D TMS, TDI Data Setup Time

—

t_{TMSH, TDIH}

t_TDOV

t_TDOI

CC²D TMS, TDI Data Hold Time

—

CC²D TCK Low to TDO Data Valid

CC²D TCK Low to TDO Data Invalid

CC²D TCK Low to TDO High Impedance

CC²D TCK Falling Edge to Output Valid

t_TDOHZ

t_BSDV

t_BSDVZ

—

CC²D TCK Falling Edge to Output Valid out of High

Impedance

t_BSDHZ

t_BSDST

t_BSDHT

CC²D TCK Falling Edge to Output High Impedance

CC²D Boundary Scan Input Valid to TCK Rising Edge

—

A1.11

A1.12

A1.13

CC²D TCK Rising Edge to Boundary Scan Input Invalid

These specifications apply to JTAG boundary scan only. JTAG timing specified at V_DD= 3.0 V to 3.6 V, T_A= -40 to 105 °C,

and CL = 50 pF with SRC = 0b01.

Parameter values guaranteed by design.

TCK

Figure 17. JTAG Test Clock Input Timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

103

TCK

TMS, TDI

TDO

Figure 18. JTAG Test Access Port Timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

104

Freescale Semiconductor

TCK

Output

Signals

Output

Signals

Input

Signals

Figure 19. JTAG Boundary Scan Timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

105

4.19.2 Nexus Debug Interface

Table 57. Nexus Debug Port Timing

Num

Symbol

t_MCYC

Characteristic

Min

Max

Unit

SpecID

CC²D MCKO Cycle Time

0.1

—

0.2

—

A2.1

A2.2

A2.3

A2.4

A2.5

A2.6

A2.7

A2.8

A2.9

A2.10

A2.11

t_MDC

t_MDOV

t_MSEOV

t_EVTOV

t_EVTIPW

t_EVTOPW

t_TCYC

CC²D MCKO Duty Cycle

CC²D MCKO Low to MDO Data Valid³

CC²D MCKO Low to MSEO Data Valid³

CC²D MCKO Low to EVTO Data Valid³

CC²D EVTI Pulse Width

t_MCYC

t_TCYC

t_MCYC

CC²D EVTO Pulse Width

—

CC²D TCK Cycle Time⁴

100

—

t_TDC

CC²D TCK Duty Cycle

—

_NTDIS,t_NTMSSCC²D TDI, TMS Data Setup Time

t_NTDIH,

t_NTMSH

CC²D TDI, TMS Data Hold Time

—

t_JOV

CC²D TCK Low to TDO Data Valid

A2.12

JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from

50% of MCKO and 50% of the respective signal. Nexus timing specified at V_DD= 3.0 V to 3.6 V, T_A= -40 to 105 °C, and CL

= 50 pF (Cl=30 pF on MCKO), with SRC = 0b10 for MCKO and 0b11 for others.

Parameter values guaranteed by design.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

The system clock frequency needs to be three times faster that the TCK frequency.

NOTE

Nexus Dual Data Rate is not supported. The timings are mentioned for dedicated pins on

416BGA. The max value for #2, 3 and 4 above, are 0.3 of tMCYC for shared nexus ports.

MCKO

MDO

MSEO

EVTO

Output Data Valid

Figure 20. Nexus Output Timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

106

Freescale Semiconductor

TCK

Figure 21. Nexus TCK Timing

TCK

TMS, TDI

TDO

Figure 22. Nexus TDI, TMS, TDO Timing

4.19.3 Interface to TFT LCD Panels (DCU3 and DCULite)

Figure 23 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure

signals are shown with positive polarity. The sequence of events for active matrix interface timing is:

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

107

•

PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active

mode, PCLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on

the panel type.

•

HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted

onto the display. When disabled, the data is invalid and the trace is off.

VSYNC

LINE 1 LINE 2

LINE 3

LINE 4

LINE n-1 LINE n

HSYNC

m-1

PCLK

LD[23:0]

Figure 23. TFT LCD interface timing overview

4.19.3.1 Interface to TFT LCD Panels—Pixel Level Timings

Figure 24 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive

polarity of the PCLK signal (meaning the data and sync signals change on the rising edge) and active-high

polarity of the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and

VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high.

The DE signal is always active-high.

Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are

programmed via the DCU Clock Confide Register (DCCR) in the system clock module.

The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H,

BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V

parameters are programmed via the VSYN_PARA register.

1. In Figure 23, the “LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

108

Freescale Semiconductor

Table 58. LCD interface timing parameters—horizontal and vertical

Num

Symbol

Characteristic

Value

Unit

SpecID

t_PCP

CC¹

Display pixel clock period

HSYNC pulse width

HSYNC back porch width

HSYNC front porch width

Screen width

31.25

A3.1

A3.2

A3.3

A3.4

A3.5

A3.6

t_PWH

t_BPH

t_FPH

t_SW

PW_H _*t_PCP

BP_H * t_PCP

FP_H * t_PCP

DELTA_X * t_PCP

t_HSP

HSYNC (line) period

(PW_H + BP_H + FP_H + DELTA_X ) *

t_PCP

t_PWV

t_BPV

t_FPV

t_SH

CC¹

VSYNC pulse width

VSYNC back porch width

VSYNC front porch width

Screen height

PWV _*t_HSP

BP_V * t_HSP

A3.7

A3.8

FP_V * t_HSP

A3.9

DELTA_Y * t_HSP

A3.10

A3.11

t_VSP

VSYNC (frame) period

(PW_V + BP_V + FP_V + DELTA_Y ) *

t_HSP

Parameter values guaranteed by design.

t_HSP

t_FPH

t_PWH

t_BPH

t_SW

Start of line

PCLK

t_PCP

Invalid Data

DELTA_X

LD[23:0]

HSYNC

Figure 24. Horizontal sync timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

109

t_VSP

t_SH

t_FPV

t_BPV

t_PWV

Start of Frame

HSYNC

t_HCP

LD[23:0]

(Line Data)

DELTA_Y

Invalid Data

HSYNC

Figure 25. Vertical sync pulse

4.19.3.2 Interface to TFT LCD panels—access level

1,2,3,4

Table 59. LCD Interface Timing Parameters

—Access Level

Min.

Value

Typical

Value

Max.

Value

Num

Symbol

Characteristic

PDI Clock Period

Unit

SpecID

t_CKPCC⁵

t_CHDCC⁵

t_DSUCC⁵

t_DHDCC⁵

t_CSUCC⁵

t_CHDCC⁵

CC⁵

31.25

—

A3.12

A3.13

A3.14

A3.15

A3.16

A3.17

A3.18

A3.19

A3.20

A3.21

A3.22

Duty cycle

interface data setup time

PDI interface data access hold time

PDI interface control signal setup time

PDI interface control signal hold time

TFT interface data valid after pixel clock

TFT interface HSYNC valid after pixel clock

TFT interface VSYNC valid after pixel clock

TFT interface DE valid after pixel clock

—

CC⁵

5.5

5.6

—

TFT interface hold time for data and control

bits

CC⁵

Relative skew between the data bits

—

3.7

A3.23

The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve

edge.

Intra bit skew is less than 2 ns.

Load CL = 50 pf for frequency up to 20 MHz.

Load CL = 25 pf for display freq from 20 to 32 MHz.

Parameter values guaranteed by design.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

110

Freescale Semiconductor

t_CHDt_CSU

HSYNC

VSYNC

DDE

PCLK

t_CKH

t_CKL

t_DSUt_DHD

LD[23:0]

Figure 26. LCD Interface Timing Parameters—Access Level

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

111

4.19.4 RSDS Interface to TFT LCD Panels

Table 60. RSDS Electrical Characteristics

Value²

Symbol

Parameter

Conditions¹

Unit SpecID

Min

Typ

Max

AVDD SR D Voltage on VSSE_A pin

with respect to ground

—

3.0

3.3

3.6

A4.1

A4.2

(V_SS

)

I_DDTXSR D Current Consumption:

RSDS Transmitter - Single

Cell

—

2.7

—

I_DDPDSR D Power Down Current

—

µA

A4.3

A4.4

I_DDBGSR D Current Consumption of

Bandgap and buffer

100

Fmax SR D Data Frequency

—

400

1.5

—

MHz

A4.5

A4.6

A4.7

A4.8

V_OD

SR D Differential Output Voltage

SR D Offset Voltage

R_L= 100 Ω

V_CM+/-5%

200

1.2

V_OFF

0.5

—

t_R/ t_FSR D Output Rise / Fall times

20% to 80%,

500

V_OD=200mV, C_L= 5pF

t_XdelaySR D Tx Delay

—

A4.9

SR D Termination Resistance

(external)

5% variation

100

A4.10

SR D Transmitter Settling time

SR D Transmitter Delay

After power down, high

to low

—

µs

A4.11

A4.12

Data in to Tx out

V_DDA= 3.3 V ± 10% T_A= -40 to +105 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

112

Freescale Semiconductor

Figure 27. TCON/RSDS Timing Diagram

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

113

4.19.5 DRAM Interface

DDR Interface specification from ‘MCD - 32 Bit Automotive MCU - CMOS090LP2’ I/O Pad

Specification Revision 1.5 - May14th 2008.

This device supports SDR, DDR1, DDR2 half and full strengths, as well as LPDDR half and full speeds.

Table 61 shows the SRE settings for the different modes.

Table 61. Pad mode configurations

ipp_sre[2:0]

Mode

000

001

010

011

100

101

110

111

1.8V LPDDR Half Speed

1.8V LPDDR Full Speed

1.8V DDR2 Half Strength

2.5V DDR1

Not supported

1.8V DDR2 Full Strength

SDR

1 2 3 4 5 6

Table 62. LPDDR, DDR and DDR2 (DDR2-250) SDRAM timing specifications

At recommended operating conditions with V_{DD_DR}of 5%

No.

—

Symbol

Parameter

Min

—

Max

Unit

—

CC Frequency of Operation (Clock Period)⁷

125

MHz

V_IX-ACCC MCK AC differential crosspoint voltage

DD_DR

× 0.5 – 0.1

× 0.5 + 0.1

DD1

DD2

DD3

DD4

t_SDCK

CC Clock period

—

t_SDCKHCC HIGH pulse width ⁸

t_SDCKLCC LOW pulse width⁹

0.45

—

0.55

tSDCK

0.55

t_CMV

t_CMS

t_CMH

t_DQSS

t_OS

CC Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

(0.5 x t_SDCK

)

SD_CS[1:0] - Output Valid⁹

+ 1.5

DD4.1

DD5

CC Address, SD_CKE, SD_CAS, SD_RAD, SD_WE,

2.5

2.0

—

SD_CS output setup ((t_SDCK- t_CMV

)

CC Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

DD6

CC Write Command to first DQS Latching Transition

WL +

0.20 x t_SDCK

DD7

CC Data and Data Mask Output Setup (DQ-->DQS)

relative to DQS (DDR Write Mode)^{11 12}

1.0

—

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

114

Freescale Semiconductor

1 2 3 4 5 6

Table 62. LPDDR, DDR and DDR2 (DDR2-250) SDRAM timing specifications

At recommended operating conditions with V_{DD_DR}of 5% (continued)

No.

—

Symbol

Parameter

Min

Max

Unit

DD8

t_OH

CC Data and Data Mask Output Hold (DQS-->DQ)

relative to DQS (DDR Write Mode)¹³

1.0

—

DD9,

t_IS

CC Input Data Skew relative to DQS¹⁴

-(0.25*t_SDCK- 0.25*t_SDCK

DD10

0.8)

0.8

value is 1.8 V for DDR2 mode, 2.5 V for DDR1 mode, and 1.8 V for LPDDR mode.

DD_DR

C_Zat -40, 140, 25 ^oC.

Measured with clock pin loaded with differential 100 ohm termination resistor.

All transitions measured at mid-supply (

V_{DD_DR}/2).

Measured with all outputs except the clock loaded with 50 ohm termination resistor to

V_{DD_DR}/2.

Data input hold is derived from each DDR_DQS clock edge. It begins with a DDR_DQS transition and ends when the first

data line becomes invalid.

The DRAM interface operates at the same frequency as the internal system bus.

Pulse width high plus pulse width low cannot exceed min and max clock period.

Command output valid should be half the memory bus clock (t_SDCK) plus some minor adjustments for process, temperature,

and voltage variations.

¹⁰This is alternate representation of t_CMVparameter for clarity.

¹¹This specification relates to the required input setup time of DDR memories. The mcu's output setup should be larger than

the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[31:24]

is relative to DDR_DQS[3]; DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and

DDR_DQ[7:0] is relative to DDR_DQS[0].

¹²The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats

are valid for each subsequent DQS edge.

¹³This specification relates to the required hold time of DDR memories. DDR_DQ[31:24] is relative to DDR_DQS[3];

DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and DDR_DQ[7:0] is relative to

DDR_DQS[0].

¹⁴Data input skew is derived from each DDR_DQS clock edge. It begins with a DDR_DQS transition and ends when the last

data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to

routing or other factors).

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

115

Figure 28 shows the DDR SDRAM write timing.

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

SD_CSn,SD_WE,

CMD

SD_RAS, SD_CAS

DD4

DD6

SD_A[13:0]

ROW

COL

DD7

SD_DM

SD_DQS

SD_D[7:0]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 28. DDR write timing

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

116

Freescale Semiconductor

Figure 29 and Figure 31 show the DDR SDRAM read timing.

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

CL=2

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

CL=2.5

SD_A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS

DD10

SD_D[7:0]

RD1 RD2 RD3 RD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS

SD_D[7:0]

RD1 RD2 RD3 RD4

Figure 29. DDR read timing

Figure 30 provides the AC test load for the DDR bus.

V_{DD_MEM_IO}/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 30. DDR AC test load

4.19.5.1 SDR Timings

Command and address follow the same timings as other modes. For SDRAM reads/Write, the timings

mentioned in the following table apply.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

117

Table 63. SDR Timings

Parameter Min

—

Symbol

Max

Units

DD1

t_QVS

C Data output Valid

(Write transaction)

—

2.5

2.0

—

(0.5 x t_SDCK

)

+ 1.5

DD1.1

DD2

t_QS

t_QH

t_IS

C Data output setup

(t_DSK- DD1)¹

—

C Data output Hold

(Write transaction)

DD3

C Data Input Setup

(Read transaction)

2.0

DD4

t_IH

C Data input Hold (Read

transaction)

—

This is alternate representation for DD1 for better clarity.

Figure 31. SDR Read and Write Timings

4.19.5.2 2.5 V DDR1

Table 64. SSTL_2 Class II 2.5 V DDR DC Specifications

Symbol

Parameter

Condition

Min

Nom

Max

Units

Notes

SpecID

vddet

vdd

P I/O Supply Voltage

P Core Supply Voltage

—

2.30

1.08

1.13

2.50

1.20

1.25

2.70

1.32

1.38

JESD8-9B

—

A5.1

A5.2

A5.3

Vref(dc) P Input Reference Volt-

age

JESD8-9B

Vtt

P Termination Voltage

C DC Input Logic High

C DC Input Logic Low

C AC Input Logic High

C AC Input Logic Low

—

Vref-0.04

Vref+0.15

-0.3

vref

—

Vref+0.04

vddet+0.3

Vref-0.15

—

JESD8-9B

—

A5.4

A5.5

A5.6

A5.7

A5.8

A5.9

V_ih(dc)

V_il(dc)

V_ih(ac)

V_il(ac)

I_in

—

Vref+0.31

—

Vref-0.31

+/-10

P Pad input Leakage

Current

—

µA

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

118

Freescale Semiconductor

Table 64. SSTL_2 Class II 2.5 V DDR DC Specifications (continued)

Symbol

Parameter

Condition

Min

Nom

Max

Units

Notes

SpecID

V_oh

C Output High Voltage

Level

—

vddet-0.35

—

A5.10

V_ol

C Output Low Voltage

Level

—

0.35

—

A5.11

I_oh(dc)

I_ol(dc)

C Output min source dc Vout=Voh

current

-16.2

16.2

mA vddet = 2.3V A5.12

Voh = 1.95V

C Output min sink dc

current

Vout=Vol

—

mA vddet = 2.3V A5.13

Vol = 0.35V

The SSTL_2 differential input switch point is at vref = 0.50*vddet.

NOTE

The JEDEC SSTL_2 specifications (JESD8-9B) for a SSTL interface for class II operation

supersedes any specification in this document.

The SSTL_2 Class II output with ipp_sre[2:0] set to enabling SSTL_2 2.5V DDR1 mode,

at the destination, have a rise/fall time (10%-90%) between 1 ns and 2 ns over process,

voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated at

the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR input

capacitance.

Vtt

70 ohms

Z =70 td= 0.167ns

ipp_do

pad_st/pad_st_odt

4pF

PAD

Figure 32. SSTL_2 CLass II Test Load

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

119

4.19.5.3 1.8 V DDR2

Table 65. SSTL_18 Class II 1.8 V DDR2 DC Specifications

Condi-

tion

Symbol C

Parameter

Min

Nom

Max

Units

Notes

SpecID

vddet

vdd

I/O Supply Voltage

—

1.7

1.08

0.833

1.8

1.2

0.9

1.9

1.32

JESD8-15A

A5.14

A5.15

A5.16

Core Supply Voltage

Vref(dc)

Input Reference Volt-

age

1.0869

JESD8-15A

Vtt

Termination Voltage

DC Input Logic High

DC Input Logic Low

AC Input Logic High

AC Input Logic Low

—

Vref-0.04

Vref+0.125

-0.3

Vref

—

Vref+0.04

vddet+0.3

Vref-0.125

—

JESD8-15A

—

A5.17

A5.18

A5.19

A5.20

A5.21

A5.22

V_ih(dc)

V_il(dc)

V_ih(ac)

V_il(ac)

I_in

—

Vref+0.25

—

Vref-0.25

+/-10

Pad input Leakage

Current

—

µA

V_oh

Output High Voltage

Level

—

vddet-0.28

—

0.28

—

A5.23

A5.24

A5.25

V_ol

Output Low Voltage

Level

I_oh(dc)

Output min source dc Vout=Voh

current

-13.4

mA JESD8-15A

vddet = 1.7V

Voh = 1.42V

I_ol(dc)

Output min sink dc

current

Vout=Vol

13.4

—

mA JESD8-15A

vddet = 1.7V

A5.26

Vol = 0.28V

The SSTL_18 differential input switch point is at vref = 0.50*vddet.

Note that the Jedec SSTL_18 specifications (JESD8-15a) for a SSTL interface for class II operation supersedes any

specification in this document.

The SSTL_18 Class II output with ipp_sre[2:0] set to enabling sstl_2 1.8V DDR2 mode, at the destination, have a rise/fall time

(10%-90%) between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

120

Freescale Semiconductor

td terminated at the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR2 input capacitance. See

Figure 33. "SSTL_18 CLass II Test Load".

Figure 33. SSTL_18 CLass II Test Load

Vtt

Z =70 td= 0.167ns

ipp_do

pad_st/pad_st_odt

4pF

PAD

4.19.5.4 1.8V LPDDR

Table 66. 1.8V LPDDR DC Specifications

Unit

Symbol

Parameter

Condition

Min

Nom

Max

Notes

SpecID

vddet

vdd

I/O Supply Voltage

Core Supply Voltage

—

1.7

1.8

1.2

1.9

JESD79-4

—

A5.27

A5.28

A5.29

A5.30

A5.31

A5.32

A5.33

A5.34

A5.35

1.08

1.32

Data Inputs (DQ, DM, DQS)

V_ih(dc)

V_il(dc)

V_ih(ac)

V_il(ac)

DC Input Logic High

DC Input Logic Low

AC Input Logic High

AC Input Logic low

—

vddet*0.7

-0.3

—

vddet+0.3

vddet*0.3

vddet+0.3

vddet*0.2

JESD79-4

vddet*0.8

-0.3

Data Outputs (DQ, DQS)

V_oh

Output High Voltage Ioh=-0.1mA

Level

vddet*0.9

—

JESD79-4

V_ol

Output Low Voltage

Level

Iol=0.1mA

vddet*0.1

A5.36

Note that the final JEDEC LPDDR SDRAM specifications (JESD79-4) for LPDDR operation supersedes any specification in

this document.

The SSTL_18 output with ipp_sre[2:0] set to enabling 1.8V LPDDR mode, at the destination, have a rise/fall time (10%-90%)

between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated

at the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR input capacitance. See ““Figure 28.

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

Freescale Semiconductor

121

4.19.6 Video Input Unit timing

Clock

f_{PIX_CLK}

t_DHD

t_DSU

Data

Figure 34. VIU2 timing diagram

Table 67. VIU2 timing parameters

Parameter C

f_{PIX_CK}

t_DSU

Description

Min

Typ

Max

Unit

SpecID

D VIU2 pixel clock frequency

D VIU2 data setup time

D VIU2 data hold time

—

MHz

A6.1

A6.2

A6.3

—

t_DHD

PIX_CLK_PERIOD(min) = C1 X IPG_CLK_PERIOD + C2 + J

where

C1 = Device parameter = 2 (if Frequency Modulation is disabled), = 2.04 (if Frequency Modulation is enabled)

C2 = Device Constant = 1.98 ns

J = Max Jitter on PIX_CLK

For example: If IPG_CLK = 125 MHz, FM on PLL is disabled and Max Jitter on PIX_CLK is (+-2ns), then the maximum

frequency of VIU pixel clock will be: PIX_CLK_F = 1/(2x8 + 1.98 + 2)ns = 50.05 MHz

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4.19.7 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing

Table 68. IRQ and NMI Timing

Min.

Value

Max.

Value

Num

Symbol

Characteristic

Unit

SpecID

t_IPWL

t_IPWH

t_ICYC

CC¹D IRQ/NMI Pulse Width Low

CC¹D IRQ/NMI Pulse Width High

CC¹D IRQ/NMI Edge to Edge Time²

200

400

—

A7.1

A7.2

A7.3

Parameter values guaranteed by design.

Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.

1,2

Figure 35. IRQ and NMI Timing

4.19.8 eMIOS timing

Table 69. eMIOS timing

Min.

Max.

value

Num

Symbol

Characteristic

Unit

SpecID

value²

t_MIPW

t_MOPW

CC³D eMIOS Input Pulse Width

CC³D eMIOS Output Pulse Width

—

t_CYC

A8.1

A8.2

eMIOS timing specified at f_SYS= 64 MHz, V_DD12= 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, T_A= -40 to 105 °C, and CL =

50 pF with SRC = 0b00.

There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays.

Refer to the pad specification section for the details.

Parameter values guaranteed by design.

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123

4.19.9 FlexCAN timing

The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain.

There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.

Table 70. FlexCAN timing

Max.

value

Num

Symbol

t_CANOV

t_CANSU

Characteristic

Min. value

Unit SpecID

CC²D CTNX Output Valid after CLKOUT Rising Edge (Output

Delay)

CC²D CNRX Input Valid to CLKOUT Rising Edge (Setup

—

22.48

A10.1

A10.2

—

12.46

Time)

FlexCAN timing specified at f_SYS= 64 MHz, V_DD12= 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, T_A= -40 to 105 °C, and CL

= 50 pF with SRC = 0b00.

Parameter values guaranteed by design.

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4.19.10 Deserial Serial Peripheral Interface (DSPI)

Table 71. DSPI Timing

Num

Symbol

Characteristic

Min

Max

Unit

SpecID

t_SCK

t_CSC

t_ASC

t_SDC

CC²D SCK Cycle TIme^3,4

CC²D PCS to SCK Delay⁶

CC²D After SCK Delay⁷

CC²D SCK Duty Cycle

60⁵

—

A11.1

A11.2

A11.3

A11.4

t_SCK/2

–2ns

t_SCK/2

+ 2ns

t_A

CC²D Slave Access Time

—

A11.5

A11.6

A11.7

(PCSx active to SOUT driven)

t_DIS

t_SUI

CC²D Slave SOUT Disable Time

—

(PCSx inactive to SOUT High-Z or invalid)

CC²D Data Setup Time for Inputs

Master (MTFE = 0)

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

t_HI

t_SUO

t_HO

CC²D Data Hold Time for Inputs

Master (MTFE = 0)

A11.8

A11.9

–4

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

CC²D Data Valid (after SCK edge)

Master (MTFE = 0)

—

Slave

Master (MTFE = 1, CPHA=0)

Master (MTFE = 1, CPHA=1)

CC²D Data Hold Time for Outputs

Master (MTFE = 0)

A11.10

–15

5.5

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

–15

DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, T_A= -40 to 105 °C, and CL = 50 pF with SRC = 0b10.

Parameter values guaranteed by design.

The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.

The actual minimum SCK Cycle Time is limited by pad performance.

Maximum clock possible is System clock/2.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK =

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.

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125

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Last Data

SIN

First Data

Data

First Data

Last Data

SOUT

Figure 36. DSPI Classic SPI Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Figure 37. DSPI Classic SPI Timing — Master, CPHA = 1

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PCSx

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Data

First Data

Last Data

SOUT

SIN

Data

Last Data

First Data

Figure 38. DSPI Classic SPI Timing — Slave, CPHA = 0

PCSx

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Figure 39. DSPI Classic SPI Timing — Slave, CPHA = 1

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Freescale Semiconductor

127

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Figure 40. DSPI Modified Transfer Format Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Figure 41. DSPI Modified Transfer Format Timing — Master, CPHA = 1

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

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Freescale Semiconductor

PCSx

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Figure 42. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

PCSx

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Last Data

First Data

Data

SOUT

SIN

First Data

Last Data

Figure 43. DSPI Modified Transfer Format Timing — Slave, CPHA = 1

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129

4.19.11 I²C timing

Table 72. I C Input Timing Specifications—SCL and SDA

Num

Symbol

Characteristic Min. Value Max. Value

Unit

SpecID

—

CC¹D Start condition hold time

CC¹D Clock low time

CC¹D Data hold time

CC¹D Clock high time

CC¹D Data setup time

—

IP-Bus Cycle²

A12.1

A12.2

A12.3

A12.4

A12.5

A12.6

0.0

IP-Bus Cycle²

0.0

CC¹D Start condition setup time (for repeated

start condition only)

IP-Bus Cycle²

—

CC¹D Stop condition setup time

—

IP-Bus Cycle²

A12.7

Parameter values guaranteed by design.

Inter Peripheral Clock is the clock at which the I²C peripheral is working in the device.

Table 73. I C Output Timing Specifications—SCL and SDA

Num

Symbol

Characteristic

Min. Value

Max. Value

Unit

SpecID

1¹

2¹

3⁴

4¹

5¹

6¹

7¹

8¹

—

CC²D Start condition hold time

CC²D Clock low time

—

IP-Bus Cycle³

IP-Bus Cycle²

A12.8

A12.9

CC²D SCL/SDA rise time

CC²D Data hold time

99.6

—

A12.10

A12.11

A12.12

A12.13

A12.14

A12.15

IP-Bus Cycle²

CC²D SCL/SDA fall time

CC²D Clock high time

CC²D Data setup time

—

99.5

—

IP-Bus Cycle²

—

CC²D Start condition setup time (for repeated

start condition only)

—

9¹

—

CC²D Stop condition setup time

—

IP-Bus Cycle²

A12.16

Programming IBFD (I²C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed.

The I²C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position

is affected by the prescale and division values programmed in IFDR.

Parameter values guaranteed by design.

Inter Peripheral Clock is the clock at which the I²C peripheral is working in the device.

Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA

takes to reach a high level depends on external signal capacitance and pull-up resistor values.

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SCL

SDA

Figure 44. I C Input/Output Timing

4.19.12 QuadSPI timing

The following notes apply to Table 74 and Table 75:

•

All data is based on a negative edge data launch from MPC5645S and a positive edge data capture, as shown in the

timing diagrams in this section.

•

The supply conditions, over a temperature range of -45 °C to 125 °C/140 °C, are as follows:

— IO voltage: 3.0 V, Core supply: 1.2 V

— IO voltage: 3.3 V, Core supply: 1.2 V

— IO voltage: 3.6 V, Core supply: 1.2 V

•

The actual frequency at which the device can work will be a combination of this data and the clock pad profile.

All measurements are considering 70% of VDDE levels for clock pin and 50% of VDDE level for data pins.

Timings assume a setting of 0x0000_000x for QSPI_SMPR register (see the reference manual for details).

A negative value of hold is an indication of pad delay on the clock pad (delay b/w actual edge capturing data in the

device vs. edge appearing at the pin).

•

Measurements are with a load of 50 pF on output pins

The clock profile is measured at 30% to 70% levels of VDDE.

Table 74. QuadSPI timing specifications, maximum temperature 125 °C

Value

Symbol

Parameter

Unit SpecID

Min

Typ

Max

Tcq

CC T Clock to Q delay

3.8

7.6

–13

0.5

0.8

5.3

12.1

13.2

–7.5

1.0

A13.1

A13.2

A13.3

A13.4

A13.5

CC T Setup time for incoming data

CC T Hold time requirement for incoming data

CC T Clock pad rise time

–8.5

0.7

0.8

CC T Clock pad fall time

1.2

The numbers in Figure 45 and Figure 46 correspond to events as described in Table 75.

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131

Table 75. QuadSPI timing events

Event

Number

Last address out

Address captured at flash memory

Data out from flash memory

Ideal data capture edge

Delayed data capture edge with QSPI_SMPR=0x0000_000X

Delayed data capture edge with QSPI_SMPR=0x0000_002X

Delayed data capture edge with QSPI_SMPR=0x0000_004X

Delayed data capture edge with QSPI_SMPR=0x0000_006X

Tcq

SCK

Figure 45. QuadSPI output timing

Tcq

SCK

Note: Ts and Th correspond to QSPI_SMPR = 0x0000_000X.

Figure 46. QuadSPI input timing

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70%

VDDE

30%

SCK

Note: tr and tf measured at 30% and 70% of VDDE

Figure 47. QuadSPI clock profile

4.19.13 TCON/RSDS timing

The following notes apply to Table 76:

•

Measurement condition: vdde/vdd33 = 3.3 V ± 10%, vdd = 1.2 V ± 10%, vss/vsse = 0 V, T = –40–140 °C

Termination: 100 Ω ± 5%

VREFH_RSDS terminations of 47 μF

Table 76. TCON/RSDS timing

Value

Symbol

Parameter

Condition

Unit SpecID

Min

Typ

Max

V_OD

V_OS

CC C Differential output voltage

CC C Common mode voltage

RSDS mode

391

—

471

1.4

A14.1

A14.2

100 Ω termination between

1.17

Pad_p and Pad_n

CC C Rise time

CC C Fall time

Transition from 20% to 80%

—

606

607

—

844

842

—

A14.3

A14.4

A14.5

tplh

CC D Propagation delay, low to

high

2.65

tphl

tdz

CC D Propagation delay, high to

low

—

2.47

—

A14.6

CC D Start-up time

—

200

—

μs

A14.7

A14.8

tskew^{1 2 3}CC C Skew between different

RSDS lines

Max and min skew between

clock and data pads

There are eight programmable bits to provide 256 different skew numbers with various combinations of these bits.

Default value of all the eight skew options are all “1”.

All “0” combination of eight bits is not valid.

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133

Figure 48. Rise/fall transition, part 1

Figure 49. Rise/fall transition, part 2

T_R

T_F

80%

20%

+V_OD

pad_p - pad_n

0V Differential

‚ÄìV

Figure 50. Illustration of tr, tf, and V

Package mechanical data

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5.1

176 LQFP

Figure 51. LQFP176 Mechanical Drawing (Part 1 of 3)

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135

Figure 52. LQFP176 Mechanical Drawing (Part 2 of 3)

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Freescale Semiconductor

Figure 53. LQFP176 Mechanical Drawing (Part 3 of 3)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

5.2

208 LQFP

Freescale Semiconductor

137

Figure 54. LQFP208 Mechanical Drawing (Part 1 of 3)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

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Freescale Semiconductor

Figure 55. LQFP208 Mechanical Drawing (Part 2 of 3)

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139

Figure 56. LQFP208 Mechanical Drawing (Part 3 of 3)

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13

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Freescale Semiconductor

5.3

416 TEPBGA

Figure 57. 416 TEPBGA Mechanical Drawing (Part 1 of 2)

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141

Figure 58. 416 TEPBGA Mechanical Drawing (Part 2 of 2)

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Ordering information

M PC 5645S F0 V VN

Qualification status

Core code

Device number

Fab and mask indicator

Temperature range

Package identifier

Tape and reel status

Temperature range

Package identifier

Tape and reel status

R = Tape and reel

(blank) = Trays

C = -40 C to 85 C

V = -40 C to 105 C

LU = 176 LQFP Pb-free

LT = 208 LQFP Pb-free

VU = 416 TEPBGA Pb-free

Qualification status

P = Pre-qualification

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

Note: Not all options are available on all devices. Refer to Table 77.

Figure 59. Commercial product code structure

Table 77. Orderable part number summary

Speed

(MHz)

Part number

SPC5645SF1VLU

Flash/SRAM

Package

2 MB/64 KB

176 LQFP (Pb free)

208 LQFP (Pb free)

416 TEPBGA (Pb free)

125

SPC5645SF1VLT

SPC5645SF1VVU

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Revision history

Table 78. Revision history

Description

Revision

(Date)

Initial release.

(06 Oct 2009)

Editorial changes.

(7 Dec 2009)

Extensive modifications throughout the “Pinout and signal descriptions” section.

Revised the “Absolute maximum ratings” table.

Revised the “Recommended operating conditions (3.3 V)” table.

Revised the “Recommended operating conditions (5 V)” table.

In the “Voltage regulator electrical characteristics” section, changed “NJD2783” to NJD2873”.

Revised the “Interface to TFT LCD panels” section.

Editorial changes.

(3 Mar 2010)

Added the RoHS logo (indicating RoHS compliance).

Added a "SpecID" column to specification tables throughout the document.

In the device-comparison table:

• Revised the “Timed I/O” entry.

• Changed “Nexus 3” to “Nexus Class 3”.

In the feature list:

• Revised the information for the TCON and RSDS interface.

• In the ADC entry, changed “20 internal channels” to “Up to 20 internal channels”.

• In the QuadSPI entry, changed “quad modes of operation” to “quad IO serial flash memory”.

• In the DCU3 and DCULite entry, changed “WVGA” to “XGA”.

In the “Feature details” section:

• Revised some module abbreviations and names to be consistent with the rest of the documentation.

• In the GFX2D section, deleted “and Adobe Flash 7”.

• In the QuadSPI section, changed “Maximum frequency 80 MHz” to “Maximum serial clock

frequency 80 MHz”

• In the FlexCAN section, changed “The FlexCan modules offer” to “Each FlexCAN module offers”.

• In the DCULite section, changed “WVGA” to “XGA”.

In the 176-pin pinout, changed “MDD” to “MDO”.

In the 208-pin pinout:

• For pin 105, changed “VDDE” to “VDDE_B”.

• Renamed pin 145 (was VRSDS, is VREF_RSDS”)

• For pin 148, changed “RSRS3+P” to “RSDS3P”.

• For pin 160, changed “SCL_D” to “SCL_3”.

• For pin 161, changed “SDA_D” to “SDA_3”.

• For pin 178, changed “DCULITE_G8” to “DCULITE_G6”.

In the 324-pin pinout:

• Renamed pin A1 (was VSS_DR, is VSS).

• Renamed pin B2 (was VDDE_DDR, is VDD_DR).

• Renamed pins D11 and J9 (were VDD33_DR, are VDDE_B).

Added the “Pad configuration during reset phases” section.

In the “Voltage supply pin descriptions” table:

• Renamed V_RSDSto V_{REF_RSDS}and added a footnote about the pin’s required termination.

• Added pin B2 to VDD_DR in the 324-pin package.

• Moved pins D11 and J9 to V_{DDE_B}

Revised the “System pin descriptions” table.

Replaced the entire “DRAM interface pin summary” table.

• In the “Nexus pins” table, added a PCR column.

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Table 78. Revision history (continued)

Description

Revision

(Date)

3 (continued)

(3 Mar 2010)

Added the “VIU muxing” section.

Added the “System design information” section and a “Power-up sequencing” subsection.

In the “Recommended operating conditions (3.3 V)” table, revised footnotes 2 and 4.

In the “Recommended operating conditions (5.0 V)” table, revised footnotes 3 and 5.

Revised the text in the “Voltage regulator electrical characteristics” section.

Added meaningful content to the “DC electrical characteristics” section.

In the “Reset electrical characteristics” table, changed the specifications for W_FRST(was max 40 ns,

is max 70 ns) and W_NFRST(was min 1000 ns, is min 400 ns).

Replaced the entire “Pad AC specifications” section.

Added meaningful content to the “Video Input Unit timing” section.

Added orderable part numbers.

Revised the “Commercial product code structure” figure.

Editorial changes and improvements.

(24 Jun 2010)

In the device-comparison table, changed the GPIO count for the 176-pin package (was 127, is 128).

In the feature list:

• Changed “4 KB, 2-way instruction cache” to “4 KB, 2/4-way instruction cache”.

• Changed “32 kHz crystal oscillator” to “32 KHz crystal oscillator”.

• Changed “188 peripheral interrupt sources” to “181 peripheral interrupt sources”.

• Changed “Primary FMPLL” to “Primary FMPLL (FMPLL0)”.

• Changed “Auxiliary FMPLL” to “Auxiliary FMPLL (FMPLL1)”.

• In the crossbar switch description, deleted the reference to AMBA.

• In the SGM description, changed “WAV file” to “PCM wave”.

• Revised the RLE decoder description.

• In the SIUL description, deleted “resets”.

• In the CMU section, changed “PLL” to “primary FMPLL (FMPLL0)”.

In the feature details:

• Changed “32 kHz oscillator” to “32 KHz oscillator”.

• Changed “128 KHz oscillator” to “128 kHz oscillator”.

• Revised the “Low-power operation” section.

• In the ADC section, changed “0 to 5V common mode conversion range” to “0–5 V or 0–3.3 V

common mode conversion range”.

• Revised the DCU3 section.

• In the “On-chip graphics SRAM” section, added an entry for independent data buffers.

• In the MPU section, changed “Protection offered for 3 concurrent read ports” to “Protection offered

for 4 concurrent read ports”.

In the 176-pin pinout:

• Added content to indicate which functions are available only in this package.

• For pin 116, changed PD113 to PDI13.

• For pin 117, changed PD114 to PDI14.

• For pin 1, changed DCU_VSYNC_TCON2 to DCU_VSYNC.

• For pin 2, changed DCU_HSYNC_TCON1 to DCU_HSYNC.

• For pin 3, changed DCU_DE_TCON3 to DCU_DE.

• For pin 16, changed DCU_TAG_TCON3 to DCU_TAG.

• For pin 56, changed PDI0(VIU0) to PDI0_VIU0.

• For pin 57, changed PD11(VIU1) to PDI1_VIU1.

• For pin 58, changed PDI12(VIU2) to PDI2_VIU2.

• For pin 59, changed PDI3(VIU3) to PDI3_VIU3.

• For pin 148, deleted TCON0.

• For pin 155, deleted DCULITE_G7.

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145

Table 78. Revision history (continued)

Description

Revision

(Date)

4 (continued)

(24 Jun 2010)

In the 208-pin pinout:

• For pin 68, changed eMIOSA23 to eMIOS0[23].

• For pin 69, changed eMIOSA16 to eMIOS0[16].

• For pin 70, changed eMIOSA15 to eMIOS0[15].

• For pin 71, changed eMIOSA14 to eMIOS0[14].

In the 324-pin pinout:

• Added content to indicate which functions are available only in this package.

• Renamed pin J10 (was VSS_DR, is VSS).

In the “Voltage supply pin descriptions” table:

• Deleted the entry for VSS_DR.

• Added pin J10 to the VSS group in the 324-pin package.

Revised the “Nexus pins” table.

In the “Recommended operating conditions (3.3 V)” table, changed the specification for TV_DD(was

0.25 V/μs, is 12 V/ms).

In the “Recommended operating conditions (5.0 V)” table, changed the specification for TV_DD(was

0.25 V/μs, is 12 V/ms).

In the “FMPLL electrical characteristics” table, changed footnote 6 (was “f_CPU64 MHz can be achieved

only at up to 105 °C”, is “f_CPUof 125 MHz can be achieved only at temperatures up to 105 °C with

a maximum FM depth of 2%.”.)

In the “DC specification for CMOS090LP2 library @ VDDE = 3.3 V” > “DC electrical specifications”

table, deleted the specifications for Vih_pci and Vil_pci.

Revised the “Low power oscillator electrical characteristics” table.

In the “ADC electrical characteristics” table, changed “V_DD-0.1” to “V_{DDE_A}–0.1” and “V_DD+0.1” to

“V_{DDE_A}+0.1”.

Renamed “QuadSPI2 Timing” to “QuadSPI timing” and added meaningful content.

Added the “TCON/RSDS timing” section.

In the “Feature List” section:

(25 Feb 2011)

• Changed RTC optional clocking from “main“ to “fast“ 4-16 MHz external oscillator.

• Changed CMU monitor feature from “main crystal oscillator“ to “fast (4–16 MHz) external crystal

oscillator”.

In the “Feature details“ section, changed “main oscillator“ to “external oscillator“ in the “System clocks

and clock generation modules“ section.

In the “Pad configuration during reset phases“ section, changed “Main oscillator pads” to “Fast (4-16

MHz oscillator pads“.

In the ““Voltage supply pin descriptions” table, changed V_{DD_DR}function from “DDR SDRAM interface

supply“ to “1.8V, 2.5V, and 3.3V SDRAM supply“

In the “System pin descriptions” table, specified an external capacitor value of 47pF in the footnote.

In the “Functional ports” section, added list of pad types.

In the “Power-up sequencing” section:

• Added list item that specifies VDDE_B and VDD33_DR are to be powered up first.

• Added VDD33_DR to the list of generic I/O or noise-free supplies.

• Added details to VREG HV list item.

• Changed post-list text regarding DDR to be a separate NOTE, and identified the 3.3V supply as

VDD33_DR.

• Added power-up information to the LV supply (VDD12) list item.

• Added “Parameter classification” section and accompanying table.

Added “C” classification column and values to tables throughout the “Electrical characteristics“ section.

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Table 78. Revision history (continued)

Description

Revision

(Date)

5 (continued)

(25 Feb 2011)

In the “Absolute maximum ratings” table:

• Changed max value for V_{DDE_B}from 5.5V to 3.6 V.

• Changed max value for V_{DD_DR}from TBD to 3.6 V.

• Changed max value for V_RSDSfrom TBD to 3.6 V.

• Changed max value for V_INfrom 5.5V to “V_DDmax(VDDE max of that segment)“.

• Removed “Relative to V_DD“ condition for V_IN.

In the “Recommended operating conditions (3.3 V)” table:

• Changed min value for “V_DD“ from 3.0 V to “V_DDmin“.

• Changed max value for “V_DD“ from 3.6 V to “V_DDmax“.

• Changed V_DDentry to include only V_{DDE_A}, V_{DDE_B}, V_{DD_DR}, and V_DDM

• Corrected error in V_{DDE_A}entry, changed reference in “parameter” column from V_{DDE_C}to V_{DDE_A}

• Added V_{DD_DR}to the V_DDfootnote.

In the “Recommended operating conditions (5.0 V)” table:

• Added footnote for V_{DDE_B}max values.

• Added footnote for V_{DD_DR}typ values.

• Changed min and max values for V_{DD_DR}from 4.5V and 5.5V to 3.0V and 3.6V, respectively.

• Changed max value for V_{DD_DR}(under “voltage drop” conditions) from 5.5V to 3.6V.

• Changed min and max values for V_DDfrom 4.5V and 5.5V to V_DDminand V_DDmax, also referenced

footnote 6.

• Removed VDDE_C and VDDE_E from the VDD “parameter” description and footnote, and added

VDD_DR.

• Changed min and max values for V_{DDE_B}from 4.5V and 5.5V to 3.0V and 3.6V, respectively.

Removed the “Libraries” column from the DC specifications “library“ tables.

Removed the 75Ω and 50Ω cases and added details on the 150Ω case in the “ODT DC electrical

characteristics” table.

Changed the “Main oscillator electrical characteristics“ section name to “Fast external crystal oscillator

(4-16 MHz) electrical characteristics“ and modified text and table name within the section

appropriately.

Removed the “Full swing Pierce” condition and the relevant footnotes from the “Fast external crystal

oscillator (4-16 MHz) electrical characteristics“ table.

Changed the “Low power oscillator electrical characteristics“ section name to “Slow external crystal

oscillator (32 KHz) electrical characteristics“ and modified the text, figure, and table names within

the section appropriately.

Changed “main oscillator” to “fast external oscillator” in the “FMPLL electrical characteristics” table.

Updated parameters, conditions, and values in the “FMPLL electrical characteristics“ table.

Changed the “Main RC oscillator electrical characteristics“ section name to “Fast Internal RC oscillator

(16 MHz) electrical characteristics“ and modified the text and table name within the section

appropriately.

Changed the “Low power RC oscillator electrical characteristics“ section name to “Slow Internal RC

oscillator (128 KHz) electrical characteristics“ and modified the text and table name within the

section appropriately.

Removed duplicate entry of TUEP in the “ADC electrical characteristics” table.

Removed pad_pci and pad_osc48 from the “Functional pad type AC specifications“ table because they

are not used.

Added new “Pad mode configurations” table to the “DRAM Interface” section.

Changed the 324-pin TEPBGA pinout to 416-pin TEPBGA.

Changed the 324-pin TEPBGA mechanical drawing to 416-pin TEPBGA.

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147

Table 78. Revision history (continued)

Description

Revision

(Date)

5 (continued)

(25 Feb 2011)

In the “Operating mode summary“ table:

• Changed the “RAM” column to “SRAM”.

• Changed “STOP” for “16MHz IRC” from “OP” to “On”.

• Changed “STOP” for “Graphics RAM” from “On” to “CG”.

• Changed “STANDBY” for “128KHz IRC” from “OP” to “ON” (both cases).

Changed “324BGA” to “416BGA” in the “Nexus Development Interface (NDI)“ section.

Updated all data in the “Thermal characteristics for 176-pin LQFP“ table.

Updated all data in the “Thermal characteristics for 208-pin LQFP“ table.

Changed “324” in the “Thermal characteristics for 324-pin TEPBGA“ table title to “416”.

Added Spec ID numbers to the “DC electrical specifications“ tables throughout the “DC electrical

specifications“ section.

Updated the NOTE reference details in the “DC specification for CMOS090LP2 library @ VDDE = 3.3

V“ and “DC specification for CMOS090LP2fg library @ VDDE = 5.0 V” sections.

Added Spec ID numbers to the “QuadSPI timing specifications“ tables.

Added Spec ID numbers to the “TCON/RSDS timing“ table.

Added values into the empty cells in the “TCON/RSDS timing“ table.

In the “Orderable part number summary“ table:

• Changed “324” to “416”.

• Updated the part numbers.

Corrected presentation problem with the 176 LQFP figure.

Changed “324” to “416“ in the “SC667108 device comparison“ table.

Changed I/O direction for EXTAL from “O” to “I” in the “System pin descriptions“ table.

Changed I/O direction for XTAL from “I” to “O” in the “System pin descriptions“ table.

In the “V_{DDE_A}“ entry of the “Recommended operating conditions (3.3 V)“ table, changed “V_{SSE_C}“ to

“V_{SSE_A}“.

(09 Aug 2011)

In the “V_{DDE_A}“ entry of the “Recommended operating conditions (5.0 V)“ table, changed “VDDE_C“

to “VDDE_A”.

In the “V_{DDE_A}“ entry of the “Recommended operating conditions (3.3 V)“ table, changed “V_{SSE_C}“ to

“V_{SSE_A}“.

In the “V_SS“ footnote of the “Recommended operating conditions (5.0 V)“ table, changed “V_{SSE_C}“ to

“V_{SSE_A}”.

Removed “QuadSPI timing specifications, maximum temperature 150 C” table.

Removed “DC electrical characteristics” table in “Low voltage domain power consumption” section and

inserted a new table.

In the “Supply leakage” table, changed “spor” to “spcr”.

Removed “pad_multv_hv” and “pull_hv” entries from “Functional pad type AC specifications” table.

Removed “pad_multv_hv”, “pad_io_hv” and “lvds_ref_hv” entries from “Supply leakage” table.

Updated values in “VIU2 timing parameters” table.

Removed “pad_fsr” and “pad_pci” parameters from “Supply leakage” table.

Added Figure 28 - RSDS/TCON Timing Diagram

Added four tables in “DRAM interface” section.

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Table 78. Revision history (continued)

Description

Revision

(Date)

I_DDRUNvalues updated in “DC electrical characteristics” table.

Min and max values of V_DD12in “Voltage regulator electrical characteristics” table changed to 1.26 V

and 1.29 V, respectively.

(7 Feb 2012)

T_Bchanged to T_Afor IDDHALT value in “DC electrical characteristics” table.

Removed ΔRCMTRIM values from “Fast internal RC oscillator (16 MHz) electrical characteristics”

table.

Removed ΔRCMTRIM values from “Slow internal RC oscillator (128 KHz) electrical characteristics”

table.

Changed max Tj to 140 C in “Recommended operating conditions (3.3V)” table.

Changed max Tj to 140 C in “Voltage regulator electrical characteristics” table.

Changed spec limits on VDD12 Post-Trimming, from min=1.270, max = 1.28 to min = 1.145, max =

1.32, in “Voltage regulator electrical characteristics” table.

Added “Low-power voltage regulator electrical characteristics” table.

Added “Ultra low-power voltage regulator electrical characteristics” table.

Offset and gain error values changed to 0.5 and 0.6 Typ, respectively, in “ADC electrical

characteristics” table.

Added “Power-up sequencing” and “Power-down sequencing” diagrams in “Power-up Sequencing”

section.

Added “LPDDR, DDR and DDR2 (DDR2-250) SDRAM timing specifications” table in “DRAM Interface”

section and removed specifications’ tables for DDR1 mode, DDR2 mode and LPDDR mode.

Updated VLVDHV3H, VLVDHV3L, VLVDHV5H and VLVDHV5L values in “Low voltage monitor

electrical characteristics” table.

Updated I_DDHALTTyp and Max values in “DC electrical characteristics” table.

Changed P25 pin to VSS pin in “416 TEPBGA pinout” figure.

In “Absolute maximum Ratings” table, changed max value of V_DDPLLfrom 1.32 V to 1.4 V.

In “DC Electrical Characteristics” table, updated max values of I_DDMAX, I_DDHALT, I_DDSTOPand

I_DDSTDBY1.

(09 Aug 2012)

Removed 1.32 V value for V_DD, from “DC electrical specifications at 3.3 V VDDE”, “DC electrical

specifications at 2.5 V VDDE” and “DC electrical specifications at 1.8 V VDDE”.

Added “Location of TCON Pins” table.

(12 Sep 2012)

Updated Table 62.

(30 Jan 2013)

Added “Section 4.19.5.1, "SDR Timings"” section.

Added a table note for “STOP mode current” entry in Table 22 in Section 4.7.3, "Low voltage domain

power consumption"”.

Added Figure 7. "Pad output delay".

(16 May 2013)

Added Table 38. "SMD pad electrical characteristics", Table 39. "SMD pad delays", and Table 40.

"SSD electrical characteristics".

Changed Vdd max specification from 1.47 V to 1.32 V in Table 23. "DC electrical specifications",

Table 30. "DC electrical specifications at 3.3 V VDDE", Table 32. "DC electrical specifications at

2.5 V VDDE", and Table 34. "DC electrical specifications for 1.8 V VDDE"

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Table 78. Revision history (continued)

Description

Revision

(Date)

In Figure 3. "208-pin LQFP pinout":

(30 Oct 2014)

• “DCU_LITE_TAG” added and “DCU_TAG” removed for PK10.

• “DCU_TAG” added and “DCULITE_TAG” removed for PK11.

• “SDA_1” added for PL0.

• “SCL_1” added for PL1.

In Section 1.4.13, "Display Control Unit (DCU3)", added a feature “Support displays up to 800 x 480

pixel resolutions”.

In Figure 4. "416 TEPBGA package pinout", added MSEO2 pin in added in column 17, 3rd last row.

In Table 7. "Port pin summary":

• Updated “Function” and “Peripheral” entries for PL[0] and PL[1].

• For PB[7], PM[0], PM[8], and PM[12], changed PWMOA to PWMO.

• For PB[8], PB[10], and PM[7], changed PWMO to PWMOA.

In Section 3.1, "Power-up sequencing", added a note “Vreg bypass mode is for factory testing only”.

Removed “Pad AC specifications (3.3 V, PAD3V5V = 1)” table and “Pad AC specifications (3.3 V,

PAD3V5V = 1)” section.

Updated values of V_DDRin Table 13. "Recommended operating conditions (5.0 V)" to 4.5-5.5 V.

Updated temperature in table note 7 of Table 22. "DC electrical characteristics", from 110 ⁰C to 105 ⁰C.

Updated Table 47. "Program and erase specifications" with following modifications:

• Added rows for 64KB and 256KB programming timings

• Updated timings for 16KB and 128KB programming timings

• Removed row for 32KB programming timings

Updated Figure 57. “416 TEPBGA Mechanical Drawing (Part 1 of 2)“ and Figure 58. “416 TEPBGA

Mechanical Drawing (Part 2 of 2)“.

Added a note in Section 2.4.1, "Pad configuration during reset phases".

In Table 67. "VIU2 timing parameters", updated the max value of VIU2 pixel clock frequency. Added a

table note for this entry.

(13 Apr 2015)

In Section 1.3, "Feature list", updated from "Interrupt Controller (INTC) with 181 peripheral interrupt

sources and eight software interrupts" to "Interrupt Controller (INTC) with 163 peripheral interrupt

sources and eight software interrupts".

In Figure 59. “Commercial product code structure“, updated the temperature range for “C” as -40 C to

85 C and for “V” as -40 C to 85/105 C.

Updated Table 77. "Orderable part number summary".

Following changes were made in Rev 12 of DS but were not captured in Rev 12’s revision history:

• In Figure 2. "176-pin LQFP pinout", changed “MCK0” to “MCKO” for pin 174 and added “MSEO2”

to pin 159

• In Table 7. "Port pin summary", added SDA_1 function and I2C1 peripheral for PL[0] port pin and

added SCL_1 function and I2C1 peripheral for PL[1] port pin.

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Document Number: MPC5645S

Rev. 13

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