935316769518_技术文档

Document Number: MC34670

Rev. 3.0, 12/2006

Freescale Semiconductor

Advance Information

IEEE 802.3af PD With Current

Mode Switching Regulator

34670

The 34670 combines a Power Interface Port for IEEE 802.3af

Powered Devices (PD) and a high performance current mode

switching regulator. It allows a designer to build PDs with a minimum

of external components by means of integrating the required IEEE

802.3af functions and all functions necessary to build a high

efficiency DC/DC converter.

POWER OVER ETHERNET

On the PD side the 34670 fully supports the IEEE802.3af standard

and provides complete signature and power classification functions.

It controls inrush current limiting and incorporates adjustable

undervoltage lockout. The switching regulator provides excellent line

and load regulation. It drives an external Power MOSFET with sense

resistor.

EG SUFFIX (PB-FREE)

98ASB42343B

20-PIN SOICW

Features

• Integrated IEEE 802.3af Compliant Interface

• Signature Detection and Classification Functionality

• Integrated Isolation Switch

• Programmable Inrush Current Limiting Control

• Adjustable Undervoltage Lockout

• Input Voltage Range up to 80 V

• Current Mode Control

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

MCZ34670EG/R2

-40°C to 85°C

20 SOICW

• Adjustable Oscillator

• Leading Edge Blanking

• Internal Slope Compensation Circuitry

• Input Overvoltage Protection

• 50% Duty Cycle Limitation

• Pb-Free Packaging Designated by Suffix Code EG

RJ-45

PSE HUB OR SWITCH

ETHERNET APPLIANCE (PD)

TX

RX

PHY

RX

TX

HOST

CONTROLLER

PSE POWER

CONTROLLER

HOST

PROCESSOR

CAT 5

CABLE

SWITCH

-48V

GND

48 V POWER

SUPPLY

34670

PD POWER

CONTROLLER

ISOLATION SWITCH

-48V

DC/DC

Figure 1. 34670 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

FREQ

HIGH VOLTAGE

REGULATOR

VPWR

VDD

2.5V

8V

INTERNAL

SUPPLY

5.7V

0.8R

R

S

R

POR

OSC

Q

GATE

SS

RCLA

EN

3.5V

UV or UVLO

UNDERVOLTAGE

UV or UVLO

5µA

LOCKOUT

+

OVERVOLTAGE

DETECTION

0.3V

S

R

CONTROL LOGIC

Q

4.5V

5k

Ω

PWM

COMPARATOR

0.6 - 2.6V

CS

BLANK

0.4V

1.4V

0.6V

+

3

CURRENT

LIMITATION

ILIM

SLOPE

COMP

GATE

DRIVE

COMP

FB

UVLO

TEMP

SENSOR

1.2V

REG

DETECT

R

SENSE

+

250mV

VIN

VOUT

RESET

Figure 2. 34670 Simplified Internal Block Diagram

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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PIN CONNECTIONS

1

VPWR

20

19

18

17

16

15

14

VDD

2

3

GATE

VPWR

RCLA

UVLO

TEST1

TEST2

FREQ

CS

FB

4

5

COMP

SS

6

7

RESET

8

13

12

11

ILIM

VIN

VOUT

9

10

Figure 3. 34670 Pin Connections

Table 1. 34670 Pin Definitions

Pin Number

Pin Name

Formal Name

Definition

This is the most positive power supply input. The load connects between this pin

and the V_OUTpin.

1, 2

VPWR

Positive Supply

Voltage Input

Connect a resistor between RCLA and V_INto select the class of the PD.

3

4

RCLA

UVLO

Classification Resistor

Undervoltage Lookout

Used to adjust the undervoltage lookout threshold voltage, connected to V_INto use

the default threshold voltage.

Connect to V_INin application mode.

5

6

7

TEST1

TEST2

FREQ

Test pins

Adjusts the internal oscillator frequency by connecting a resistor between FREQ

Frequency Adjustment

Inrush Current Limit

and V_IN

.

Used to adjust the inrush current limit of the isolation switch, add a resistor

8

ILIM

between ILIM and V_IN

.

This is the most negative power supply input.

9

10

VIN

Negative Supply Voltage

This pin is the drain of the internal Power MOSFET (high current path).

This pin is the drain of the internal Power MOSFET (low current path).

This is an active-low RESET output signal. This pin is referenced to V_OUT

11, 12

13

VOUT

RESET

Output Voltage

.

14

RESET Output

(active low)

Connect an external capacitor to SS. The internal current source charges the

capacitor and generates a soft-start ramp.

15

16

17

18

19

20

SS

COMP

FB

Soft Start Input

Compensation Pin

Feedback Input

Current Sense

COMP is the output of the error amplifier and is available for feedback

compensation. COMP is pulled-up by an internal 5.0 kΩ resistor to 5.0 V.

This is the inverting input of the error amplifier. In non-isolated applications it’s

connected to the secondary output through a resistor divider.

The current sense pin CS senses a voltage that is proportional to the current

through the sense resistor.

CS

GATE drives the gate of the external power MOSFET. GATE sources and sinks

up to 1.0 A.

GATE

VDD

Gate Driver Output

V_DDOutput

V_DDmainly supplies the gate of the external power MOSFET. Connect a capacitor

from V_DDto V_OUT

.

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to V_INunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

Supply Current

V

-0.3 to 80

18

V

mA

V

PWR

I

PWR

VOUT Pins Voltage

UVLO Voltage

V

-0.3 to (V

+ 0.3)

OUT

PWR

V

-0.3 to 10

V

UVLO

RCLA

RCLA Voltage

V

-0.3 to 5.0

V

ILIM Voltage

V

ILIM

FREQ Voltage

V_FREQ

V

With respect to:

(2)

(3)

V_OUT

V_IN

FB, COMP Voltage

V_FB, V_COMP

-0.3 to 5.0

-0.3 to 16

-0.3 to 80

V

SS Voltage

SS

VDD Voltage

V

DD

GATE Voltage

CS Voltage

V

-0.3 to (V

+ 0.3)

DD

GATE

V

-0.3 to 5.0

CS

RESET Voltage

V

-0.3 to 15

RESET

ESD Voltage ⁽¹⁾

Human Body Model

Machine Model

V

ESD1

±2000

±200

V

ESD2

Output Clamp Energy

E

12

mJ

CL

NotesNotes

1. ESD1 testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω). ESD2 testing is performed in

ZAP

accordance with the Machine Model (C

2. Measured value relative to V_OUT

= 200 pF, R

= 0 Ω).

ZAP

3. Measured value relative to V

IN

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings (continued)

All voltages are with respect to V_INunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

THERMAL RATINGS

Operating Temperature

Ambient ⁽⁴⁾

°C

-40 to 85

120

T

A

Junction ^{(8), (9)}

T

J

Storage Temperature

T_STG

-65 to 150

800

°C

Power Dissipation (T = 25 °C) ⁽⁷⁾

P

D

mW

°C/W

A

Thermal Resistance

R_θ

JA

103

47

Junction to Ambient

20LD SOIC W/B Package ⁽⁹⁾

R_θJB

(6)

Peak Package Reflow Temperature During Reflow ⁽⁵⁾

Thermal Shutdown Temperature

Thermal Shutdown Recovery Temperature

NotesNotes

,

T_PPRT

Note 6

180

°C

T

SHUT

150

HYST

4. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.

5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

7. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.

8. For T = 85°C and P = 700 mW and R = 47°C/W.

θJB

A

D

9. Measured with 4 layers 2s2p JEDEC std. PCB.

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 30 V ≤ V_PWR≤ 60 V, -40°C ≤ T_A≤ 85°C, V_IN= 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SIGNATURE DETECTION

Input Offset Current (1.4 V ≤ V

≤ 9.5 V)

I

—

10

—

µA

kΩ

PORT

OFFSET

Differential Input Resistance (1.4 V ≤ V

≤ 9.5 V)

R

600

PORT

DIFF

CLASSIFICATION

Classification Current (13.5 V ≤ V

≤ 20 V)

I

mA

PORT

CLASS

Class 0: R

Class 1: R

Class 2: R

Class 3: R

Class 4: R

= 4.42 kΩ

= 475 Ω

= 261 Ω

= 169 Ω

= 113 Ω

0

—

4.0

12

20

30

44

CLASS

9.0

17

26

36

Classification Current Limit

I

—

50

mA

V

CLASS(LIM)

RCLA Reference Voltage (13.5 V ≤ V

≤ 20 V)

V

4.0

4.5

5.0

PORT

RCLA

INRUSH CURRENT LIMITATION (37 V ≤ V

≤ 60 V) (RLIM)

PORT

Input Inrush Current, ILIM connected to V_IN

I

—

350

mA

INRUSH

Input Inrush Current, ILIM connected via resistor R

to V_IN

ILIM

R

= 12.1 kΩ

= 42.2 kΩ

= 191 kΩ

130

70

180

110

65

250

165

100

ILIM

30

NORMAL OPERATION (VPWR, UVLO)

Supply Voltage

V

—

4.5

—

60

7.3

40

V

mA

V

PWR

Supply Current ⁽¹⁰⁾

I

PWR

Default Turn-On Voltage (UVLO = V_IN

Default Turn-Off Voltage (UVLO = V_IN

UVLO Hysteresis when set internally

External UVLO Programming Range

UVLO Reference Voltage

)

V

—

UVLO(ON)

V

30

6.0

25

1.96

—

V

UVLO(OFF)

V

—

V

HYST(INT)

V

—

50

V

UVLO(PR)

V

2.0

15

—

2.04

—

V

UVLO(REF)

UVLO Hysteresis when set externally

UVLO Bias Current

V

%

µA

HYST(EXT)

I

—

1.0

UVLO(B)

ISOLATION SWITCH (ILIM)

On-Resistance (V

= 48 V, I

= 350 mA) ⁽¹¹⁾

PORT

R

—

500

700

mΩ

PORT

DS(ON)

Isolation Switch Current Limit in Normal Operation Mode

I

380

mA

LIM

Notes

10. GATE pin open, PWM controller running.

11. Measured across V_INand V_OUT

.

34670

Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics(continued)

Characteristics noted under conditions 30 V ≤ V_PWR≤ 60 V, -40°C ≤ T_A≤ 85°C, V_IN= 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

PWM COMPARATOR (COMP)

Symbol

Min

Typ

Max

Unit

COMP Control Voltage Range

COMP Input Bias Current

V

1.3

—

4.0

1.8

V

COMP

I

mA

COMP(B)

HIGH VOLTAGE REGULATOR

Regulator Output Voltage

VDD

8.0

9.0

10

—

V

REG

Regulator Turn-Off Voltage ⁽¹²⁾

V

VDD

Reg

REG(OFF)

+0.5

Regulator Current Limitation ⁽¹³⁾

Regulator Continuous Current

GATE DRIVER (UVLO)

Gate Driver UVLO, Rising

Gate Driver UVLO, Falling

CURRENT LIMIT (CS)

CS Threshold Voltage

CS Bias Current

I

7.0

—

15

mA

REGLIM

I

—

5.0

REGDC

V

VDD-0.5

—

V

GATE(R)

V

6.5

GATE(F)

V

320

—

400

—

480

30

mV

CS

I

µA

CS(B)

ERROR AMPLIFIER

Reference Voltage

V

1.164

1.2

1.236

V

REF

OVERVOLTAGE SHUTDOWN

OVLO Threshold, Rising

OVLO Threshold, Falling

OVLO Hysteresis

V

66

63

—

72

69

—

V

OV(R)

V

OV(F)

V

3.0

OV(HYS)

SOFT-START (SS)

SS Output Voltage

V

—

3.25

—

2.0

5.0

2.0

—

V

µA

mA

V

SS

SS Source Current

I

6.75

2.25

SS(OUT)

SS Sink Current

I

SS(IN)

Shutdown Threshold Voltages

V

0.48

0.24

0.6

0.3

0.72

0.40

SS(R)

V

SS(F)

THERMAL SHUTDOWN

Thermal Shutdown Temperature

Thermal Hysteresis

T

150

—

165

30

180

—

°C

SHUTDOWN

T

HYS

Notes

12. An external voltage has to be applied.

13. Thermal limitations of the device might derate usable current range.

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 30 V ≤ V_PWR≤ 60 V, -40°C ≤ T_A≤ 85°C, V_IN= 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

NORMAL OPERATION

Turn-On Filter Time

Turn-Off Filter Time

PWM COMPARATOR

t

—

200

—

µs

FILT(ON)

t

FILT(OFF)

Slope Compensation Ramp as a Function of Switching Frequency

mV/µs

f

= 100 kHz

= 250 kHz

= 400 kHz

m

—

10

25

40

—

PWM

100

m

250

m

400

Duty Cycle Limit ⁽¹⁴⁾

GATE DRIVER

D

—

48

%

MAX

Rise Time (10% - 90%), C

Fall Time (90% - 10%), C

= 2.0 nF, VDD

= 9.0 V

REG

t

—

50

30

ns

Load

R

= 2.0 nF, VDD

= 9.0 V

REG

t

Load

F

CURRENT LIMIT

Blanking Time ⁽¹⁴⁾

PWM OSCILLATOR

t

40

50

60

ns

BLANK

Default Clock Frequency (FREQ connected to V_IN

Oscillator Frequency Adjusting Resistor Range

)

f

175

121

320

80

225

—

325

499

480

120

kHz

kΩ

PWM

R

FREQ

Oscillator Frequency Range, R

ERROR AMPLIFIER

= 121 kΩ

= 499 kΩ

f_RANGE

—

kHz

FREQ

—

FREQ

Gain Bandwidth ⁽¹⁴⁾

GBW

1.0

—

MHz

dB

DC Open Loop Gain

A

80

VOL

RESET OUTPUT

RESET Output Low Voltage (I

= 20 mA)

V

—

0.8

—

V

RESET, SINK

RESET,LOW

t_RESET

RESET Output Filter Time

20

µs

Notes

14. Guaranteed by design. Not production tested.

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

TYPICAL SWITCHING WAVEFORMS

w/o snubber

w/ snubber

w/o snubber

Figure 4. Drain Voltage of Switching MOSFET

Figure 6. Secondary Voltage before Diode

Figure 5. Secondary and Output Voltage

Figure 7. Gate Voltage and Voltage at CS pin

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

MC34670 Efficiency Plot: V_o= 5V, w/o bias winding, Coilcraft

DA2142-AL

90.00

85.00

80.00

75.00

70.00

65.00

60.00

55.00

50.00

57V

48V

36V

0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

I_O[A]

MC34670 Efficiency Plot: V_o= 5V, w/ bias winding, Coilcraft

DA2362-AL

90.00

85.00

80.00

75.00

70.00

65.00

60.00

55.00

50.00

57V

48V

36V

0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

I_O[A]

Figure 8. Efficiency Plot

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 34670 combines a Power Interface Port for IEEE

802.3af Powered Devices (PD) and a high performance

current mode switching regulator. It allows a designer to build

PDs with a minimum of external components by means of

integrating the required IEEE 802.3af functions and all

functions necessary to build a high efficiency DC/DC

converter. Thus 34670 gives the system designer a device

that drastically reduces cost and board space.

The 34670 also offers an input overvoltage detection to

protect the external switching MOSFET by disabling the gate

driver in case of input line overvoltage.

The switching regulator provides excellent line and load

regulation. It drives an external power MOSFET with sense

resistor. The switching frequency is adjustable between

100 kHz and 400 kHz. The output voltage feedback

information can be accomplished by an optocoupler, if

isolation is required.

On the PD side the 34670 fully supports the IEEE802.3af

standard and provides complete signature detection and

power classification functions. It controls inrush current

limiting and incorporates an adjustable undervoltage lockout.

The 34670 includes thermal protection circuitry to protect the

device in case of high power dissipation.

An internal logic control block manages the sequencing of

signature detection, classification and proper turn on and turn

off of the DC/DC converter.

FUNCTIONAL PIN DESCRIPTION

POSITIVE SUPPLY VOLTAGE INPUT (VPWR)

RESET OUTPUT (RESET)

This is the most positive power supply input. The load

connects between this pin and the V_OUTpin.

This is an active-low RESET output signal. This pin is

referenced to V_OUT

.

CLASSIFICATION RESISTOR (RCLA)

SOFT START INPUT (SS)

Connect a resistor between RCLA and V_INto select the

class of the PD.

Connect an external capacitor to SS. The internal current

source charges the capacitor and generates a soft-start

ramp.

UNDERVOLTAGE LOOKOUT (UVLO)

COMPENSATION PIN (COMP)

Used to adjust the undervoltage lookout threshold voltage,

connected to V_INto use the default threshold voltage.

COMP is the output of the error amplifier and is available

for feedback compensation. COMP is pulled-up by an

internal 5.0 kΩ resistor to 5.0 V.

TEST PINS (TEST1, TEST2)

Connect to V_INin application mode.

FEEDBACK INPUT (FB)

This is the inverting input of the error amplifier. In non-

isolated applications it’s connected to the secondary output

through a resistor divider.

FREQUENCY ADJUSTMENT (FREQ)

Adjusts the internal oscillator frequency by connecting a

resistor between FREQ and V_IN.

CURRENT SENSE (CS)

INRUSH CURRENT LIMIT (ILIM)

The current sense pin CS senses a voltage that is

proportional to the current through the sense resistor.

Used to adjust the inrush current limit of the isolation

switch, add a resistor between ILIM and V_IN.

GATE DRIVER OUTPUT (GATE)

NEGATIVE SUPPLY VOLTAGE (VIN)

GATE drives the gate of the external power MOSFET.

GATE sources and sinks up to 1.0 A.

This is the most negative power supply input.

OUTPUT VOLTAGE (VOUT)

VDD OUTPUT (VDD)

This pin is the drain of the internal Power MOSFET (high

current path and low current path).

V_DDmainly supplies the gate of the external power

MOSFET. Connect a capacitor from V_DDto V_OUT

.

34670

Analog Integrated Circuit Device Data

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11

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

POWER DEVICES (PD) INTERFACE

The PD interface of the 34670 has been designed to

comply with the requirements of the IEEE standard 802.3af.

The device operates in three different modes, depending on

the input voltage.

I

PD OPERATING MODES

The IEEE 802.3af standard defines three operating modes

in general. These modes are summarized in Table 5.

I₂

I₁

Table 5. PD Operating Modes

Operating Mode

Voltage at PD Input Connector

Signature Resistor Detection

Classification

2.7 V - 10.1 V

14.5 V - 20.5 V

37 V - 57 V

Normal Operation Mode

V

V₁

V₂

SIGNATURE RESISTOR DETECTION

A PD shall present a valid detection signature at the PD

input connector to get properly detected as a power over LAN

enabled pin. Valid and non-valid detection signature regions

are separated by guard bands. See Figure 9 for valid and

non-valid signature regions.

V

– V

2

1

dR = --------------------

– I

I

2

1

Figure 10. dR Measurement

It can be seen in Figure 11, that a signature resistor of

25 kΩ as defined in IEEE 802.3af and two diodes in series

would lead to an effective resistance out of the valid region

specified in Figure 9. At low voltages the effective resistance

is above the maximum allowed value of 26.25 kΩ, as

illustrated in Figure 11. Therefore one has to adjust the

signature resistor RSIG (R₁and R₂, see UVLO Adjustment

on page 13) to a value below 25 kΩ to stay within the valid

region.

valid region

non-valid region

Signature [kΩ]

12

23.75 26.25

45

Figure 9. Signature Resistance Guard Bands

The effective resistance across the input pins is calculated

by two subsequent voltage-current measurements made

during the detection process by the PSE.

VALID PD DETECTION SIGNATURE

CHARACTERISTICS

During signature detection phase the Power Sourcing

Equipment (PSE) applies a voltage in the range 2.7 V -

10.1 V on the PI connector and looks for the 25 kΩ signature

resistor. Since the PD circuitry includes bridge rectifiers, the

PD has to compensate for the voltage drop across the diodes

and the diodes serial resistance. The effective signature

resistance dR is obtained by the V-I-Slope measurement of

the PSE (Figure 10).

Figure 11. dR at Low Input Voltages

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

CLASSIFICATION

CLASSIFICATION SIGNATURE LOAD CURRENT

A PD may optionally be classified by the PSE. The intent

of classification is to provide a method for more efficient

power allocation through the PSE. The PD classification

allows the PSE to identify four different (power) classes

depending on the required power that the PD will draw during

normal operation. The classes and the corresponding

maximum power drawn by the PD is shown in Table 6.

The implementation for the classification circuitry is shown

in Figure 12.

+V_PORT

34670

VPWR

Table 6. PD Classes

Maximum Power

V_ref

+

-

Class

Usage

EN

[W]

0

1

2

3

4

Default

Optional

Reserved

0.44 - 12.95

0.44 - 3.84

3.84 - 6.49

6.49 - 12.95

—

RCLA

I_CLASS

VIN

R_CLASS

-V_PORT

PD CLASSES

Figure 12. Classification Circuitry

During classification probing by the PSE, the PD applies

the appropriate load current onto the line. The PSE measures

the load current and can determine the classification as

described in Table 7.

A constant voltage is applied at pin RCLA and depending

on the resistor R_CLASS, a current from +V_PORTto -V_PORTis

flowing with the following relation:

V_RCLA

I_CLASS= --------------------

R_CLASS

.

Table 7. PD Class vs. Classification Current

I_CLASSis the classification current that is measured by the

PSE. The values for the R_CLASSresistor corresponding to the

appropriate class are listed in Table 8.

Classification Current [mA]

Class

Condition

Min

Max

Table 8. PD Class vs. Classification Resistor R_CLASS

14.5 - 20.5 Volts

measured at PD

input connector

0

1

2

3

4

0

4

R_CLASS[Ω]

4.42k

475

Class

Classification Current [mA]

9

12

20

30

44

0

1

2

3

4

2.0

10.5

18.5

28

17

26

36

261

169

40

113

UVLO ADJUSTMENT

The 34670 has default UVLO settings that corresponds to

the IEEE 802.3af standard. Nevertheless the user can adjust

the UVLO by an external resistor divider as sketched in

Figure 13. Since the UVLO resistor divider replaces the

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

signature resistor, the total resistance of R₁+R₂must equal

25 kΩ.

R

= R

– R

SIG

1

2

V_UVLO(OFF)= V_UVLO(ON)⋅ 0.85

+V_PORT

The typical turn-off voltage V_UVLO(OFF)is 85% of the turn

VPWR

on voltage V_UVLO(ON)

.

RCLA

INRUSH CURRENT LIMITATION

The 34670 has been designed to interface also with legacy

PoE-PSEs which do not meet the inrush current requirement

of the IEEE 802.3af specification. By setting the initial inrush

current limit to a low level, a PD using the 34670 minimizes

the current drawn from the PSE during start-up. The

maximum inrush current level can be set by connecting a

resistor from ILIM to V_INas illustrated in Figure 15.

R₁

UVLO

R₂

ILIM

VIN

-V_PORT

+V_PORT

Figure 13. UVLO Adjustment by External

Resistor Divider

VPWR

To use the default settings for UVLO, the pin UVLO must

be connected to VIN. In this case, a valid signature resistor

has to be placed between -V_PORTand +V_PORT. This

configuration can be seen in Figure 14.

R_CLASS

RCLA

R_SIG

25kΩ

+V_PORT

UVLO

R_ILIM

ILIM

VPWR

VIN

RCLA

-V_PORT

R_SIG

25kΩ

Figure 15. Inrush Current Limitation by External

Resistor R_ILIM

UVLO

ILIM

The following table shows the selectable current limits and

the corresponding resistor value that has to be connected

between pins ILIM and VIN:

VIN

-V_PORT

Table 9. Inrush Current Limit vs. R_ILIM

Figure 14. Default UVLO Settings

Inrush Current Limit [mA]

R

Value [kΩ]

ILIM

To calculate the values for R₁and R₂the following

equations should be used:

180

110

65

12.1

42.2

191

R

+ R = R

SIG

1

2

V_UVLO(REF)

---------------------------------

V_UVLO(ON)

R

=

⋅ R

SIG

2

After powering up, the 34670 switches to the high level

current limit, thereby allowing the PD to consume up to

12.95 W if a 802.3af PSE is present.

where V_UVLO(ON)is the desired turn-on voltage threshold and

_UVLO(ref)the UVLO reference voltage.

V

PULSE WITH MODULATOR CONTROLLER

diode reverse recovery current of the power circuit. The

leading-edge blanking of the CS signal prevents the PWM

comparator from premature termination of the on cycle.

CURRENT-MODE CONTROL OPERATION

The 34670 offers current-mode control operation with

leading-edge blanking. The current-limit comparator monitors

the CS pin at all times and provides cycle-by-cycle current

limit.

The 34670 limits the duty cycle to 50%. This is

advantageous for applications which are not allowed to

exceed an on-time of 50 % of the switching period T_S. Beside

the duty-cycle limit, slope compensation is provided to

stabilize the inner current loop and avoid oscillations for

The CS signal contains a leading-edge spike that is the

result of the MOSFET gate charge current, capacitive and

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

converters running in continuos conduction mode (CCM).

The value of the slope compensation depends on the

switching frequency. See Table 10.

T1

N_P

N_S

Table 10. Slope Compensation Values

Switching Frequency [kHz]

Slope Compensation [mV/µs]

100

250

400

10

25

50

R_V

ISOLATED OPTOCOUPLER FEEDBACK

Isolated voltage feedback can be accomplished by using

an optocoupler and a shunt regulator (see Figure 19). The

output voltage accuracy is a function of the accuracy of the

shunt regulator and feedback resistor divider tolerance,

therefore the feedback resistors should have an appropriate

accuracy.

R₁

R₂

Since the error amplifier function is implemented on the

secondary side by the optocoupler and a 3-pin adjustable

shunt regulator, the internal error amplifier of the 34670 is not

used. The FB pin is connected to V_OUT, thus disabling the

internal open-drain error amplifier.

TLV431

Figure 16. Isolated Optocoupler Feedback

The bias voltage for the optocoupler is accomplished

through the internal 5.0 kΩ pull-up resistor between COMP

and an internal 5.0 V reference.

ISOLATED PRIMARY CONTROL FEEDBACK

Another option to accomplish isolated feedback is the use

of a tertiary winding (see Figure 21). The advantage of this

solution without optocoupler and shunt regulator is clearly the

cost effectiveness. Nevertheless the line and load regulation

is worse than with optocoupler feedback.

When a TL431 or TLV431 shunt regulator is used for

output voltage regulation, the output voltage is set by the ratio

of resistors R₁and R₂, see Figure 16 for details. The output

voltage is given by the following equation:

When isolated primary feedback is used, the loop

compensation components are connected between pins

COMP and FB.

R

⎛

⎞

⎟

⎠

1

V

= V

⋅ 1 + -------

⎜

O

REF

R

⎝

2

where V_REF= 1.24 V for the TLV431 (V_REF= 2.5 V for the

TL431).

INTERNAL REGULATORS

The internal high voltage regulator of the 34670 regulates

from the input voltage across VPWR and VIN down to the

V_DDvoltage. During start-up the high voltage regulator

provides the necessary voltage for the internal gate driver to

commence switching. If the external MOSFET gate drive

pulls less than 3.0 mA under all circumstances, an auxiliary

transformer winding that usually provides the bias voltage for

the chip and the gate driver is not required.

In cases where the external MOSFET gate drive pulls

more than 5.0 mA, an auxiliary winding is needed to reduce

the power dissipation in the internal high voltage LDO. See

Figure 18 for an application drawing. It is recommended to

add a 0.1 µF ceramic capacitor in parallel with the existing

load capacitor. This reduces noise at the V_DDpin caused by

the auxiliary winding.

The high voltage regulator is disabled when the V_DDpin is

forced by an external voltage above the V_DDregulation point.

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

This reduces power dissipation in the device and improves

overall efficiency.

When the overvoltage protection is triggered

(V_PWR> V_OV(R)), the gate driver is immediately disabled. At

the same time, the slow discharge of C_SSis initiated. While

the soft-start capacitor is discharging, the gate driver remains

disabled. Once V_SS= 0.3 V and the overvoltage

(V_PWR< V_OV(F)) condition disappears, operation resumes

through a regular soft-start.

12

V_REG(OFF)

10

V_GATE(R)

CURRENT-SENSE COMPARATOR

8

The current-sense (CS) comparators and its associated

circuitry limits the peak current through the MOSFET. Current

is sensed at CS pin as a voltage across the sense resistor

V_GATE(F)

6

4

2

R_CSbetween the source of the MOSFET and V_OUT

.

The CS input has two voltage trip levels, a 600mV high

limit and a 400 mV low limit. When the voltage on CS

produced by a current through the current sense resistor

exceeds the high limit threshold, the current ON-cycle is

immediately terminated and the GATE output is pulled low.

t

GATE enable

If the low limit threshold is exceeded for longer than 50 ns

(typical blanking time), the current ON-cycle is also

terminated. The blanking time ensures a false termination of

the switching cycle caused by the leading-edge spike on the

sense waveform.

HVReg enable

Figure 17. V_DDand MOSFET Driver Output Behavior

A load capacitor connected to V_DDensures a proper

filtering of the V_DDvoltage. The minimum capacitance value

for this load capacitor should be at least 10 µF. An electrolytic

type capacitor is sufficient.

The current-sense resistor R_CSis selected according to

the following equation:

400mV

R

= ----------------------------------------

CS

I

LIM(primary)

Please refer to application note A/N3279 for further

information about the size of the capacitor.

where I_LIM(primary)is the maximum peak primary-side

current.

If V_DDfalls below the UVLO threshold, the voltage

regulator is disabled and the MOSFET driver output (GATE)

is held low.

In case of an overcurrent in the external MOSFET the

current switching cycle is terminated and GATE is pulled low.

The soft-start capacitor C_SSis discharged and after removal

of the faulty condition the PWM is re-started through a regular

soft start.

PWM CONTROLLER UVLO, SOFT-START, AND

SHUTDOWN FUNCTION

The soft-start function provided by the 34670 allows the

output voltage to ramp up in a controlled way, thus

eliminating output voltage overshoot.

PWM OSCILLATOR

A default 250 kHz oscillator sets the switching frequency

of the PWM controller. The frequency of the oscillator can be

adjusted between 100 kHz and 400 kHz by an optional

external resistor R_FREQconnected from the FREQ pin of the

integrated circuit to V_IN.

While the PWM controller is in undervoltage lockout, the

capacitor C_SSconnected to the SS pin is fully discharged.

After coming out of undervoltage lockout, an internal current

source starts charging the capacitor C_SSto initiate soft-start.

When V_SShas reached 0.6 V, the gate driver is enabled and

PWM operation begins. The duty cycle during soft-start is

primarily controlled by the internal sawtooth voltage and the

voltage at the SS pin. If the voltage at the SS pin is above

2.6 V, the regular PWM control through pins CS, COMP, and

FB takes over and soft-start is finished.

The appropriate switching frequency f_PWMcan be

calculated as shown below:

47920

f

[kHz] = ----------------------------------- + 4

PWM

R

[kΩ]

FREQ

where f_PWMis the PWM switching frequency and R_FREQis the

frequency adjusting resistor.

The following equation calculates the total soft-start time:

t

[ms] = 0.4 ⋅ C

[nF]

To use the default frequency of 250 kHz the FREQ pin can

be connected to V_INor can be left open.

SS

OVERVOLTAGE SHUTDOWN

RESET OUTPUT

The 34670 includes an overvoltage protection (OVP)

feature that turns off the external MOSFET when the input

voltage exceeds the overvoltage threshold.

The RESET pin is an open drain output. The reset control

circuit supervises the FB voltage and recognizes if the output

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

voltage is out of regulation. In this case the RESET pin is

pulled low.

N-CHANNEL MOSFET GATE DRIVER

GATE drives an N-channel MOSFET. GATE sources and

sinks large transient currents up to 1.0 A to charge and

discharge the MOSFET gate. The GATE output is supplied

by the internal generated V_DDvoltage, which is internally set

to approximately 9.0 V.

The RESET output can only be used in non-isolated

applications.

There is a 20 µs delay filter preventing erroneous RESET

output pulses. During soft-start, RESET is held low. RESET

is released when the PWM controller is in regulation.

For Power-over-Ethernet applications, the used MOSFET

must be able to withstand a DC level of ~60 V plus the

reflected voltage at the primary side of the transformer. This

requires a MOSFET rated at 150 V or 200 V.

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

TYPICAL APPLICATIONS

Please refer to application note AN3279 for further information of PD design and layout recommendations.

T1

N_AUX

+V_PORT

V_OUT= 5V@2A

3

N_P

N_S

34670

RX

VPWR

RCLA

6

1

RESET

VDD

TX

R_V

C_DD0.1

F

2

C_PORT

M1

R₁

R₂

GATE

CS

R_CLASS

C_IN

UVLO

ILIM

R_CS

4

5

VIN SS

FREQ COMP FB VOUT

-V_PORT

C_SS

7

8

Figure 18. Isolated Flyback Converter with Bias Winding

+V_PORT

V_OUT= 5V@2A

D₁

T1

RX⁺

3

N_P

N_S

34670

RX

TX

RX^-

TX⁺

VPWR

RESET

RCLA

VDD

6

1

TX^-

R_V

2

C_DD

C_PORT

M1

R₁

R₂

GATE

CS

R_CLASS

C_IN

UVLO

ILIM

R_CS

4

5

VIN SS

FREQ COMP FB VOUT

SPARE⁺

SPARE^-

-V_PORT

C_SS

7

8

Figure 19. Isolated Flyback Converter without Bias Winding

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

TYPICAL APPLICATIONS

T1

+V_PORT

N_R

N_P

3

N_S

34670

RX

TX

VPWR

RCLA

6

1

RESET

VDD

R_V

2

C_DD

C_PORT

M1

R₁

R₂

GATE

CS

R_CLASS

C_IN

UVLO

ILIM

R_CS

4

5

R_v1

R_v2

VIN SS

FREQ COMP FB VOUT

-V_PORT

C_SS

7

8

Figure 20. Isolated Forward Converter

T1

C_AUX

N_AUX

+V_PORT

V_OUT= 5V@2A

3

N_P

N_S

34670

RX

TX

VPWR

RESET

RCLA

VDD

6

1

2

C_DD

C_PORT

M1

R₁

GATE

R_CLASS

C_IN

UVLO

ILIM

CS

R₂

R_CS

4

5

VIN SS

FREQ COMP FB VOUT

-V_PORT

C₂

C_SS

R₂

7

8

C₁

Figure 21. Isolated Flyback with Primary Control

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

TYPICAL APPLICATIONS

+V_PORT

V_OUT= 5V@2A

T1

3

D₁

N_P

N_S

C_O

34670

RX

VPWR

RCLA

6

RESET

VDD

1

TX

2

C_DD

C_PORT

M1

R₃

R₄

GATE

CS

R_CLASS

C_IN

UVLO

ILIM

R_CS

4

5

VIN SS

FREQ COMP FB VOUT

R₁

R_b

-V_PORT

C₂

C_SS

R₂

7

8

C₁

Figure 22. Non-Isolated Flyback Converter

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

REFERENCE DOCUMENTS

Table 11. Reference Documents

Title

LIterature Order Number

Publication Date

IEEE Std 802.3af™-2003

AN3279

18 June 2003

MC34670 Usage and Configuration

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EG SUFFIX (PB-FREE)

20-PIN

PLASTIC PACKAGE

98ASB42343B

ISSUE J

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

REVISION HISTORY

Revision

Date

8/2006

Description of Changes

• Initial release

1.0

2.0

• Change to UVLO Hysteresis when set internally on page 6, Regulator Current Limitation

⁽¹³⁾on page 7, OVLO Threshold, Rising on page 7, OVLO Threshold, Falling on page 7,

Shutdown Threshold Voltages on page 7, and Default Clock Frequency (FREQ

connected to VIN) on page 8

9/2006

• Changed Data Sheet category to “Advanced Information*”

• Typ and Max change to RCLA Reference Voltage (13.5 V ≤ V_PORT≤ 20 V) on page 6

• Deleted Oscillator Frequency Adjusting Resistor Range in Static Electrical

Characteristics

12/2006

3.0

• Split Oscillator Frequent Range into two parameters, Oscillator Frequency Range,

R_FREQ= 121 kΩ on page 8 and Oscillator Frequency Range, R_FREQ= 499 kΩ on page 8

• Added note to Duty Cycle Limit ⁽¹⁴⁾on page 8, Blanking Time ⁽¹⁴⁾on page 8, and Gain

Bandwidth ⁽¹⁴⁾on page 8

• Changed nomenclature for Peak Package Reflow Temperature During Reflow ^{(5) (6)}

on

,

page 5

• Changed name and value for Thermal Shutdown Recovery Temperature on page 5

34670

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

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Tempe, Arizona 85284

+1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

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Freescale Semiconductor reserves the right to make changes without further notice to

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All other product or service names are the property of their respective owners.

1-800-441-2447 or 303-675-2140

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LDCForFreescaleSemiconductor@hibbertgroup.com

MC34670

Rev. 3.0

12/2006


型号：	935316769518
厂家：	NXP
描述：	Switching Regulator 开关
文件：	总24页 (文件大小：1252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935316769518 [NXP]

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